29F080-90_技术文档

PRELIMINARY

MX29F080

8M-BIT[1024Kx8]CMOSEQUALSECTORFLASHMEMORY

FEATURES

•

1,048,576 x 8 byte mode only

•

Status Reply

Single power supply operation

- Data polling & Toggle bit for detection of program

and erase operation completion.

Ready/Busy (RY/BY)

- 5.0V only operation for read, erase and program

operation

•

Fast access time: 70/90/120ns

- Provides a hardware method of detecting program

and erase operation completion.

Sector Group protect/chip unprotect for 5V/12V sys-

tem.

Low power consumption

- 30mA maximum active current

- 0.2uA typical standby current

•

Command register architecture

Sector Group protection

- Byte Programming (7us typical)

- Sector Erase of 16 equal sector with 64K-Byte each

Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors with

Erase Suspend capability.

- Hardware protect method for each group which con-

sists of two adjacent sectors

- Temporary sector group unprotect allows code

changes in previously locked sectors

10,000 minimum erase/program cycles

Latch-up protected to 100mA from -1V toVCC+1V

Low VCC write inhibit is equal to or less than 3.2V

Package type:

•

- Automatically program and verify data at specified

address

•

Erase suspend/Erase Resume

- Suspends sector erase operation to read data from,

or program data to, another sector that is not being

erased, then resumes the erase.

- 40-pinTSOP or 44-pin SOP

•

Compatibility with JEDEC standard

- Pinout and software compatible with single-power

supply Flash

GENERAL DESCRIPTION

TTL level control inputs and fixed power supply levels

during erase and programming, while maintaining maxi-

mum EPROM compatibility.

The MX29F080 is a 8-mega bit Flash memory organized

as 1024K bytes of 8 bits. MXIC's Flash memories offer

the most cost-effective and reliable read/write non-vola-

tile random access memory. The MX29F080 is pack-

aged in 40-pinTSOP or 44-pin SOP. It is designed to be

reprogrammed and erased in system or in standard

EPROM programmers.

MXIC Flash technology reliably stores memory contents

even after 10,000 erase and program cycles. The MXIC

cell is designed to optimize the erase and program

mechanisms. In addition, the combination of advanced

tunnel oxide processing and low internal electric fields

for erase and programming operations produces reliable

cycling. The MX29F080 uses a 5.0V±10% VCC supply

to perform the High Reliability Erase and auto Program/

Erase algorithms.

The standard MX29F080 offers access time as fast as

70ns, allowing operation of high-speed microprocessors

without wait states. To eliminate bus contention, the

MX29F080 has separate chip enable (CE) and output

enable (OE ) controls.

The highest degree of latch-up protection is achieved

with MXIC's proprietary non-epi process. Latch-up pro-

tection is proved for stresses up to 100 milliamps on

address and data pin from -1V to VCC + 1V.

MXIC's Flash memories augment EPROM functionality

with in-circuit electrical erasure and programming. The

MX29F080 uses a command register to manage this

functionality. The command register allows for 100%

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1

MX29F080

LOGIC SYMBOL

PIN CONFIGURATIONS

40TSOP (StandardType) (10mm x 20mm)

20

8

A0-A19

1

NC

WE

OE

RY/BY

Q7

A19

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

Q0-Q7

2

A18

3

A17

4

A16

5

A15

6

A14

7

Q6

A13

8

Q5

A12

CE

9

Q4

CE

10

VCC

VSS

Q3

VCC

MX29F080

OE

11

NC

12

RESET

13

WE

A11

14

Q2

A10

RY/BY

15

A9

16

A8

17

A7

18

A6

19

A5

20

A4

Q1

RESET

Q0

A0

A1

A2

A3

44 SOP

PIN DESCRIPTION

VCC

CE

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

NC

RESET

A11

A10

A9

SYMBOL

A0~A19

Q0~Q7

CE

PIN NAME

Address Input

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

A12

A13

A14

A15

A16

A17

A18

A19

NC

WE

OE

8 Data Inputs/Outputs

Chip Enable Input

A8

A7

A6

A5

WE

Write Enable Input

A4

OE

Output Enable Input

NC

A3

A2

A1

A0

Q0

Q1

Q2

RESET

RY/BY

VCC

Hardware Reset Pin, Active Low

Read/Busy Output

+5.0V single power supply

Device Ground

RY/BY

Q7

Q6

Q5

Q4

VSS

NC

Pin Not Connected Internally

Q3

VSS

VCC

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REV. 1.6, NOV. 21, 2002

2

MX29F080

SECTOR STRUCTURE

MX29F080 SECTOR ADDRESSTABLE

Sector Group

SGA0

SGA1

SGA2

SGA3

SGA4

SGA5

SGA6

SGA7

Sector

SA0

A19

0

A18

0

A17

0

A16

0

Address Range

000000h-00FFFFh

010000h-01FFFFh

020000h-02FFFFh

030000h-03FFFFh

040000h-04FFFFh

050000h-05FFFFh

060000h-06FFFFh

070000h-07FFFFh

080000h-08FFFFh

090000h-09FFFFh

0A0000h-0AFFFFh

0B0000h-0BFFFFh

0C0000h-0CFFFFh

0D0000h-0DFFFFh

0E0000h-0EFFFFh

0F0000h-0FFFFFh

SA1

0

1

SA2

0

1

0

SA3

0

1

SA4

0

1

0

SA5

0

1

0

1

SA6

0

1

0

SA7

0

1

SA8

1

0

SA9

1

0

1

SA10

SA11

SA12

SA13

SA14

SA15

1

0

1

0

1

0

1

0

1

0

1

0

1

Legend:SA=Sector Address ; SGA=Sector Group Address

Note:All sectors are 64 Kbytes in size.

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REV. 1.6, NOV. 21, 2002

3

MX29F080

BLOCK DIAGRAM

WRITE

STATE

CONTROL

INPUT

PROGRAM/ERASE

HIGH VOLTAGE

CE

OE

WE

MACHINE

(WSM)

LOGIC

STATE

MX29F080

FLASH

ADDRESS

LATCH

REGISTER

ARRAY

A0-A19

AND

SOURCE

HV

BUFFER

Y-PASS GATE

COMMAND

DATA

DECODER

PGM

SENSE

DATA

HV

AMPLIFIER

COMMAND

DATA LATCH

PROGRAM

DATA LATCH

Q0-Q7

I/O BUFFER

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REV. 1.6, NOV. 21, 2002

4

MX29F080

AUTOMATIC PROGRAMMING

AUTOMATIC ERASE ALGORITHM

The MX29F080 is byte programmable using the Auto-

matic Programming algorithm. The Automatic Program-

ming algorithm makes the external system do not need

to have time out sequence nor to verify the data pro-

grammed. The typical chip programming time at room

temperature of the MX29F080 is less than 8 seconds.

MXIC's Automatic Erase algorithm requires the user to

write commands to the command register using stand-

ard microprocessor write timings. The device will auto-

matically pre-program and verify the entire array. Then

the device automatically times the erase pulse width,

provides the erase verification, and counts the number

of sequences. A status bit toggling between consecu-

tive read cycles provides feedback to the user as to the

status of the programming operation.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses

according to MXIC's Automatic Chip Erase algorithm.

Typical erasure at room temperature is accomplished in

less than 8 seconds. The Automatic Erase algorithm

automatically programs the entire array prior to electri-

cal erase. The timing and verification of electrical erase

are controlled internally within the device.

Register contents serve as inputs to an internal state-

machine which controls the erase and programming cir-

cuitry. During write cycles, the command register inter-

nally latches address and data needed for the program-

ming and erase operations. During a system write cycle,

addresses are latched on the falling edge, and data are

latched on the rising edge of WE or CE, whichever hap-

pens first .

MXIC's Flash technology combines years of EPROM

experience to produce the highest levels of quality, re-

liability, and cost effectiveness.The MX29F080 electri-

cally erases all bits simultaneously using Fowler-Nord-

heim tunneling. The bytes are programmed by using

the EPROM programming mechanism of hot electron

injection.

AUTOMATIC SECTOR ERASE

The MX29F080 is sector(s) erasable using MXIC's

Auto Sector Erase algorithm. Sector erase modes

allow sectors of the array to be erased in one erase

cycle. The Automatic Sector Erase algorithm

automatically programs the specified sector(s) prior to

electrical erase. The timing and verification of

electrical erase are controlled internally within the

device.

During a program cycle, the state-machine will control

the program sequences and command register will not

respond to any command set. During a Sector Erase

cycle, the command register will only respond to Erase

Suspend command. After Erase Suspend is completed,

the device stays in read mode. After the state machine

has completed its task, it will allow the command regis-

ter to respond to its full command set.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm require the

user to only write program set-up commands (including

2 unlock write cycle and A0H) and a program command

(program data and address). The device automatically

times the programming pulse width, provides the pro-

gram verification, and counts the number of sequences.

A status bit similar to DATA polling and a status bit tog-

gling between consecutive read cycles, provide feed-

back to the user as to the status of the programming

operation.

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5

MX29F080

TABLE 1. SOFTWARE COMMAND DEFINITIONS

First Bus

Cycle

Second Bus Third Bus

Cycle Cycle

Fourth Bus

Cycle

Fifth Bus

Cycle

Sixth Bus

Cycle

Command

Bus

Cycle Addr

Data Addr Data Addr Data Addr

XXXH F0H

RA RD

555H AAH 2AAH 55H 555H 90H ADI

Data Addr Data Addr Data

Reset

1

4

Read

Read Silicon ID

Sector Group

Protect Verify

Program

DDI

555H AAH 2AAH 55H 555H 90H SGAx02 00H

01H

4

6

1

555H AAH 2AAH 55H 555H A0H PA

555H AAH 2AAH 55H 555H 80H 555H

XXXH B0H

PD

Chip Erase

AAH 2AAH 55H 555H 10H

Sector Erase

Sector Erase Suspend

Sector Erase Resume

AAH 2AAH 55H SA

30H

XXXH 30H

Note:

1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code. A2-A19=do

not care. (Refer to Table 3)

DDI = Data of Device identifier : C2H for manufacture code, D5H for device code.

X = X can be VIL or VIH

RA=Address of memory location to be read.

RD=Data to be read at location RA.

2. PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA.

SA = Address of the sector to be erased. Address A16-A19 select a unique sector.

SGA=Address of the sector group. Address A17~A19 select a unique sector group.

3. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 .

Address bit A11~A19=X=Don't care for all address commands except for Program Address (PA) and Sector

Address (SA). Write Sequence may be initiated with A11~A19 in either state.

4. For Sector Group ProtectVerify Operation :If read out data is 01H, it means the sector has been protected.If read

out data is 00H, it means the sector is still not being protected.

COMMAND DEFINITIONS

Device operations are selected by writing specific ad-

dress and data sequences into the command register.

Writing incorrect address and data values or writing them

in the improper sequence will reset the device to the

read mode. Table 1 defines the valid register command

sequences. Note that the Erase Suspend (B0H) and

Erase Resume (30H) commands are valid only while the

Sector Erase operation is in progress. Either of the two

reset command sequences will reset the device(when

applicable).

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6

MX29F080

TABLE 2. MX29F080 BUS OPERATION

Pins

Mode

CE

OE

WE

A0

A1

A6

A9

Q0 ~ Q7

Read Silicon ID

ManufacturerCode(1)

Read Silicon ID

DeviceCode(1)

Read

L

H

L

X

V_ID(2)

C2H

L

H

L

X

V_ID(2)

D5H

L

H

L

X

L

H

X

H

L

A0

X

A1

X

A6

X

A9

D_OUT

Standby

X

HIGH Z

D_IN(3)

X

OutputDisable

Write

H

X

H

A0

X

A1

X

A6

L

A9

Sector Group Protect (6)

ChipUnprotect(6)

Verify Sector Protect

Reset

V_ID(2)

L

V_ID(2)

X

L

X

H

X

H

X

H

Code(5)

HIGH Z

X

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 13V.

3. Refer toTable 1 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H means unprotected.

Code=01H means protected.

6. A19~A17=Sector group address for sector group protect.

Refer to sector group protect/chip unprotect algorithm and waveform.

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7

MX29F080

SET-UP AUTOMATIC CHIP/SECTOR ERASE

READ/RESET COMMAND

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

"set-up" command 80H. Two more "unlock" write cycles

are then followed by the chip erase command 10H.

The read or reset operation is initiated by writing the

read/reset command sequence into the command reg-

ister. Microprocessor read cycles retrieve array data.

The device remains enabled for reads until the command

register contents are altered.

The Automatic Chip Erase does not require the device

to be entirely pre-programmed prior to executing the Au-

tomatic Chip Erase. Upon executing the Automatic Chip

Erase, the device will automatically program and verify

the entire memory for an all-zero data pattern. When the

device is automatically verified to contain an all-zero

pattern, a self-timed chip erase and verify begin. The

erase and verify operations are completed when the data

on Q7 is "1" at which time the device returns to the Read

mode. The system is not required to provide any control

or timing during these operations.

If program-fail or erase-fail happen, the write of F0H will

reset the device to abort the operation. A valid com-

mand must then be written to place the device in the

desired state.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications where

the local CPU alters memory contents. As such, manu-

facturer and device codes must be accessible while the

device resides in the target system. PROM program-

mers typically access signature codes by raising A9 to

a high voltage. However, multiplexing high voltage onto

address lines is not generally desired system design

practice.

When using the Automatic Chip Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

(no erase verification command is required).

If the Erase operation was unsuccessful, the data on Q5

is "1" (see Table 4), indicating the erase operation ex-

ceed internal timing limit.

The MX29F080 contains a Silicon-ID-Read operation to

supplement traditional PROM programming methodol-

ogy. The operation is initiated by writing the read silicon

ID command sequence into the command register. Fol-

lowing the command write, a read cycle with

A1=VIL,A0=VIL retrieves the manufacturer code of C2H.

A read cycle with A1=VIL, A0=VIH returns the device

code of D5H for MX29F080.

The automatic erase begins on the rising edge of the

lastWE pulse in the command sequence and terminates

when the data on Q7 is "1" and the data on Q6 stops

toggling for two consecutive read cycles, at which time

the device returns to the Read mode.

TABLE 3. EXPANDED SILICON ID CODE

Pins

A0

A1

Q7

1

Q6

1

Q5

0

Q4

0

Q3

0

Q2

0

Q1

1

Q0

0

Code(Hex)

C2H

Manufacturecode

VIL VIL

Device code for MX29F080 VIH VIL

1

0

1

0

1

0

1

D5H

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8

MX29F080

SECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the

device to be entirely pre-programmed prior to

executing the Automatic Set-up Sector Erase

command and Automatic Sector Erase command.

Upon executing the Automatic Sector Erase

command, the device will automatically program and

verify the sector(s) memory for an all-zero data

pattern. The system is not required to provide any

control or timing during these operations.

memory array (no erase verification command is

required). Sector erase is a six-bus cycle operation.

There are two "unlock" write cycles. These are

followed by writing the set-up command 80H. Two

more "unlock" write cycles are then followed by the

sector erase command 30H. The sector address is

latched on the falling edge of WE or CE, whichever

happens later , while the command (data) is latched

on the rising edge of WE or CE, whichever happens

first. Sector addresses selected are loaded into

internal register on the sixth falling edge of WE or CE,

whichever happens later. Each successive sector

load cycle started by the falling edge of WE or CE,

whichever happens later must begin within 80us from

the rising edge of the preceding WE or CE, whichever

happens first. Otherwise, the loading period ends and

internal auto sector erase cycle starts. (Monitor Q3

to determine if the sector erase timer window is still

open, see section Q3, Sector Erase Timer.) Any

command other than Sector Erase (30H) or Erase

Suspend (B0H) during the time-out period resets the

device to read mode.

When the sector(s) is automatically verified to

contain an all-zero pattern, a self-timed sector erase

and verify begin. The erase and verify operations

are complete when the data on Q7 is "1" and the data

on Q6 stops toggling for two consecutive read

cycles, at which time the device returns to the Read

mode. The system is not required to provide any

control or timing during these operations.

When using the Automatic Sector Erase algorithm,

note that the erase automatically terminates when

adequate erase margin has been achieved for the

TABLE 4. WRITE OPERATION STATUS

Status

Q7

0

Q6

Toggle

1

Q5

0

Q3

0

Q2

1

Byte Program in Auto Program Algorithm

Auto Erase Algorithm

0

1

Toggle

(Note1)

EraseSuspendRead

1

0

In Progress

(EraseSuspendedSector)

EraseSuspendedMode EraseSuspendRead

(Non-EraseSuspendedSector)

Data

Q7

Data

Data Data Data

EraseSuspendProgram

Toggle

(Note2)

Toggle

0

1

(Note3)

1

(Non-EraseSuspendedSector)

Byte Program in Auto Program Algorithm

Program/Erase in Auto Erase Algorithm

Q7

0

1

0

1

0

Exceeded

N/A

Time Limits EraseSuspendedMode EraseSuspendProgram

(Non-EraseSuspendedSector)

Q7

Notes:

1. Performing successive read operations from the erase-suspended sector will cause Q2 to toggle.

2. Performing successive read operations from any address will cause Q6 to toggle.

3. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1" at the

Q2 bit.

However, successive reads from the erase-suspended sector will cause Q2 to toggle.

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REV. 1.6, NOV. 21, 2002

9

MX29F080

vice will automatically provide an adequate internally gen-

erated program pulse and verify margin.

ERASE SUSPEND

This command only has meaning while the state ma-

chine is executing Automatic Sector Erase operation,

and therefore will only be responded during Automatic

Sector Erase operation. When the Erase Suspend com-

mand is written during a sector erase operation, the de-

vice requires a maximum of 100us to suspend the erase

operations.However,When the Erase Suspend command

is written during the sector erase time-out, the device

immediately terminates the time-out period and suspends

the erase operation. After this command has been ex-

ecuted, the command register will initiate erase suspend

mode. The state machine will return to read mode auto-

matically after suspend is ready. At this time, state ma-

chine only allows the command register to respond to

the Read Memory Array, Erase Resume and program

commands.

If the program operation was unsuccessful, the data on

Q5 is "1"(seeTable 4), indicating the program operation

exceed internal timing limit.The automatic programming

operation is completed when the data read on Q6 stops

toggling for two consecutive read cycles and the data

on Q7 and Q6 are equivalent to data written to these two

bits, at which time the device returns to the Read mode

(no program verify command is required).

DATA POLLING-Q7

The MX29F080 also features Data Polling as a method

to indicate to the host system that the Automatic Pro-

gram or Erase algorithms are either in progress or com-

pleted.

The system can determine the status of the program

operation using the Q7 or Q6 status bits, just as in the

standard program operation. After an erase-suspend pro-

gram operation is complete, the system can once again

read array data within non-suspended sector.

While the Automatic Programming algorithm is in opera-

tion, an attempt to read the device will produce the

complement data of the data last written to Q7. Upon

completion of the Automatic Program Algorithm an at-

tempt to read the device will produce the true data last

written to Q7. The Data Polling feature is valid after the

rising edge of the fourth WE or CE, whichever happens

first, of the four write pulse sequences for automatic

program.

ERASE RESUME

This command will cause the command register to clear

the suspend state and return back to Sector Erase mode

but only if an Erase Suspend command was previously

issued. Erase Resume will not have any effect in all

other conditions. Another Erase Suspend command can

be written after the chip has resumed erasing.

While the Automatic Erase algorithm is in operation, Q7

will read "0" until the erase operation is competed. Upon

completion of the erase operation, the data on Q7 will

read "1". The Data Polling feature is valid after the rising

edge of the sixth WE or CE, whichever happens first, of

six write pulse sequences for automatic chip/sector

erase.

SET-UP AUTOMATIC PROGRAM COMMANDS

To initiate Automatic Program mode, A three-cycle com-

mand sequence is required. There are two "unlock" write

cycles. These are followed by writing the Automatic Pro-

gram command A0H.

The Data Polling feature is active during Automatic Pro-

gram/Erase algorithm or sector erase time-out. (see sec-

tion Q3 Sector Erase Timer)

Once the Automatic Program command is initiated, the

nextWE pulse causes a transition to an active program-

ming operation. Addresses are latched on the falling

edge, and data are internally latched on the rising edge

of the WE or CE, whichever happens first pulse. The

rising edge of WE or CE, whichever happens first also

begins the programming operation. The system is not

required to provide further controls or timings. The de-

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10

MX29F080

pens first pulse in the command sequence.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Pro-

gram or Erase algorithm is in progress or complete, or

whether the device has entered the Erase Suspend mode.

Toggle Bit I may be read at any address, and is valid

after the rising edge of the final WE or CE, whichever

happens first pulse in the command sequence(prior to

the program or erase operation), and during the sector

time-out.

Q2 toggles when the system reads at addresses within

those sectors that have been selected for erasure. (The

system may use either OE or CE to control the read

cycles.) But Q2 cannot distinguish whether the sector

is actively erasing or is erase-suspended. Q6, by com-

parison, indicates whether the device is actively eras-

ing, or is in Erase Suspend, but cannot distinguish which

sectors are selected for erasure. Thus, both status bits

are required for sectors and mode information. Refer to

Table 4 to compare outputs for Q2 and Q6.

During an Automatic Program or Erase algorithm opera-

tion, successive read cycles to any address cause Q6

to toggle. The system may use either OE or CE to con-

trol the read cycles.When the operation is complete, Q6

stops toggling.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit

status, it must read Q7-Q0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, the

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has

completed the program or erase operation. The system

can read array data on Q7-Q0 on the following read cycle.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Q6 toggles and

returns to reading array data. If not all selected sectors

are protected, the Automatic Erase algorithm erases the

unprotected sectors, and ignores the selected sectors

that are protected.

The system can use Q6 and Q2 together to determine

whether a sector is actively erasing or is erase sus-

pended.When the device is actively erasing (that is, the

Automatic Erase algorithm is in progress), Q6 toggling.

When the device enters the Erase Suspend mode, Q6

stops toggling. However, the system must also use Q2

to determine which sectors are erasing or erase-sus-

pended. Alternatively, the system can use Q7.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of Q5 is high

(see the section on Q5). If it is, the system should then

determine again whether the toggle bit is toggling, since

the toggle bit may have stopped toggling just as Q5 went

high. If the toggle bit is no longer toggling, the device

has successfully completed the program or erase opera-

tion. If it is still toggling, the device did not complete the

operation successfully, and the system must write the

reset command to return to reading array data.

If a program address falls within a protected sector, Q6

toggles for approximately 2us after the program com-

mand sequence is written, then returns to reading array

data.

Q6 also toggles during the erase-suspend-program mode,

and stops toggling once the Automatic Program algo-

rithm is complete.

The remaining scenario is that system initially determines

that the toggle bit is toggling and Q5 has not gone high.

The system may continue to monitor the toggle bit and

Q5 through successive read cycles, determining the sta-

tus as described in the previous paragraph. Alternatively,

it may choose to perform other system tasks. In this

case, the system must start at the beginning of the al-

gorithm when it returns to determine the status of the

operation.

Table 4 shows the outputs for Toggle Bit I on Q6.

Q2:Toggle Bit II

The "Toggle Bit II" on Q2, when used with Q6, indicates

whether a particular sector is actively erasing (that is,

the Automatic Erase algorithm is in process), or whether

that sector is erase-suspended. Toggle Bit I is valid af-

ter the rising edge of the final WE or CE, whichever hap-

P/N:PM0579

REV. 1.6, NOV. 21, 2002

11

MX29F080

TEMPORARY SECTOR GROUP UNPROTECT

Q5

Exceeded Timing Limits

This feature allows temporary unprotection of previously

protected sector group to change data in-system. The

Temporary Sector group Unprotect mode is activated by

setting the RESET pin toVID(11.5V-12.5V). During this

mode, formerly protected sectors can be programmed or

erased as un-protected sector.OnceVID is remove from

the RESET pin, all the previously protected sector groups

are protected again.

Q5 will indicate if the program or erase time has exceeded

the specified limits (internal pulse count). Under these

conditions Q5 will produce a "1". This time-out condition

indicates that the program or erase cycle was not suc-

cessfully completed. Data Polling andToggle Bit are the

only operating functions of the device under this condi-

tion.

If this time-out condition occurs during sector erase op-

eration, it specifies that a particular sector is bad and it

may not be reused. However, other sectors are still func-

tional and may be used for the program or erase opera-

tion. The device must be reset to use other sectors.

Write the Reset command sequence to the device, and

then execute program or erase command sequence. This

allows the system to continue to use the other active

sectors in the device.

Q3

Sector Erase Timer

After the completion of the initial sector erase command

sequence, the sector erase time-out will begin. Q3 will

remain low until the time-out is complete. Data Polling

andToggle Bit are valid after the initial sector erase com-

mand sequence.

If Data Polling or theToggle Bit indicates the device has

been written with a valid erase command, Q3 may be

used to determine if the sector erase timer window is

still open. If Q3 is high ("1") the internally controlled

erase cycle has begun; attempts to write subsequent

commands to the device will be ignored until the erase

operation is completed as indicated by Data Polling or

Toggle Bit. If Q3 is low ("0"), the device will accept addi-

tional sector erase commands. To insure the command

has been accepted, the system software should check

the status of Q3 prior to and following each subsequent

sector erase command. If Q3 were high on the second

status check, the command may not have been accepted.

If this time-out condition occurs during the chip erase

operation, it specifies that the entire chip is bad or com-

bination of sectors are bad.

If this time-out condition occurs during the byte program-

ming operation, it specifies that the entire sector con-

taining that byte is bad and this sector maynot be re-

used, (other sectors are still functional and can be re-

used).

The time-out condition may also appear if a user tries to

program a non blank location without erasing. In this

case the device locks out and never completes the Au-

tomatic Algorithm operation. Hence, the system never

reads a valid data on Q7 bit and Q6 never stops toggling.

Once the Device has exceeded timing limits, the Q5 bit

will indicate a "1". Please note that this is not a device

failure condition since the device was incorrectly used.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns( typical) on CE or WE will

not initiate a write cycle.

DATA PROTECTION

The MX29F080 is designed to offer protection against

accidental erasure or programming caused by spurious

system level signals that may exist during power transi-

tion. During power up the device automatically resets

the state machine in the Read mode. In addition, with its

control register architecture, alteration of the memory

contents only occurs after successful completion of spe-

cific command sequences. The device also incorporates

several features to prevent inadvertent write cycles re-

sulting fromVCC power-up and power-down transition or

system noise.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE =VIL, CE =

VIH or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

P/N:PM0579

REV. 1.6, NOV. 21, 2002

12

MX29F080

It is also possible to determine if the chip is unprotected

in the system by writing the Read Silicon ID command.

Performing a read operation with A1=VIH, it will produce

00H at data outputs (Q0-Q7) for an unprotected sector.It

is noted that all sectors are unprotected after the chip

unprotect algorithm is completed.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device

should have a 0.1uF ceramic capacitor connected be-

tween itsVCC and GND.

SECTOR GROUP PROTECTION

POWER-UP SEQUENCE

The MX29F080 features hardware sector group protec-

tion. This feature will disable both program and erase

operations for these group sector protected. To activate

this mode, the programming equipment must force VID

on address pin A9 and control pin OE, (suggest VID =

12V) A6 = VIL and CE = VIL. (see Table 2) Program-

ming of the protection circuitry begins on the falling edge

of the WE or CE, whichever happens later pulse and is

terminated on the rising edge. Please refer to group sector

protect algorithm and waveform.

The MX29F080 powers up in the Read only mode. In

addition, the memory contents may only be altered after

successful completion of the predefined command se-

quences.

To verify programming of the protection circuitry, the pro-

gramming equipment must forceVID on address pin A9

( with CE and OE atVIL and WE at VIH). When A1=1, it

will produce a logical "1" code at device output Q0 for a

protected sector. Otherwise the device will produce 00H

for the unprotected sector. In this mode, the addresses,

except for A1, are don't care. Address locations with A1

=VIL are reserved to read manufacturer and device codes.

(Read Silicon ID)

It is also possible to determine if the group is protected

in the system by writing a Read Silicon ID command.

Performing a read operation with A1=VIH, it will produce

a logical "1" at Q0 for the protected sector.

CHIP UNPROTECT

The MX29F080 also features the chip unprotect mode,

so that all sectors are unprotected after chip unprotect

is completed to incorporate any changes in the code. It

is recommended to protect all sectors before activating

chip unprotect mode.

To activate this mode, the programming equipment must

forceVID on control pin OE and address pin A9. The CE

pins must be set at VIL. Pins A6 must be set to VIH.

(seeTable 2) Refer to chip unprotect algorithm and wave-

form for the chip unprotect algorithm. The unprotection

mechanism begins on the falling edge of the WE or CE,

whichever happens later pulse and is terminated on the

rising edge.

P/N:PM0579

REV. 1.6, NOV. 21, 2002

13

MX29F080

CAPACITANCE (TA = 25^oC, f = 1.0 MHz)

SYMBOL

CIN1

PARAMETER

MIN.

TYP

MAX.

8

UNIT

pF

CONDITIONS

VIN = 0V

Input Capacitance

Control Pin Capacitance

Output Capacitance

CIN2

12

pF

VIN = 0V

COUT

12

pF

VOUT = 0V

READ OPERATION

DC CHARACTERISTICS (TA = 0^°CTO 70^°C,VCC = 5V±10%)

SYMBOL PARAMETER

MIN.

TYP

MAX.

±1

1

UNIT

uA

mA

uA

mA

V

CONDITIONS

ILI

Input Leakage Current

VIN = GND to VCC

VOUT = GND to VCC

CE = VIH

ILO

Output Leakage Current

Standby VCC current

ISB1

ISB2

ICC1

ICC2

VIL

0.2

5

CE = VCC + 0.3V

IOUT = 0mA, f=1MHz

IOUT = 0mA, f=10MHz

Operating VCC current

30

50

0.8

Input Low Voltage

-0.3(NOTE 1)

2.0

VIH

Input High Voltage

VCC + 0.3

0.45

V

VOL

VOH1

VOH2

Output Low Voltage

Output High Voltage(TTL)

V

IOL = 2.1mA

IOH = -2mA

2.4

V

Output High Voltage(CMOS) VCC-0.4

V

IOH = -100uA,

VCC=VCC MIN

NOTES:

1. VIL min. = -1.0V for pulse width < 50 ns.

VIL min. = -2.0V for pulse width < 20 ns.

2. VIH max. = VCC + 1.5V for pulse width < 20 ns.

If VIH is over the specified maximum value, read operation

cannot be guaranteed.

AC CHARACTERISTICS (TA = 0^oC to 70^oC,VCC = 5V±10%)

29F080-70*

29F080-90

29F080-12

SYMBOL PARAMETER

MIN. MAX. MIN. MAX. MIN. MAX.

UNIT

ns

CONDITIONS

CE=OE=VIL

OE=VIL

tACC

tCE

tOE

tDF

Address to Output Delay

70

40

20

90

40

30

120

50

CE to Output Delay

ns

OE to Output Delay

ns

CE=VIL

OE High to Output Float (Note1)

Address to Output hold

0

30

ns

CE=VIL

tOH

ns

CE=OE=VIL

TEST CONDITIONS:

NOTE:

•

Input pulse levels: 0.45V/2.4V*

Input rise and fall times is equal to or less than 0ns

1. tDF is defined as the time at which the output achieves the

open circuit condition and data is no longer driven.

* For -70, the input levels : 0.0/3.0V, the output load : 1TTL

gate+30pF (including scope and jig)

Output load: 1 TTL gate + 100pF* (Including scope and jig)

Reference levels for measuring timing: 0.8V, 2.0V

P/N:PM0579

REV. 1.6, NOV. 21, 2002

14

MX29F080

ABSOLUTE MAXIMUM RATINGS

RATING

VALUE

NOTICE:

Ambient Operating Temperature 0^oC to 70^oC

Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is

a stress rating only and functional operational sections of this

specification is not implied. Exposure to absolute maximum rating

conditions for extended period may affect reliability.

Storage Temperature

Applied Input Voltage

Applied Output Voltage

VCC to Ground Potential

A9 & OE

-65^oC to 125^oC

-0.5V to 7.0V

-0.5V to 13.5V

NOTICE:

Specifications contained within the following tables are subject to

change.

READ TIMING WAVEFORMS

VIH

ADD Valid

Addresses

VIL

tCE

VIH

CE

VIL

VIH

WE

tDF

VIL

tOE

VIH

OE

tACC

VIL

tOH

HIGH Z

VOH

VOL

Outputs

DATA Valid

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION

DC CHARACTERISTICS (TA = 0^oC to 70^oC,VCC = 5V±10%)

SYMBOL

PARAMETER

MIN.

TYP

MAX.

30

UNIT

mA

CONDITIONS

ICC1 (Read)

ICC2

Operating VCC Current

IOUT=0mA, f=1MHz

IOUT=0mA, F=10MHz

In Programming

50

ICC3 (Program)

ICC4 (Erase)

ICCES

50

In Erase

VCC Erase Suspend Current

2

CE=VIH, Erase Suspended

NOTES:

1. VILmin.=-0.6Vforpulsewidthisequaltoorlessthan20ns.

2. If VIH is over the specified maximum value, programming

operation cannot be guranteed.

device is read during erase suspend mode, current draw

is the sum of ICCES and ICC1 or ICC2.

4. All current are in RMS unless otherwise noted.

3. ICCES is specified with the device de-selected. If the

P/N:PM0579

REV. 1.6, NOV. 21, 2002

15

MX29F080

AC CHARACTERISTICS TA = 0^oC to 70^oC, VCC = 5V ±10%

29F080-70

29F080-90

29F080-12

SYMBOL PARAMETER

MIN.

MAX.

MIN.

50

90

45

20

0

MAX.

MIN.

50

120

50

20

0

MAX. UNIT

tOES

tCWC

tCEP

tCEPH1

tCEPH2

tAS

OE setup time

50

70

35

20

0

ns

Command programming cycle

WE programming pulse width

WE programming pulse width High

Address setup time

tAH

Address hold time

45

30

0

45

0

50

0

tDS

Data setup time

tDH

Data hold time

tCESC

tDF

CE setup time before command write

Output disable time (Note 1)

Total erase time in auto chip erase

0

20

30

ns

s

tAETC

tAETB

tAVT

8(TYP.)

64

8(TYP.)

64

8(TYP.)

64

Total erase time in auto sector erase 1.3(TYP.)

Total programming time in auto verify 7(TYP.)

10.4

210

1.3(TYP.)

10.4

210

1(TYP.)

10.4

210

s

7(TYP.)

us

ns

us

ms

tBAL

Sector address load time

CE Hold Time

80

0

80

0

80

0

tCH

tCS

CE setup to WE going low

Voltge Transition Time

0

tVLHT

tOESP

tWPP1

tWPP2

4

OE Setup Time to WE Active

Write pulse width for sector protect

4

10

12

10

12

Write pulse width for sector unprotect 12

NOTES:

1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

P/N:PM0579

REV. 1.6, NOV. 21, 2002

16

MX29F080

SWITCHING TEST CIRCUITS

DEVICE UNDER

1.6K ohm

+5V

TEST

CL

1.2K ohm

DIODES=IN3064

OR EQUIVALENT

CL=30pF Including jig capacitance for -70 grade, CL=100pF for others

SWITCHING TEST WAVEFORMS

2.4V

2.0V

0.8V

2.0V

0.8V

TEST POINTS

0.45V

INPUT

OUTPUT

AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".

Input pulse rise and fall times are <20ns.

COMMAND WRITE TIMING WAVEFORM

VCC

5V

VIH

VIL

Addresses

ADD Valid

tAH

tAS

VIH

VIL

WE

CE

tOES

tCEPH1

tCEP

tCWC

VIH

VIL

tCS

tCH

tDH

VIH

VIL

OE

tDS

VIH

VIL

Data

DIN

P/N:PM0579

REV. 1.6, NOV. 21, 2002

17

MX29F080

AUTOMATIC PROGRAMMING TIMING WAVEFORM

bit checking after automatic verification starts. Device

outputs DATA during programming and DATA after pro-

gramming on Q7.(Q6 is for toggle bit; see toggle bit,

DATA polling, timing waveform)

One byte data is programmed. Verify in fast algorithm

and additional programming by external control are not

required because these operations are executed auto-

matically by internal control circuit. Programming

completion can be verified by DATA polling and toggle

Vcc 5V

A11~A19

ADD Valid

2AAH

555H

ADD Valid

tAVT

A0~A10

WE

555H

tAS

tCWC

tCEPH1

tAH

tCESC

CE

OE

tCEP

tDS tDH

tDF

Q0,Q1,

DATA

Command In

Data In

DATA polling

Q4(Note 1)

DATA

Command In

Q7

Command #A0H

Command #55H

Command #AAH

(Q0~Q7)

tOE

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

P/N:PM0579

REV. 1.6, NOV. 21, 2002

18

MX29F080

AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data A0H Address 555H

Write Program Data/Address

NO

Toggle Bit Checking

Q6 not Toggled

YES

NO

Invalid

Verify Byte Ok

Command

YES

NO

Q5 = 1

Reset

Auto Program Completed

YES

.

Auto Program Exceed

Timing Limit

P/N:PM0579

REV. 1.6, NOV. 21, 2002

19

MX29F080

AUTOMATIC CHIP ERASE TIMING WAVEFORM

All data in chip are erased. External erase verification is

not required because data is erased automatically by

internal control circuit. Erasure completion can be

verified by DATA polling and toggle bit checking after

automaticerasestarts. Deviceoutputs0duringerasure

and1aftererasureonQ7.(Q6isfortogglebit;seetoggle

bit, DATA polling, timing waveform)

AUTOMATIC CHIP ERASE TIMING WAVEFORM

Vcc 5V

A11~A19

2AAH

555H

2AAH

A0~A10

WE

555H

tAS

tCWC

tAH

tCEPH1

tAETC

CE

OE

tCEP

tDS tDH

Q0,Q1,

Command In

Q4(Note 1)

DATA polling

Command In

Q7

Command #80H

Command #AAH

Command #55H

Command #10H

Command #AAH

Command #55H

(Q0~Q7)

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

P/N:PM0579

REV. 1.6, NOV. 21, 2002

20

MX29F080

AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 10H Address 555H

NO

Toggle Bit Checking

Q6 not Toggled

YES

NO

Invalid

DATA Polling

Q7 = 1

Command

YES

.

NO

Q5 = 1

Auto Chip Erase Completed

YES

Reset

Auto Chip Erase Exceed

Timing Limit

P/N:PM0579

REV. 1.6, NOV. 21, 2002

21

MX29F080

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

BlockdataindicatedbyA16toA19 areerased. External

erase verify is not required because data are erased

automaticallybyinternalcontrolcircuit. Erasurecomple-

tion can be verified by DATA polling and toggle bit

checking after automatic erase starts. Device outputs 0

duringerasureand1aftererasureonQ7.(Q6isfortoggle

bit; see toggle bit, DATA polling, timing waveform)

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Vcc 5V

Sector

Addressn

Sector

Address0

Sector

Address1

A16-A19

555H

tAS

2AAH

A0~A10

tCWC

tAH

WE

CE

tCEPH1

tBAL

tAETB

tCEP

tDS

OE

tDH

Command

In

Command

In

Q0,Q1,

Command

In

Command

In

Command

In

Command

In

Q4(Note 1)

DATA polling

Command

In

Command

In

Command

In

Command

In

Command

In

Command

In

Command

In

Command

In

Q7

Command #AAH Command #55H Command #80H Command #AAH Command #55H Command #30H

(Q0~Q7)

Command #30H

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

P/N:PM0579

REV. 1.6, NOV. 21, 2002

22

MX29F080

AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 30H Sector Address

NO

Toggle Bit Checking

Invalid Command

Q6 Toggled ?

YES

Load Other Sector Addrss If Necessary

(Load Other Sector Address)

NO

Last Sector

to Erase

YES

NO

Time-out Bit

Checking Q3=1 ?

YES

Toggle Bit Checking

Q6 not Toggled

YES

.

Q5 = 1

Reset

DATA Polling

Q7 = 1

Auto Sector Erase Completed

Auto Sector Erase Exceed

Timing Limit

P/N:PM0579

REV. 1.6, NOV. 21, 2002

23

MX29F080

ERASE SUSPEND/ERASE RESUME FLOWCHART

START

Write Data B0H

NO

Toggle Bit checking Q6

not toggled

YES

Read Array or

Program

Reading or

NO

Programming End

YES

Write Data 30H

Continue Erase

.

Another

NO

Erase Suspend ?

YES

P/N:PM0579

REV. 1.6, NOV. 21, 2002

24

MX29F080

TIMING WAVEFORM FOR SECTOR GROUP PROTECTION

A1

A6

12V

5V

A9

tVLHT

Verify

12V

5V

OE

tVLHT

tWPP 1

WE

tOESP

CE

Data

01H

F0H

tOE

A19-A17

Sector Address

P/N:PM0579

REV. 1.6, NOV. 21, 2002

25

MX29F080

TIMING WAVEFORM FOR CHIP UNPROTECTION

A1

12V

5V

A9

tVLHT

A6

Verify

12V

5V

OE

tVLHT

tWPP 2

WE

tOESP

CE

Data

00H

F0H

tOE

A19-A17

Sector Address

P/N:PM0579

REV. 1.6, NOV. 21, 2002

26

MX29F080

SECTOR GROUP PROTECTION ALGORITHM

START

Set Up Sector Group Addr

(A19, A18, A17)

PLSCNT=1

OE=VID,A9=VID,CE=VIL

A6=VIL

Activate WE Pulse

Time Out 10us

Set WE=VIH, CE=OE=VIL

A9 should remain VID

Read from Sector Group

Addr=SGA, A1=1

No

.

No

Data=01H?

PLSCNT=32?

Yes

Device Failed

Yes

Protect Another

Sector Group?

Remove VID from A9

Write Reset Command

Sector Group Protection

Complete

P/N:PM0579

REV. 1.6, NOV. 21, 2002

27

MX29F080

CHIP UNPROTECTION ALGORITHM

START

Protect All Sectors

PLSCNT=1

Set OE=A9=VID

CE=VIL,A6=1

Activate WE Pulse

Time Out 12ms

Increment

PLSCNT

Set OE=CE=VIL

A9=VID,A1=1

Set Up First Sector Addr

Read Data from Device

No

Data=00H?

Yes

PLSCNT=1000?

Increment

Sector Addr

Yes

Device Failed

No

All sectors have

been verified?

Yes

Remove VID from A9

Write Reset Command

Chip Unprotect

Complete

* It is recommended before unprotect the whole chip, all sectors should be protected in advance.

P/N:PM0579

REV. 1.6, NOV. 21, 2002

28

MX29F080

AC CHARACTERISTICS

Parameter Std Description

Test Setup All Speed Options Unit

tREADY1

tREADY2

RESET PIN Low (During Automatic Algorithms)

MAX

MIN

20

us

to Read or Write (See Note)

RESET PIN Low (NOT During Automatic

Algorithms) to Read orWrite (See Note)

RESET Pulse Width (During Automatic Algorithms)

500

ns

tRP1

tRP2

tRH

10

500

0

us

ns

RESET Pulse Width (NOT During Automatic Algorithms) MIN

RESET HighTime Before Read (See Note)

RY/BY Recovery Time (to CE, OE go low)

RY/BY Recovery Time (to WE go low)

MIN

tRB1

tRB2

0

50

Note:Not 100% tested

RESET TIMING WAVEFORM

RY/BY

tRH

CE, OE

RESET

tRP2

tReady2

Reset Timing NOT during Automatic Algorithms

tReady1

RY/BY

CE, OE

WE

tRB1

tRB2

RESET

tRP1

Reset Timing during Automatic Algorithms

P/N:PM0579

REV. 1.6, NOV. 21, 2002

29

MX29F080

TEMPORARY SECTOR UNPROTECT

Parameter Std. Description

Test Setup All Speed Options Unit

tVIDR

tRSP

VID Rise and Fall Time (See Note)

RESET SetupTime forTemporary Sector Unprotect

Min

500

4

ns

us

Note:

Not 100% tested

TEMPORARY SECTOR GROUP UNPROTECT TIMING WAVEFORM

12V

RESET

0 or 5V

Program or Erase Command Sequence

tVIDR

CE

WE

tRSP

RY/BY

P/N:PM0579

REV. 1.6, NOV. 21, 2002

30

MX29F080

TEMPORARY SECTOR GROUP UNPROTECT ALGORITHM

Start

RESET = VID (Note 1)

Perform Erase or Program Operation

Operation Completed

RESET = VIH

Temporary Sector Group Unprotect Completed(Note 2)

Note :

1. All protected sectors are temporary unprotected.

VID=11.5V~12.5V

2. All previously protected sectors are protected again.

P/N:PM0579

REV. 1.6, NOV. 21, 2002

31

MX29F080

ID CODE READ TIMING WAVEFORM

VCC

5V

VID

ADD

VIH

A9

VIL

VIH

ADD

VIL

A0

tACC

VIH

A1

VIL

ADD

A2-A8

VIH

A10-A19 VIL

CE

VIH

VIL

tCE

VIH

VIL

WE

OE

tOE

VIH

VIL

tDF

tOH

VIH

VIL

DATA

Q0-Q7

DATA OUT

C2H

DATA OUT

D5H

P/N:PM0579

REV. 1.6, NOV. 21, 2002

32

MX29F080

ERASE AND PROGRAMMING PERFORMANCE (1)

LIMITS

PARAMETER

MIN.

TYP.(2)

MAX.

10.4

64

UNITS

sec

Sector Erase Time

Chip Erase Time

1.3

8

sec

Byte Programming Time

Chip Programming Time

Erase/Program Cycles

7

210

24

us

8

sec

10,000

Cycles

Note: 1. Not 100% Tested, Excludes external system level over head.

2.Typical values measured at 25°C,5V.

LATCH-UP CHARACTERISTICS

MIN.

-1.0V

MAX.

Input Voltage with respect to GND on all pins except I/O pins

Input Voltage with respect to GND on all I/O pins

Current

13.5V

Vcc + 1.0V

+100mA

-1.0V

-100mA

Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.

P/N:PM0579

REV. 1.6, NOV. 21, 2002

33

MX29F080

ORDERING INFORMATION

PLASTIC PACKAGE

PART NO.

ACCESS TIME

OPERATING CURRENT

STANDBY CURRENT PACKAGE

(ns)

MAX.(mA)

MAX. (uA)

MX29F080TC-70

MX29F080TC-90

MX29F080TC-12

70

50

5

40 Pin TSOP

(Normal Type)

40 Pin TSOP

(Normal Type)

40 Pin TSOP

(Normal Type)

44 Pin SOP

90

50

5

120

MX29F080MC-70 70

MX29F080MC-90 90

MX29F080MC-12 120

50

5

44 Pin SOP

P/N:PM0579

REV. 1.6, NOV. 21, 2002

34

MX29F080

PACKAGE INFORMATION

P/N:PM0579

REV. 1.6, NOV. 21, 2002

35

MX29F080

P/N:PM0579

REV. 1.6, NOV. 21, 2002

36

MX29F080

REVISION HISTORY

Revision

Description

Page

Date

1.1

Add erase suspend ready max. 100us in ERASE SUSPEND's P10

MAY/29/2000

section at page10

1.2

1.3

Modify Package Information 40-pinTSOP

To modify "Package Information"

Modify "Chip Unprotection Algorithm"

To modify Package Information--40-TSOP(10x20mm)

To corrected typing error

P35

P35~36

P28

P35

All

AUG/10/2000

JUN/18/2001

1.4

1.5

1.6

JAN/16/2002

JUN/10/2002

NOV/21/2002

To modify Package Information

P35~36

P/N:PM0579

REV. 1.6, NOV. 21, 2002

37

MX29F080

MACRONIX INTERNATIONAL CO., LTD.

HEADQUARTERS:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

EUROPE OFFICE:

TEL:+32-2-456-8020

FAX:+32-2-456-8021

JAPAN OFFICE:

TEL:+81-44-246-9100

FAX:+81-44-246-9105

SINGAPORE OFFICE:

TEL:+65-348-8385

FAX:+65-348-8096

TAIPEI OFFICE:

TEL:+886-2-2509-3300

FAX:+886-2-2509-2200

MACRONIX AMERICA, INC.

TEL:+1-408-453-8088

FAX:+1-408-453-8488

CHICAGO OFFICE:

TEL:+1-847-963-1900

FAX:+1-847-963-1909

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

38


型号：	29F080-90
厂家：	MACRONIX INTERNATIONAL
描述：	8M-BIT [1024K x 8] CMOS EQUAL SECTOR FLASH MEMORY 8M - BIT [ 1024K ×8 ] CMOS EQUAL部门FLASH MEMORY
文件：	总38页 (文件大小：664K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

29F080-90 [Macronix]

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