29F1610A-12_技术文档

PRELIMINARY

MX29F1610A

16M-BIT [2M x8/1M x16] CMOS

SINGLE VOLTAGE FLASH EEPROM

FEATURES

• Pageprogramoperation

• 5V ±10% write and erase

- Internal address and data latches for

128 bytes/64 words per page

- Page programming time: 0.9ms typical

- Byte programming time: 7us in average

• JEDEC-standard EEPROM commands

• Endurance:100,000 cycles

• Fast access time: 90/100/120ns

• Sector erase architecture

• Low power dissipation

- 30mA typical active current

- 1uA typical standby current

- 16 equal sectors of 128k bytes each

- Sector erase time: 1.3 s typical

• Auto Erase and Auto Program Algorithms

- Automatically erases any one of the sectors

or the whole chip with Erase Suspend capability

- Automatically programs and verifies data at

specified addresses

• Status Register feature for detection of

program or erase cycle completion

• CMOS and TTL compatible inputs and outputs

• Sector Protection

- Hardware method that can protect any combination

of sectors from write or erase operations.

• Deep Power-Down Input

- 1uA ICC typical

• Industry standard surface mount packaging

- 48 lead TSOP, TYPE I

• Low VCC write inhibit is equal to or less than 3.2V

• Software and hardware data protection

- 44 lead SOP

GENERAL DESCRIPTION

The MX29F1610A is a 16-mega bit Flash memory

organized as either 1M wordx16 or 2M bytex8. The

MX29F1610A includes 16-128KB(131,072) blocks or 16-

64KW(65,536) blocks. MXIC's Flash memories offer the

most cost-effective and reliable read/write non-volatile

random access memory. The MX29F1610A is packaged

in48-pinTSOPor44-pinSOP. For48-pinTSOP,CE2and

RY/BYareextrapinscomparedwith44-pinSOPpackage.

This is to optimize the products (such as solid-state disk

drives or flash memory cards) control pin budget. All the

above three pins(CE2,RY/BY and PWD) plus one extra

VCC pin are not provided in 44-pin SOP. It is designed to

be reprogrammed and erased in-system or in-standard

EPROMprogrammers.

functionality. Thecommandregisterallowsfor100%TTL

level control inputs and fixed power supply levels during

erase and programming, while maintaining maximum

EPROM compatibility.

To allow for simple in-system reprogrammability, the

MX29F1610A does not require high input voltages for

programming. Five-volt-only commands determine the

operation of the device. Reading data out of the device

is similar to reading from an EPROM.

MXIC Flash technology reliably stores memory contents

even after 100,000 cycles. The MXIC's cell is designed

to optimize the erase and programming mechanisms. In

addition, the combination of advanced tunnel oxide

processing and low internal electric fields for erase and

programming operations produces reliable cycling. The

MX29F1610Ausesa5V±10%VCCsupplytoperformthe

Auto Erase and Auto Program algorithms.

ThestandardMX29F1610Aoffersaccesstimesasfastas

90ns,allowing operation of high-speed microprocessors

without wait. To eliminate bus contention, the

MX29F1610A has separate chip enables(CE1 and CE2),

output enable (OE), and write enable (WE) controls.

The highest degree of latch-up protection is achieved

with MXIC's proprietary non-epi process. Latch-up

protection is proved for stresses up to 100 milliamps on

address and data pin from -1V to VCC +1V.

MXIC's Flash memories augment EPROM functionality

with in-circuit electrical erasure and programming. The

MX29F1610A uses a command register to manage this

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MX29F1610A

PIN CONFIGURATIONS

48 TSOP(TYPE I) (12mm x 20mm)

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

RY/BY

A16

A15

A14

A13

A12

A11

A10

A9

1

2

3

4

5

6

7

8

RY/BY

A16

A15

A14

A13

A12

A11

A10

A9

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

PWD

BYTE

GND

Q15/A-1

Q7

Q14

Q6

Q13

Q5

Q12

Q4

VCC

Q11

Q3

Q10

Q2

Q9

Q1

Q8

Q0

OE

GND

CE1

CE2

PWD

BYTE

GND

Q15/A-1

Q7

Q14

Q6

Q13

Q5

Q12

Q4

VCC

Q11

Q3

Q10

Q2

Q9

Q1

Q8

Q0

OE

GND

CE1

CE2

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

A8

A19

WP

WE

A18

A17

A7

A6

A5

A4

A3

A19

WP

WE

A18

A17

A7

A6

A5

A4

A3

MX29F1610A

A2

A1

A0

VCC

A2

A1

A0

VCC

(NORMAL TYPE)

(REVERSE TYPE)

PIN DESCRIPTION

44 SOP(500mil)

SYMBOL

A0 - A19

Q0 - Q14

Q15/A - 1

CE1/CE2

PWD

PIN NAME

WP

A19

A8

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

WE

A18

A17

A7

A6

A5

A4

A3

A2

A1

Address Input

Data Input/Output

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

A9

A10

A11

A12

A13

A14

A15

A16

BYTE

GND

Q15/A-1

Q7

Q14

Q6

Q13

Q5

Q12

Q4

VCC

Q15(Word mode)/LSB addr.(Byte mode)

Chip Enable Input

Deep Power- Down Input

Output Enable Input

Write Enable Input

A0

OE

CE1

GND

OE

Q0

Q8

Q1

Q9

Q2

Q10

Q3

Q11

WE

RY/BY

WP

Ready/Busy Output

Sector Write Protect Input

Word/Byte Selection Input

Power Supply

BYTE

VCC

GND

Ground Pin

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MX29F1610A

BLOCK DIAGRAM

WE

WRITE

CONTROL

PROGRAM/ERASE

HIGH VOLTAGE

CE1/CE2

OE

STATE

RY/BY

MACHINE

INPUT

LOGIC

WP

(WSM)

PWD

BYTE

COMMAND INTERFACE

REGISTER

MX29F1610A

FLASH

(CIR)

ADDRESS

LATCH

ARRAY

Q15/A-1

A0-A19

SOURCE

HV

AND

COMMAND

DATA

BUFFER

Y-PASS GATE

DECODER

PGM

SENSE

DATA

COMMAND

AMPLIFIER

HV

DATA LATCH

PAGE

PROGRAM

DATA LATCH

Q0-Q15/A-1

I/O BUFFER

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MX29F1610A

Table1.PIN DESCRIPTIONS

SYMBOL

TYPE

NAME AND FUNCTION

A0 - A19

INPUT

ADDRESS INPUTS: for memory addresses. Addresses are internally latched

during a write cycle.

Q0 - Q7

INPUT/OUTPUT LOW-BYTE DATA BUS: Input data and commands during Command Interface

Register(CIR) write cycles. Outputs array,status and identifier data in the

appropriate read mode. Floated when the chip is de-selected or the outputs are

disabled.

Q8 - Q14

INPUT/OUTPUT HIGH-BYTEDATABUS:Inputsdataduringx16Data-Writeoperations. Outputs

array, identifier data in the appropriate read mode; not used for status register

reads. Floated when the chip is de-selected or the outputs are disabled

INPUT/OUTPUT Selects between high-byte data INPUT/OUTPUT(BYTE = HIGH) and LSB

ADDRESS(BYTE = LOW)

.Q15/A -1

CE1/CE2

INPUT

CHIP ENABLE INPUTS: Activate the device's control logic, Input buffers,

decoders and sense amplifiers. With either CE1 or CE2 high, the device is de-

selected and power consumption reduces to Standby level upon completion of

any current program or erase operations. Both CE1,CE2 must be low to

select the device. CE2 is not provided in 44-pin SOP package.

All timing specifications are the same for both signals. Device selection occurs

with the latter falling edge of CE1 or CE2. The first rising edge of CE1 or CE2

disables the device.

PWD

INPUT

POWER-DOWN:Putsthedeviceindeeppower-downmode. PWDisactivelow;

PWD high gates normal operation. PWD also locks out erase or program

operation when active low providing data protection during power transitions.

OUTPUT ENABLES: Gates the device's data through the output buffers during

a read cycle OE is active low.

OE

INPUT

WE

WRITE ENABLE: Controls writes to the Command Interface Register(CIR).

WE is active low.

RY/BY

OPEN DRAIN

OUTPUT

READY/BUSY: Indicates the status of the internal Write State Machine(WSM).

When low it indicates that the WSM is performing a erase or program operation.

RY/BY high indicate that the WSM is ready for new commands, sector erase is

suspended or the device is in deep power-down mode. RY/BY is always active

and does not float to tristate off when the chip is deselected or data output are

disabled.

WP

INPUT

WRITEPROTECT:Allsectorscanbeprotectedbywritinganon-volatileprotect-

bit for each sector. When WP is low, all prottect-bits status can not be changed,

i.e., the user can not execute Sector Protection and Sector Unprotect. The WP

input buffer is disabled when PWD transitions low(deep power-down mode).

BYTE ENABLE: BYTE Low places device in x8 mode. All data is then input or

output on Q0-7 and Q8-14 float. AddressQ15/A-1 selects between the high

and low byte. BYTE high places the device in x16 mode, and turns off the Q15/

A-1 input buffer. Address A0, then becomes the lowest order address.

DEVICE POWER SUPPLY(5V±10%)

BYTE

VCC

GND

GROUND

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MX29F1610A

BUS OPERATION

Flash memory reads,erasesandwritesin-systemviathelocalCPU. Allbuscyclestoorfromthe flash memoryconform

to standard microprocessor bus cycles.

Table 2.1 Bus Operations for Word-Wide Mode (BYTE = VIH)

Mode

Notes PWD CE1 CE2 OE WE A0 A1 A9

Q0-Q7

DOUT

HighZ

Q8-Q14

DOUT

HighZ

Q15/A-1 RY/BY

Read

1,2,7

1,6,7

VIH

VIL VIL VIL

VIH

X

DOUT

HighZ

X

OutputDisable

Standby

VIL VIL VIH VIH

VIL VIH

VIH VIL

X

HIghZ

VIH VIH

DeepPower-Down

ManufacturerID

1,3

4,8

VIL

VIH

X

HighZ

C2H

HighZ

00H

HighZ

0B

VOH

X

VIL VIL VIL

VIL VIL VIH

VIH VIL VIL VID

DeviceID

MX29F1610A

Write

4,8

VIH VIH VIL VID FAH/FBH

VIL DIN

00H

DIN

0B

1,5,6

X

DIN

Table2.2 Bus Operations for Byte-Wide Mode (BYTE = VIL)

Mode

Notes PWD CE1 CE2 OE WE A0 A1 A9

Q0-Q7

DOUT

HighZ

Q8-Q14

HighZ

Q15/A-1 RY/BY

Read

1,2,7,9 VIH

VIL VIL VIL

VIH

X

VIL/VIH

X

OutputDisable

Standby

1,6,7

VIH

VIL VIL VIH VIH

HIghZ

HighZ

X

VIL VIH

VIH VIL

X

VIH VIH

DeepPower-Down

ManufacturerID

1,3

4,8

VIL

VIH

X

HighZ

C2H

HIghZ

HighZ

HIghZ

X

VIL

VOH

X

VIL VIL VIL

VIL VIL VIH

VIH VIL VIL VID

DeviceID

MX29F1610A

Write

4,8

VIH VIH VIL VID FAH/FBH

VIL DIN

VIL

1,5,6

X

VIL/VIH

NOTES :

1.X can be VIH or VIL for address or control pins except for RY/BY which is either VOL or VOH.

2.RY/BY output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode, RY/BY will be at VOH

if it is tied to VCC through a 1K ~ 100K resistor. When the RY/BY at VOH is independent of OE while a WSM operation is in progress.

3.PWD at GND ± 0.2V ensures the lowest deep power-down current.

4. A0 and A1 at VIL provide manufacturer ID codes. A0 at VIH and A1 at VIL provide device ID codes. A0 at VIL, A1 at VIH and with appropriate

sector addresses provide Sector Protect Code.(Refer to Table 4)

5. Commands for different Erase operations, Data program operations or Sector Protect operations can only be successfully completed through

proper command sequence.

6.While the WSM is running. RY/BY in Level-Mode stays at VOL until all operations are complete. RY/BY goes to VOH when the WSM is not

busy or in erase suspend mode.

7. RY/BY may be at VOL while the WSM is busy performing various operations. For example, a status register read during a write operation.

8. VID = 11.5V- 12.5V.

9. Q15/A-1 = VIL, Q0 - Q7 =D0-D7 out . Q15/A-1 = VIH, Q0 - Q7 = D8 -D15 out.

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MX29F1610A

WRITE OPERATIONS

will only respond to status reads. During a sector/chip

erase cycle, the CIR will respond to status reads and

erase suspend. After the write state machine has

completeditstask, itwillallowtheCIRtorespondtoitsfull

command set. The CIR stays at read status register

mode until the microprocessor issues another valid

command sequence.

Commands are written to the COMMAND INTERFACE

REGISTER (CIR) using standard microprocessor write

timings. The CIR serves as the interface between the

microprocessor and the internal chip operation. The CIR

can decipher Read Array, Read Silicon ID, Erase and

Program command. In the event of a read command, the

CIR simply points the read path at either the array or the

silicon ID, depending on the specific read command

given. For a program or erase cycle, the CIR informs the

write state machine that a program or erase has been

requested. During a program cycle, the write state

machine will control the program sequences and the CIR

Device operations are selected by writing commands into

the CIR. Table 3 below defines 16 Mbit flash family

command.

TABLE 3. COMMAND DEFINITIONS

Command

Sequence

Read/

Reset

Silicon Page/Byte Chip

Sector

Erase

Read

Clear

ID Read Program

Erase

Erase Suspend Resume Status Reg. Status Reg.

Bus Write

4

6

1

4

3

Cycles Req'd

First Bus

Write Cycle

Addr

Data

5555H

AAH

5555H

AAH

5555H

AAH

5555H

AAH

5555H

AAH

XXXX

B0H

XXXX

D0H

5555H

AAH

5555H

AAH

Second Bus

Write Cycle

Addr

Data

2AAAH

55H

2AAAH 2AAAH 2AAAH

2AAAH

55H

2AAAH

55H

2AAAH

55H

Third Bus

Write Cycle

Addr

Data

5555H

F0H

5555H

90H

5555H

A0H

5555H

80H

5555H

80H

5555H

70H

5555H

50H

Fourth Bus

Read/Write Cycle Data

Addr

RA

RD

00H/01H

C2H/FAH

(FBH)

PA

PD

5555H

AAH

5555H

AAH

X

SRD

Fifth Bus

Write Cycle

Addr

Data

2AAAH

55H

2AAAH

55H

Sixth Bus

Write Cycle

Addr

Data

5555H

10H

SA

30H

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MX29F1610A

COMMAND DEFINITIONS(continue Table 3.)

Command

Sequence

Sector

Protection Unprotect

.

Sector

Verify Sector

Protect

Bus Write

6

4

Cycles Req'd

First Bus

Write Cycle

Addr

Data

5555H

AAH

5555H

AAH

5555H

AAH

Second Bus

Write Cycle

Addr

Data

2AAAH

55H

2AAAH

55H

2AAAH

55H

Third Bus

Write Cycle

Addr

Data

5555H

60H

5555H

60H

5555H

90H

Fourth Bus

Read/Write Cycle Data

Addr

5555H

AAH

5555H

AAH

*

C2H*

Fifth Bus

Write Cycle

Addr

Data

2AAAH

55H

2AAAH

55H

Sixth Bus

Write Cycle

Addr

Data

SA**

20H

SA**

40H

Notes:

1. Address bit A15 -- A19 = X = Don't care for all address commands except for Program Address(PA) and Sector

Address(SA).

5555H and 2AAAH address command codes stand for Hex number starting from A0 to A14.

2. Bus operations are defined in Table 2.

3. RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.

SA = Address of the sector to be erased. The combination of A16 -- A19 will uniquely select any sector.

4. RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.

SRD = Data read from status register.

5. Only Q0-Q7 command data is taken, Q8-Q15 = Don't care.

* Refer to Table 4, Figure 12.

6. The details of sector protection/unprotect algorithm are shown in Fig.10 and Fig.11.

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MX29F1610A

DEVICE OPERATION

SILICON ID READ

TheSiliconIDReadmodeallowsthereadingoutofabinary

codefromthedeviceandwillidentifyitsmanufacturerand

type. This mode is intended for use by programming

equipment for the purpose of automatically matching the

device to be programmed with its corresponding

programming algorithm. This mode is functional over the

entire temperature range of the device.

The manufacturer and device codes may also be read via

the command register, for instances when the

MX29F1610A is erased or programmed in a system

without access to high voltage on the A9 pin. The

command sequence is illustrated in Table 3.

Byte 0 (A0=VIL) represents the manfacturer's code

(MXIC=C2H) and byte 1 (A0=VIH) the device identifier

code(MX29F1610A=FAH).

To activate this mode, the programming equipment must

force VID (11.5V~12.5V) on address pin A9. Two

identifier bytes may then be sequenced from the device

outputs by toggling address A0 from VIL to VIH. All

addresses are don't cares except A0 and A1.

The Silicon ID Read mode will be terminated after the

following write command cycle.

Table 4. MX29F1610 Silion ID Codes and Verify Sector Protect Code

Type

A₁₉A₁₈A₁₇A₁₆A₁A₀Code(HEX) DQ₇DQ₆DQ₅DQ₄DQ₃DQ₂DQ₁DQ₀

Manufacturer Code

X

VIL VIL

VIL VIH

VIH VIL

C2H*

FAH

1

0

1

0

1

0

1

0

1

0

0/1

0

MX29F1610A Device Code X

Verify Sector Protect

Sector Address***

C2H**

* MX29F1610A Manufacturer Code = C2H, Device Code = FAH when BYTE = VIL

MX29F1610A Manufacturer Code = 00C2H, Device Code = 00FAH when BYTE = VIH

** Outputs C2H at protected sector address, 00H at unprotected scetor address.

***All sectors have protect-bit feature. Sector address = (A19, A18,A17,A16)

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MX29F1610A

READ/RESET COMMAND

BYTE-WIDE LOAD/WORD-WIDE LOAD

Thereadorresetoperationisinitiatedbywriting theread/

reset command sequence into the command register.

Microprocessor read cycles retrieve array data from the

memory. The device remains enabled for reads until the

CIR contents are altered by a valid command sequence.

Byte(word) loads are used to enter the 128 bytes(64

words)ofapagetobeprogrammedorthesoftwarecodes

for data protection. A byte load(word load) is performed

by applying a low pulse on the WE or CE input with CE or

WE low (respectively) and OE high. The address is

latchedonthefallingedgeofCEorWE,whicheveroccurs

last. The data is latched by the first rising edge of CE or

WE.

The device will automatically power-up in the read/reset

state. In this case, a command sequence is not required

to read data. Standard microprocessor read cycles will

retrieve array data. This default value ensures that no

spurious alteration of the memory content occurs during

the power transition. Refer to the AC Read

Characteristics and Waveforms for the specific timing

parameters.

Either byte-wide load or word-wide load is

determined(Byte = VIL or VIH is latched) on the falling

edge of the WE(or CE) during the 3rd command write

cycle.

TheMX29F1610AisaccessedlikeanEPROM. WhenCE

and OE are low and WE is high the data stored at the

memory location determined by the address pins is

asserted on the outputs. The outputs are put in the high

impedance state whenever CE or OE is high. This dual

line control gives designers flexibility in preventing bus

contention.

PROGRAM

Any page to be programmed should have the page in the

erased state first, i.e. performing sector erase is

suggested before page programming can be performed.

The device is programmed on a page basis. If a

byte(word)ofdatawithinapageistobechanged,datafor

the entire page can be loaded into the device. Any

byte(word) that is not loaded during the programming of

its page will be still in the erased state (i.e. FFH). Once

the bytes of a page are loaded into the device, they are

simultaneously programmed during the internal

programming period. After the first data byte(word) has

been loaded into the device, successive bytes(words)

are entered in the same manner. The time between byte

(word) loads must be less than 30us otherwise the load

period could be teminated. A6 to A19 specify the page

address, i.e., the device is page-aligned on 128 bytes(64

words)boundary. Thepageaddressmustbevalidduring

eachhightolowtransitionofWEorCE.A-1 toA5specify

the byte address within the page, A0 to A5 specify the

word address withih the page. The byte(word) may be

loaded in any order; sequential loading is not required. If

ahightolowtransitionofCEorWEisnotdetectedwhithin

100us of the last low to high transition, the load period will

end and the internal programming period will start. The

Auto page program terminates when status on DQ7 is '1'

at which time the device stays at read status register

mode until the CIR contents are altered by a valid

commandsequence.(Refertotable3,6andFigure1,7,8)

CE stands for the combination of CE1 and CE2 in

MX29F1610A 48-pin TSOP package. CE and stands for

CE in 44-pin SOP package.

Note that the read/reset command is not valid when

program or erase is in progress.

PAGE PROGRAM

To initiate Page program mode, a three-cycle command

sequence is required. There are two " unlock" write

cycles. These are followed by writing the page program

command-A0H.

Any attempt to write to the device without the three-cycle

command sequence will not start the internal Write State

Machine(WSM), no data will be written to the device.

After three-cycle command sequence is given, a

byte(word) load is performed by applying a low pulse on

the WE or CE input with CE or WE low (respectively) and

OE high. The address is latched on the falling edge of CE

or WE, whichever occurs last. The data is latched by the

first rising edge of CE or WE. Maximum of 128 bytes of

data may be loaded into each page by the same

procedureasoutlinedinthepageprogramsectionbelow.

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MX29F1610A

Sector erase does not require the user to program the

device prior to erase. The system is not required to

provide any controls or timings during these operations.

CHIP ERASE

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

"set-up" command-80H. Two more "unlock" write cycles

are then followed by the chip erase command-10H.

The automatic sector erase begins on the rising edge of

the last WE pulse in the command sequence and

terminates when the status on DQ7 is "1" at which time

thedevicestaysatreadstatusregistermode. Thedevice

remains enabled for read status register mode until the

CIR contents are altered by a valid command

sequence.(Refer to table 3,6 and Figure 3,4,7,9))

Chip erase does not require the user to program the

device prior to erase.

The automatic erase begins on the rising edge of the last

WE pulse in the command sequence and terminates

when the status on DQ7 is "1" at which time the device

stays at read status register mode. The device remains

enabled for read status register mode until the CIR

ERASE SUSPEND

contents are altered by

a

valid command

sequence.(Refer to table 3,6 and Figure 2,7,9)

This command only has meaning while the the WSM is

executing SECTOR erase operation, and therefore will

only be responded to during SECTOR erase operation.

After this command has been executed, the CIR will

initiate the WSM to suspend erase operations, and then

return to Read Status Register mode. The WSM will set

the DQ6 bit to a "1". Once the WSM has reached the

Suspend state,the WSM will set the DQ7 bit to a "1", At

this time, WSM allows the CIR to respond to the Read

Array, Read Status Register and Erase Resume

commands only. In this mode, the CIR will not resopnd to

any other comands. The WSM will continue to run, idling

in the SUSPEND state, regardless of the state of all input

control pins, with the exclusion of PWD. PWD low will

immediatelyshutdowntheWSMandtheremainderofthe

chip.

Table 5. MX29F1610 Sector Address Table

(Byte-Wide Mode)

A19 A18 A17 A16 Address Range[A19, -1]

SA0

SA1

SA2

SA3

SA4

0

1

000000H--01FFFFH

020000H--03FFFFH

040000H--05FFFFH

060000H--07FFFFH

080000H--09FFFFH

................

0

1

0

1

0

1

0

...

1

....

1

...

1

...

1

ERASE RESUME

SA15

1E0000H--1FFFFFH

This command will cause the CIR to clear the suspend

stateandsettheDQ6toa'0',butonly ifanEraseSuspend

command was previously issued. Erase Resume will not

have any effect in all other conditions.

SECTOR ERASE

Sector erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

set-up command-80H. Two more "unlock" write cycles

are then followed by the sector erase command-30H.

The sector address is latched on the falling edge of WE,

while the command (data) is latched on the rising edge of

WE.

REV.1.7, JUN. 15, 2001

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MX29F1610A

CLEAR STATUS REGISTER

READ STATUS REGISTER

The MXIC's16Mbitflashfamilycontainsastatusregister

whichmaybereadtodeterminewhenaprogramorerase

operation is complete, and whether that operation

completed successfully. The status register may be read

at any time by writing the Read Status command to the

CIR. After writing this command, all subsequent read

operations output data from the status register until

another valid command sequence is written to the CIR.

A Read Array command must be written to the CIR to

return to the Read Array mode.

The Eraes fail status bit (DQ5) and Program fail status bit

(DQ4) are set by the write state machine, and can only be

reset by the system software. These bits can indicate

various failure conditions(see Table 6). By allowing the

system software to control the resetting of these bits,

several operations may be performed (such as

cumulatively programming several pages or erasing

multiple blocks in squence). The status register may then

be read to determine if an error occurred during that

programmingorerasureseries. Thisaddsflexibilitytothe

way the device may be programmed or erased.

Additionally, once the program(erase) fail bit happens,

the program (erase) operation can not be performed

further. The program(erase) fail bit must be reset by

system software before further page program or sector

(chip) erase are attempted. To clear the status register,

the Clear Status Register command is written to the CIR.

Then, any other command may be issued to the CIR.

Note again that before a read cycle can be initiated, a

Read command must be written to the CIR to specify

whether the read data is to come from the Array, Status

Register or Silicon ID.

The status register bits are output on DQ2 - DQ7(table 6)

whether the device is in the byte-wide (x8) or word-wide

(x16)modefortheMX29F1610A. Intheword-widemode

the upper byte, DQ(8:15) is set to 00H during a Read

Status command. In the byte-wide mode, DQ(8:14) are

tri-stated and DQ15/A-1 retains the low order address

function. DQ0-DQ1 is set to 0H in either x8 or x16 mode.

It should be noted that the contents of the status register

are latched on the falling edge of OE or CE whichever

occurs last in the read cycle. This prevents possible bus

errors which might occur if the contents of the status

register change while reading the status register. CE or

OEmustbetoggledwitheachsubsequentstatusread, or

thecompletionofaprogramoreraseoperationwillnotbe

evident.

The Status Register is the interface between the

microprocessor and the Write State Machine (WSM).

When the WSM is active, this register will indicate the

status of the WSM, and will also hold the bits indicating

whetherornottheWSMwassuccessfulinperformingthe

desiredoperation. TheWSMsetsstatusbitsfourthrough

seven and clears bits six and seven, but cannot clear

statusbitsfourandfive. IfErasefailorProgramfailstatus

bit is detected, the Status Register is not cleared until the

Clear Status Register command is written. The

MX29F1610AautomaticallyoutputsStatusRegisterdata

whenreadafterChipErase,SectorErase,PageProgram

or Read Status Command write cycle. The internal state

machine is set for reading array data upon device power-

up, orafterdeeppower-downmode.

REV.1.7, JUN. 15, 2001

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11

MX29F1610A

TABLE 6. MX29F1610 STATUS REGISTER

STATUS

NOTES

1,2

DQ7

0

DQ6

0

DQ5

0

DQ4

0

DQ3

0

IN PROGRESS

PROGRAM

ERASE

1,3

0

SUSPEND (NOT COMPLETE)

(COMPLETE)

PROGRAM

1,4

0

1

0

COMPLETE

FAIL

1,2

1,3

1,5

1

0

ERASE

1

0

PROGRAM

1

0

1

0

ERASE

1

0

1

0

AFTER CLEARING STATUS REGISTER

1

0

NOTES:

1. DQ7 : WRITE STATE MACHINE STATUS

1 = READY, 0 = BUSY

DQ6 : ERASE SUSPEND STATUS

1 = SUSPEND, 0 = NO SUSPEND

DQ5 : ERASE FAIL STATUS

1 = FAIL IN ERASE, 0 = SUCCESSFUL ERASE

DQ4 : PROGRAM FAIL STATUS

1 = FAIL IN PROGRAM, 0 = SUCCESSFUL PROGRAM

DQ3=0 = RESERVED FOR FUTURE ENHANCEMENTS.

These bits are reserved for future use ; mask them out when polling the Status Register.

2. PROGRAM STATUS is for the status during Page Programming or Sector Unprotect mode.

3. ERASE STATUS is for the status during Sector/Chip Erase or Sector Protection mode.

4. SUSPEND STATUS is for Sector Erase mode .

5. FAIL STATUS bit(DQ4 or DQ5) is provided during Page Program or Sector/Chip Erase modes respectively.

6. DQ3 = 0 all the time.

REV.1.7, JUN. 15, 2001

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MX29F1610A

HARDWARE SECTOR PROTECTION

SECTOR UNPROTECT

TheMX29F1610A featuressectorprotection. Thisfeature

willdisablebothprogramanderaseoperations. Thesector

protectionfeatureisenabledusingsystemsoftwarebythe

user(Refer to table 3). The device is shipped with all

sectors unprotected. Alternatively, MXIC may protect all

sectors in the factory prior to shipping the device.

Itisalsopossibletounprotectthesector,sameasthefirst

five write command cycles in activating sector protection

mode followed by the Unprotect Sector command - 40H,

the automatic Unprotect operation begins on the rising

edge of the last WE pulse in the command sequence and

terminateswhentheStatusonDQ7is'1'atwhichtimethe

device stays at the read status register mode.(Refer to

table 3,6 and Figure 11,12)

SECTOR PROTECTION

The users have to write Verify Sector Protect command

to verify protect status after executing Sector Unprotect.

To activate this mode, a six-bus cycle operation is

required. There are two 'unlock' write cycles. These are

followed by writing the 'set-up' command. Two more

'unlock' write cycles are then followed by the Lock Sector

command - 20H. Sector address is latched on the falling

edge of CE or WE of the sixth cycle of the command

sequence. The automatic Lock operation begins on the

rising edge of the last WE pulse in the command

sequence and terminates when the Status on DQ7 is '1'

at which time the device stays at the read status register

mode.

The device remains enabled for read status register

mode until the CIR contents are altered by a valid

command sequence.

Either Protect or Unprotect sector mode is accomplished

by keeping WP high, i.e. protect-bit status can only be

changedwithavalidcommandsequenceandWPathigh.

Protect-bit status will not be changed during chip/sector

erase operations. Only unprotected sectors can be

programmed or erased regardless of the WP pin.

The users have to write Verify Sector Protect command

to verify protect status after executing Sector Protector.

DEEP POWER-DOWN MODE

The device remains enabled for read status register

mode until the CIR contents are altered by a valid

command sequence (Refer to table 3,6 and Figure 10,12

).

The MXIC's16 Mbit flash family supports a typical ICC of

1uAindeeppower-downmode. Oneofthetargetmarkets

for these devices is in protable equipment where the

power consumption of the machine is of prime

importance. When PWD is a logic low (GND ±0.2V), all

circuits are turned off and the device typically draws 1uA

of ICC current.

VERIFY SECTOR PROTECT

To verify the Protect status, operation is initiated by

writing Silicon ID read command into the command

register. Following the command write, a read cycle from

address XXX0H retrieves the Manufacturer code of C2H.

A read cycle from XXX1H returns the Device code FAH/

FBH. A read cycle from appropriate address returns

information as to which sectors are protected. To

terminate the operation, it is necessary to write the read/

reset command sequence into the CIR.

During erase or program modes, PWD low will abort

either erase or program operation. The contents of the

memory are no longer valid as the data has been

corrupted by the PWD function.

PWD transitions to VIL or turning power off to the device

will clear the status register.

(Refer to table 3,4 and Figure 12)

PWD pin is not provided in 44-pin SOP package.

A few retries are required if Protect status can not be

verified successfully after each operation.

REV.1.7, JUN. 15, 2001

P/N: PM0506

13

MX29F1610A

RY/BY PIN AND PROGRAM/ERASE

POLLING

LOW VCC WRITE INHIBIT

To avoid initiation of a write cycle during VCC power-up

and power-down, a write cycle is locked out for VCC less

than VLKO(= 3.2V , typically 3.5V). If VCC < VLKO, the

command register is disabled and all internal program/

erase circuits are disabled. Under this condition the

device will reset to the read mode. Subsequent writes will

be ignored until the VCC level is greater than VLKO. It is

the user's responsibility to ensure that the control pins are

logically correct to prevent unintentional write when VCC

is above VLKO.

RY/BYisadedicated,open-drainpageprogramandsector

erase completion. It transitions to VOL after a program or

erasecommandsequenceiswrittentotheMX29F1610A,

andreturnstoVCCwhentheWSMhasfinishedexecuting

the internal algorithm. Since RY/BY is an open-drain

output, severalRY/BYpinscanbetiedtogetherinparallel

with a pull-up resistor to VCC.

RY/BY can be connected to the interrupt input of the

system CPU or controller. It is active at all times, not

tristated if the CE or OE inputs are brought to VIH. RY/

BY is also VCC when the device is in erase suspend or

deep power-down modes.

WRITE PULSE "GLITCH" PROTECTION

RY/BY pin is not provided in 44-pin SOP package.

Noise pulses of less than 10ns (typical) on CE or WE will

not initiate a write cycle.

DATA PROTECTION

LOGICAL INHIBIT

The MX29F1610A is designed to offer protection against

accidental erasure or programming caused by spurious

system level signals that may exist during power

transitions. During power up the device automatically

resetstheinternalstatemachineintheReadArraymode.

Also, withitscontrolregisterarchitecture, alterationofthe

memory contents only occurs after successful

completion of specific multi-bus cycle command

sequences.

Writing is inhibited by holding any one of OE = VIL,CE =

VIH or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

The device also incorporates several features to prevent

inadvertent write cycles resulting from VCC power-up

and power-down transitions or system noise.

REV.1.7, JUN. 15, 2001

P/N: PM0506

14

MX29F1610A

Figure 1. AUTOMATIC PAGE PROGRAM FLOW CHART

START

Write Data AAH Address 5555H

Write Data 55H Address 2AAAH

Write Data A0H Address 5555H

Write Program Data/Address

NO

Loading End?

YES

Wait 100us

Read Status Register

NO

SR7 = 1

?

YES

NO

SR4 = 0

?

YES

Page Program Completed

Program Error

To Continue Other Operations,

Do Clear S.R. Mode First

YES

Program

another page?

NO

Operation Done, Device Stays At Read S.R. Mode

Note : S.R. Stands for Status Register

REV.1.7, JUN. 15, 2001

P/N: PM0506

15

MX29F1610A

Figure 2. AUTOMATIC CHIP ERASE FLOW CHART

START

Write Data AAH Address 5555H

Write Data 55H Address 2AAAH

Write Data 80H Address 5555H

Write Data AAH Address 5555H

Write Data 55H Address 2AAAH

Write Data 10H Address 5555H

Read Status Register

NO

YES

To Execute

SR7 = 1

Erase Suspend Flow (Figure 4.)

Suspend Mode ?

?

YES

NO

SR5 = 0

?

YES

Chip Erase Completed

Erase Error

To Continue Other

Operation Done,

Device Stays at

Read S.R. Mode

Operations, Do Clear

S.R. Mode First

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MX29F1610A

Figure 3. AUTOMATIC SECTOR ERASE FLOW CHART

START

Write Data AAH Address 5555H

Write Data 55H Address 2AAAH

Write Data 80H Address 5555H

Write Data AAH Address 5555H

Write Data 55H Address 2AAAH

Write Data 30H Sector Address

Read Status Register

NO

YES

To Execute

SR7 = 1

Erase Suspend Flow (Figure 4.)

Suspend Erase ?

?

YES

NO

SR5 = 0

?

YES

Sector Erase Completed

Erase Error

To Continue Other

Operation Done,

Device Stays at

Read S.R. Mode

Operations, Do Clear

S.R. Mode First

REV.1.7, JUN. 15, 2001

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17

MX29F1610A

Figure 4. ERASE SUSPEND/ERASE RESUME FLOW CHART

START

Write Data B0H Address xxxxH

Read Status Register

NO

SR7 = 1

?

YES

NO

SR5 = 0

?

SR6 = 1

?

YES

Erase Error

Erase has completed

Erase Suspend

Operation Done,

Device Stays at

Read S,R, Mode

To Continue Other

Operations, Do Clear

S.R. Mode First

Write Data AAH Address 5555H

Write Data 55H Address 2AAAH

Write Data F0H Address 5555H

Read Array

NO

Reading End ?

YES

Write Data D0H Address xxxxH

Continue Erase

REV.1.7, JUN. 15, 2001

P/N: PM0506

18

MX29F1610A

ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

NOTICE:

Stresses greater than those listed under ABSOLUTE

MAXIMUM RATINGS may cause permanent damage to the

device. This is stress rating only and functional operational

sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended period may

affect reliability.

RATING

Ambient Operating Temperature

VALUE

0°C to 70°C

Storage Temperature

Applied Input Voltage

Applied Output Voltage

VCC to Ground Potential

A9

-65°C to 125°C

-0.5V to 7.0V

-0.5V to 13.5V

NOTICE:

Specifications contained within the following tables are subject

to change.

CAPACITANCE TA = 25°C, f = 1.0 MHz

SYMBOL

CIN1

PARAMETER

MIN.

TYP.

MAX.

14

UNIT

pF

CONDITIONS

VIN = 0V

Input Capacitance

CIN2

Control Pin Input Capacitance

Output Capacitance

16

pF

VIN=0V

COUT

16

pF

VOUT = 0V

SWITCHING TEST CIRCUITS

1.6K ohm

DEVICE

UNDER

TEST

+5V

DIODES = IN3064

OR EQUIVALENT

CL

1.2K ohm

CL = 100 pF Including jig capacitance

SWITCHING TEST WAVEFORMS

2.4V

2.0V

0.8V

2.0V

0.8V

TEST POINTS

0.45V

OUTPUT

INPUT

AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".

Input pulse rise and fall times are < 10ns.

REV.1.7, JUN. 15, 2001

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MX29F1610A

DC CHARACTERISTICS = 0°C to 70°C, VCC = 5V±10%

SYMBOL

PARAMETER

NOTES MIN.

TYP.

MAX.

UNITS TEST CONDITIONS

IIL

Input Load

Current

1

±10

uA

VCC = VCC Max

VIN = VCC or GND

ILO

Output Leakage

Current

1

±10

100

VCC = VCC Max

VIN = VCC or GND

ISB1

VCC Standby

1

VCC = VCC Max

Current(CMOS)

CE1, CE2, PWD = VCC ± 0.2V

ISB2

IDP

VCC Standby

Current(TTL)

2

4

mA

uA

VCC = VCC Max

CE1, CE2, PWD = VIH

VCC Deep

Power-Down

Current

1

20

60

PWD = GND ± 0.2V

ICC1

VCC Read

Current

50

mA

VCC = VCC Max

CMOS: CE1, CE2 = GND ± 0.2V

BYTE = GND ±0.2V or VCC ±0.2V

Inputs = GND ±0.2V or VCC ±0.2V

TTL : CE1, CE2 = VIL,

BYTE = VIL or VIH

Inputs = VIL or VIH,

f = 10MHz, IOUT = 0 mA

ICC2

VCC Read

Current

1

30

35

mA

VCC = VCC Max,

CMOS: CE1, CE2 = GND ± 0.2V

BYTE = VCC ±0.2V or GND ±0.2V

Inputs = GND ±0.2V or VCC ±0.2V

TTL: CE1, CE2 = VIL,

BYTE = VIH or VIL

Inputs = VIL or VIH,

f = 5MHz, IOUT = 0mA

ICC3

ICC4

VCC Erase

Suspend Current

1,2

1

5

10

50

mA

CE1, CE2 = VIH

BLock Erase Suspended

VCC Program

Current

30

Program in Progress

Erase in Progress

ICC5

VIL

VCC Erase Current

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

1

50

mA

V

3

4

-0.3

2.4

0.8

VIH

VCC+0.3

0.45

V

VOL

VOH

V

IOL = 2.1mA

IOH = -2mA

2.4

V

REV.1.7, JUN. 15, 2001

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MX29F1610A

DC CHARACTERISTICS = 0°C to 70°C, VCC = 5V±10%(CONTINUE P.21)

NOTES:

^{1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, T = 25}°C. These currents are valid for all product

versions (package and speeds).

2. ICC3 is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of ICC3

and ICC1/2.

3. VIL min. = -1.0V for pulse width is equal to or less than 50ns.

VIL min. = -2.0V for pulse width is equal to or less than 20ns.

4. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20ns. If VIH is over the specified maximum value, read operation

cannot be guaranteed.

AC CHARACTERISTICS READ OPERATIONS

29F1610A-90

29F1610A-10

29F1610A-12

SYMBOL DESCRIPTIONS

MIN.

MAX.

MIN.

MAX.

100

55

MIN.

MAX.

120

60

UNIT CONDITIONS

tACC

tCE

Address to Output Delay

90

ns

CE=OE=VIL

OE=VIL

CE to Output Delay

90

tOE

OE to Output Delay

50

CE=VIL

tDF

OE High to Output Delay

Address to Output hold

BYTE to Output Delay

BYTE Low to Output in High Z

Deep Power-Down Recovery

0

35

0

55

0

55

CE=VIL

tOH

CE=OE=VIL

CE= OE=VIL

CE=VIL

tBACC

tBHZ

tDPR

90

50

0

100

55

0

120

55

0

NOTE:

TEST CONDITIONS:

1. tDF is defined as the time at which the output achieves the

• Input pulse levels: 0.45V/2.4V

• Input rise and fall times: 10ns

open circuit condition and data is no longer driven.

• Outputload: 1TTLgate+100pF(Includingscopeandjig)

• Reference levels for measuring timing: 0.8V, 2.0V

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MX29F1610A

Figure 5. READ TIMING WAVEFORMS

Device and

address selection

Outputs Enabled

Standby

Power-up

Vcc

Power-down

Data valid

Vcc

VIH

ADDRESSES STABLE

ADDRESSES

VIL

VIH

VIL

CE (1)

VIH

VIL

OE

tDF

VIH

VIL

tOE

WE

tCE

tOH

VOH

VOL

HIGH Z

DATA OUT

Data out valid

tACC

5.0V

VCC

GND

tDPR

VIH

VIL

PWD

NOTE:

1.CE is defined as the latter of CE1 or CE2 going Low or the first of CE1 or CE2 going High.

2.For real world application, BYTE pin should be either static high(word mode) or static low(byte mode);

dynamic switching of BYTE pin is not recommended.

REV.1.7, JUN. 15, 2001

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MX29F1610A

Figure 6. BYTE TIMING WAVEFORMS

Device and

address selection

Outputs Enable

VCC

Power-up

Standby

Power-down

Standby

Data valid

VCC

VIH

ADDRESSES STABLE

ADDRESSES

VIL

VIH

VIL

CE (1)

VIH

VIL

OE

tDF

VIH

VIL

tOE

WE

tCE

tOH

VOH

VOL

HIGH Z

Data Output

DATAOUT

tACC

VOH

VOL

VCC

PWD

tDPR

VIH

VIL

NOTE:

1.CE is defined as the latter of CE1 or CE2 going Low or the first of CE1 or CE2 going High.

2.For real world application, BYTE pin should be either static high(word mode) or static low(byte mode);

dynamic switching of BYTE pin is not recommended.

REV.1.7, JUN. 15, 2001

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MX29F1610A

AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS

29F1610A-90

29F1610A-10

29F1610A-12

SYMBOL

tWC

DESCRIPTION

MIN.

90

0

MAX.

MIN.

100

0

MAX.

MIN.

120

0

MAX.

UNIT

ns

Write Cycle Time

tAS

Address Setup Time

Address Hold Time

ns

tAH

50

0

55

0

60

0

ns

tDS

Data Setup Time

ns

tDH

Data Hold Time

ns

tOES

tCES

tGHWL

tCS

Output Enable Setup Time

CE Setup Time

0

ns

0

ns

Read Recover TimeBefore Write

CE Setup Time

0

ns

us

ns

us

tCH

CE Hold Time

0

tWP

Write Pulse Width

50

30

0.3

100

90

70

90

55

50

0.3

100

70

90

60

50

0.3

100

120

70

90

tWPH

tBALC

tBAL

Write Pulse Width High

Byte(Word) Address Load Cycle

Byte(Word) Address Load Time

Status Register Access Time

CE Setup before S.R. Read

WE High to RY/BY Going Low

30

tSRA

tCESR

tWHRL

tWHRLP

WE High to RY/BY Going Low

(in Page Program mode)

tPHWL

tVCS

PWD High Recovery to WE Going Low

VCC Setup Time

0

ns

us

50

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24

MX29F1610A

Figure 7. COMMAND WRITE TIMING WAVEFORMS

tCH

CE

tOES

tCS

OE

tWC

WE

tGHWL

tWPH

tWP

tAS

tAH

ADDRESSES

VALID

tDH

tDS

HIGH Z

DATA

(D/Q)

DIN

VCC

tVCS

PWD

tPHWL

NOTE:

1.BYTE pin is treated as Address pin. All timing specifications for BYTE pin are the same as those for address pin.

2.BYTE pin is sampled on the falling edge of WE or CE during the 3rd command write bus cycle; for real world application,

BYTE pin should be either static high(word mode) or static low(byte mode).

REV.1.7, JUN. 15, 2001

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25

MX29F1610A

Figure 8. AUTOMATIC PAGE PROGRAM TIMING WAVEFORMS

Word offset

Last Word

A0~A5

AAH

55H

Address

offset Address

Low/High

Last Low/High

Byte Select

A-1

Byte Select

(byte mode only)

Page Address

55H

2AH

55H

A6~A14

tAS

tAH

Page Address

A15~A19

tWC

tBAL

tBALC

CE(1)

WE

tWPH

tWP

tCES

OE

tWHRLP

RY/BY

tDS

tDH

tSRA

Write

Data

Last Write

SRD

DATA

PWD

AAH

55H

A0H

Data

tPHWL

NOTE:

1.CE is defined as the latter of CE1 or CE2 going low, or the first of CE1 or CE2 going high.

2.Please refer to page 9 for detail page program operation.

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26

MX29F1610A

Figure 9. AUTOMATIC SECTOR/CHIP ERASE TIMING WAVEFORMS

5555H

A0~A14

5555H

2AAAH

5555H

2AAAH

*/5555H

tAS

tAH

A15

SA/*

A16~A19

tCESR

CE#

tWPH

tWP

WE

tWC

tCES

OE

tWHRL

RY/BY

tDS

tDH

tSRA

DATA

PWD

AAH

55H

80H

AAH

55H

30H/10H

SRD

tPHWL

NOTES:

1.CE# is defined as the latter of CE1 or CE2 going low, or the first of CE1 or CE2 going high.

2."*" means "don't care" in this diagram.

3."SA" means "Sector Adddress".

REV.1.7, JUN. 15, 2001

P/N: PM0506

27

MX29F1610A

Figure 10. SECTOR PROTECTION ALGORITHM

(Only one sector can be protected at one time)

START

N=1

N=N+1

Sector protect Flow

Verify Sector

NO

Protect/Unprotect Flow

NO

N=1024?

Pass?

YES

Write RESET Command

Device Failed

Sector Unprotect Complete

and Device Return to Read Mode

NOTE 1 : Address means A14-A0 for word and byte mode

NOTE 2 : Sector Address=(A19,A18,A17,A16)

NOTE 3 : Sector protection will be disabled when WP is low

REV.1.7, JUN. 15, 2001

P/N: PM0506

28

MX29F1610A

Sector Protect Flow

Verify Sector Protect/Unprotect Flow

START

Write Command

Address=5555H

Data=AAH

Write Command

Address=5555H

Data=AAH

Write Command

Address=2AAAH

Data=55H

Write Command

Address=2AAAH

Data=55H

Write Command

Address=5555H

Data=90H

Write Command

Address=5555H

Data=60H

Write Command

Address=5555H

Data=AAH

Wait 1us

Read Data Ouput

DQ7-DQ0 with

Write Command

Address=2AAAH

Data=55H

Address=Sector

Address and A1=VIH

Write Command

Address=Sector

Address;Data=20H

Data=C2:Protect

Data=00:Unprotect

Read Status

Register

Verify

YES

Another

Sector?

NO

SR7=1?

END

YES

END

REV.1.7, JUN. 15, 2001

P/N: PM0506

29

MX29F1610A

Figure 11. SECTOR UNPROTECT ALGORITHM

START

N=1

N=N+1

Sector Unprotect Flow

Verify Sector

NO

Protect/Unprotect Flow

NO

N=1024?

Pass?

YES

Write RESET Command

Device Failed

Sector Unprotect Complete

and Device Return to Read Mode

NOTE 1 : Address means A14-A0 for word and byte mode

NOTE 2 : During interation, sector address should be the sectors which have not passed the verify procedure after previous interation

NOTE 3 : The sector(s), which had passed the sector unprotect verification must not enter the sector unprotect flow anymore

NOTE 4 : During loading sector addresses, DATA=BOH means the last sector address loaded to be unprotected

NOTE 5 : Sector Address=(A19, A18, A17, A16)

NOTE 6 : Sector Unprotect will be disabled when WP is low

REV.1.7, JUN. 15, 2001

P/N: PM0506

30

MX29F1610A

Sector Unprotect Flow

Verify Sector Protect/Unprotect Flow

START

Write Command

Address=5555H

Data=AAH

Write Command

Address=5555H

Data=AAH

Write Command

Address=2AAAH

Data=55H

Write Command

Address=2AAAH

Data=55H

Write Command

Address=5555H

Data=60H

Write Command

Address=5555H

Data=90H

Write Command

Address=5555H

Data=AAH

Wait 1us

Write Command

Address=2AAAH

Data=55H

Read Data Ouput

DQ7-DQ0 with

Address=Sector

Address and A1=VIH

Write Command

Address=Sector

Address;Data=40H

(NOTE 2)

(NOTE 3)

(NOTE 4)

Data=C2:Protect

Data=00:Unprotect

Load Other Sector

Addresses If

Read Status

Register

Necessary;Data=40H

Load The Last

Sector Address;

Data=B0H

Verify

YES

Another

Sector?

Read Status

Register

NO

END

NO

SR7=1?

YES

END

REV.1.7, JUN. 15, 2001

P/N: PM0506

31

MX29F1610A

Figure 12. VERIFY SECTOR PROTECT FLOW CHART

START

Write Data AAH, Address 5555H

Write Data 55H, Address 2AAAH

Write Data 90H, Address 5555H

Ptoect Status Read*

* 1. Protect Status:

Data Outputs C2H as Protected Sector Verified Code.

Data Outputs 00H as Unprotected Sector Verified Code.

2. Sepecified address will be

(A19,A18,A17,A16) = Sector address

(A1, A0)=(1,0) the rest of the address pins are don't care.

3. Silicon ID can be read via this Flow Chart.

Refer to Table 4.

REV.1.7, JUN. 15, 2001

P/N: PM0506

32

MX29F1610A

Figure 13. COMMAND WRITE TIMING WAVEFORMS(Alternate CE Controlled)

tWH

WE

OE

CE

tOES

tWS

tWC

tGHWL

tCPH

tCP

tAS

tAH

ADDRESSES

VALID

tDH

tDS

HIGH Z

DATA

(D/Q)

DIN

VCC

tVCS

PWD

tPHWL

NOTE:

1.BYTE pin is treated as Address pin. All timing specifications for BYTE pin are the same as those for address pin.

2.BYTE pin is sampled on the falling edge of WE or CE during the 3rd command write bus cycle; for real world application,

BYTE pin should be either static high(word mode) or static low(byte mode).

REV.1.7, JUN. 15, 2001

P/N: PM0506

33

MX29F1610A

Figure 14. AUTOMATIC PAGE PROGRAM TIMING WAVEFORM(Alternate CE Controlled)

Word offset

Address

Last Word

A0~A5

AAH

55H

Offset Address

Low/High

Last Low/High

Byte Select

A-1

Byte Select

((Byte Mode Only)

Page Address

55H

2AH

55H

A6~A14

tAS

tAH

Page Address

A15~A19

tWC

tBALC

WE

tCPH

tCP

tBAL

CE(1)

tCES

OE

tWHRLP

RY/BY

tDS

tDH

tSRA

Write

Data

Last Write

Data

DATA

PWD

AAH

55H

A0H

SRD

tPHWL

NOTE:

1.CE is defined as the latter of CE1 or CE2 going low, or the first of CE1 or CE2 going high.

2.Please refer to page 9 for detail page program operation.

REV.1.7, JUN. 15, 2001

P/N: PM0506

34

MX29F1610A

ERASE AND PROGRAMMING PERFORMANCE

LIMITS

TYP.(1)

PARAMETER

MIN.

MAX.(2)

UNITS

Sector Erase Time

1

8

s

Chip Erase Time

32

0.9

14

256

27

Page Programming Time

Chip Programming Time

Erase/Program Cycles

Byte Program Time

ms

42

sec

Cycles

us

100,000

7

300

Note: 1.All numbers are sampled, not 100% tested.

2.Typical values measured at 25°C,VCC=5.0V.

LATCHUP CHARACTERISTICS

MIN.

-1.0V

MAX.

Input Voltage with respect to GND on all pins except I/O pins

Input Voltage with respect to GND on all I/O pins

Current

13.5V

-1.0V

Vcc + 1.0V

+100mA

-100mA

Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.

REV.1.7, JUN. 15, 2001

P/N: PM0506

35

MX29F1610A

PACKAGE INFORMATION

48-PIN PLASTIC TSOP

REV.1.7, JUN. 15, 2001

P/N: PM0506

36

MX29F1610A

44-PIN PLASTIC SOP

REV.1.7, JUN. 15, 2001

P/N: PM0506

37

MX29F1610A

Revision History

Revision#

Description

Page

Date

1.1

Update ISB1 typical value to 1uA--P20

Add Control Pin Input Capacitance

May/13/1998

1.2

Change resistance value at switching test circuits

Change IOH value at DC characteristics

Change Pin12 of MX29F1610B TSOP from NC to GND

Remove the 70ns speed grade.

P19

P20

P2

Nov/10/1998

1.3

1.4

MAR/31/1999

MAY/18/1999

P1

ModifyEraseandProgrammingPerformance

Added 100ns to access time

Cancel the MX29F1610B Type section

P35

1.5

1.6

P1,21,24 JUN/20/2000

P1~3,8~14 NOV/16/2000

P21,24

1.7

To modify "Package Information"

P36~37

JUN/15/2001

REV.1.7, JUN. 15, 2001

P/N: PM0506

38

MX29F1610A

MACRONIX INTERNATIONAL CO., LTD.

HEADQUARTERS:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

EUROPE OFFICE:

TEL:+32-2-456-8020

FAX:+32-2-456-8021

JAPAN OFFICE:

TEL:+81-44-246-9100

FAX:+81-44-246-9105

SINGAPORE OFFICE:

TEL:+65-348-8385

FAX:+65-348-8096

TAIPEI OFFICE:

TEL:+886-2-2509-3300

FAX:+886-2-2509-2200

MACRONIX AMERICA, INC.

TEL:+1-408-453-8088

FAX:+1-408-453-8488

CHICAGO OFFICE:

TEL:+1-847-963-1900

FAX:+1-847-963-1909

http : //www.macronix.com

^MACRONIX3^IN9^{TERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.}


型号：	29F1610A-12
厂家：	MACRONIX INTERNATIONAL
描述：	16M-BIT [2M x8/1M x16] CMOS SINGLE VOLTAGE FLASH EEPROM 16M - BIT [ 2M ×8 / 1M X16 ] CMOS单电压闪存EEPROM 闪存可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总39页 (文件大小：669K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

29F1610A-12 [Macronix]

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