MAXQ8913X-0000+ [MAXIM]
RISC Microcontroller, CMOS;
| 型号： | MAXQ8913X-0000+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | RISC Microcontroller, CMOS 微控制器 外围集成电路 |
| 文件： | 总22页 (文件大小：273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4605; Rev 0; 6/09
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
General Description
Features
♦ High-Performance, Low-Power, 16-Bit MAXQ
®
The MAXQ8913 is a single-chip servo controller
designed as a complete solution for dual axis optical
image stabilization (OIS) applications. The device
incorporates all the necessary elements for condition-
ing of sensor signals, analog-to-digital conversion, digi-
tal servo algorithm implementation using a 16-bit RISC
microcontroller, and digital-to-analog conversion, as
well as including dual servo amplifiers.
RISC Core
♦ One-Cycle, 16 x 16 Hardware Multiply/Accumulate
with 48-Bit Accumulator
♦ Two Current Sinks for Driving Hall-Effect Elements
♦ Four DACs
Even though the device is targeted for OIS applica-
tions, it can be effectively used in many other types of
servo control. The MAXQ8913 supports both voice coil
and stepper motor applications.
♦ DC to 10MHz Operation; Approaching 1MIPS per MHz
♦ 2.7V to 3.6V Logic/Analog Operating Voltage
♦ 33 Instructions, Most Single Cycle
The MAXQ8913 includes four op amps; a 7-channel,
12-bit ADC; dual 10-bit differential DACs; and dual 8-bit
single-ended DACs. It also contains 64KB of flash mem-
ory, 4KB of RAM, 4KB of ROM, a 16-bit timer/counter, a
universal asynchronous/synchronous receiver-transmit-
♦ Three Independent Data Pointers Accelerate Data
Movement with Automatic Increment/Decrement
♦ 16-Level Hardware Stack
♦ 16-Bit Instruction Word, 16-Bit Data Bus
♦ 16 x 16-Bit General-Purpose Working Registers
♦ Optimized for C Compilers
2
ter (USART), an I C port, and an SPI™ master/slave
port.
For the ultimate in low-power performance, the OIS
device includes a low-power sleep mode, the ability to
selectively disable peripherals, and multiple power-sav-
ing operating modes.
♦ Memory Features
64KB Flash Memory
4KB of Internal Data RAM
4KB of Utility ROM
Applications
Digital Camera and Cell Phone Optical Image
Stabilization
JTAG Bootloader for Programming and Debug
♦ Peripherals
Four Operational Amplifiers
12-Bit SAR ADC with Internal Reference and Autoscan
Up to 312ksps Sample Rate
Servo Loop Control
Tone Generation with Speaker Drive
Seven-Input Mux (Four Internally Connected to
Op-Amp Outputs, One Internally Connected
to Temp Sensor, and Two Connected to
Uncommitted External Pins)
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
Brownout Reset Generation
MAXQ8913EWG+T
-40°C to +85°C
58 WLP
16-Bit Programmable Timer/Counter
USART, I C, and SPI Master/Slave
On-Chip Power-On Reset/Brownout Reset
Programmable Watchdog
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
2
Pin Configuration appears at end of data sheet.
♦ Low-Power Consumption
3mA (max) at 10MHz Flash Operation at 3.3V
4.5µA (max) in Stop Mode
Low-Power Power-Management Mode (PMM)
SPI is a trademark of Motorola, Inc.
MAXQ is a registered trademark of Maxim Integrated Products, Inc.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be
simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
ABSOLUTE MAXIMUM RATINGS
Voltage Range on All Pins (including AVDD,
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Soldering Temperature...........................Refer to the IPC/JEDEC
J-STD-020 Specification.
DVDD) Relative to Ground .................................-0.5V to +3.6V
Voltage Range on Any Pin Relative to Ground
except AVDD, DVDD...........................-0.5V to (V
+ 0.5V)
DVDD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MAXQ8913
RECOMMENDED DC OPERATING CONDITIONS
(V
DVDD
= V = 2.7V to 3.6V, T = -40°C to +85°C.) (Note 1)
AVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
3.6
3.6
1.89
3.6
0
UNITS
Digital Supply Voltage
Digital Operating Voltage
Regulator Voltage Output
Analog Supply Voltage
Ground
V
DVDD
V
= V
V
3.3
V
V
V
V
V
V
AVDD
DVDD
RST
RST
V
V
(Note 2)
V = V
AVDD
1.71
2.7
0
1.8
0
REG18
V
AVDD
DVDD
GND
AGND = DGND
Monitors V
Digital Power-Fail Reset Voltage
V
RST
2.58
2.68
2.2
3.0
4.5
40
DVDD
I
I
f
f
= 10MHz, V
= 10MHz, V
= 2.7V
= 3.3V
DD_HFX3
DD_HFX4
CK
CK
DVDD
Active Current (Note 3)
Stop-Mode Current
mA
DVDD
I
I
I
t
t
(Notes 4, 5)
(Notes 4, 6)
(Notes 4, 7)
0.2
STOP_1
STOP_2
STOP_3
STOP_1
STOP_2
μA
500
Internal regulator on
Internal regulator off, brownout or SVM on
15
Stop-Mode Resume Time
μs
V
375
0.20 x
Input Low Voltage on HFXIN
V
V
IL1
IL2
IH1
IH2
DGND
V
DVDD
Input Low Voltage on All Other
Port Pins
0.30 x
V
V
V
DGND
V
DVDD
0.75 x
Input High Voltage on HFXIN
V
V
V
DVDD
V
V
DVDD
Input High Voltage on All Other
Port Pins
0.70 x
V
DVDD
V
V
V
V
DVDD
Input Hysteresis (Schmitt)
V
0.18
IHYS
Output Low Voltage for All Port
Pins Except SHDNL, SHDNR
V
I
I
I
= 4mA (Note 8)
= 1.5mA
V
V
0.4
0.4
OL
OL
OH
OL
OL
OH
DGND
Output Low Voltage for SHDNL,
SHDNR
V
V
DGND
Output High Voltage for All Port
Pins
V
DVDD
- 0.4
V
= -4mA (Note 8)
V
I/O Pin Capacitance
C
IO
Guaranteed by design
15
pF
2
_______________________________________________________________________________________
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
RECOMMENDED DC OPERATING CONDITIONS (continued)
(V
DVDD
= V = 2.7V to 3.6V, T = -40°C to +85°C.) (Note 1)
AVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
100
UNITS
μA
Input Low Current for Port Pins
Input-Leakage Current
I
V
= 0.4V
IN
IL
I
L
Internal pullup disabled
-300
30
+300
110
nA
Input Pullup Resistor
R
70
kꢀ
PU
CLOCK SOURCE
External Clock Frequency
External Clock Duty Cycle
Internal Ring Oscillator
System Clock Frequency
FLASH AC CHARACTERISTICS
f
DC
40
10
60
MHz
%
HFIN
t
XCLK_DUTY
1
MHz
MHz
f
DC
10
CK
System Clock During Flash
Programming/Erase
2
MHz
Program Time
t
20
20
40
40
40
μs
ms
PROG
t
ERASETME
Page Erase Time
Mass Erase Time
Write/Erase Cycles
Data Retention
20
ms
1000
100
Cycles
Years
T
A
= +25°C
ANALOG-TO-DIGITAL CONVERTER (Note 9)
ADC Clock Frequency
f
0.1
0
5
MHz
V
SCLK
Unipolar (single-ended)
V
REF
Input Voltage Range
V
AIN
Bipolar (differential) (Note 10)
-V
/2
+V
/2
REF
REF
Analog Input Capacitance
C
16
pF
AIN
I
I
f
f
= 5MHz, internal reference
3.0
mA
AVDD1
AVDD2
ASTOP
SCLK
SCLK
= 5MHz, external reference (internal
Current Consumption
800
2.5
reference disabled)
μA
I
Power-down mode
ANALOG-TO-DIGITAL CONVERTER PERFORMANCE (V
= 3V, 0.1μF capacitor on REFA, f
= 5MHz)
12
REF
SCLK
Resolution
Bits
LSB
LSB
LSB
%
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
±1
±2
±1
DNL
No missing codes from +25°C to +85°C
±10
±1
Gain Error
Gain Temperature Coefficient
Signal-to-Noise Plus Distortion
Spurious-Free Dynamic Range
Throughput
±0.5
ppm/°C
dB
SINAD
SFDR
f
f
= 1kHz
= 1kHz
69
76
IN
IN
dB
16f
samples
312
4
ksps
μs
SCLK
ADC Setup Time
t
(Note 11)
ADC_SETUP
Shutdown or conversion stopped;
Input-Leakage Current
I
±1
μA
ILA
AIN0/AIN1 and V
AEREF
_______________________________________________________________________________________
3
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
RECOMMENDED DC OPERATING CONDITIONS (continued)
(V
DVDD
= V = 2.7V to 3.6V, T = -40°C to +85°C.) (Note 1)
AVDD A
PARAMETER
Autoscan Throughput
ANALOG-TO-DIGITAL CONVERTER REFERENCE
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ksps
per
channel
All channels active
39
Internal Reference Voltage
V
1.44
0.9
1.5
1.56
50
V
AIREF
MAXQ8913
Internal Reference Voltage
Startup Time
t
μs
AIREF
V
AVDD
External Reference Voltage Input
Internal Reference Voltage Drift
V
V
AEREF
+ 0.05
V
Guaranteed by design
±50
ppm/°C
ADRIFT
Reference Settle Time
(Switching ADC Reference from
Either Internal or External
Reference to AVDD)
t
AAVDD_
SETUP
(Note 12)
4
Samples
V
Reference Output
V
REFA
V
REF
SUPPLY VOLTAGE MONITOR
Supply Voltage Set Point
S
2.7
80
3.5
V
mV
V
VTR
Supply Voltage Increment
Resolution
100
2.7
120
Supply Voltage Default Set Point
Supply Voltage Monitor Start
Time
t
50
2
μs
SVMST
Changing from one set point to another set
point
t
t
SVM_SU1
SVM_SU2
Supply Voltage Monitor Setup
Time
μs
Exit from stop mode
8
CLASS D AMPLIFIER CONTROL DACs, 10-BIT DACs
Resolution
10
2.3
Bits
V
Code 0 = -2.5, code 1023 = +2.5,
= 1.5V
Full-Scale Output Voltage
VFS
2.5
2.8
1.4
V
REF
Output Common-Mode Voltage
DC Output Impedance
Integral Nonlinearity
Differential Nonlinearity
Settling Time
VCM
ZOUT
INL
1.15
1.25
10
V
At DC, per side
kꢀ
2
LSB
LSB
μs
DNL
Guaranteed monotonic by design
From 1/4 FS to 3/4 FS to 1 LSB
-1
0.10
2
Digital Feedthrough
Glitch Impulse
0.15
12
nV-s
nV-s
ksps
Major carry transition
(Note 13)
Update Rate
100
4
_______________________________________________________________________________________
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
RECOMMENDED DC OPERATING CONDITIONS (continued)
(V
DVDD
= V = 2.7V to 3.6V, T = -40°C to +85°C.) (Note 1)
AVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DAC3 AND DAC4 INCLUDING BUFFER
Resolution
8
Bits
V
Code 0 = 0.35, code 255 = 2.35,
0.30 to 0.35 to 0.45 to
2.20
Full-Scale Output Voltage
VFS
V
REF
= 1.5
2.35
2.7
Output Common-Mode Voltage
DC Drive Capability
Integral Nonlinearity
Differential Nonlinearity
Settling Time
VCM
Code = 128, V
(Note 14)
= 1.5V
1.25
1
1.35
1.55
V
REF
I
mA
LSB
LSB
μs
DRIVE
INL
1
0.5
5
DNL
Guaranteed monotonic by design
From 1/4 FS to 3/4 FS to 1 LSB
(Note 14)
-1
100
-8
Update Rate
ksps
OP AMP A, B, C, D
Offset Voltage
V
V
V
= 2V
= 2V
2
+8
1
mV
μV/°C
nA
OS
CM
Offset Drift
V
10
OSDRIFT
CM
Input Bias Current
I
T = +25°C (Note 13)
A
BIAS
Common-Mode Rejection Ratio
Gain Bandwidth Product
Input Common-Mode Range
TEMPERATURE SENSOR
CMMR
GB
60
1
80
dB
> 200
kHz
V
CMR
V
AVDD
NG
Code 0 = -273.15C; absolute 0; 8 LSB/°C
for V = 1.5V, 12-bit ADC; 4 LSB/°C for
Sensitivity
2.9304
mV/°C
°C
REF
V
REF
= 3.0V
Raw Accuracy
No correction, T = 300°K (Note 14)
-6
+6
CURRENT SINK
Code 0 = 0, code 1 = 62.5μA,
code 255 = 15.94mA
Resolution
8
Bits
Full-Scale Sink Current
Zero-Scale Sink Current
LSB Size
I
Code = 255, V = 2V, V = 1.5V
REF
14.9
15.94
0
18.0
1
mA
μA
μA
S15
DS
I
Code = 0, V = 2V
DS
S0
LSB
V
DS
= 2V, V
= 1.5V
REF
62.5
SPI: MASTER MODE (See Figures 1, 2)
SPI Master Operating Frequency
1/t
f
/2
MHz
ns
MCK
SYS
SCLK Output Pulse Width-
High/Low
t
/
MCK
t
, t
MCH MCL
2 - t
RF
I/O Rise/Fall Time
(This parameter is device
dependent.)
t
RF
C = 15pF, pullup = 560ꢀ
L
16
ns
MOSI Output Valid to SCLK
Sample Edge (MOSI Setup)
t
/
MCK
t
t
ns
ns
MOV
2 - t
RF
MOSI Output Hold After SCLK
Sample Edge
t
/
MCK
MOH
2 - t
RF
_______________________________________________________________________________________
5
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
RECOMMENDED DC OPERATING CONDITIONS (continued)
(V
DVDD
= V = 2.7V to 3.6V, T = -40°C to +85°C.) (Note 1)
AVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Last Sample Edge to MOSI
Output Change (MOSI Last Hold)
t
/
MCK
t
ns
MLH
2 - t
RF
MISO Input Valid to SCLK
Sample Edge (MISO Setup)
t
(Note 13)
2t
ns
ns
MIS
RF
MISO Input Hold After SCLK
Sample Edge
t
0
MIH
MAXQ8913
SPI: SLAVE MODE (See Figures 1, 3)
SPI Slave Operating Frequency
1/t
f
/4
kHz
ns
SCK
SYS
SCLK Input Pulse-Width
High/Low
t
/
SCK
t
, t
SCH SCL
2 - t
RF
I/O Rise/Fall Time
(This parameter is device
dependent.)
t
RF
C = 15pF, pullup = 560ꢀ
L
16
ns
SSEL Active to First Shift Edge
t
t
t
ns
ns
SSE
RF
MOSI Input to SCLK Sample
Edge Rise/Fall Setup
t
SIS
RF
MOSI Input from SCLK Sample
Edge Transition Hold
t
t
ns
ns
ns
ns
ns
SIH
RF
MISO Output Valid After SCLK
Shift Edge Transition
t
(Note 13)
2t
RF
SOV
SSH
SSEL Inactive to Next SSEL
Asserted
t
+
SYS
t
t
RF
SCLK Inactive to SSEL
Deasserted
t
t
RF
SD
MISO Output Disabled After
SSEL Edge Deasserted
2t
SYS
+ 2t
RF
t
SLH
Note 1: Specifications to -20°C are guaranteed by design and are not production tested.
Note 2: Connect to ground through a 1µF capacitor.
Note 3: Crystal connected to HFXIN, HFXOUT. Operating in /1 mode. Measured on the DVDD pin and the device not in reset. All
inputs are connected to GND or DVDD. Outputs do not source/sink any current. One timer B enabled, with the device exe-
cuting code from flash.
Note 4:
I
is the total current into the device when the device is in stop mode.
STOP
Note 5: Regulator, brownout disabled. Stop mode current through AVDD and DVDD.
Note 6: Regulator disabled, brownout enabled. Stop mode current through AVDD and DVDD.
Note 7: Regulator enabled, brownout enabled.
Note 8:
Note 9:
I
V
+ I
AVDD
for all outputs combined should not exceed 35mA to meet the specification.
OH(MAX)
OL(MAX)
.
= V
REF
Note 10: The operational input voltage range for each individual input of a differentially configured pair is from GND to AVDD. The
operational input voltage difference is from -V /2 to +V /2.
REF
REF
Note 11: The typical value is applied when a conversion is requested with ADPMO = 0. Under these conditions, the minimum delay
is met. If ADPMO = 1, the user is responsible for ensuring the 4µs delay time is met.
Note 12: Total on-board decoupling capacitance on the AVDD pin < 100nF. The output impedance of the regulator driving the
AVDD pin < 10Ω.
Note 13: This value is the sum of input R/F and output R/F.
Note 14: Guaranteed by design and characterization.
6
_______________________________________________________________________________________
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
SHIFT
SAMPLE
SHIFT
SAMPLE
SSEL
(SAS = 0)
t
MCK
1/0
0/1
1/0
0/1
SCLK
CKPOL/CKPHA
t
t
MCL
MCH
1/1
0/0
1/1
0/0
SCLK
CKPOL/CKPHA
t
MOH
t
t
t
MLH
MOV
RF
MOSI
MISO
MSB
MSB-1
LSB
t
t
MIH
MIS
MSB
MSB-1
LSB
Figure 1. Enhanced SPI Master Timing
SHIFT
SAMPLE
SHIFT
SAMPLE
t
t
SSH
SSEL
SSE
(SAS = 0)
t
t
SD
SCK
SCLK
CKPOL/CKPHA
0/1
t
t
SCL
SCH
SCLK
CKPOL/CKPHA
1/1
t
t
SIH
SIS
MOSI
MISO
MSB
MSB-1
LSB
t
t
RF
t
SLH
SOV
MSB
MSB-1
LSB
Figure 2. Enhanced SPI Slave Mode Timing (CKPHA = 1)
_______________________________________________________________________________________
7
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
SHIFT
SAMPLE
SHIFT
SAMPLE
t
t
SSH
SSEL
SSE
(SAS = 0)
t
t
SD
SCK
SCLK
CKPOL/CKPHA
1/0
t
t
SCL
SCH
MAXQ8913
SCLK
CKPOL/CKPHA
0/0
t
t
SIH
SIS
MOSI
MISO
MSB
MSB-1
LSB
t
t
RF
t
SLH
SOV
MSB
MSB-1
LSB
MSB
Figure 3. Enhanced SPI Slave Mode Timing (CKPHA = 0)
8
_______________________________________________________________________________________
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
2
I C BUS CONTROLLER AC CHARACTERISTICS
(V
DVDD
= 1.8V to 3.6V, T = -40°C to +85°C.) (See Figure 4.)
A
STANDARD MODE
FAST MODE
MIN MAX
0.3 x V
TEST
CONDITIONS
PARAMETER
SYMBOL
UNITS
MIN
MAX
DVDD
Input Low Voltage
V
-0.5
0.3 x V
-0.5
V
V
V
IL_I2C
DVDD
(Note 15)
Input High Voltage
V
0.7 x V
DVDD
0.7 x V
(Note 16)
IH_I2C
DVDD
0.05 x
Input Hysteresis (Schmitt)
V
V
> 2V
IHYS_I2C
DVDD
V
DVDD
Output Logic-Low (Open Drain
or Open Collector)
V
> 2V, 3mA
sink current
DVDD
V
0
0.4
0
0.4
V
OL_I2C
Output Fall Time from V
IH(MIN)
to V
with Bus
IL(MAX)
t
250
20 + 0.1C
250
ns
OF_I2C
B
Capacitance from 10pF to
400pF (Notes 17, 18)
Pulse Width of Spike Filtering
That Must Be Suppressed by
Input Filter
t
0
50
ns
SP_I2C
Input Current Each I/O Pin
with an Input Voltage
I
-10
+10
10
-10
+10
10
μA
pF
IN_I2C
Between 0.1 x V
and 0.9
DVDD
x V
(Note 19)
DVDD(MAX)
I/O Capacitance
C
IO_I2C
2
Note 15: Devices that use nonstandard supply voltages that do not conform to the intended I C-bus system levels must relate their
input levels to the V voltage to which the pullup resistors R are connected.
DVDD
P
Note 16: Maximum V
= V
+ 0.5V.
IH_I2C
DVDD(MAX)
Note 17: C = capacitance of one bus line in pF.
B
2
Note 18: The maximum fall time of 300ns for the SDA and SCL bus lines as shown in the I C Bus Controller Timing table is longer
than the specified maximum t of 250ns for the output stages. This allows series protection resistors (R ) to be con-
OF_I2C
s
2
2
nected between the SDA/SCL pins and the SDA/SCL bus lines as shown in the I C Bus Controller Timing (Acting as I C
Slave) table without exceeding the maximum specified fall time. See Figure 4.
Note 19: I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if V
is switched off.
DVDD
V
V
DVDD
DVDD
2
2
I C
I C
DEVICE
DEVICE
R
R
P
P
R
S
R
R
S
R
S
S
SDA
SCL
Figure 4. Series Resistors (R ) for Protecting Against High-Voltage Spikes
S
_______________________________________________________________________________________
9
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
2
I C BUS CONTROLLER TIMING
(All values referenced to V
and V
. See Figure 5.)
IL_I2C(MAX)
IH_I2C(MIN)
STANDARD MODE
FAST MODE
PARAMETER
Operating Frequency
SYMBOL
UNITS
MIN
0
MAX
MIN
MAX
f
100
0
0.6
400
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
μs
pF
I2C
Hold Time After (Repeated) START
Clock Low Period
t
4.0
4.7
4.0
4.7
0
HD:STA
t
1.3
LOW_I2C
Clock High Period
t
0.6
HIGH_I2C
MAXQ8913
Setup Time for Repeated START
Hold Time for Data (Notes 20, 21)
Setup Time for Data (Note 22)
SDA/SCL Fall Time (Note 23)
SDA/SCL Rise Time (Note 23)
Setup Time for STOP
t
t
t
0.6
SU:STA
HD:DAT
SU:DAT
3.45
0
0.9
250
100
t
300
20 + 0.1C
20 + 0.1C
0.6
300
300
F_I2C
B
t
1000
R_I2C
B
t
4.0
4.7
SU:STO
Bus-Free Time Between STOP and START
Capacitive Load for Each Bus Line
t
1.3
BUF
C
400
400
B
Noise Margin at the Low Level for Each Connected
Device (Including Hysteresis)
0.1 x
0.1 x
V
DVDD
V
V
NL_I2C
V
DVDD
Noise Margin at the High Level for Each Connected
Device (Including Hysteresis)
0.2 x
0.2 x
V
DVDD
V
V
NH_I2C
V
DVDD
Note 20: A device must internally provide a hold time of at least 300ns for the SDA signal (referenced to the V
of the SCL
IH_I2C(MIN)
signal) to bridge the undefined region of the falling edge of SCL.
Note 21: The maximum t
need only be met if the device does not stretch the low period (t
) of the SCL signal.
LOW_I2C
HD:DAT
2
2
Note 22: A fast-mode I C-bus device can be used in a standard-mode I C-bus system, but the requirement t
≥ 250ns must
SU:DAT
be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does
stretch the low period of the SCL signal, it must output the next data bit to the SDA line t
= 1250ns (according to the standard-mode I C specification) before the SCL line is released.
+ t
= 1000 + 250
R_I2C(MAX)
SU:DAT
2
Note 23: C = Total capacitance of one bus line in pF.
B
10 ______________________________________________________________________________________
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
2
2
I C BUS CONTROLLER TIMING (ACTING AS I C MASTER)
STANDARD MODE
FAST MODE
MIN MAX
PARAMETER
SYMBOL
UNITS
MIN
MAX
System Frequency
f
1
3.60
MHz
Hz
SYS
Operating Frequency
f
f
/8
f
/8
I2C
SYS
SYS
Hold Time After (Repeated) START
Clock Low Period
t
t
t
μs
HD:STA
HIGH_I2C
HIGH_I2C
t
5
3
5
3
t
t
LOW_I2C
SYS
SYS
μs
Clock High Period
t
HIGH_I2C
Setup Time for Repeated START
Hold Time for Data
t
t
t
t
t
SU:STA
HD:DAT
SU:DAT
LOW_I2C
LOW_I2C
0
3.45
0
0.9
μs
Setup Time for Data
250
100
ns
SDA/SCL Fall Time
t
300
20 + 0.1C
20 + 0.1C
300
300
ns
F_I2C
R_I2C
B
SDA/SCL Rise Time
t
1000
ns
B
Setup Time for STOP
t
t
t
HIGH_I2C
μs
SU:STO
HIGH_I2C
Bus-Free Time Between STOP and START
Capacitive Load for Each Bus Line
t
t
t
μs
BUF
LOW_I2C
LOW_I2C
C
400
400
pF
B
Noise Margin at the Low Level for Each Connected
Device (Including Hysteresis)
0.1 x
0.1 x
V
DVDD
V
V
V
NL_I2C
V
DVDD
Noise Margin at the High Level for Each Connected
Device (Including Hysteresis)
0.2 x
0.2 x
V
DVDD
V
NH_I2C
V
DVDD
2
2
I C BUS CONTROLLER TIMING (ACTING AS I C SLAVE)
STANDARD MODE
FAST MODE
MIN MAX
3.60
PARAMETER
SYMBOL
UNITS
MIN
MAX
System Frequency
f
t
1
MHz
Hz
μs
μs
μs
μs
μs
μs
ns
ns
ns
μs
μs
pF
SYS
Operating Frequency
f
f
/8
f
/8
SYS
I2C
SYS
System Clock Period
1/f
1/f
I2C
SYS
I2C
SYS
SYS
SYS
SYS
0
Hold Time After (Repeated) START
Clock Low Period
t
3t
5t
3t
5t
3t
HD:STA
SYS
SYS
SYS
SYS
0
t
5t
3t
5t
LOW_I2C
Clock High Period
t
HIGH_I2C
Setup Time for Repeated START
Hold Time for Data
t
t
t
SU:STA
HD:DAT
SU:DAT
3.45
0.9
Setup Time for Data
250
100
SDA/SCL Fall Time
t
300
20 + 0.1C
20 + 0.1C
300
300
F_I2C
R_I2C
B
SDA/SCL Rise Time
t
1000
B
Setup Time for STOP
t
3t
5t
3t
5t
SU:STO
SYS
SYS
SYS
SYS
Bus-Free Time Between STOP and START
Capacitive Load for Each Bus Line
t
BUF
C
400
400
B
Noise Margin at the Low Level for Each Connected
Device (Including Hysteresis)
0.1 x
0.1 x
V
V
V
NL_I2C
V
DVDD
V
DVDD
Noise Margin at the High Level for Each Connected
Device (Including Hysteresis)
0.2 x
0.2 x
V
DVDD
V
NH_I2C
V
DVDD
______________________________________________________________________________________ 11
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
S
Sr
P
S
SDA
SCL
t
BUF
t
t
R_I2C
F_I2C
t
t
t
SU:STA
LOW
SU:DAT
MAXQ8913
t
t
HIGH
HD:STA
t
t
SU:STO
HD:DAT
NOTE: TIMING REFERENCED TO V
AND V
.
IH_I2C(MIN)
IL_I2C(MAX)
2
Figure 5. I C Timing Diagram
FS = V
REF
1 LSB = V /1024
ZS = 0
+FS = V /2
REF
1FF
1FE
3FF
3FE
3FD
-FS = -V /2
REF
REF
1 LSB = V /1024
REF
ZS = 0
001
000
3FF
004
003
002
001
000
201
200
FS - 0.5 LSB
-FS + 0.5 LSB
+FS - 0.5 LSB
1
2
3
4
FS
-FS
0
+FS
INPUT VOLTAGE (LSB)
INPUT VOLTAGE (LSB)
Figure 6. Single-Ended Unipolar Transfer Function
Figure 7. Differential Bipolar Transfer Function
12 ______________________________________________________________________________________
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
Block Diagram
OUTA
MAXQ20
16-BIT RISC
CORE
INA-
AIN2
AIN3
AIN4
AIN5
INA+
OUTB
INB-
DAC1
RIN+
RIN-
10-BIT
DAC
INB+
OUTC
INC-
DAC2
INC+
OUTD
IND-
LIN+
LIN-
10-BIT
DAC
IND+
REFA
1.5V
REFERENCE
SYNCIN
FAULT
SHDNR
SHDNL
CLASS
D-AMP
CONTROL
AVDD
AIN0
AIN1
REF
12-BIT
SAR DAC
AIN2
AIN3
AIN4
AIN5
AIN6
MUX
REG18
1.8V CORE
LDO REG
MAXQ8913
TEMP
SENSOR
AIN6
DVDD
DGND
AVDD
AGND
RST
POWER-ON
RESET,
BROWNOUT
MONITOR
AGND
WATCHDOG
TIMER
DAC3
SINK1
DAC4
SINK2
8-BIT DAC
8-BIT DAC
8-BIT
8-BIT
CURRENT SINK
CURRENT SINK
P0.0/INT0/TCK
P0.1/INT1/TDI
JTAG
P0.2/INT2/TMS
P0.3/INT3/TDO
P0.4/INT4/SSEL
P0.5/INT5/SCLK
P0.6/INT6/MOSI
P0.7/INT7/MISO
PORT 0
AND
INTERRUPT
4-WIRE
(SPI)
INTERFACE
FLASH
64KB
SRAM
4KB
2
I C
P1.0/INT8/SCL/TX
P1.1/INT9/SDA/RX
P1.2/INT10/TB0A
P1.3/INT11/TB0B
PORT 1
AND
INTERRUPT
UTILITY ROM
4KB
USART
CLOCK GENERATOR
RC OSC, HF CRYSTAL OSC,
1MHz RING OSC
HFXIN
HFXOUT
TIMER B
16 x 16
HARDWARE MULTIPLY
ACCUMULATE UNIT
______________________________________________________________________________________ 13
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
Pin Description
PIN
NAME
FUNCTION
POWER PINS
L4
M5
E4
B5
DVDD
DGND
AVDD
AGND
Digital Supply Voltage
Digital Ground
Analog Supply Voltage
Analog Ground
Regulator Output. This pin must be connected to ground through a 1.0μF capacitor. It provides the
1.8V internal regulated output. This pin is not meant to provide power externally.
K1
REG18
MAXQ8913
ANALOG MEASUREMENT PINS
Analog Voltage Reference. When using an external reference source, this pin must be connected to
1μF and a 0.01μF filter capacitors in parallel. When using an internal reference source, this pin must
be connected to a 0.01μF capacitor. The external reference can only be used for the ADC.
G2
REFA
Operational Amplifier A Noninverting Input. This analog input pin serves as the operational amplifier
A noninverting input.
A8
B7
B9
D3
A2
B3
E2
C2
B1
F1
INA+
INA-
Operational Amplifier A Inverting Input. This analog input pin serves as the operational amplifier A
inverting input.
Operational Amplifier A Output. This analog input pin serves as the operational amplifier A output.
This pin is also internally connected to the ADC input mux.
OUTA
INB+
INB-
Operational Amplifier B Noniverting Input. This analog input pin serves as the operational amplifier B
noninverting input.
Operational Amplifier B Inverting Input. This analog input pin serves as the operational amplifier B
inverting input.
Operational Amplifier B Output. This analog input pin serves as the operational amplifier B output.
This pin is also internally connected to the ADC input mux.
OUTB
INC+
INC-
Operational Amplifier C Noninverting Input. This analog input pin serves as the operational amplifier
C noninverting input.
Operational Amplifier C Inverting Input. This analog input pin serves as the operational amplifier C
inverting input.
Operational Amplifier C Output. This analog input pin serves as the operational amplifier C output.
This pin is also internally connected to the ADC input mux.
OUTC
IND+
IND-
Operational Amplifier D Noninverting Input. This analog input pin serves as the operational amplifier
A noninverting input.
Operational Amplifier D Inverting Input. This analog input pin serves as the operational amplifier D
inverting input.
F3
Operational Amplifier D Output. This analog input pin serves as the operational amplifier D output.
This pin is also internally connected to the ADC input mux.
D1
OUTD
H1
H3
C6
C4
A6
A4
AIN0
AIN1
ADC Input 0, 1. These two analog pins function as single-ended ADC inputs or a differential pair.
DAC3
DAC4
SINK1
SINK2
DAC3 Single-Ended Output
DAC4 Single-Ended Output
Programmable Current Sink 1
Programmable Current Sink 2
14 ______________________________________________________________________________________
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
Pin Description (continued)
PIN
C8
D7
E6
NAME
DAC1
DAC2
LIN+
LIN-
FUNCTION
DAC1 Buffer Output. Positive terminal of the differential DAC1’s output buffered signal.
DAC2 Buffer Output. Positive terminal of the differential DAC2’s output buffered signal.
DAC2 Output. Positive DAC output voltage to drive the left Class D amplifier.
DAC2 Output. Negative DAC output voltage to drive the left Class D amplifier.
DAC1 Output. Positive DAC output voltage to drive the right Class D amplifier.
DAC1 Output. Negative DAC output voltage to drive the right Class D amplifier.
RESET PIN
D9
H9
H7
RIN+
RIN-
Digital, Active-Low, Reset Input/Output. The CPU is held in reset when this pin is low and begins
executing from the reset vector when released. The pin includes a pullup current source and should
be driven by an open-drain external source capable of sinking in excess of 4mA. This pin is driven
low as an output when an internal reset condition occurs.
N6
RST
CLOCK PINS
High-Frequency Crystal Input. Connect an external crystal or resonator between HFXIN and HFXOUT
as the high-frequency system clock. Alternatively, HFXIN is the input for an external high-frequency
CMOS clock source when HFXOUT is floating.
M1
HFXIN
High-Frequency Crystal Output. Connect an external crystal or resonator between HFXIN and HFXOUT
J2
F9
HFXOUT as the high-frequency system clock. Alternatively, float HFXOUT when an external high-frequency
CMOS clock source is connected to the HFXIN pin.
SYNCIN Clock. This pin acts as the input clock to the Class D amplifier’s sawtooth generator.
SYNCIN
SYNCIN is a divided system clock with the divide ratio set by programmable bits.
GENERAL-PURPOSE I/O, SPECIAL FUNCTION PINS
P0.0 I/O with Interrupt or JTAG Test Clock. This pin defaults as an input with weak pullup after a reset
and functions as a general-purpose I/O with interrupt capability. Enabling the pin’s special function
disables the general-purpose I/O on the pin and makes the pin function as the test clock input. Note
that the JTAG function can be disabled using the TAP bit in the SC register.
P.0.0/INT0/
TCK
M9
L8
P0.1 I/O with Interrupt or JTAG Test Data In. This pin defaults as an input with a weak pullup after a
P0.1/INT1/ reset and functions as a general-purpose I/O with interrupt capability. Enabling the pin’s special
function disables the general-purpose I/O on the pin and makes the pin function as the test data
input. Note that the JTAG function can be disabled using the TAP bit in the SC register.
TDI
P0.2 I/O with Interrupt or JTAG Test Mode Select. This pin defaults as an input with a weak pullup
after a reset and functions as a general-purpose I/O with interrupt capability. Enabling the pin’s
special function disables the general-purpose I/O on the pin and makes the pin function as the test
mode select. Note that the JTAG function can be disabled using the TAP bit in the SC register. The
TMS should be gated high when JTAG is disabled.
P0.2/INT2/
TMS
K7
J6
P0.3 I/O with Interrupt or JTAG Test Data Out. This pin defaults as an input with a weak pullup after a
reset and functions as a general-purpose I/O with interrupt capability. The output function of the test
data is only enabled during the TAP’s Shift_IR or Shift_DR states. Enabling the pin's special function
disables the general-purpose I/O on the pin and makes the pin function as the test data output. Note
that the JTAG function can be disabled using the TAP bit in the SC register.
P0.3/INT3/
TDO
P0.4 I/O with Interrupt or SPI Chip Select. This port pin functions as a bidirectional I/O pin with interrupt
capability or as the SPI chip select. This port pin defaults to an input with a weak pullup after a reset
and functions as a general-purpose I/O. The port pad also contains a Schmitt input circuit.
P0.4/INT4/
SSEL
N8
P0.5 I/O with Interrupt or SPI Clock. This port pin functions as a bidirectional I/O pin with interrupt
capability or as the SPI clock. This port pin defaults to an input with a weak pullup after a reset and
functions as a general-purpose I/O. The port pad also contains a Schmitt input circuit.
P0.5/INT5/
SCLK
M7
______________________________________________________________________________________ 15
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
Pin Description (continued)
PIN
NAME
FUNCTION
P0.6 I/O with Interrupt or Master Out-Slave In. This port pin functions as a bidirectional I/O pin with
interrupt capability or as the SPI master out-slave in. This port pin defaults to an input with a weak
pullup after a reset and functions as a general-purpose I/O. The port pad also contains a Schmitt input
circuit.
P0.6/INT6/
MOSI
L6
P0.7 I/O with Interrupt or Master In-Slave Out. This port pin functions as a bidirectional I/O pin with
P0.7/INT7/ interrupt capability or as the SPI master in-slave out. This port pin defaults to an input with a weak
K5
N4
M3
K3
L2
pullup after a reset and functions as a general-purpose I/O. The port pad also contains a Schmitt input
circuit.
MISO
MAXQ8913
2
P1.0 I/O with Interrupt or I C Clock or USART Transmit. This pin defaults to an input with a weak
P1.0/INT8/ pullup after reset and functions as a general-purpose I/O with interrupt capability. The port pad
contains a Schmitt input circuit. Enabling the pin’s special function disables the general-purpose I/O
on the pin and enables the I C clock or USART transmitter function.
SCL/TX
2
2
P1.1 I/O with Interrupt or I C Data or USART Receive. This pin defaults to an input with a weak pullup
after reset and functions as a general-purpose I/O with interrupt capability. The port pad contains a
Schmitt input circuit. Enabling the pin’s special function disables the general-purpose I/O on the pin
and enables the I C data or USART receiver function.
P1.1/INT9/
SDA/RX
2
P1.2 I/O with Interrupt or Timer B0 Pin A. This pin defaults to an input with a weak pullup after reset
P1.2/INT10/ and functions as a general-purpose I/O. The port pad contains a Schmitt input circuit. Enabling the
pin’s special function disables the general-purpose I/O on the pin and enables the timer B pin A
function.
TB0A
P1.3 I/O with Interrupt or Timer B0 Pin B. This pin defaults to an input with a weak pullup after reset
and functions as a general-purpose I/O. The port pad contains a Schmitt input circuit. Enabling the
pin’s special function disables the general-purpose I/O on the pin and enables the timer B pin B
function.
P1.3/INT11/
TB0B
MISCELLANEOUS PINS
E8
G8
F7
SHDNL
SHDNR
FAULT
Shutdown for Left Motor Driver. Shutdown signal for the motor drivers.
Shutdown for Right Motor Driver. Shutdown signal for the motor drivers.
Fault Indicator. Thermal or short circuit fault indicator from the driver IC.
NO CONNECTION PINS
D5, F5, G6,
G4, H5, J4,
J8, K9, N2
N.C.
No Connection. Reserved for future use. Leave these pins unconnected.
16 ______________________________________________________________________________________
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
The 16-bit instruction word is designed for efficient exe-
Detailed Description
cution. Bit 15 indicates the format for the source field of
The following is an introduction to the primary features
the instruction. Bits 0 to 7 represent the source for the
of the microcontroller. More detailed descriptions of the
transfer. Depending on the value of the format field, this
device features can be found in the data sheets, errata
can be either an immediate value or a source register.
sheets, and user’s guides described later in the
If this field represents a register, the lower 4 bits con-
Additional Documentation section.
tain the module specifier and the upper 4 bits contain
the register index in that module. Bits 8 to 14 represent
MAXQ Core Architecture
the destination for the transfer. This value always repre-
The MAXQ core is a low-cost, high-performance,
sents a destination register, with the lower 4 bits con-
CMOS, fully static, 16-bit RISC microcontroller with
taining the module specifier and the upper 3 bits
flash memory. The MAXQ8913 supports 7 channels of
containing the register subindex within that module.
high-performance measurement using a 10-bit succes-
Any time that it is necessary to directly select one of the
sive approximation register (SAR) ADC with internal ref-
upper 24 registers as a destination, the prefix register,
erence. These parts are structured on a highly
PFX, is needed to supply the extra destination bits. This
advanced, accumulator-based, 16-bit RISC architec-
prefix register write is inserted automatically by the
ture. Fetch and execution operations are completed in
assembler and requires only one additional execution
one cycle without pipelining because the instruction
cycle.
contains both the op code and data. The result is a
streamlined microcontroller performing at up to 1 million
Memory Organization
instructions per second (MIPS) for each MHz of the sys-
The device incorporates several memory areas:
tem operating frequency.
• 4KB utility ROM
The highly efficient core is supported by a 16-level
• 64KB of flash memory for program storage
hardware stack, enabling fast subroutine calling and
task switching. Data can be quickly and efficiently
manipulated with three internal data pointers. Multiple
data pointers allow more than one function to access
data memory without having to save and restore data
pointers each time. The data pointers can automatically
increment or decrement following an operation, elimi-
nating the need for software intervention. As a result,
application speed is greatly increased.
• 4KB of SRAM for storage of temporary variables
• 16-level stack memory for storage of program return
addresses and general-purpose use
The incorporation of flash memory allows the devices to
be reprogrammed multiple times allowing modifications
to user applications post production. Additionally, the
flash can be used to store application information
including configuration data and log files.
Instruction Set
The default memory organization is organized as a
Harvard architecture, with separate address spaces for
program and data memory. Pseudo-Von Neumann
memory organization is supported through the utility
ROM for applications that require dynamic program
modification and execution from RAM. The pseudo-Von
Neumann memory organization places the code, data
and utility ROM memories into a single contiguous
memory map.
The instruction set is composed of fixed-length, 16-bit
instructions that operate on registers and memory loca-
tions. The instruction set is highly orthogonal, allowing
arithmetic and logical operations to use any register
along with the accumulator. Special function registers
control the peripherals and are subdivided into register
modules. The family architecture is modular so new
devices and modules can reuse code developed for
existing products.
Stack Memory
A 16-bit-wide hardware stack provides storage for pro-
gram return addresses and can also be used as gener-
al-purpose data storage. The stack is used
automatically by the processor when the CALL, RET,
and RETI instructions are executed and when an inter-
rupt is serviced. An application can also store values in
the stack explicitly by using the PUSH, POP, and POPI
instructions.
The architecture is transport triggered. This means that
writes or reads from certain register locations can also
cause side effects to occur. These side effects form the
basis for the higher level op codes defined by the
assembler, such as ADDC, OR, JUMP, etc. The op
codes are actually implemented as MOVE instructions
between certain register locations, while the assembler
handles the encoding, which need not be a concern to
the programmer.
______________________________________________________________________________________ 17
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
On reset, the stack pointer, SP, initializes to the top of
the stack (0Fh). The CALL, PUSH, and interrupt-vector-
ing operations increment SP, then store a value at the
location pointed to by SP. The RET, RETI, POP, and
POPI operations retrieve the value at SP and then
decrement SP.
reduce the life-cycle cost of the embedded system.
These features can be password protected to prevent
unauthorized access to code memory.
(Bootloader) In-System Programming
An internal bootstrap loader allows the device to be
reloaded over a simple JTAG interface. As a result,
software can be upgraded in-system, eliminating the
need for a costly hardware retrofit when updates are
required. Remote software updates enable application
updates to physically inaccessible equipment. The
interface hardware can be a JTAG connection to anoth-
er microcontroller or a connection to a PC serial port
using a serial-to-JTAG converter such as the
MAXQJTAG-001, available from Maxim. If in-system
programmability is not required, a commercial gang
programmer can be used for mass programming.
Utility ROM
The utility ROM is a 4KB block of internal ROM memory
that defaults to a starting address of 8000h. The utility
ROM consists of subroutines that can be called from
application software. These include the following:
MAXQ8913
• In-system programming (bootstrap loader) using
JTAG interface
• In-circuit debug routines
• Test routines (internal memory tests, memory loader,
etc.)
Activating the JTAG interface and loading the test
access port (TAP) with the system programming instruc-
tion invokes the bootstrap loader. Setting the SPE bit to
1 during reset through the JTAG interface executes the
bootstrap-loader mode program that resides in the utility
ROM. When programming is complete, the bootstrap
loader can clear the SPE bit and reset the device, allow-
ing the device to bypass the utility ROM and begin exe-
cution of the application software.
• User-callable routines for in-application flash pro-
gramming and fast table lookup
Following any reset, execution begins in the utility ROM.
The ROM software determines whether the program
execution should immediately jump to location 0000h,
the start of user-application code, or to one of the spe-
cial routines mentioned. Routines within the utility ROM
are user accessible and can be called as subroutines
by the application software. More information on the
utility ROM contents is contained in the MAXQ Family
User’s Guide: MAXQ8913 Supplement.
The following bootstrap loader functions are supported:
• Load
• Dump
• CRC
• Verify
• Erase
Some applications require protection against unautho-
rized viewing of program code memory. For these
applications, access to in-system programming, in-
application programming, or in-circuit debugging func-
tions is prohibited until a password has been supplied.
The password is defined as the 16 words of physical
program memory at addresses 0010h to 001Fh.
In-Application Programming
The in-application programming feature allows the
microcontroller to modify its own flash program memory
while simultaneously executing its application software.
This allows on the fly software updates in mission-criti-
cal applications that cannot afford downtime.
Alternatively, it allows the application to develop cus-
tom loader software that can operate under the control
of the application software. The utility ROM contains
user-accessible flash programming functions that erase
and program flash memory. These functions are
described in detail in the MAXQ Family User’s Guide:
MAXQ8913 Supplement.
A single password lock (PWL) bit is implemented in the
SC register. When the PWL is set to one (power-on
reset default) and the contents of the memory at
addresses 0010h to 001Fh are any value other than FFh
or 00h, the password is required to access the utility
ROM, including in-circuit debug and in-system pro-
gramming routines that allow reading or writing of inter-
nal memory. When PWL is cleared to zero, these
utilities are fully accessible without password. The
password is automatically set to all ones following a
mass erase.
Register Set
Programming
The flash memory of the microcontroller can be pro-
grammed by two different methods: in-system program-
ming and in-application programming. Both methods
afford great flexibility in system design as well as
Most functions of the device are controlled by sets of
registers. These registers provide a working space for
memory operations as well as configuring and address-
ing peripheral registers on the device. Registers are
18 ______________________________________________________________________________________
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
divided into two major types: system registers and
peripheral registers. The common register set, also
known as the system registers, includes the ALU, accu-
mulator registers, data pointers, interrupt vectors and
control, and stack pointer. The peripheral registers
define additional functionality that could be included by
different products based on the MAXQ architecture.
This functionality is broken up into discrete modules so
that only the features required for a given product need
to be included.
after timer rollover becomes effective during the fol-
lowing counter cycle.
Watchdog Timer
An internal watchdog timer greatly increases system
reliability. The timer resets the device if software execu-
tion is disturbed. The watchdog timer is a free-running
counter designed to be periodically reset by the appli-
cation software. If software is operating correctly, the
counter is periodically reset and never reaches its max-
imum count. However, if software operation is interrupt-
ed, the timer does not reset, triggering a system reset
and optionally a watchdog timer interrupt. This protects
the system against electrical noise or electrostatic dis-
charge (ESD) upsets that could cause uncontrolled
processor operation. The internal watchdog timer is an
upgrade to older designs with external watchdog
devices, reducing system cost and simultaneously
increasing reliability.
The module and register functions are covered fully in
the MAXQ Family User’s Guide and the MAXQ Family
User’s Guide: MAXQ8913 Supplement. This information
includes the locations of status and control bits and a
detailed description of their function and reset values.
Refer to this documentation for a complete understand-
ing of the features and operation of the microcontroller.
Programmable Timer
The microcontroller incorporates one instance of the
16-bit programmable timer/counter B peripheral. It can
be used in counter/timer/capture/compare/PWM func-
tions, allowing precise control of internal and external
events. The timer/counter supports clock input prescal-
ing and set/reset/toggle PWM/output control functionali-
ty not found on other MAXQ timer implementations. A
new register, TBC, supports PWM/output control func-
tions. A distinguishing characteristic of timer/counter B
is that its count ranges from 0000h to the value stored
in the 16-bit capture/reload register (TBR) counting up.
The timer/counter B timer is fully described in the
MAXQ Family User’s Guide: MAXQ8913 Supplement.
The watchdog timer is controlled through bits in the
WDCN register. Its timeout period can be set to one of
12
21
four programmable intervals ranging from 2 to 2
system clocks in its default mode, allowing flexibility to
support different types of applications. The interrupt
occurs 512 system clocks before the reset, allowing the
system to execute an interrupt and place the system in
a known, safe state before the device performs a total
system reset. At 10MHz, watchdog timeout periods can
be programmed from 410µs to 54s, depending on the
system clock mode.
Op Amps
The MAXQ8913 contains four uncommitted op amps. It
is electrically acceptable for op-amp outputs to exceed
the reference voltage, but they saturate the ADC code.
Gains and offsets introduced in the op-amp circuits
should be carefully set to maintain the outputs of the op
amps at or below the reference voltage if the ADC con-
verted values are expected to be unsaturated. The
device provides REFA as an output to aid in this
endeavor.
Timer B operational modes include the following:
• Autoreload
• Autoreload using external pin
• Capture using external pin
• Up/down count using external pin
• Up-count PWM/output
• Up/down PWM/output
The outputs of the op amps are internally connected to
ADC channels 2 to 5. Unused op amps should be con-
nected with their “+” input terminal grounded and the
output and “-” input terminals shorted together.
• Clock output on TBxB pin
• Up/down PWM mode with double-buffered output
mode:
• On interrupt, the user loads buffered output data,
which does not begin sending until current iteration
is completed. This enables a glitchless PWM
because there is no output pause while interrupt is
being serviced, and a race condition does not occur
in setting TBC before it is used. A TBC value written
Differential DAC and External
Class D Amplifier Output Stage
Operation
The power stage of the MAXQ8913 is designed to drive
a stereo Class D amplifier (DAMP). These amplifiers are
______________________________________________________________________________________ 19
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
suitable for driving self-commutating DC motors or
voice coil motors.
The DAMP FAULT bit goes high for at least 500ns fol-
lowing a thermal shutdown or current-limit event. It
stays low in shutdown and is glitch-free during power-
up. FAULT interrupts the microcontroller if enabled.
Alternatively, the firmware can poll the bit periodically to
detect faults of the type previously described.
Each external DAMP is differentially driven by a 10-bit
DAC. The DAC output common mode is 1.25V, based
on the bandgap reference, and each differential output
can swing from GND to 2.5V (if V
≥ 3V), so the
DVDD
effective differential peak-to-peak voltage is 5V. The
DAMP has a 6dB gain, so its ouput can swing 10V (if
DAMP supply = 5V).
DAC1 and DAC2 Buffers
While the MAXQ8913 contains power drivers for the
actuator, the positive terminal of each differential DAC
output pair is buffered and available as an output pin.
This feature is intended primarily for test, and no signifi-
cant load should be added to the DAC1 and DAC2
pins. The specifications for these pins are not yet deter-
mined, except for the no-load output voltage, which is
expected to be between GND and 2.5V.
The differential output voltage follows the simple formula:
MAXQ8913
V
DIFF
= 2.5 x (code - 512)/512V
There are four Class D amplifier control bits and one
status bit. The SHDNR and SHDNL pins are the active-
high shutdown controls for the two Class D amplifiers,
respectively. The SYNCIN_DIV bits control the input
clock to the Class D amplifier sawtooth generator. The
SYNCIN frequency must fall within 2MHz and 2.8MHz.
The optimal frequency is 2.2MHz. The frequency of the
high-frequency oscillator and the divide ratio need to
be chosen wisely to accomodate this requirement. For
example, if a 9MHz crystal is used, a divide-by-4 ratio
produces a SYNCIN frequency of 2.25MHz.
DAC3 and DAC4
DAC3 and DAC4 are single-ended DACs. Their outputs
are intended for driving the positive terminal (through a
resistor) of single-supply op amps to force the virtual
GND to a value that allows the op amp to operate
below and above the virtual ground DC value.
Operated in this fashion, the DACs can also serve as
offset cancellation devices as necessary.
Table 1 shows the divide ratio applied to the high-fre-
quency oscillator output based on the value of
SYNCIN_DIV.
SINK1 and SINK2
Popular optical-image stabilization implementations
include the use of Hall-effect elements for position feed-
back. Hall-effect elements require a current to flow
through two of its terminals for proper operation. The
device includes two current sinks intended to drive
these elements. The current sinks are programmable
between 0 and 15.94mA with 62.5mA resolution
through an 8-bit code. Code 0 turns them off.
Table 1. SYNCIN Divisor vs. SYNCIN_DIV
Value
SYNCIN_DIV
HF DIVIDED BY
0 (default)
SYNCIN clock off
1
2
3
2
3
4
When operating Hall-effect elements from 3V, the maxi-
mum achievable current is given by (3V - 0.5V)/R
,
HALL
where 0.5V is the minimum voltage value at the input of
To start operating the DACs and DAMPs, the following
procedural steps should be followed:
the current sink. For example, if R
maximum current is 10mA.
= 250Ω, the
HALL
1) Set both DAC inputs to code 512.
If higher currents are desirable, the user must provide a
larger supply voltage to the Hall-effect element. In this
case, care must be exercised so that the output nodes
2) Enable the SYNCIN clock by setting an appropriate
value for SYNCIN_DIV.
of the Hall-effect element do not exceed V
.
AVDD
3) Wait 100µs. Clear the SHDNR and SHDNL bits.
4) Wait 100µs.
Exceeding V
could cause the input-protection
AVDD
diodes of the op-amp terminals to begin conduction
and waste power when the device is in sleep mode. If
One or both DAMPs can be shut down at any time by
setting the corresponding SHDN bit. If both DAMPs are
shut down, the firmware should disable the SYNCIN
signal.
supplying a voltage larger than V
to the Hall-effect
AVDD
element, a switchable supply is recommended to avoid
the leakage path identified above.
20 ______________________________________________________________________________________
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
MAXQ8913
Additional Documentation
Development and Technical
Support
A variety of highly versatile, affordably priced develop-
ment tools for this microcontroller are available from
Maxim and third-party suppliers, including:
Designers must have four documents to fully use all the
features of this device. This data sheet contains pin
descriptions, feature overviews, and electrical specifi-
cations. Errata sheets contain deviations from pub-
lished specifications. The user’s guides offer detailed
information about device features and operation.
• Compilers
• In-circuit emulators
• This MAXQ8913 data sheet, which contains electri-
cal/timing specifications and pin descriptions.
• Integrated development environments (IDEs)
• The MAXQ8913 errata sheet for the specific device
• JTAG-to-serial converters for programming and
debugging.
revision, available at www.maxim-ic.com/errata.
• The MAXQ Family User's Guide, which contains
detailed information on core features and operation,
including programming. This document is available
on our website at www.maxim-ic.com/MAXQUG.
A partial list of development tool vendors can be found
at www.maxim-ic.com/MAXQ_tools.
For technical support, go to https://support.maxim-
ic.com/micro.
• The MAXQ Family User's Guide: MAXQ8913
Supplement, which contains detailed information on
features specific to the MAXQ8913.
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
21-0220
58 WLP
W584B2+1
______________________________________________________________________________________ 21
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
Pin Configuration
MAXQ8913
TOP VIEW
1
2
3
4
5
6
7
8
9
+
A
B
C
D
E
INB-
SINK2
SINK1
INA+
MAXQ8913
OUTC
OUTD
IND+
OUTB
INB+
IND-
AIN1
AGND
N.C.
N.C.
N.C.
INA-
DAC2
FAULT
RIN-
OUTA
LIN-
INC-
INC+
DAC4
AVDD
N.C.
DAC3
LIN+
N.C.
DAC1
SHDNL
SHDNR
N.C.
F
SYNCIN
RIN+
G
H
J
REFA
AIN0
P0.3/
INT3/
TDO
HFXOUT
N.C.
P1.2/
INT10/
TBOA
P0.7/
INT7/
MISO
P0.2/
INT2/
TMS
K
L
REG18
HFXIN
N.C.
P1.3/
INT11/
TB0B
P0.6/
INT6/
MOSI
P0.1/
INT1/
TDI
DVDD
P1.1/
INT9/SDA/
RX
P0.5/
INT5/
SCLK
P0.0/
INT0/
TCK
M
N
DGND
P1.0/
INT8/SCL/
TX
P0.4/
INT4/
SSEL
N.C.
RST
WLP
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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