MAX9312EGJ [MAXIM]
Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), CQCC32, 5 X 5 MM, 0.90 MM HEIGHT, QFN-32;
| 型号： | MAX9312EGJ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), CQCC32, 5 X 5 MM, 0.90 MM HEIGHT, QFN-32 驱动 逻辑集成电路 |
| 文件： | 总11页 (文件大小：332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2079; Rev 1; 2/02
Dual 1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
General Description
Features
The MAX9312/MAX9314 are low skew, dual 1-to-5 dif-
ferential drivers designed for clock and data distribu-
tion. These devices accept two inputs. Each input is
reproduced at five differential outputs. The differential
inputs can be adapted to accept single-ended inputs
ꢀ +2.25V to +3.8V Differential HSTL/LVPECL
Operation
ꢀ -2.25V to -3.8V Differential LVECL Operation
ꢀ 30ps (typ) Part-to-Part Skew
by connecting the on-chip V supply to one input as a
BB
ꢀ 12ps (typ) Output-to-Output Skew
ꢀ 312ps (typ) Propagation Delay
ꢀ ≥ 300mV Differential Output at 3GHz
ꢀ On-Chip Reference for Single-Ended Inputs
ꢀ Output Low with Open Input
reference voltage.
The MAX9312/MAX9314 feature low part-to-part skew
(30ps) and output-to-output skew (12ps), making them
ideal for clock and data distribution across a backplane
or a board. For interfacing to differential HSTL and
LVPECL signals, these devices operate over a +2.25V
to +3.8V supply range, allowing high-performance
clock or data distribution in systems with a nominal
+2.5V or +3.3V supply. For differential LVECL opera-
tion, these devices operate from a -2.25V to -3.8V sup-
ply.
ꢀ Pin Compatible with MC100LVEP210 (MAX9312)
and MC100EP210 (MAX9314)
ꢀ Offered in Tiny QFN* Package (70% Smaller
Footprint than LQFP)
The MAX9312 features an on-chip V reference output
BB
of 1.425V below the positive supply voltage. The
Ordering Information
MAX9314 offers an on-chip V
reference output of
BB
PART
TEMP. RANGE
PIN-PACKAGE
1.32V below the positive supply voltage.
MAX9312ECJ
-40°C to +85°C
32 TQFP (7mm ✕ 7mm)
32 QFN (5mm ✕ 5mm)
32 TQFP (5mm ✕ 5mm)
32 TQFP (7mm ✕ 7mm)
32 QFN (5mm ✕ 5mm)
32 TQFP (5mm ✕ 5mm)
Both devices are offered in space-saving, 32-pin 5mm ✕
5mm TQFP, 5mm x 5mm QFN, and industry-standard
32-pin 7mm ✕ 7mm TQFP packages.
MAX9312EGJ* -40°C to +85°C
MAX9312EHJ* -40°C to +85°C
Applications
MAX9314ECJ
-40°C to +85°C
MAX9314EGJ* -40°C to +85°C
MAX9314EHJ* -40°C to +85°C
Precision Clock Distribution
Low-Jitter Data Repeater
*Future product—contact factory for availability.
Functional Diagram
QB0
QA0
V
CC
V
CC
QB0
QB1
QA0
QA1
75kΩ
75kΩ
QB1
QB2
QA1
QA2
CLKB
CLKB
CLKA
CLKA
QB2
QB3
QA2
QA3
75kΩ
75kΩ
75kΩ
75kΩ
QB3
QB4
QA3
QA4
V
EE
V
EE
V
EE
V
EE
V
BB
QB4
QA4
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual 1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
ABSOLUTE MAXIMUM RATINGS
V
- V ...............................................................................4.1V
Junction-to-Case Thermal Resistance
32-Pin 7mm 7mm TQFP..........................................+12°C/W
CC
EE
✕
Inputs (CLK_, CLK_).............................V - 0.3V to V
+ 0.3V
EE
CC
CLK_ to CLK_ .................................................................... 3.0V
Continuous Output Current.................................................50mA
Surge Output Current........................................................100mA
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-ꢁ5°C to +150°C
ESD Protection
V
Sink/Source Current ............................................... 0.ꢁ5mA
BB
Junction-to-Ambient Thermal Resistance in Still Air
32-Pin 7mm 7mm TQFP..........................................+90°C/W
Human Body Model (CLK_, CLK_, Q_, Q_) ........................2kV
Soldering Temperature (10s)...........................................+300°C
✕
Junction-to-Ambient Thermal Resistance with
500 LFPM Airflow
✕
32-Pin 7mm 7mm TQFP..........................................+ꢁ0°C/W
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
- V = +2.25V to +3.8V, outputs loaded with 50Ω 1ꢀ to V
- 2V.) (Notes 1–4)
CC
EE
CC
-40°C
+25°C
+85°C
PARAMETER
SYMBOL
CONDITIONS
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
_
INPUTS (CLK_, CLK )
V
BB
V
1.23
-
-
V
1.23
-
V
CC
1.23
-
CC
CC
MAX9312
MAX9314
MAX9312
MAX9314
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
connected
to CLK_
(V for V
connected
to CLK_)
Single-Ended
Input High
Voltage
V
V
IH
IL
BB
V
V
-
V
-
CC
CC
CC
1.165
1.165
1.165
V
BB
V
-
V
-
V
-
CC
CC
CC
V
V
V
V
V
V
EE
EE
EE
EE
EE
EE
connected
to CLK_
(V for V
connected
to CLK_)
1.62
1.62
1.62
Single-Ended
Input Low
Voltage
V
V
IL
IL
BB
V
-
V
-
V
-
CC
CC
CC
1.475
1.475
1.475
High Voltage of
Differential Input
V
+
1.2
V
+
1.2
V
+
EE
1.2
EE
EE
V
V
V
V
CC
V
V
IHD
CC
CC
Low Voltage of
Differential Input
V
-
V
-
V
-
CC
CC
CC
V
V
V
V
EE
ILD
EE
EE
0.095
0.095
0.095
V
V
-
V
V
-
V
V
EE
-
CC
CC
CC
For V
For V
- V < 3.0V
0.095
0.095
0.095
0.095
0.095
0.095
CC
CC
EE
Differential Input
Voltage
V
V
-
IHD
V
EE
EE
ILD
- V ≥ 3.0V
EE
3.0
3.0
3.0
Input High
Current
I
150
150
150
µA
µA
IH
CLK_ Input Low
Current
I
-10
+10
-10
+10
-10
+10
ILCLK
2
_______________________________________________________________________________________
Dual 1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
- V = +2.25V to +3.8V, outputs loaded with 50Ω 1ꢀ to V
- 2V.) (Notes 1–4)
EE
CC
-40°C
+25°C
+85°C
PARAMETER
SYMBOL
CONDITIONS
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
CLK_ Input Low
Current
I
-150
-150
-150
µA
ILCLK
__
)
OUTPUTS (Q__, Q
Single-Ended
Output High
Voltage
V
-
V
-
V
-
V
-
V
-
V
-
CC
CC
CC
CC
CC
CC
V
Figure 1
V
OH
1.025
0.900
1.025
0.900
1.025
0.900
Single-Ended
Output Low
Voltage
V
-
V
-
V
-
V
-
V
-
V
-
CC
CC
CC
CC
CC
CC
V
Figure 1
Figure 1
V
OL
- V
-1.930
1.695
-1.930
1.695
-1.930
1.695
Differential
V
670
950
670
950
670
950
mV
OH
OL
Output Voltage
REFERENCE (V
)
BB
V
-
V
-
V
-
V
-
V
-
V
-
CC
CC
CC
CC
CC
CC
MAX9312
MAX9314
Reference
Voltage Output
(Note 5)
1.525
1.325
1.525
1.325
1.525
1.325
I
=
BB
V
V
BB
0.5mA
V
1.38
-
V
1.26
-
V
1.38
-
V
1.26
-
V
1.38
-
V
1.26
-
CC
CC
CC
CC
CC
CC
POWER SUPPLY
Supply Current
(Note 6)
I
75
82
95
mA
EE
_______________________________________________________________________________________
3
Dual 1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
AC ELECTRICAL CHARACTERISTICS
(V
- V = +2.25V to +3.8V, outputs loaded with 50Ω 1ꢀ to V
- 2V, input frequency = 1.5GHz, input transition time = 125ps
CC
EE
CC
- 0.15V, V
(20ꢀ to 80ꢀ), V
= V + 1.2V to V , V
= V to V
- V
= 0.15V to the smaller of 3V or V - V , unless oth-
CC EE
IHD
EE
CC ILD
EE
CC
IHD
ILD
erwise noted. Typical values are at V - V = 3.3V, V
= V - 1V, V = V - 1.5V.) (Note 7)
CC
EE
IHD
CC ILD CC
-40°C
+25°C
+85°C
TYP MAX
PARAMETER
SYMBOL
CONDITIONS
Figure 2
UNITS
MIN
TYP MAX MIN
TYP MAX MIN
Differential Input-
to-Output Delay
t ,
PLHD
220
321
12
380
46
220
312
12
410
46
260
322
10
400
35
ps
ps
ps
t
PHLD
Output-to-Output
Skew (Note 8)
t
SKOO
Part-to-Part Skew
(Note 9)
t
30
160
30
190
30
140
SKPP
f
= 1.5GHz
IN
1.2
1.2
2.5
2.6
1.2
1.2
2.5
2.6
1.2
1.2
2.5
2.6
clock pattern
Added Random
Jitter (Note 10)
ps
(RMS)
t
RJ
f
IN
= 3.0GHz
clock pattern
Added
Deterministic
Jitter (Note 10)
3Gbps,
223 -1 PRBS pattern
ps
(pk-pk)
t
80
95
80
95
80
95
DJ
V
- V ≥ 300mV,
OL
OH
3.0
3.0
3.0
clock pattern, Figure 2
Switching
Frequency
f
GHz
ps
MAX
V
- V ≥ 500mV,
OH
OL
1.5
1.5
1.5
clock pattern, Figure 2
Output Rise/Fall
Time (20ꢀ to 80ꢀ)
t , t
R
Figure 2
100
112
140
100
116
140
100
121
140
F
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: Single-ended input operation using V is limited to V
- V = 3.0V to 3.8V for the MAX9312 and V
- V = 2.7V to
CC EE
BB
CC
EE
3.8V for the MAX9314.
Note 4: DC parameters production tested at T = +25°C. Guaranteed by design and characterization over the full operating temper-
A
ature range.
Note 5: Use V only for inputs that are on the same device as the V reference.
BB
BB
Note 6: All pins open except V
and V .
EE
CC
Note 7: Guaranteed by design and characterization limits are set at 6 sigma.
Note 8: Measured between outputs on the same part at the signal crossing points for a same-edge transition.
Note 9: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition.
Note 10:Device jitter added to the input signal.
4
_______________________________________________________________________________________
Dual 1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
Typical Operating Characteristics
(V
CC
= +3.3V, V = 0, V
= V
- 0.95V, V
= V - 1.25V, input transition time = 125ps (20ꢀ to 80ꢀ), f = 1.5GHz, outputs
EE
IHD
CC
ILD
CL
IN
loaded with 50Ω to V
- 2V, T = +25°C, unless otherwise noted.)
CC
A
OUTPUT AMPLITUDE (V - V
OH
)
OL
SUPPLY CURRENT, I
vs. TEMPERATURE
EE
TRANSITION TIME vs. TEMPERATURE
vs. FREQUENCY
80
75
70
65
60
55
50
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
130
125
120
115
110
105
100
95
t
R
t
F
90
-40
-15
10
35
60
85
0
1000
2000
3000
-40
-15
10
35
60
85
TEMPERATURE (°C)
FREQUENCY (MHz)
TEMPERATURE (°C)
PROPAGATION DELAY vs.
SINGLE-ENDED HIGH VOLTAGE OF
DIFFERENTIAL INPUT (V
PROPAGATION DELAY vs. TEMPERATURE
)
IHD
340
320
300
280
306
304
302
300
298
296
294
292
290
288
V
= V - 0.95V
CC
CC
V -V = 150mV
IHD ILD
IHD
V
ILD
= V - 1.1V
t
PLHD
t
PLHD
t
t
PHLD
PHLD
3.8
1.0
1.4 1.8 2.2 2.6 3.0 3.4
(V)
-40
-15
10
35
60
85
V
IHD
TEMPERATURE (°C)
_______________________________________________________________________________________
5
Dual 1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
Pin Description
PIN
NAME
FUNCTION
Positive Supply Voltage. Bypass from V
to V with 0.1µF and 0.01µF ceramic capacitors.
CC
EE
Place the capacitors as close to the device as possible with the smaller value capacitor closest to
the device.
1, 9, 16, 25, 32
V
CC
2
3
4
N.C.
CLKA
CLKA
Not Connected
Noninverting Differential Clock Input A
Inverting Differential Clock Input A
Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a
reference for single-ended operation. When used, bypass to V with a 0.01µF ceramic
CC
5
V
BB
capacitor.
6
CLKB
Noninverting Differential Clock Input B
Inverting Differential Clock Input B
Negative Supply Voltage
7
CLKB
8
V
EE
10
11
12
13
14
15
17
18
19
20
21
22
23
24
26
27
28
29
30
31
QB4
QB4
QB3
QB3
QB2
QB2
QB1
QB1
QB0
QB0
QA4
QA4
QA3
QA3
QA2
QA2
QA1
QA1
QA0
QA0
Inverting QB4 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting QB4 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Inverting QB3 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting QB3 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Inverting QB2 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting QB2 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Inverting QB1 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting QB1 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Inverting QB0 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting QB0 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Inverting QA4 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting QA4 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Inverting QA3 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting QA3 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Inverting QA2 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting QA2 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Inverting QA1 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting QA1 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Inverting QA0 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting QA0 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
6
_______________________________________________________________________________________
Dual 1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
This limit also applies to the difference between any ref-
Detailed Description
erence voltage input and a single-ended input.
The MAX9312/MAX9314 are low-skew, dual 1-to-5 differ-
The differential inputs have bias resistors that drive the
outputs to a differential low when the inputs are open.
The inverting inputs (CLKA and CLKB) are biased with a
ential drivers designed for clock and data distribution.
For interfacing to differential HSTL and LVPECL signals,
these devices operate over a +2.25V to +3.8V supply
range, allowing high-performance clock or data distribu-
tion in systems with a nominal +2.5V or +3.3V supply.
For differential LVECL operation, these devices operate
from a -2.25V to -3.8V supply.
75kΩ pullup to V
and a 75kΩ pulldown to V . The
EE
CC
noninverting inputs (CLKA and CLKB) are biased with a
75kΩ pulldown to V
.
EE
Specifications for the high and low voltages of a differen-
tial input (V and V ) and the differential input volt-
IHD
ILD
The differential inputs can be configured to accept sin-
age (V
- V ) apply simultaneously (V
cannot be
IHD
ILD
ILD
gle-ended inputs when operating at approximately V
-
CC
higher than V ).
IHD
V
EE
= 3.0V to 3.8V for the MAX9312 or V
- V = 2.7V
CC EE
Output levels are referenced to V
and are considered
CC
to 3.8V for the MAX9314. This is accomplished by con-
LVPECL or LVECL, depending on the level of the V
CC
necting the on-chip reference voltage, V , to an input
BB
supply. With V
EE
outputs are LVECL when V
connected to a positive supply and
CC
as a reference. For example, the differential CLKA, CLKA
V
connected to GND, the outputs are LVPECL. The
input is converted to a noninverting, single-ended input
is connected to GND and
CC
by connecting V
to CLKA and connecting the single-
BB
V
is connected to a negative supply.
EE
ended input to CLKA. Similarly, an inverting input is
obtained by connecting V to CLKA and connecting
BB
A single-ended input of at least V
95mV or a differen-
BB
the single-ended input to CLKA. With a differential input
configured as single ended (using V ), the single-
tial input of at least 95mV switches the outputs to the
and V levels specified in the DC Electrical
BB
V
OH
OL
ended input can be driven to V
and V or with a sin-
CC
EE
Characteristics table.
gle-ended LVPECL/LVECL signal.
When a differential input is configured as a single-ended
input (using V ), the approximate supply range is V
Applications Information
-
CC
EE
BB
Supply Bypassing
to V with high-frequency surface-mount
V
EE
= 3.0V to 3.8V for the MAX9312 and V
- V
=
CC
Bypass V
CC
EE
2.7V to 3.8V for the MAX9314. This is because one of the
inputs must be V + 1.2V or higher for proper operation
ceramic 0.1µF and 0.01µF capacitors in parallel as close
to the device as possible, with the 0.01µF value capaci-
tor closest to the device. Use multiple parallel vias for
EE
of the input stage. V
must be at least V
+ 1.2V
EE
BB
because it becomes the high-level input when the other
(single-ended) input swings below it. Therefore, mini-
low inductance. When using the V
reference output,
BB
bypass it with a 0.01µF ceramic capacitor to V
(if the
CC
mum V = V + 1.2V.
BB
EE
V
BB
reference is not used, it can be left open).
The minimum V
output for the MAX9312 is V
-
CC
BB
Traces
1.525V and the minimum V output for the MAX9314 is
BB
Input and output trace characteristics affect the perfor-
mance of the MAX9312/MAX9314.
V
- 1.38V. Substituting the minimum V
output for
CC
BB
each device into V = V + 1.2V results in a minimum
BB
EE
Connect each signal of a differential input or output to a
50Ω characteristic impedance trace. Minimize the num-
ber of vias to prevent impedance discontinuities. Reduce
reflections by maintaining the 50Ω characteristic imped-
ance through connectors and across cables. Reduce
skew within a differential pair by matching the electrical
length of the traces.
supply of 2.725V for the MAX9312 and 2.58V for the
MAX9314. Rounding up to standard supplies gives the
single-ended operating supply ranges of V
- V
=
CC
EE
3.0V to 3.8V for the MAX9312 and V
3.8V for the MAX9314.
- V = 2.7V to
CC
EE
When using the V
reference output, bypass it with a
BB
0.01µF ceramic capacitor to V . If the V reference is
CC
BB
not used, it can be left open. The V
source or sink 0.5mA, which is sufficient to drive two
reference can
BB
Output Termination
Terminate outputs through 50Ω to V
- 2V or use an
CC
inputs. Use V
only for inputs that are on the same
BB
equivalent Thevenin termination. When a single-ended
signal is taken from a differential output, terminate both
outputs. For example, if QA0 is used as a single-ended
output, terminate both QA0 and QA0.
device as the V reference.
BB
The maximum magnitude of the differential input from
CLK_ to CLK_ is 3.0V or V
- V , whichever is less.
EE
CC
_______________________________________________________________________________________
7
Dual 1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
CLK_
V
IH
CLK_
V
BB
V
IL
(CONNECTED TO CLK_)
V
Q_
Q_
OH
V - V
OH OL
V
OL
Figure 1. Switching with Single-Ended Input
CLK_
CLK_
V
IHD
V
V
IHD - ILD
V
ILD
t
t
PHLD
PLHD
Q_
Q_
V
OH
V
V
OH - OL
V
OL
80%
0 (DIFFERENTIAL)
80%
0 (DIFFERENTIAL)
20%
20%
(Q_) - (Q_)
t
R
t
F
Figure 2. Differential Transition Time and Propagation Delay Timing Diagram
Pin Configuration
Chip Information
TRANSISTOR COUNT: 250
TOP VIEW
V
CC
QA0 QA0 QA1 QA1 QA2 QA2
V
CC
32 31 30 29 28 27 26 25
V
1
2
3
4
5
6
7
8
24 QA3
QA3
23
CC
N.C.
CLKA
CLKA
22 QA4
21 QA4
20 QB0
19 QB0
18 QB1
MAX9312
MAX9314
V
BB
CLKB
CLKB
V
17
QB1
EE
9
10 11 12 13 14 15 16
QB4 QB4 QB3 QB3 QB2 QB2
V
V
CC
CC
×
×
TQFP (7mm 7mm), TQFP (5mm 5mm),
QFN (NO LEADS EXTENDING FROM QFN PACKAGE)
8
_______________________________________________________________________________________
Dual 1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
Package Information
_______________________________________________________________________________________
9
Dual 1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
Package Information (continued)
10 ______________________________________________________________________________________
Dual 1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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