MAX9313ECJ+ [MAXIM]
Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, LQFP-32;
| 型号： | MAX9313ECJ+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总12页 (文件大小：369K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2078; Rev 2; 10/02
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
General Description
Features
The MAX9311/MAX9313 are low-skew, 1-to-10 differen-
tial drivers designed for clock and data distribution.
These devices allow selection between two inputs. The
selected input is reproduced at 10 differential outputs.
The differential inputs can be adapted to accept single-
ꢀ +2.25V to +3.8V Differential HSTL/LVPECL
Operation
ꢀ -2.25V to -3.8V LVECL Operation
ꢀ 30ps (typ) Part-to-Part Skew
ꢀ 12ps (typ) Output-to-Output Skew
ꢀ 312ps (typ) Propagation Delay
ꢀ ≥ 300mV Differential Output at 3GHz
ꢀ On-Chip Reference for Single-Ended Inputs
ꢀ Output Low with Open Input
ended inputs by connecting the on-chip V
one input as a reference voltage.
supply to
BB
The MAX9311/MAX9313 feature low part-to-part skew
(30ps) and output-to-output skew (12ps), making them
ideal for clock and data distribution across a backplane
or a board. For interfacing to differential HSTL and
LVPECL signals, these devices operate over a +2.25V
to +3.8V supply range, allowing high-performance clock
or data distribution in systems with a nominal +2.5V or
+3.3V supply. For differential LVECL operation, these
devices operate from a -2.25V to -3.8V supply.
ꢀ Pin Compatible with MC100LVEP111 (MAX9311)
and MC100EP111 (MAX9313)
ꢀ Offered in Tiny QFN* Package (70% Smaller
The MAX9311 features an on-chip V reference output
BB
of 1.425V below the positive supply voltage. The
Footprint than LQFP)
MAX9313 offers an on-chip V
reference output of
BB
Ordering Information
1.32V below the positive supply voltage.
PART
TEMP. RANGE
PIN-PACKAGE
Both devices are offered in space-saving, 32-pin 5mm ✕
5mm TQFP, 5mm x 5mm QFN, and industry-standard
32-pin 7mm x 7mm LQFP packages.
MAX9311ECJ
-40°C to +85°C
32 LQFP (7mm ✕ 7mm)
32 QFN (5mm ✕ 5mm)
32 TQFP (5mm ✕ 5mm)
32 LQFP (7mm ✕ 7mm)
32 QFN (5mm ✕ 5mm)
32 TQFP (5mm ✕ 5mm)
MAX9311EGJ* -40°C to +85°C
MAX9311EHJ*
MAX9313ECJ
MAX9313EGJ*
MAX9313EHJ*
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Applications
Precision Clock Distribution
Low-Jitter Data Repeater
*Future product—contact factory for availability.
Pin Configuration
TOP VIEW
V
Q0 Q0 Q1 Q1 Q2 Q2
V
CC
CC
32 31 30 29 28 27 26 25
V
1
2
3
4
5
6
7
8
24 Q3
Q3
CC
×
×
CLKSEL
CLK0
23
LQFP (7mm 7mm), TQFP (5mm 5mm),
QFN (NO LEADS EXTENDING FROM QFN PACKAGE)
22 Q4
21 Q4
20 Q5
19 Q5
18 Q6
17 Q6
MAX9311/MAX9313
CLK0
MAX9311
MAX9313
CLKSEL CLK0, CLK0 CLK1, CLK1
V
BB
0
1
ON
OFF
ON
CLK1
CLK1
OFF
V
EE
9
10 11 12 13 14 15 16
Q9 Q9 Q8 Q8 Q7 Q7
V
V
CC
CC
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
ABSOLUTE MAXIMUM RATINGS
V
- V ...............................................................................4.1V
Junction-to-Case Thermal Resistance
CC
EE
Inputs (CLK_, CLK_, CLKSEL)..............V - 0.3V to V
+ 0.3V
7mm x 7mm LQFP .....................................................+12°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-ꢁ5°C to +150°C
ESD Protection
EE
CC
CLK_ to CLK_ .................................................................... 3.0V
Continuous Output Current.................................................50mA
Surge Output Current........................................................100mA
V
Sink/Source Current ............................................... 0.ꢁ5mA
BB
Junction-to-Ambient Thermal Resistance in Still Air
7mm x 7mm LQFP .....................................................+90°C/W
Junction-to-Ambient Thermal Resistance with
500 LFPM Airflow
Human Body Model (CLKSEL, CLK_, CLK_,
Q_, Q_, V ).......................................................................2kV
BB
Soldering Temperature (10s)...........................................+300°C
7mm x 7mm LQFP .....................................................+ꢁ0°C/W
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V - V = +2.25V to +3.8V, outputs loaded with 50Ω 1ꢀ to V - 2V, CLKSEL = high or low, unless otherwise noted.) (Notes 1–4)
CC
EE
CC
-40°C
+25°C
+85°C
PARAMETER
SYMBOL
CONDITIONS
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
SINGLE-ENDED INPUT (CLKSEL)
V
V
V
CC
- 1.23
CC
CC
MAX9311
MAX9313
MAX9311
MAX9313
V
V
V
CC
CC
CC
Internal
- 1.23
- 1.23
Input High
Voltage
V
V
V
V
IH
BB
V
V
V
CC
- 1.165
CC
CC
threshold
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
- 1.165
- 1.165
V
V
V
V
V
V
EE
EE
EE
EE
EE
EE
Internal
- 1.62
- 1.62
- 1.62
Input Low
Voltage
V
V
BB
IL
V
V
V
CC
- 1.475
CC
CC
threshold
- 1.475
- 1.475
Input High
Current
I
150
150
150
µA
µA
IH
Input Low
Current
I
-10
+10
-10
+10
-10
+10
IL
DIFFERENTIAL INPUTS (CLK_, CLK_)
V
BB
V
V
V
CC
- 1.23
CC
CC
connected
to CLK_
(V for V
connected
to CLK_),
Figure 1
MAX9311
MAX9313
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
Single-Ended
Input High
Voltage
- 1.23
- 1.23
V
V
IH
IL
BB
V
V
V
CC
- 1.165
CC
CC
- 1.165
- 1.165
2
_______________________________________________________________________________________
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
DC ELECTRICAL CHARACTERISTICS (continued)
(V - V = +2.25V to +3.8V, outputs loaded with 50Ω 1ꢀ to V - 2V, CLKSEL = high or low, unless otherwise noted.) (Notes 1–4)
CC
EE
CC
-40°C
+25°C
+85°C
PARAMETER
SYMBOL
CONDITIONS
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
V
BB
V
V
V
CC
-1.62
CC
CC
connected
to CLK_
(V for V
connected
to CLK_),
Figure 1
MAX9311
MAX9313
V
V
V
V
V
V
EE
EE
EE
Single-Ended
Input Low
Voltage
- 1.62
- 1.62
V
V
IL
IH
BB
V
V
V
CC
-1.475
CC
CC
EE
EE
EE
- 1.475
- 1.475
High Voltage
of Differential
Input
V
V
+1.2
V
V
+ 1.2
V
V
+1.2
V
V
V
V
IHD
EE
V
CC
EE
CC
CC
EE
V
CC
Low Voltage
of Differential
Input
V
V
CC
CC
V
V
EE
ILD
EE
EE
- 0.095
- 0.095
- 0.095
V
- V
V
- V
V
CC
- V
EE
CC
CC
For V
For V
- V < 3.0V
0.095
0.095
0.095
0.095
0.095
0.095
CC
CC
EE
Differential
Input Voltage
V
IHD -
V
ILD
EE
EE
V
- V ≥ 3.0V
EE
3.0
3.0
3.0
Input High
Current
I
150
+10
150
+10
150
+10
µA
µA
µA
IH
CLK_ Input Low
Current
I
I
-10
-10
-10
ILCLK
ILCLK
CLK_ Input Low
Current
-150
-150
-150
_
OUTPUTS (Q_, Q )
Single-Ended
Output High
Voltage
V
V
V
V
V
V
CC
- 0.900
CC
CC
CC
CC
CC
V
Figure 1
V
OH
- 1.025
- 0.900
- 1.025
- 0.900
- 1.025
Single-Ended
Output Low
Voltage
V
V
V
V
V
V
CC
- 1.695
CC
CC
CC
CC
CC
V
Figure 1
Figure 1
V
OL
- 1.93
- 1.695
- 1.93
- 1.695
- 1.93
Differential
Output Voltage
V
-
OH
670
950
670
950
670
950
mV
V
OL
REFERENCE (V
)
BB
V
V
V
V
V
V
CC
- 1.325
CC
CC
CC
CC
CC
MAX9311
MAX9313
Reference
Voltage Output
(Note 5)
- 1.525
- 1.325
- 1.525
- 1.325
- 1.525
I
=
BB
V
V
BB
0.5mA
V
V
V
V
V
V
CC
- 1.26
CC
CC
CC
CC
CC
- 1.38
- 1.26
- 1.38
- 1.26
- 1.38
POWER SUPPLY
Supply Current
(Note 6)
I
75
82
95
mA
EE
_______________________________________________________________________________________
3
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
AC ELECTRICAL CHARACTERISTICS
(V
- V = 2.25V to 3.8V, outputs loaded with 50Ω 1ꢀ to V
- 2V, input frequency = 1.5GHz, input transition time = 125ps
CC
CC
EE
(20ꢀ to 80ꢀ), CLKSEL = high or low, V
= V + 1.2V to V , V
= V to V
- 0.15V, V
- V
= 0.15V to the smaller of 3V or
IHD
EE
CC ILD
EE
CC
IHD
ILD
V
CC
- V , unless otherwise noted. Typical values are at V
- V = 3.3V, V
= V -1V, V = V -1.5V.) (Note 7)
CC
IHD
CC ILD CC
EE
EE
-40°C
+25°C
+85°C
PARAMETER SYMBOL CONDITIONS
UNITS
MA
MIN
TYP
MAX
MIN
TYP
MIN
TYP
MAX
Differential
Input-to-
Output Delay
t
t
,
PLHD
Figure 2
220
321
12
380
220
312
410
260
322
400
ps
PHLD
Output-to-
Output Skew
(Note 8)
t
46
12
46
10
35
ps
ps
SKOO
Part-to-Part
Skew (Note 9)
t
30
1.2
1.2
160
2.5
2.6
30
1.2
1.2
190
2.5
2.6
30
1.2
1.2
140
2.5
2.6
SKPP
f
= 1.5GHz,
Clock pattern
IN
Added
Random Jitter
(Note 10)
ps
(RMS)
t
RJ
f
IN
= 3.0GHz,
Clock pattern
Added
Deterministic
Jitter (Note 10)
3Gbps,
223 -1 PRBS
pattern
ps
(p-p)
t
80
95
80
95
80
95
DJ
V
- V
OL
≥
OH
350mV, Clock
pattern,
2.0
2.0
3.0
2.0
Figure 2
Switching
Frequency
f
GHz
MAX
V
- V
OL
≥
OH
500mV, Clock
pattern,
1.5
1.5
1.5
Figure 2
Output
Rise/Fall Time
(20ꢀ to 80ꢀ)
t , t
R
Figure 2
100
112
140
100
116
140
100
121
140
ps
F
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: Single-ended input operation using V is limited to V
- V = 3.0V to 3.8V for the MAX9311 and V
- V = 2.7V to 3.8V
CC EE
BB
CC
EE
for the MAX9313.
Note 4: DC parameters production tested at T = +25°C. Guaranteed by design and characterization over the full operating temper-
A
ature range.
Note 5: Use V only for inputs that are on the same device as the V reference.
BB
BB
Note 6: All pins open except V
and V
.
CC
EE
Note 7: Guaranteed by design and characterization. Limits are set at 6 sigma.
Note 8: Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 9: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge
transition.
Note 10:Device jitter added to the input signal.
4
_______________________________________________________________________________________
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
Typical Operating Characteristics
(V
CC
= +3.3V, V = 0, V
= V
- 0.95V, V
= V
- 1.25V, input transition time = 125ps (20ꢀ to 80ꢀ), f = 1.5GHz, outputs
CC IN
EE
IHD
CC
ILD
loaded with 50Ω to V
- 2V, T = +25°C, unless otherwise noted.)
CC
A
SUPPLY CURRENT (I
vs. TEMPERATURE
)
OUTPUT AMPLITUDE (V - V )
OH OL
EE
vs. FREQUENCY
TRANSITION TIME vs. TEMPERATURE
85
80
75
70
65
60
55
50
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
130
125
120
115
110
105
100
t
R
t
F
-40
-15
10
35
60
85
0
1000
2000
3000
-40
-15
10
35
60
85
TEMPERATURE (°C)
FREQUENCY (MHz)
TEMPERATURE (°C)
PROPAGATION DELAY
vs. HIGH VOLTAGE OF
DIFFERENTIAL INPUT (V
PROPAGATION DELAY
vs. TEMPERATURE
)
IHD
313
312
311
310
309
308
307
306
305
304
303
360
340
320
300
280
260
240
220
200
V
V
= 150mV
IHD - ILD
t
PLHD
t
PLHD
t
PHLD
t
PHLD
V
= V - 0.95V
CC
CC
IHD
V
= V - 1.1V
ILD
1.0 1.4 1.8 2.2 2.6 3.0 3.4
(V)
3.8
-40
-15
10
35
60
85
V
TEMPERATURE (°C)
IHD
_______________________________________________________________________________________
5
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
Pin Description
PIN
NAME
FUNCTION
1, 9, 16,
25, 32
Positive Supply Voltage. Bypass from V
CC
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
to V with 0.1µF and 0.01µF ceramic capacitors. Place the
EE
V
CC
Clock Select Input (Single-Ended). Drive low to select the CLK0, CLK0 input. Drive high to select the
2
CLKSEL CLK1, CLK1 input. The CLKSEL threshold is V . If CLKSEL is not driven by a logic signal, use a 1kΩ
BB
pulldown to V to select CLK0, CLK0, or a 1kΩ pullup to V to select CLK1, CLK1.
EE
CC
3
4
CLK0
Noninverting Differential Clock Input 0. Internal 75kΩ pulldown resistor.
CLK0
Inverting Differential Clock Input 0. Internal 75kΩ pullup and pulldown resistors.
Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a reference for
single-ended operation. When used, bypass with a 0.01µF ceramic capacitor to V ; otherwise, leave open.
CC
5
V
BB
6
CLK1
Noninverting Differential Clock Input 1. Internal 75kΩ pulldown resistor.
Inverting Differential Clock Input 1. Internal 75kΩ pullup and pulldown resistors.
Negative Supply Voltage
7
CLK1
8
V
EE
10
11
12
13
14
15
17
18
19
20
21
22
23
24
26
27
28
29
30
31
Q9
Q9
Q8
Q8
Q7
Q7
Q6
Q6
Q5
Q5
Q4
Q4
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
Inverting Q9 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting Q9 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
Inverting Q8 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting Q8 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
Inverting Q7 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting Q7 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
Inverting Q6 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting Q6 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
Inverting Q5 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting Q5 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
Inverting Q4 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting Q4 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
Inverting Q3 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting Q3 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
Inverting Q2 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting Q2 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
Inverting Q1 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting Q1 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
Inverting Q0 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting Q0 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
6
_______________________________________________________________________________________
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
When using the V
reference output, bypass it with a
BB
Detailed Description
0.01µF ceramic capacitor to V . If the V reference is
CC
BB
The MAX9311/MAX9313 are low skew, 1-to-10 differen-
tial drivers designed for clock and data distribution.
not used, it can be left open. The V
source or sink 0.5mA, which is sufficient to drive two
reference can
BB
A 2:1 mux selects between the two differential inputs,
CLK0, CLK0 and CLK1, CLK1. The 2:1 mux is switched
by the single-ended CLKSEL input. A logic low selects
the CLK0, CLK0 input. A logic high selects the CLK1,
CLK1 input. The logic threshold for CLKSEL is set by an
inputs. Use V
only for inputs that are on the same
BB
device as the V reference.
BB
The maximum magnitude of the differential input from
CLK_ to CLK_ is 3.0V or V
This limit also applies to the difference between any ref-
erence voltage input and a single-ended input.
- V , whichever is less.
EE
CC
internal V
voltage reference. The CLKSEL input can
BB
be driven to V
and V or by a single-ended LVPECL/
EE
CC
The differential inputs have bias resistors that drive the
outputs to a differential low when the inputs are open.
The inverting inputs (CLK0 and CLK1) are biased with a
LVECL signal. The selected input is reproduced at 10
differential outputs.
For interfacing to differential HSTL and LVPECL signals,
these devices operate over a +2.25V to +3.8V supply
range, allowing high-performance clock or data distribu-
tion in systems with a nominal +2.5V or +3.3V supply.
For differential LVECL operation, these devices operate
from a -2.25V to -3.8V supply.
75kΩ pullup to V
and a 75kΩ pulldown to V . The
EE
CC
noninverting inputs (CLK0 and CLK1) are biased with a
75kΩ pulldown to V . The single-ended CLKSEL input
EE
does not have a bias resistor. If not driven, pull CLKSEL
up or down with a 1kHz resistor (see Pin Description).
Specifications for the high and low voltages of a differen-
The differential inputs can be configured to accept sin-
tial input (V
and V ) and the differential input volt-
ILD
ILD
IHD
IHD
gle-ended inputs when operating at approximately V
-
CC
age (V
- V ) apply simultaneously (V
cannot be
IHD
ILD
V
EE
= +3.0V to +3.8V for the MAX9311 or V
- V
=
CC
EE
higher than V ).
+2.7V to +3.8V for the MAX9313. This is accomplished
Output levels are referenced to V
LVPECL or LVECL, depending on the level of the V
and are considered
CC
by connecting the on-chip reference voltage, V , to an
BB
CC
input as a reference. For example, the differential CLK0,
supply. With V
EE
outputs are LVECL when V
connected to a positive supply and
CC
CLK0 input is converted to a noninverting, single-ended
V
connected to GND, the outputs are LVPECL. The
input by connecting V
to CLK0 and connecting the
BB
is connected to GND and
CC
single-ended input to CLK0. Similarly, an inverting input
V
EE
is connected to a negative supply.
is obtained by connecting V to CLK0 and connecting
BB
the single-ended input to CLK0. With a differential input
A single-ended input of at least V
95mV or a differen-
BB
configured as single-ended (using V ), the single-
BB
tial input of at least 95mV switches the outputs to the
and V levels specified in the DC Electrical
ended input can be driven to V
and V or with a sin-
CC
EE
V
OH
OL
gle-ended LVPECL/LVECL signal.
When a differential input is configured as a single-ended
input (using V ), the approximate supply range is V
Characteristics table.
Applications Information
-
CC
EE
BB
V
EE
= +3.0V to +3.8V for the MAX9311 and V
- V
=
CC
Supply Bypassing
to V with high-frequency surface-mount
+2.7V to +3.8V for the MAX9313. This is because one of
the inputs must be V + 1.2V or higher for proper oper-
Bypass V
CC
EE
EE
ceramic 0.1µF and 0.01µF capacitors in parallel as close
to the device as possible, with the 0.01µF value capaci-
tor closest to the device. Use multiple parallel vias for
ation of the input stage. V must be at least V + 1.2V
BB
EE
because it becomes the high-level input when the other
(single-ended) input swings below it. Therefore, mini-
low inductance. When using the V
reference output,
BB
mum V = V + 1.2V.
BB
EE
bypass it with a 0.01µF ceramic capacitor to V
(if the
CC
V
BB
reference is not used, it can be left open).
The minimum V
output for the MAX9311 is V
-
CC
BB
1.525V and the minimum V output for the MAX9313 is
BB
Traces
V
- 1.38V. Substituting the minimum V
output for
CC
BB
Input and output trace characteristics affect the perfor-
mance of the MAX9311/MAX9313. Connect each signal
of a differential input or output to a 50Ω characteristic
impedance trace. Minimize the number of vias to prevent
impedance discontinuities. Reduce reflections by main-
taining the 50Ω characteristic impedance through con-
nectors and across cables. Reduce skew within a
each device into V = V + 1.2V results in a minimum
BB
EE
supply of 2.725V for the MAX9311 and 2.58V for the
MAX9313. Rounding up to standard supplies gives the
single-ended operating supply ranges of V
- V
=
CC
EE
3.0V to 3.8V for the MAX9311 and V
3.8V for the MAX9313.
- V = 2.7V to
CC
EE
_______________________________________________________________________________________
7
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
differential pair by matching the electrical length of the
traces.
Chip Information
TRANSISTOR COUNT: 250
Output Termination
Terminate outputs through 50Ω to V - 2V or use an
CC
equivalent Thevenin termination. When a single-ended
signal is taken from a differential output, terminate both
outputs. For example, if Q0 is used as a single-ended
output, terminate both Q0 and Q0.
CLK_
CLK_
V
IH
V
BB
V
IL
(CONNECTED TO CLK_)
V
Q_
Q_
OH
V
- V
OH OL
V
OL
Figure 1. Switching with Single-Ended Input
CLK_
CLK_
V
IHD
V
- V
IHD ILD
V
ILD
t
t
PLHD
PHLD
V
V
Q_
Q_
OH
OL
V
- V
OL
OH
80%
0 (DIFFERENTIAL)
80%
0 (DIFFERENTIAL)
20%
20%
(Q_) - (Q_)
t
t
F
R
Figure 2. Differential Transition Time and Propagation Delay Timing Diagram
8
_______________________________________________________________________________________
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
Functional Diagram
Q0
Q0
V
CC
Q1
Q1
Q2
75kΩ
CLK0
CLK0
Q2
Q3
75kΩ
75kΩ
Q3
Q4
V
V
V
EE
EE
0
1
Q4
Q5
CC
Q5
Q6
75kΩ
CLK1
CLK1
Q6
Q7
75kΩ
75kΩ
Q7
Q8
V
V
EE
EE
CLKSEL
Q8
Q9
V
BB
Q9
_______________________________________________________________________________________
9
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
10 ______________________________________________________________________________________
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
______________________________________________________________________________________ 11
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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