MAX9205EAI+T [MAXIM]
Line Driver, 1 Func, 1 Driver, CMOS, PDSO28, 5.30 MM, 0.65 MM PITCH, SSOP-28;
| 型号： | MAX9205EAI+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Line Driver, 1 Func, 1 Driver, CMOS, PDSO28, 5.30 MM, 0.65 MM PITCH, SSOP-28 |
| 文件： | 总13页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2029; Rev 0; 5/01
10-Bit Bus LVDS Serializers
General Description
Features
The MAX9205/MAX9207 serializers transform 10-bit-
wide parallel LVCMOS/LVTTL data into a serial high-
speed bus low-voltage differential signaling (LVDS)
data stream. The serializers typically pair with deserial-
izers like the MAX9206*/MAX9208*, which receive the
serial output and transform it back to 10-bit-wide paral-
lel data.
ꢀ Standalone Serializer (vs. SERDES) Ideal for
Unidirectional Links
ꢀ Framing Bits for Deserializer Resync Allow Hot
Insertion Without System Interruption
ꢀ LVDS Serial Output Rated for Point-to-Point and
Bus Applications
The MAX9205/MAX9207 transmit serial data at speeds
up to 400Mbps and 660Mbps, respectively, over PC
board traces or twisted-pair cables. Since the clock is
recovered from the serial data stream, clock-to-data
and data-to-data skew that would be present with a
parallel bus are eliminated.
ꢀ Wide Reference Clock Input Range
16MHz to 40MHz (MAX9205)
40MHz to 66MHz (MAX9207)
ꢀ Low 140ps (pk-pk) Deterministic Jitter (MAX9207)
ꢀ Low 34mA Supply Current (MAX9205)
The serializers require no external components and few
control signals. The input data strobe edge is selected
by TCLK_R/F. PWRDN is used to save power when the
devices are not in use. Upon power-up, a synchroniza-
tion mode is activated, which is controlled by two SYNC
inputs, SYNC1 and SYNC2.
ꢀ 10-Bit Parallel LVCMOS/LVTTL Interface
ꢀ Up to 660Mbps Payload Data Rate (MAX9207)
ꢀ Programmable Active Edge on Input Latch
ꢀ Pin-Compatible Upgrades to DS92LV1021 and
The MAX9205 can lock to a 16MHz to 40MHz system
clock, while the MAX9207 can lock to a 40MHz to
66MHz system clock. The serializer output is held in
high impedance until the device is fully locked to the
local system clock, or when the device is in power-
down mode.
DS92LV1023
Ordering Information
TEMP.
RANGE
PIN-
REF CLOCK
PART
Both the devices operate from a single +3.3V supply,
are specified for operation from -40°C to +85°C, and
are available in 28-pin SSOP packages.
PACKAGE RANGE (MHz)
MAX9205EAI -40 C to +85 C
MAX9207EAI -40 C to +85 C
28 SSOP
28 SSOP
16 to 40
40 to 66
Applications
Cellular Phone Base
Stations
Add Drop Muxes
DSLAMs
Network Switches and
Routers
Pin Configuration and Functional Diagram appear at end of
data sheet.
Digital Cross-Connects
Backplane Interconnect
Typical Application Circuit
BUS
LVDS
OUT+
IN+
10
10
100
100
OUT_
IN_
OUT-
IN-
TCLK_R/F
TCLK
PC BOARD OR
TWISTED PAIR
REFCLK
EN
LOCK
EN
TIMING AND
CONTROL
TIMING AND
CONTROL
PLL
PLL
PWRDN
SYNC 1
SYNC 2
RCLK
CLOCK
RECOVERY
MAX9205
MAX9207
MAX9206*
MAX9208*
RCLK_R/F
*FUTURE PRODUCT
*Future product–contact factory for availability.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
10-Bit Bus LVDS Serializers
ABSOLUTE MAXIMUM RATINGS
CC
IN_, SYNC1, SYNC2, EN, TCLK_R/F, TCLK,
PWRDN to GND......................................-0.3V to (V
OUT+, OUT- to GND .............................................-0.3V to +4.0V
Output Short-Circuit Duration.....................................Continuous
V
to GND.........................................……………-0.3V to +4.0V
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Lead Temperature (soldering, 10s) .................................+300°C
ESD Protection (Human Body Model, OUT+, OUT-) ........... 8kV
+ 0.3V)
CC
Continuous Power Dissipation (T = +70°C)
A
28-Pin SSOP (derate 9.5mW/°C above +70°C) ..........762mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, R = 27
1ꢀ or 50
1ꢀ, C = 10pF, T = -40°C to +85°C. Typical values are at V
= +3.3V and T =
CC A
CC
L
L
A
+25°C, unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LVCMOS/LVTLL LOGIC INPUTS (IN0 TO IN9, EN, SYNC1, SYNC2, TCLK, TCLK_R/F, PWRDN)
High-Level Input Voltage
Low-Level Input Voltage
Input Current
V
2.0
GND
-20
V
V
V
A
IH
CC
V
0.8
IL
I
V
= 0 or V
CC
+20
IN
IN_
BUS LVDS OUTPUTS (OUT+, OUT-)
R = 27
200
250
286
460
400
600
mV
mV
L
Differential Output Voltage
V
V
Figure 1
OD
R = 50
L
Change in V
Between
OD
V
Figure 1
Figure 1
Figure 1
1
1.15
3
35
1.3
35
mV
V
OD
Complementary Output States
Output Offset Voltage
0.9
OS
Change in V Between
OS
Complementary Output States
V
mV
OS
OUT+ or OUT- = 0,
IN0 to IN9 = PWRDN = EN = high
Output Short-Circuit Current
I
-13
-15
mA
OS
PWRDN or EN = 0.8V,
OUT+ or OUT- = 0 or V
Output High-Impedance Current
I
I
-10
-10
+10
+10
A
A
OZ
CC
Power-Off Output Current
V
= 0, OUT+ or OUT- = 0 or 3.6V
CC
OX
POWER SUPPLY
16MHz
40MHz
40MHz
66MHz
23
34
32
45
35
45
50
60
8
MAX9205
MAX9207
R = 27 or 50
L
worst-case pattern
(Figures 2, 4)
Supply Current
I
mA
mA
CC
Power-Down Supply Current
I
PWRDN = low
CCX
2
_______________________________________________________________________________________
10-Bit Bus LVDS Serializers
AC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, R = 27
1ꢀ or 50
1ꢀ, C = 10pF, T = -40°C to +85°C. Typical values are at V
= +3.3V and T =
CC A
CC
L
L
A
+25°C, unless otherwise noted.) (Notes 2, 4)
PARAMETER SYMBOL
TRANSMIT CLOCK (TCLK) TIMING REQUIREMENTS
CONDITIONS
MIN
TYP
MAX
UNITS
MAX9205
16
40
40
66
MHz
MHz
ppm
TCLK Center Frequency
TCLK Frequency Variation
TCLK Period
f
TCCF
MAX9207
TCFV
-200
25
200
62.5
25
MAX9205
MAX9207
t
ns
TCP
15.15
40
TCLK Duty Cycle
TCDC
60
ꢀ
TCLK Input Transition Time
t
Figure 3
3
6
ns
CLKT
ps
(RMS)
TCLK Input Jitter
t
150
JIT
SWITCHING CHARACTERISTICS
Low-to-High Transition Time
R = 27
150
150
150
150
1
300
350
300
350
400
500
400
500
L
t
Figure 4
Figure 4
ps
ps
LHT
HLT
R = 50
L
R = 27
L
High-to-Low Transition Time
t
R = 50
L
IN_ Setup to TCLK
IN_ Hold from TCLK
t
S
Figure 5
Figure 5
ns
ns
t
3
H
OUTPUT High State to High-
Impedance Delay
t
Figures 6, 7
Figures 6, 7
Figures 6, 7
Figures 6, 7
4.5
4.5
4.5
4.5
10
10
10
10
ns
ns
ns
HZ
OUTPUT Low State to High-
Impedance Delay
t
LZ
OUTPUT High Impedance to
High-State Delay
t
ZH
OUTPUT High Impedance to
Low-State Delay
t
ns
ns
ns
ns
ns
ZL
SYNC Pulse Width
t
6 x t
TCP
SPW
2048 x
2049 x
t
TCP
PLL Lock Time
t
Figure 7
Figure 8
PL
t
TCP
Bus LVDS Bit Width
Serializer Delay
t
t
/ 12
TCP
BIT
(t
/ 6)
TCP
t
t
/ 6
SD
TCP
+ 5
_______________________________________________________________________________________
3
10-Bit Bus LVDS Serializers
AC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, R = 27
1ꢀ or 50
1ꢀ, C = 10pF, T = -40°C to +85°C. Typical values are at V
= +3.3V and T =
CC A
CC
L
L
A
+25°C, unless otherwise noted.) (Notes 2, 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
200
140
140
140
13
UNITS
16MHz
MAX9205
MAX9207
MAX9205
MAX9207
40MHz
40MHz
66MHz
16MHz
40MHz
40MHz
66MHz
ps
(pk-pk)
Deterministic Jitter (Figure 9)
t
DJIT
RJIT
9
ps
(RMS)
Random Jitter (Figure 10)
t
9
6
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V , and V
,
V
OD
.
OS
OD
Note 2: C includes scope probe and test jig capacitance.
L
Note 3: Parameters 100ꢀ tested at T = +25°C. Limits over operating temperature range guaranteed by design and characterization.
A
Note 4: AC parameters are guaranteed by design and characterization.
Typical Operating Characteristics
(V
= +3.3V, R = 27 , C = 10pF, T = +25°C, unless otherwise noted.)
L
L A
CC
WORST-CASE PATTERN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
DETERMINISTIC JITTER vs.
SUPPLY VOLTAGE
60
50
40
30
50
40
30
20
10
TCLK = 40MHz
MAX9205
20
10
TCLK = 40MHz
MAX9205
3.0
3.3
3.6
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
4
_______________________________________________________________________________________
10-Bit Bus LVDS Serializers
Pin Description
PIN
NAME
FUNCTION
LVCMOS/LVTTL Logic Inputs. The two SYNC pins are ORed. When at least one of the two pins
are asserted high for at least six cycles of TCLK, the serializer initiates a transmission of 1024
SYNC patterns. If held high after 1024 SYNC patterns have been transmitted, SYNC patterns
continue to be sent until the SYNC pin is asserted low. Toggling a SYNC pin after six TCLK cycles
high and before 1024 SYNC patterns have been transmitted does not affect the output of the 1024
SYNC patterns.
SYNC 1,
SYNC 2
1, 2
3–12
IN0–IN9
LVCMOS/LVTTL Data Inputs. Data is loaded into a 10-bit latch by the selected TCLK edge.
LVCMOS/LVTTL Logic Input. High selects a TCLK rising-edge data strobe. Low selects a TCLK
falling-edge data strobe.
13
TCLK_R/F
LVCMOS/LVTTL Reference Clock Input. The MAX9205 accepts a 16MHz to 40MHz clock. The
MAX9207 accepts a 40MHz to 66MHz clock. TCLK provides a frequency reference to the PLL and
strobes parallel data into the input latch.
14
TCLK
15, 16
17, 26
DGND
Digital Circuit Ground. Connect to ground plane.
Analog Circuit Power Supply (Includes PLL). Bypass AV to ground with a 0.1 F capacitor and a
0.001 F capacitor. Place the 0.001 F capacitor closest to AV
CC
AV
CC
.
CC
18, 20,
23, 25
AGND
EN
Analog Circuit Ground. Connect to ground plane.
LVCMOS/LVTTL Logic Input. High enables serial data output. Low puts the bus LVDS output into
high impedance.
19
21
22
OUT-
Inverting Bus LVDS Differential Output
OUT+
Noninverting Bus LVDS Differential Output
LVCMOS/LVTTL Logic Input. Low puts the device into power-down mode and the output into high
impedance.
24
PWRDN
Digital Circuit Power Supply. Bypass DV
capacitor. Place the 0.001 F capacitor closest to DV
to ground with a 0.1 F capacitor and a 0.001 F
CC
27, 28
DV
CC
.
CC
A high-state start bit and a low-state stop bit, added
internally, frame the 10-bit parallel input data and
ensure a transition in the serial data stream. Therefore,
12 serial bits are transmitted for each 10-bit parallel
input. The MAX9205 accepts a 16MHz to 40MHz refer-
ence clock, producing a serial data rate of 192Mbps
(12 bits x 16MHz) to 480Mbps (12 bits x 40MHz). The
MAX9207 accepts a 40MHz to 66MHz reference clock,
producing 480Mbps to 792Mbps. However, since only
10 bits are from input data, the actual throughput is 10
times the TCLK frequency.
Detailed Description
The MAX9205/MAX9207 are 10-bit serializers designed
to transmit data over balanced media that may be a
standard twisted-pair cable or PC board traces at
160Mbps to 660Mbps. The interface may be double-
terminated point-to-point or a heavily loaded multipoint
bus. The characteristic impedance of the media and
connected devices can range from 100 for a point-to-
point interface to 54 for a heavily loaded multipoint
bus. A double-terminated point-to-point interface uses
a 100 -termination resistor at each end of the inter-
face, resulting in a load of 50 . A heavily loaded multi-
point bus requires a termination as low as 54 at each
end of the bus, resulting in a termination load of 27 .
The serializer requires a deserializer such as the
MAX9206/MAX9208 for a complete data transmission
application.
To transmit data, the serializers sequence through
three modes: initialization mode, synchronization mode,
and data transmission mode.
_______________________________________________________________________________________
5
10-Bit Bus LVDS Serializers
data transmission, the data at IN0–9 are ignored and
Initialization Mode
SYNC patterns are sent for at least 1024 TCLK cycles.
When V
is applied, the outputs are held in high
CC
impedance and internal circuitry is disabled by on-chip
A start bit high and a stop bit low frame the 10-bit data
and function as the embedded clock edge in the serial
data stream. The serial rate is the TCLK frequency
times the data and appended bits. For example, if
TCLK is 40MHz, the serial rate is 40 x 12 (10 + 2 bits) =
480Mbps. Since only 10 bits are from input data, the
payload rate is 40 x 10 = 400Mbps.
power-on-reset circuitry. When V
reaches 2.35V, the
CC
PLL starts to lock to a local reference clock (16MHz to
40MHz for MAX9205 and 40MHz to 66MHz for
MAX9207). The reference clock, TCLK, is provided by
the system. A serializer locks within 2049 cycles of
TCLK. Once locked, a serializer is ready to send data
or SYNC patterns depending on the levels of SYNC 1
and SYNC 2.
Power-Down
Power-down mode is entered when the PWRDN pin is
driven low. In power-down mode, the PLL of the serial-
izer is stopped and the outputs (OUT+ and OUT-) are
in high impedance, disabling drive current and also
reducing supply current. When PWRDN is driven high,
the serializer must reinitialize and resynchronize before
data can be transferred.
Synchronization Mode
To rapidly synchronize with a deserializer, SYNC pat-
terns can be sent. A SYNC pattern is six consecutive
ones followed by six consecutive zeros repeating every
TCLK period. When one or both SYNC inputs are
asserted high for at least six cycles of TCLK, the serial-
izer will initiate the transmission of 1024 SYNC patterns.
The serializer will continue to send SYNC patterns if
either of the SYNC input pins remains high. Toggling
one SYNC input with the other SYNC input low before
1024 SYNC patterns are output does not interrupt the
output of the 1024 SYNC patterns.
High-Impedance State
The serializer output pins (OUT+ and OUT-) are held in
high impedance when V
is first applied and while the
CC
PLL is locking to the local reference clock. Setting EN
or PWRDN low puts the device in high impedance.
After initialization, EN functions asynchronously. For
example, the serializer output can be put into high
impedance while SYNC patterns are being sent without
affecting the internal timing of the SYNC pattern gener-
ation. However, if the serializer goes into high imped-
ance, a deserializer loses PLL lock and needs to
resynchronize before data transfer can resume.
Data Transmission Mode
After initialization, both SYNC input pins must be set
low by users or through a control signal from the dese-
rializer before data transmission begins. Provided that
SYNC inputs are low, input data at IN0–9 are clocked
into the serializer by the TCLK input. Setting TCLK_R/F
high selects the rising edge of TCLK for data strobe
and low selects the falling edge. If either of the SYNC
inputs goes high for six TCLK cycles at any time during
Table 1. Input /Output Function Table
INPUTS
OUTPUTS
EN
PWRDN
SYNC 1
SYNC 2
OUT+, OUT-
When either or both SYNC 1
and SYNC 2 are held high for
at least six TCLK cycles
Synchronization Mode. SYNC patterns of six 1s and six 0s are
transmitted every TCLK cycle for at least 1024 TCLK cycles.
Data at IN0–9 are ignored.
H
H
Data Transmission Mode. IN0–9 and 2 frame bits are
transmitted every TCLK cycle.
H
H
L
L
X
L
X
X
X
X
X
Output in high-impedance.
L
X = Don’t care
6
_______________________________________________________________________________________
10-Bit Bus LVDS Serializers
Avoid the use of unbalanced cables such as ribbon or
Applications Information
Power-Supply Bypassing
with high-frequency surface-mount
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by a differential receiver.
Bypass AV
CC
ceramic 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smaller valued
capacitor closest to AV . Bypass DV
with high-fre-
CC
CC
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
quency surface-mount ceramic 0.1µF and 0.001µF
capacitors in parallel as close to the device as possi-
ble, with the smaller valued capacitor closest to DV
.
CC
Differential Traces and Termination
Output trace characteristics affect the performance of
the MAX9205/MAX9207. Use controlled-impedance
media and terminate at both ends of the transmission
line in the media's characteristic impedance.
Termination with a single resistor at the end of a point-
to-point link typically provides acceptable performance.
However, the MAX9205/MAX9207 output levels are
specified for double-terminated point-to-point and mul-
tipoint applications. With a single 100 termination, the
output swing is larger.
The differential output signals should be routed close to
each other to cancel their external magnetic field.
Maintain a constant distance between the differential
traces to avoid discontinuities in differential impedance.
Avoid 90° turns and minimize the number of vias to fur-
ther prevent impedance discontinuities.
TCLK
R
2
L
L
OUT+
OUT-
V
OD
ODD IN_
EVEN IN_
V
OS
R
2
TCLK_R/F = LOW
Figure 1. Output Voltage Definitions
Figure 2. Worst-Case I
Test Pattern
CC
3V
90%
CLKT
90%
TCLK
10%
10%
0
t
t
CLKT
Figure 3. Input Clock Transition Time Requirement
_______________________________________________________________________________________
7
10-Bit Bus LVDS Serializers
10pF
OUT+
80%
HLT
80%
V
= 0
DIFF
R
L
20%
20%
V
DIFF
OUT-
10pF
t
t
LHT
V
= (OUT+) - (OUT-)
DIFF
Figure 4. Output Load and Transition Times
t
TCP
1.5V
1.5V
1.5V
TCLK
t
t
H
S
1.5V
1.5V
IN_
TIMING SHOWN FOR TCLK_R/F = LOW
Figure 5. Data Input Setup and Hold Times
PARASITIC PACKAGE AND
TRACE CAPACITANCE
10pF
13.5
13.5
OUT+
OUT-
+1.1V
EN
10pF
3V
0
1.5V
1.5V
EN
t
t
ZH
HZ
V
OH
50%
50%
50%
1.1V
1.1V
OUT
t
t
ZL
LZ
50%
V
OL
Figure 6. High-Impedance Test Circuit and Timing
_______________________________________________________________________________________
8
10-Bit Bus LVDS Serializers
2.0V
PWRDN
TCLK
0.8V
t
PL
t OR t
HZ LZ
1.5V
t
OR t
ZL
ZH
OUT
ACTIVE
HIGH IMPEDANCE
HIGH IMPEDANCE
SYNC 1 = SYNC 2 = LOW
EN = HIGH
TCLK_R/F = HIGH
Figure 7. PLL Lock Time and PWRDN High-Impedance Delays
IN
IN0 - IN9 SYMBOL N + 1
IN0 - IN9 SYMBOL N
t
SD
TCLK
OUT
1.5V
TIMING SHOWN FOR TCLK_R/F = HIGH
START BIT OUT0 - OUT9 SYMBOL N
OUT0 - OUT9 SYMBOL N+1
STOP BIT START BIT
STOP BIT
TCLK_ R/F = HIGH
V
DIFF
= 0
V
= (OUT+) - (OUT-)
DIFF
Figure 8. Serializer Delay
(OUT+) - (OUT-)
WAVEFORM
(OUT+) - (OUT-)
WAVEFORM
O DIFFERENTIAL
O DIFFERENTIAL
t
t
RJIT
RJIT
t
DJIT
"CLOCK" PATTERN (1010...)
SUPERIMPOSED RANDOM DATA
Figure 9. Definition of Deterministic Jitter (t
)
Figure 10. Definition of Random Jitter (t
)
DJIT
RJIT
_______________________________________________________________________________________
9
10-Bit Bus LVDS Serializers
reduces reflections compared to a single 100 termi-
Topologies
The serializers can operate in a variety of topologies.
Examples of double-terminated point-to-point, mul-
tidrop, point-to-point broadcast, and multipoint topolo-
gies are shown in Figures 11 through 14. Use 1ꢀ
surface-mount termination resistors.
nation. A single 100 termination at the deserializer
input is feasible and will make the differential signal
swing larger.
A serializer located at one end of a backplane bus dri-
ving multiple deserializers in a multidrop configuration
is shown in Figure 12. A 54 resistor at the far end ter-
minates the bus. This topology allows “broadcast” of
data with a minimum of interconnect.
A point-to-point connection terminated at each end in
the characteristic impedance of the cable or PC board
traces is shown in Figure 11. The total load seen by the
serializer is 50 . The double termination typically
SERIALIZED DATA
PARALLEL
DATA IN
PARALLEL
DATA OUT
100
100
MAX9205
MAX9207
MAX9206
MAX9208
Figure 11. Double-Terminated Point-to-Point
ASIC
ASIC
ASIC
ASIC
ASIC
MAX9205
MAX9207
MAX9206
MAX9208
MAX9206
MAX9208
MAX9206
MAX9208
MAX9206
MAX9208
54
Figure 12. Multidrop
10 ______________________________________________________________________________________
10-Bit Bus LVDS Serializers
A point-to-point version of the multidrop bus is shown in
the primary serializer. The typical close spacing (1in or
less) of cards on a backplane reduces the characteris-
tic impedance by as much as half the initial, unloaded
value. Termination resistors that match the loaded char-
acteristic impedance are required at each end of the
bus. The total loaded seen by the serializer is 27 in
this case.
Figure 13. The low-jitter MAX9150 10-port repeater is
used to reproduce and transmit the serializer output
over 10 double-terminated point-to-point links.
Compared to the multidrop bus, more interconnect is
traded for more robust hot-plug capability.
The repeater eliminates nine serializers compared to 10
individual point-to-point serializer-to-deserializer con-
nections. Since repeater jitter subtracts from the serial-
izer-deserializer timing margin, a low-jitter repeater is
essential in most high data rate applications.
Board Layout
For bus LVDS applications, a four-layer PC board that
provides separate power, ground, and input/output sig-
nals is recommended. Separate LVTTL/LVCMOS and
bus LVDS signals from each other to prevent coupling
into the bus LVDS lines.
Multiple serializers and deserializers bused over a dif-
ferential serial connection on a backplane are shown in
Figure 14. The second serializer can be a backup to
ASIC
ASIC
ASIC
MAX9206
MAX9208
MAX9206
MAX9208
MAX9205
MAX9207
MAX9150
REPEATER
100
100
100
100
Figure 13. Point-to-Point Broadcast Using MAX9150 Repeater
______________________________________________________________________________________ 11
10-Bit Bus LVDS Serializers
ASIC
ASIC
ASIC
ASIC
ASIC
MAX9205
MAX9207
MAX9205
MAX9207
MAX9206
MAX9208
MAX9206
MAX9208
MAX9206
MAX9208
54
54
Figure 14. Multipoint
Pin Configuration
Functional Diagram
TOP VIEW
1
2
3
4
5
6
7
8
9
SYNC1
SYNC2
IN0
DV
DV
AV
28
27
26
CC
CC
CC
OUT+
OUT-
10
IN_
IN1
AGND 25
PWRDN 24
AGND 23
OUT+ 22
OUT- 21
AGND 20
EN 19
MAX9205
MAX9207
TCLK_R/F
TCLK
IN2
IN3
EN
TIMING AND
PLL
CONTROL
PWRDN
IN4
SYNC 1
SYNC 2
IN5
IN6
MAX9205
MAX9207
10 IN7
11 IN8
AGND 18
12 IN9
AV
17
CC
13 TCLK_R/F
14 TCLK
DGND 16
DGND 15
Chip Information
TRANSISTOR COUNT: 3036
SSOP
PROCESS: CMOS
12 ______________________________________________________________________________________
10-Bit Bus LVDS Serializers
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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