MAX9206EAI+T [MAXIM]
Line Receiver, 1 Func, 1 Rcvr, CMOS, PDSO28, 5.30 MM, 0.65 MM PITCH, SSOP-28;
| 型号： | MAX9206EAI+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Line Receiver, 1 Func, 1 Rcvr, CMOS, PDSO28, 5.30 MM, 0.65 MM PITCH, SSOP-28 |
| 文件： | 总12页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2130; Rev 0; 8/01
10-Bit Bus LVDS Deserializers
General Description
Features
The MAX9206/MAX9208 deserializers transform a high-
speed serial bus low-voltage differential signaling
(BLVDS) data stream into 10-bit-wide parallel LVCMOS/
LVTTL data and clock. The deserializers pair with seri-
alizers such as the MAX9205/MAX9207, which gener-
ate a serial BLVDS signal from 10-bit-wide parallel
data. The serializer/deserializer combination reduces
interconnect, simplifies PC board layout, and reduces
board size.
ꢀ Stand-Alone Deserializer (vs. SERDES) Ideal for
Unidirectional Links
ꢀ Automatic Clock Recovery
ꢀ Allow Hot Insertion and Synchronization Without
System Interruption
ꢀ BLVDS Serial Input Rated for Point-to-Point and
Bus Applications
ꢀ Fast Pseudorandom Lock
The MAX9206/MAX9208 receive serial data at
400Mbps and 600Mbps, respectively, over board
traces or twisted-pair cables. These devices combine
frequency lock, bit lock, and frame lock to produce a
parallel-rate clock and word-aligned 10-bit data.
Serialization eliminates parallel bus clock-to-data and
data-to-data skew.
ꢀ Wide Reference Clock Input Range
16MHz to 40MHz (MAX9206)
40MHz to 60MHz (MAX9208)
ꢀ High 720ps (p-p) Jitter Tolerance (MAX9206)
ꢀ Low 30mA Supply Current (MAX9206 at 16MHz)
ꢀ 10-Bit Parallel LVCMOS/LVTTL Output
ꢀ Up to 600Mbps Throughput (MAX9208)
ꢀ Programmable Output Strobe Edge
A power-down mode reduces typical supply current to
less than 600µA. Upon power-up (applying power or
driving PWRDN high), the MAX9206/MAX9208 estab-
lish lock after receiving synchronization signals or serial
data from the MAX9205/MAX9207. An output enable
allows the outputs to be disabled, putting the parallel
data outputs and recovered output clock into a high-
impedance state without losing lock.
ꢀ Pin Compatible to DS92LV1212A and
DS92LV1224
The MAX9206/MAX9208 operate from a single +3.3V
supply and are specified for operation from -40°C to
+85°C. The MAX9206/MAX9208 are available in 28-pin
SSOP packages.
Ordering Information
TEMP.
REF CLOCK PIN-
PART
RANGE
RANGE (MHz) PACKAGE
Applications
MAX9206EAI -40°C to +85°C
MAX9208EAI -40°C to +85°C
16 to 40
40 to 60
28 SSOP
28 SSOP
Cellular Phone Base
Stations
Add/Drop Muxes
DSLAMs
Network Switches and
Routers
Pin Configuration appears at end of data sheet.
Digital Cross-Connects
Backplane Interconnect
Typical Operating Circuit
BUS
LVDS
OUT+
RI+
10
10
100Ω
100Ω
RI-
ROUT_
IN_
OUT-
TCLK_R/F
TCLK
PC BOARD OR
TWISTED PAIR
REFCLK
REN
LOCK
EN
TIMING AND
CONTROL
TIMING AND
CONTROL
PLL
PLL
PWRDN
SYNC 1
SYNC 2
RCLK
CLOCK
RECOVERY
MAX9205
MAX9207
MAX9206
MAX9208
RCLK_R/F
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
10-Bit Bus LVDS Deserializers
ABSOLUTE MAXIMUM RATINGS
AV , DV
to AGND, DGND .................................-0.3V to +4V
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
ESD Rating (Human Body Model, RI+, RI-)......................... 8kV
Lead Temperature (soldering, 10s) .................................+300°C
CC
CC
RI+, RI- to AGND, DGND .........................................-0.3V to +4V
All Other Pins to DGND..............................-0.3V to DV + 0.3V
ROUT_ Short-Circuit Duration (Note 1) ......................Continuous
CC
Continuous Power Dissipation (T = +70°C)
A
28-Pin SSOP (derate 9.5mW/°C above +70°C) ..........762mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(AV
= DV
= +3.0V to +3.6V, differential input voltage |V | = 0.1V to 1.2V, common-mode voltage V
= |V /2| to 2.4V
CC
CC
ID
CM
ID
ID
- |V /2|, T = -40°C to +85°C, unless otherwise noted. Typical values are at AV
= DV
= +3.3V, V
= 1.1V, |V | = 0.2V,
ID
A
CC
CC
CM
T
A
= +25°C.) (Notes 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
16MHz
40MHz
40MHz
60MHz
30
57
55
80
45
75
75
100
1
C = 15pF,
L
worst-case
pattern,
MAX9206
MAX9208
Supply Current
I
mA
mA
CC
Figure 1
Power-Down Supply Current
I
PWRDWN = low
CCX
LVCMOS/LVTTL LOGIC INPUTS (REN, REFCLK, RCLK_R/F, PWRDN)
High-Level Input Voltage
Low-Level Input Voltage
Input Current
V
2.0
0
V
V
V
IH
CC
V
0.8
15
IL
I
V
= 0, AV , or DV
CC
-15
µA
IN
IN
CC
LVCMOS/LVTTL LOGIC OUTPUTS (ROUT_, RCLK, LOCK)
High-Level Output Voltage
Low-Level Output Voltage
Output Short-Circuit Current
V
I
I
= -5mA
= 5mA
2.2
0
2.9
0.33
-38
V
V
V
OH
OH
OL
CC
0.5
-85
V
OL
OS
I
V
= 0
-15
mA
ROUT_
PWRDN = low, V
= V
= V
RCLK LOCK
ROUT_
Output High-Impedance Current
I
-1
1
µA
OZ
= 0, AV , or DV
CC
CC
BLVDS SERIAL INPUT (RI+, RI-)
Differential Input High Threshold
Differential Input Low Threshold
V
9
100
mV
mV
TH
V
-100
-64
-82
-64
-82
4
-9
TL
0.1V ≤ |V | ≤ 0.45V
64
82
64
82
ID
Input Current
I
, I
µA
µA
RI+ RI-
0.45V < |V | ≤ 0.6V
ID
0.1V ≤ |V | ≤ 0.45V, AV
= DV
= 0
CC
ID
CC
I
,
RI+OFF
Power-Off Input Current
I
RI-OFF
0.45V < |V | ≤ 0.6V, AV
= DV = 0
CC
ID
CC
Input Resistor 1
Input Resistor 2
R
R
AV
= DV
= DV
= 3.6V or 0, Figure 2
= 3.6V or 0, Figure 2
kΩ
kΩ
IN1
IN2
CC
CC
CC
CC
AV
150
2
_______________________________________________________________________________________
10-Bit Bus LVDS Deserializers
AC ELECTRICAL CHARACTERISTICS
(AV
= DV
= +3.0V to +3.6V, C = 15pF, differential input voltage |V | = 0.15V to 1.2V, common-mode voltage V
= |V /2| to
CC
CC
L
ID
CM
ID
2.4V - |V /2|, T = -40°C to +85°C, unless otherwise noted. Typical values are at AV
= DV
= +3.3V, V
= +1.1V, |V | = 0.2V,
ID
A
CC
CC
CM
ID
T
A
= +25°C.) (Notes 4, 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE CLOCK TIMING REQUIREMENTS (REFCLK)
MAX9206
16
40
40
60
REFCLK Frequency
REFCLK Frequency Variation
REFCLK Period
f
MHz
ppm
ns
RFF
MAX9208
RFFV
-200
25
200
62.5
25
MAX9206
MAX9208
t
RFCP
16.666
30
REFCLK Duty Cycle
RFDC
50
3
70
%
REFCLK Input Transition Time
SWITCHING CHARACTERISTICS
t
6
ns
RFTT
MAX9206
MAX9208
Figure 3
25
62.5
25
3
Recovered Clock (RCLK) Period
(Note 6)
t
ns
RCP
16.666
Low-to-High Transition Time
High-to-Low Transition Time
t
1.5
2
ns
ns
CLH
CHL
t
Figure 3
3
1.75 x t
1.75 x t
1.75 x t
+ 6.5
1.75 x t
RCP
RCP
RCP RCP
MAX9206, 40MHz
MAX9208, 60MHz
+ 2
+ 3.3
Deserializer Delay
t
Figure 4
ns
DD
1.75 x t
1.75 x t
RCP
RCP
+ 1.1
+ 3.3
+ 5.6
ROUT_ Data Valid Before RCLK
ROUT_ Data Valid After RCLK
RCLK Duty Cycle
t
Figure 5
Figure 5
0.4 x t
0.5 x t
0.5 x t
50
ns
ns
%
ROS
RCP
RCP
RCP
t
0.4 x t
43
ROH
RCP
t
57
8
RDC
OUTPUT High-to-High
Impedance Delay
t
C = 5pF, Figure 6
L
ns
ns
ns
ns
HZR
OUTPUT Low-to-High
Impedance Delay
t
C = 5pF, Figure 6
L
8
6
6
LZR
OUTPUT High-Impedance to
High-State Delay
t
C = 5pF, Figure 6
L
ZHR
OUTPUT High-Impedance to
Low-State Delay
t
C = 5pF, Figure 6
L
ZLR
Sync patterns at input; supply and
REFCLK stable; measured from
PWRDN transition high to LOCK
transition low; Figure 7
PLL Lock Time (from PWRDN
Transition High)
(2048 + 42)
x t
t
ns
DSR1
RFCP
_______________________________________________________________________________________
3
10-Bit Bus LVDS Deserializers
AC ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +3.0V to +3.6V, C = 15pF, differential input voltage |V | = 0.15V to 1.2V, common-mode voltage V
= |V /2| to
CC
CC
L
ID
CM
ID
2.4V - |V /2|, T = -40°C to +85°C, unless otherwise noted. Typical values are at AV
= DV
= +3.3V, V
= +1.1V, |V | = 0.2V,
ID
A
CC
CC
CM
ID
T
A
= +25°C.) (Notes 4, 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PLL locked to stable REFCLK; supply
stable; static input; measured from start
of sync patterns at input to LOCK
transition low; Figure 8
PLL Lock Time (from Start of
Sync Patterns)
t
42 x t
ns
DSR2
ZHLK
RFCP
LOCK High-Z to High-State
Delay
t
Figure 7
30
ns
ps
16MHz
1300
720
720
320
MAX9206
40MHz
Input Jitter Tolerance
t
Figure 9
JT
40MHz
MAX9208
60MHz
Note 1: Short one output at a time. Do not exceed the Absolute Maximum continuous power dissipation.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Voltages are referenced to ground
except V , V , and V , which are differential input voltages.
TH TL
ID
Note 3: DC parameters are production tested at T = +25°C and guaranteed by design and characterization over operating temper-
A
ature range.
Note 4: AC parameters guaranteed by design and characterization.
Note 5: C includes scope probe and test jig capacitance.
L
Note 6: t
is determined by the period of TCLK, which is the reference clock of the serializer driving the deserializer. The frequen-
RCP
cy of TCLK must be within 400ppm of the REFCLK frequency.
4
_______________________________________________________________________________________
10-Bit Bus LVDS Deserializers
Pin Description
PIN
NAME
FUNCTION
1, 12, 13
AGND
Analog Ground
Strobe Edge Select for Recovered Clock (RCLK). LVTTL/LVCMOS level input. Drive RCLK_ R/F high
to strobe ROUT_ on the rising edge of RCLK. Drive RCLK_R/F low to strobe ROUT_ on the falling
edge of RCLK.
2
RCLK_R/F
3
4, 11
5
REFCLK
Reference Clock for PLL. LVTTL/LVCMOS level input.
AV
Analog Power Supply. Bypass AV
with a 0.1µF and a 0.001µF capacitor to AGND.
CC
CC
RI+
Serial Data Input. Noninverting BLVDS differential input.
Serial Data Input. Inverting BLVDS differential input.
6
RI-
Power Down. LVTTL/LVCMOS level input. Drive PWRDN low to stop the PLL and put ROUT_, LOCK,
and RCLK in high impedance.
7
PWRDN
Output Enable. LVTTL/LVCMOS level input. Drive REN low to put ROUT_ and RCLK in high
impedance. LOCK remains active, indicating the status of the serial input.
8
9
REN
RCLK
LOCK
Recovered Clock. LVTTL/LVCMOS level output. Use RCLK to strobe ROUT_.
Lock Indicator. LVTTL/LVCMOS level output. LOCK goes low when the PLL has achieved frequency
and phase lock to the serial input, and the framing bits have been identified.
10
14, 20,
22
DGND
Digital Ground
15–19,
24–28
ROUT9–
ROUT0
Parallel Output Data. LVTTL/LVCMOS level outputs. ROUT_ is valid on the second selected strobe
edge of RCLK after LOCK goes low.
21, 23
DV
Digital Power Supply. Bypass DV
with a 0.1µF and a 0.001µF capacitor to DGND.
CC
CC
Test Circuits/Timing Diagrams
START
BIT
START
BIT
START
BIT
END
BIT
END
BIT
RI
0
1
2
3
4
5
6
7
9
0
1
3
4
5
6
7
8
9
0
1
2
8
2
T
DD
RCLK
RCLK_R/F = HIGH
ODD
ROUT
EVEN
ROUT
Figure 1. Worst-Case ICC Test Pattern
_______________________________________________________________________________________
5
10-Bit Bus LVDS Deserializers
Test Circuits/Timing Diagrams (continued)
V
CC
LVCMOS/LVTTL
OUTPUT
R
IN2
C
L
15pF
TO DESERIALIZING
CIRCUITRY
V
CC
- 0.3V
RI+
R
IN1
80%
80%
20%
20%
R
IN1
RI-
t
CHL
t
CLH
Figure 3. LVCMOS/LVTTL Output Load and Transition Times
Figure 2. Input Fail-Safe Circuit
START
BIT
START
BIT
START
SYMBOL N
BIT
SYMBOL N+1
5
END
BIT
END
BIT
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
6
7
8
9
0
1
2
RI
RCLK
t
DD
RCLK_R/F = HIGH
SYMBOL N-1
ROUT_
SYMBOL N
Figure 4. Input-to-Output Delay
+7V FOR t AND t
LZR
ZLR
ZHR
OPEN FOR t AND t
HZR
500Ω
450Ω
SCOPE
RCLK
RCLK_R/F = LOW
C
L
50%
50Ω
RCLK
RCLK_R/F = HIGH
50%
t
t
ROH
REN
ROS
1.5V
t
ZLR
DATA VALID
AFTER RCLK
DATA VALID
t
LZR
BEFORE RCLK
ROUT_
V
V
+0.5V
-0.5V
OL
V
OL
ROUT_
RCLK
V
OH
Figure 5. Data Valid Times
OH
t
HZR
t
ZHR
Figure 6. High-Impedance Test Circuit and Timing
______________________________________________________________________________________
6
10-Bit Bus LVDS Deserializers
Test Circuits/Timing Diagrams (continued)
t
≤ (2048 + 42)t
RFCP
DSR1
PWRDN
REFCLK
t
RFCP
SYNC PATTERNS
DATA
111111
DON'T CARE
HIGH-Z
RI
000000
t
ZHLK
t
DD
LOCK
HIGH-Z
RCLK
HIGH-Z
HIGH-Z
2048 x t
HIGH-Z
t
RCP
t
OR t
LZR
HZR
ROUT_
HIGH-Z
SYNC
DATA
RCLK_R/F = LOW
≤42 x t
RFCP
RFCP
Figure 7. PLL Lock Time from PWRDN
REFCLK
t
RFCP
DATA
SYNC PATTERNS
111111
RI
000000
t
DD
LOCK
RCLK
≤42t
RFCP
t
DSR2
t
RCP
SYNC
DATA
RCLK_R/F = LOW
DATA
DATA
ROUT_
Figure 8. Deserializer PLL Lock Time from Sync Patterns
_______________________________________________________________________________________
7
10-Bit Bus LVDS Deserializers
impedance, LOCK goes high, and the on-chip PLL
Detailed Description
locks to REFCLK in 2048 cycles. After locking to REF-
CLK, ROUT_ is active, RCLK tracks REFCLK, and
LOCK remains high. If transitions are detected at the
serial input, the PLL locks to the phase and frequency
of the serial input, finds the frame bits, and drives
LOCK low. If the serial input is sync patterns, LOCK
goes low in 42 or fewer cycles of RCLK. When LOCK
goes low, RCLK switches from tracking REFCLK to
tracking the serializer reference clock (TCLK).
Deserialized data at ROUT_ is valid on the second
selected strobe edge of RCLK after LOCK goes low.
Initialization restarts when power is cycled or on the ris-
ing edge of PWRDN.
The MAX9206/MAX9208 deserialize a BLVDS serializ-
er's output into 10-bit wide parallel LVCMOS/LVTTL
data and a parallel rate clock. The MAX9206/MAX9208
include a PLL that locks to the frequency and phase of
the serial input, and digital circuits that deserialize and
deframe the data. The MAX9206/MAX9208 have high-
input jitter tolerance while receiving data at speeds
from 160Mbps to 600Mbps. Combination with the
MAX9205/MAX9207 BLVDS serializers allows data
transmission across backplanes using PC board
traces, or across twin-ax or twisted-pair cables.
The MAX9206/MAX9208 deserializers provide a power-
saving, power-down mode when PWRDN is driven low.
The output enable, REN, allows the parallel data out-
puts (ROUT_) and recovered clock (RCLK) to be
enabled or disabled while maintaining lock to the serial
input. LOCK, along with RCLK, indicates when data is
valid at ROUT_. Parallel, deserialized data at ROUT_ is
strobed out on the selected strobe edge of RCLK. The
strobe edge of RCLK is programmable. The falling
edge is selected when RCLK_R/F is low and the rising
edge is selected when RCLK_R/F is high.
Lock to Pseudorandom Data
The MAX9206/MAX9208 lock to pseudorandom serial
input data by deductively eliminating rising edges due
to data until the embedded end/start edge is found.
The end/start edge is identified unless the data con-
tains a permanent, consecutive, frame-to-frame rising
edge at the same bit position. Send sync patterns to
guarantee lock. A sync pattern is six consecutive ones
followed by six consecutive zeros, repeating every
RCLK period with only one rising edge (at the end/start
boundary). The MAX9205/MAX9207 serializers gener-
ate sync patterns when SYNC1 or SYNC2 is driven
high.
The interface may be point-to-point or a heavily loaded
bus. The characteristic impedance of the media and
connections can range from 100Ω for a point-to-point
interface to 54Ω for a heavily loaded bus. A double-ter-
minated point-to-point interface uses a 100Ω termina-
tion resistor at each end of the interface, resulting in a
total load of 50Ω. A heavily loaded bus with a termina-
tion as low as 54Ω at each end of the bus (resulting in a
total load of 27Ω) can be driven.
A high state bit and a low state bit, added by the
BLVDS serializer, frame each 10 bits of serial data and
create a guaranteed transition for clock recovery. The
high bit is prepended at the start and the low bit is
appended at the end of the 10-bit data. The rising edge
formed at the end/start bit boundary functions as an
embedded clock. Twelve serial bits (10 data + 2 frame)
are transmitted by the serializer and received by the
deserializer for each 10 bits of data transferred. The
MAX9206 accepts a 16MHz to 40MHz reference clock,
and receives serial data at 160Mbps (10 data bits x
16MHz) to 400Mbps (10 data bits x 40MHz). The
MAX9208 accepts a 40MHz to 60MHz reference clock,
and receives serial data at a rate of 400Mbps to
600Mbps.
Since sending sync patterns to initialize a deserializer
disrupts data transfer to all deserializers receiving the
same serial input (Figure 11, for example), lock to
pseudorandom data is preferred in many applications.
Lock to pseudorandom data allows initialization of a
deserializer after hot insertion without disrupting data
communication on other links.
The MAX9206/MAX9208s’ deductive algorithm pro-
vides very fast pseudorandom data lock times. Table 1
compares typical lock times for pseudorandom and
sync pattern inputs.
Power-Down
Drive PWRDN low to enter the power-down mode. In
power-down, the PLL is stopped and the outputs
(ROUT_, RCLK, and LOCK) are put in high impedance,
disabling drive current and also reducing supply cur-
rent.
Output Enable
When the deserializer is initialized and REN is high,
ROUT_ is active, RCLK tracks the serializer reference
clock (TCLK), and LOCK is low. Driving REN low dis-
ables the ROUT_ and RCLK output drivers and does
not affect state machine timing. ROUT_ and RCLK go
Initialization
Initialize the MAX9206/MAX9208 before receiving data.
When power is applied, with REFCLK stable and
PWRDN high, RCLK and ROUT_ are held in high
8
_______________________________________________________________________________________
10-Bit Bus LVDS Deserializers
Table 1. Typical Lock Times
REFCLK
FREQUENCY
16MHz
35MHz
40MHz
40MHz
DATA
PATTERN
PSEUDORANDOM
PSEUDORANDOM
DATA
PSEUDORANDOM
DATA
SYNC
PATTERNS
DATA
Maximum
0.749µs
0.375µs
0.354µs
0.134µs
Maximum (Clock
Cycles)
11.99
0.318µs
5.09
13.14
14.18
5.37
Average
0.158µs
5.52
0.144µs
5.76
0.103µs
4.11
Average (Clock
Cycles)
Minimum
0.13µs
2.08
0.068µs
2.37
0.061µs
2.44
0.061µs
2.45
Minimum (Clock
Cycles)
15
Note: Pseudorandom lock performed with 2 -1 PRBS pattern, 10,000 lock time tests.
into high impedance but LOCK continues to reflect the
status of the serial input. Driving REN high again
enables the ROUT_ and RCLK drivers.
detected in spite of LOCK switching since LOCK is
high long enough to be sampled (LOCK is high for at
least two RCLK cycles after a missed clock edge and
RCLK keeps running, allowing sampling). If it is
required that LOCK remain high for an undriven input,
the on-chip fail-safe circuit can be supplemented with
external pullup bias resistors.
Losing Lock on Serial Data
If one embedded clock edge (rising edge formed by
end/start bits) is not detected, LOCK goes high, RCLK
tracks REFCLK, and ROUT_ stays active but with
invalid data. LOCK stays high for a minimum of two
RCLK cycles. Then, if transitions are detected at the
serial input, the PLL attempts to lock to the serial input.
When the PLL locks to serial input data, LOCK goes
low, RCLK tracks the serializer reference clock (TCLK),
and ROUT_ is valid on the second selected strobe
edge of RCLK after LOCK goes low. A minimum of two
embedded clock edges in a row are required to regain
lock to the serial input after LOCK goes high.
Deserializer Jitter Tolerance
The t parameter specifies the total zero-to-peak input
JT
jitter the deserializer can tolerate before a sampling
error occurs (Figure 9). Zero-to-peak jitter is measured
from the mean value of the deterministic jitter distribu-
tion. Sources of jitter include the serializer (supply
noise, reference clock jitter, pulse skew, and intersym-
bol interference), the interconnect (intersymbol interfer-
ence, crosstalk, within-pair skew, ground shift), and the
deserializer (supply noise). The sum of the zero-to-peak
individual jitter sources must be less than or equal to
For automatic resynchronization, LOCK can be con-
nected to the MAX9205/MAX9207 serializer SYNC1 or
SYNC2 input. With this connection, when LOCK goes
high, the serializer sends sync patterns until the deseri-
alizer locks to the serial input and drives LOCK low.
the minimum value of t
.
JT
For example, at 40MHz, the MAX9205 serializer has
140ps (p-p) maximum deterministic output jitter. The
zero-to-peak value is 140ps/2 = 70ps. If the intercon-
nect jitter is 100ps (p-p) with a symmetrical distribution,
the zero-to-peak jitter is 50ps. The MAX9206 deserializ-
er jitter tolerance is 720ps at 40MHz. The total zero-to-
peak input jitter is 70ps + 50ps = 120ps, which is less
than the jitter tolerance. In this case, the margin is
720ps - 120ps = 600ps.
Input Fail-Safe
When the serial input is undriven (a disconnected cable
or serializer output in high impedance, for example) an
on-chip fail-safe circuit (Figure 2) drives the serial input
high. The response time of the fail-safe circuit depends
on interconnect characteristics. With an undriven input,
LOCK may switch high and low until the fail-safe circuit
takes effect. The undriven condition of the link can be
_______________________________________________________________________________________
9
10-Bit Bus LVDS Deserializers
simple coaxial cable. Balanced cables such as twisted
tRCP/12
pair offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by a differential receiver.
tJT
tJT
Eliminate reflections and ensure that noise couples as
common mode by running differential traces close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
VID = 150mV
Maintain a constant distance between the differential
traces to avoid discontinuities in differential impedance.
Avoid 90° turns and minimize the number of vias to fur-
ther prevent impedance discontinuities.
Figure 9. Input Jitter Tolerance
Applications Information
Power-Supply Bypassing
Bypass each supply pin with high-frequency surface-
mount ceramic 0.1µF and 0.001µF capacitors in paral-
lel as close to the device as possible, with the smaller
valued capacitor the closest to the supply pin.
SERIALIZED DATA
PARALLEL
DATA IN
PARALLEL
DATA OUT
100Ω
100Ω
MAX9205
MAX9207
MAX9206
MAX9208
Differential Traces and Termination
Trace characteristics affect the performance of the
MAX9206/MAX9208. Use controlled-impedance media.
Avoid the use of unbalanced cables such as ribbon or
Figure 10. Double-Termination Point-to-Point
ASIC
ASIC
ASIC
MAX9206
MAX9208
MAX9206
MAX9208
MAX9205
MAX9207
MAX9150
REPEATER
100Ω
100Ω
100Ω
100Ω
Figure 11. Point-to-Point Broadcast Using MAX9150 Repeater
10 _____________________________________________________________________________________
10-Bit Bus LVDS Deserializers
Table 2. Input/Output Function Table
LOGIC INPUTS
CONDITIONS
Power applied and stable
Deserializer initialized
Deserializer initialized
OUTPUTS
REN
PWRDN
Power-down mode. PLL is stopped. Current consumption is reduced
to 400µA (typ). ROUT_, RCLK, and LOCK are high impedance.
X
Low
RCLK and ROUT_ are high impedance. LOCK is active, indicating
Low
High
High
the serial input status.
RCLK and ROUT_ are active. LOCK is active, indicating the serial
High
input status.
X = don’t care
Topologies
Pin Configuration
The MAX9206/MAX9208 deserializers can operate in a
variety of topologies. Examples of double-terminated
point-to-point and point-to-point broadcast are shown
in Figures 10 and 11. Use 1% surface-mount termina-
tion resistors.
TOP VIEW
AGND
RCLK_R/F
REFCLK
1
2
3
4
5
6
7
8
9
28 ROUT0
27 ROUT1
26 ROUT2
25 ROUT3
24 ROUT4
A point-to-point interface terminated at each end in the
characteristic impedance of the cable or PC board
traces is shown in Figure 10. The total load seen by the
serializer is 50Ω. The double termination typically
reduces reflections compared to a single 100Ω termi-
nation. A single 100Ω termination at the deserializer
input is feasible and makes the differential signal swing
larger.
AV
CC
RI+
RI-
MAX9206/
MAX9208
23 DV
CC
PWRDN
REN
22 DGND
21 DV
CC
RCLK
20 DGND
19 ROUT5
18 ROUT6
17 ROUT7
16 ROUT8
15 ROUT9
A point-to-point version of a multidrop bus is shown in
Figure 11. The low-jitter MAX9150 10-port repeater is
used to reproduce and transmit the serializer output
over 10 double-terminated point-to-point links.
Compared to a bus, more interconnect is traded for
robust hot-plug capability.
LOCK 10
AV 11
CC
AGND 12
AGND 13
DGND 14
The repeater eliminates nine serializers compared to 10
individual point-to-point serializer-to-deserializer con-
nections. Since repeater jitter is a component of the
total jitter seen at the deserializer input (along with
other sources of jitter), a low-jitter repeater is essential
in most high data-rate applications.
SSOP
Chip Information
TRANSISTOR COUNT: 9602
PROCESS: CMOS
Board Layout
A four-layer PC board providing separate power,
ground, and signal layers is recommended. Keep the
LVTTL/LVCMOS inputs and outputs separated from the
BLVDS inputs to prevent coupling into the BLVDS lines.
______________________________________________________________________________________ 11
10-Bit Bus LVDS Deserializers
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
©2020 ICPDF网 联系我们和版权申明