MAX9123EUE+TG60 [MAXIM]
Line Driver;
| 型号： | MAX9123EUE+TG60 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Line Driver 驱动 接口集成电路 |
| 文件： | 总10页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1927; Rev 0; 2/01
Quad LVDS Line Driver with
Flow-Through Pinout
General Description
Features
The MAX9123 quad low-voltage differential signaling
(LVDS) differential line driver is ideal for applications
requiring high data rates, low power, and low noise. The
MAX9123 is guaranteed to transmit data at speeds up to
800Mbps (400MHz) over controlled impedance media of
approximately 100Ω. The transmission media may be
printed circuit (PC) board traces, backplanes, or cables.
ꢀ Flow-Through Pinout
Simplifies PC Board Layout
Reduces Crosstalk
ꢀ Pin Compatible with DS90LV047A
ꢀ Guaranteed 800Mbps Data Rate
ꢀ 250ps Maximum Pulse Skew
The MAX9123 accepts four LVTTL/LVCMOS input levels
and translates them to LVDS output signals. Moreover,
the MAX9123 is capable of setting all four outputs to a
high-impedance state through two enable inputs, EN and
EN, thus dropping the device to an ultra-low-power state
of 16mW (typ) during high impedance. The enables are
common to all four transmitters. Outputs conform to the
ANSI TIA/EIA-644 LVDS standard. Flow-through pinout
simplifies PC board layout and reduces crosstalk by sep-
arating the LVTTL/LVCMOS inputs and LVDS outputs.
ꢀ Conforms to TIA/EIA-644 LVDS Standard
ꢀ Single +3.3V Supply
ꢀ 16-Pin TSSOP and SO Packages
Ordering Information
PART
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
16 TSSOP
16 SO
The MAX9123 operates from a single +3.3V supply and is
specified for operation from -40°C to +85°C. It is available
in 16-pin TSSOP and SO packages. Refer to the MAX9121/
MAX9122* data sheet for quad LVDS line receivers with
integrated termination and flow-through pinout.
MAX9123EUE
MAX9123ESE
Typical Applications Circuit
Applications
LVDS SIGNALS
Digital Copiers
Laser Printers
DSLAMs
MAX9122*
MAX9123
Network
Switches/Routers
Cell Phone Base
Stations
Backplane
T
X
107Ω
107Ω
107Ω
107Ω
R
X
Interconnect
Add Drop Muxes
Clock Distribution
Digital Cross-Connects
T
X
T
X
T
X
R
X
R
X
R
X
Pin Configuration
LVTTL/CMOS
DATA INPUT
LVTTL/CMOS
DATA OUTPUT
TOP VIEW
EN
IN1
IN2
1
2
3
4
5
6
7
8
16 OUT1-
15 OUT1+
14 OUT2+
V
CC
MAX9123
13 OUT2-
12 OUT3-
11 OUT3+
10 OUT4+
GND
IN3
IN4
EN
OUT4-
9
TSSOP/SO
100Ω SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES
* Future product—contact factory for availability.
________________________________________________________________ Maxim Integrated Products
1
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Quad LVDS Line Driver with
Flow-Through Pinout
ABSOLUTE MAXIMUM RATINGS
CC
IN_, EN, EN to GND....................................-0.3V to (V
OUT_+, OUT_- to GND..........................................-0.3V to +3.9V
Short-Circuit Duration (OUT_+, OUT_-) .....................Continuous
V
to GND...........................................................-0.3V to +4.0V
Storage Temperature Range.............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Lead Temperature (soldering, 10s) .................................+300°C
ESD Protection
+ 0.3V)
CC
Continuous Power Dissipation (T = +70°C)
A
16-Pin TSSOP (derate 9.4mW/°C above +70°C) .........755mW
Human Body Model, IN_, OUT_+, OUT_-....................... 4kV
16-Pin SO (derate 8.7mW/°C above +70°C)................696mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, R = 100Ω 1ꢀ, T = -40°C to +85°C. Typical values are at V
= +3.3V, T = +25°C, unless otherwise
CC A
CC
L
A
noted.) (Notes 1, 2)
MAX
UNITS
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
368
1
LVDS OUTPUT (OUT_+, OUT_-)
Differential Output Voltage
V
Figure 1
Figure 1
Figure 1
Figure 1
250
450
35
mV
mV
V
OD
Change in Magnitude of V
Between Complementary Output
States
OD
∆V
OD
Offset Voltage
V
1.125
0.90
1.25
4
1.375
25
OS
Change in Magnitude of V
Between Complementary Output
States
OS
∆V
mV
OS
Output High Voltage
Output Low Voltage
V
1.6
V
V
OH
V
OL
Differential Output Short-Circuit
Current (Note 3)
I
Enabled, V
= 0
OD
-9
-9
mA
mA
µA
OSD
OUT_+ = 0 at IN_ = V
= 0, enabled
or OUT_- = 0 at IN_
CC
Output Short-Circuit Current
Output High-Impedance Current
Power-Off Output Current
I
I
-3.8
OS
EN = low and EN = high, OUT_+ = 0 or V
OUT_- = 0 or V
,
CC
-10
-20
10
20
OZ
, R = ∞
L
CC
V
= 0 or open, OUT_+ = 0 or 3.6V, OUT_-
CC
I
µA
OFF
= 0 or 3.6V, R = ∞
L
INPUTS (IN_, EN, EN)
High-Level Input Voltage
Low-Level Input Voltage
Input Current
V
2.0
GND
-20
V
V
V
IH
CC
V
0.8
20
IL
I
IN_, EN, EN = 0 or V
µA
IN
CC
SUPPLY CURRENT
No-Load Supply Current
Loaded Supply Current
I
R = ∞, IN_ = V or 0 for all channels
CC
9.2
11
30
mA
mA
CC
L
I
R = 100Ω, IN_ = V or 0 for all channels
22.7
CCL
L
CC
Disabled, IN_ = V or 0 for all channels,
CC
Disabled Supply Current
I
4.9
6
mA
CCZ
EN = 0, EN = V
CC
2
_______________________________________________________________________________________
Quad LVDS Line Driver with
Flow-Through Pinout
SWITCHING CHARACTERISTICS
(V
= +3.0V to +3.6V, R = 100Ω 1ꢀ, C = 15pF, T = -40°C to +85°C. Typical values are at V
= +3.3V, T = +25°C, unless
CC A
CC
L
L
A
otherwise noted.) (Notes 4, 5, 6)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Differential Propagation Delay
High to Low
t
Figures 2 and 3
0.7
0.7
1.7
ns
PHLD
PLHD
Differential Propagation Delay
Low to High
t
Figures 2 and 3
Figures 2 and 3
Figures 2 and 3
1.7
ns
ns
ns
Differential Pulse Skew (Note 7)
t
t
0.04
0.25
0.35
SKD1
SKD2
Differential Channel-to-Channel
Skew (Note 8)
0.07
0.13
0.43
Differential Part-to-Part Skew
(Note 9)
t
t
Figures 2 and 3
Figures 2 and 3
0.8
1.0
ns
ns
SKD3
SKD4
Differential Part-to-Part Skew
(Note 10)
Rise Time
t
t
Figures 2 and 3
Figures 2 and 3
Figures 4 and 5
Figures 4 and 5
Figures 4 and 5
Figures 4 and 5
0.2
0.2
0.39
0.39
2.7
1.0
1.0
5
ns
ns
ns
ns
ns
ns
TLH
THL
PHZ
Fall Time
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
t
t
2.7
5
PLZ
t
2.3
7
PZH
t
2.3
7
PZL
Maximum Operating Frequency
(Note 11)
f
400
MHz
MAX
Note 1: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100ꢀ tested
at T = +25°C.
A
Note 2: Currents into the device are positive, and current out of the device is negative. All voltages are referenced to ground except
V
OD
.
Note 3: Guaranteed by correlation data.
Note 4: AC parameters are guaranteed by design and characterization.
Note 5: C includes probe and jig capacitance.
L
Note 6: Signal generator conditions for dynamic tests: V = 0, V
= 3V, f = 100MHz, 50ꢀ duty cycle, R = 50Ω, t ≤ 1ns, t ≤
O R F
OL
OH
1ns (0ꢀ to 100ꢀ).
Note 7: t
Note 8: t
is the magnitude difference of differential propagation delay. t
= |t
PHLD
- t
|.
SKD1
SKD2
SKD1
PHLD PLHD
is the magnitude difference of t
or t
of one channel to the t
or t
of another channel on the same
PHLD
PLHD
PLHD
device.
Note 9: t is the magnitude difference of any differential propagation delays between devices at the same V
and within 5°C
CC
SKD3
of each other.
Note 10:t is the magnitude difference of any differential propagation delays between devices operating over the rated supply
SKD4
and temperature ranges.
Note 11: f signal generator conditions: V = 0, V
= 3V, f = 400MHz, 50ꢀ duty cycle, R = 50Ω, t ≤ 1ns, t ≤ 1ns (0ꢀ to
MAX
OL
OH
O
R
F
100ꢀ). Transmitter output criteria: duty cycle = 45ꢀ to 55ꢀ, V
≥ 250mV.
OD
_______________________________________________________________________________________
3
Quad LVDS Line Driver with
Flow-Through Pinout
Typical Operating Characteristics
(V
= +3.3V, R = 100Ω, C = 15pF, T = +25°C, unless otherwise noted.)
CC
L
L
A
OUTPUT LOW VOLTAGE
vs. POWER-SUPPLY VOLTAGE
OUTPUT HIGH VOLTAGE
vs. POWER-SUPPLY VOLTAGE
OUTPUT SHORT-CIRCUIT CURRENT
vs. POWER-SUPPLY VOLTAGE
-3.700
-3.695
-3.690
-3.685
-3.680
-3.675
-3.670
-3.665
-3.660
-3.655
-3.650
1.100
1.100
1.098
1.096
1.094
1.092
1.090
V
GND
= V or
CC
IN
1.098
1.096
1.094
1.092
1.090
3.0
3.3
3.6
3.0
3.3
3.6
3.0
3.3
3.6
POWER-SUPPLY VOLTAGE (V)
POWER-SUPPLY VOLTAGE (V)
POWER-SUPPLY VOLTAGE (V)
DIFFERENTIAL OUTPUT VOLTAGE
vs. POWER SUPPLY
OUTPUT HIGH-IMPEDANCE STATE CURRENT
DIFFERENTIAL OUTPUT VOLTAGE
vs. LOAD RESISTOR
vs. POWER-SUPPLY VOLTAGE
0
390
385
380
375
370
365
360
355
350
600
550
500
450
400
350
300
V
GND
= V or
CC
IN
-50
-100
-150
-200
-250
3.0
3.3
3.6
3.0
3.3
3.6
90
100
110
120
130
140
150
POWER-SUPPLY VOLTAGE (V)
LOAD RESISTOR (Ω)
POWER-SUPPLY VOLTAGE (V)
POWER-SUPPLY CURRENT
vs. POWER-SUPPLY VOLTAGE
OFFSET VOLTAGE
vs. POWER-SUPPLY VOLTAGE
POWER-SUPPLY CURRENT
vs. FREQUENCY
40
38
35
33
30
28
25
23
20
1.260
1.256
1.252
1.248
1.244
1.240
25.0
24.0
23.0
22.0
21.0
20.0
V
IN
= 0 to 3V
FREQ = 1MHz
IN
V
= 0 to 3V
ALL SWITCHING
ONE SWITCHING
100
3.0
3.3
3.6
0.1
1
10
1000
3.0
3.3
POWER-SUPPLY VOLTAGE (V)
3.6
POWER-SUPPLY VOLTAGE (V)
FREQUENCY (MHz)
4
_______________________________________________________________________________________
Quad LVDS Line Driver with
Flow-Through Pinout
Typical Operating Characteristics (continued)
(V
= +3.3V, R = 100Ω, C = 15pF, T = +25°C, unless otherwise noted.)
CC
L
L
A
POWER-SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
DIFFERENTIAL PROPAGATION DELAY
vs. AMBIENT TEMPERATURE
DIFFERENTIAL PROPAGATION DELAY
vs. POWER SUPPLY
1.600
1.500
1.400
1.300
1.200
1.100
25.0
1.600
1.550
1.500
1.450
1.400
1.350
1.300
1.250
1.200
FREQ = 1MHz
= 0 to 3V
FREQ = 1MHz
V
IN
24.0
23.0
22.0
21.0
20.0
t
t
PLHD
PLHD
t
PHLD
t
PHLD
FREQ = 1MHz
-40
-15
10
35
60
85
-40
-15
10
35
60
85
3.0
3.3
3.6
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
POWER-SUPPLY VOLTAGE (V)
DIFFERENTIAL SKEW
vs. POWER-SUPPLY VOLTAGE
DIFFERENTIAL SKEW
vs. AMBIENT TEMPERATURE
100
80
60
40
20
0
200
175
150
125
100
75
FREQ = 1MHz
FREQ = 1MHz
50
25
0
3.0
3.3
3.6
-40
-15
10
35
60
85
POWER-SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
TRANSITION TIME
vs. AMBIENT TEMPERATURE
TRANSITION TIME
vs. POWER-SUPPLY VOLTAGE
600
550
500
450
400
350
300
250
200
400
390
380
370
360
350
340
FREQ = 1MHz
FREQ = 1MHz
t
t
TLH
t
TLH
t
THL
THL
-40
-15
10
35
60
85
3.0
3.3
POWER-SUPPLY VOLTAGE (V)
3.6
AMBIENT TEMPERATURE (°C)
_______________________________________________________________________________________
5
Quad LVDS Line Driver with
Flow-Through Pinout
Pin Description
PIN
NAME
EN
FUNCTION
Driver Enable Input. The driver is disabled when EN is low. EN is internally pulled down. When EN =
high and EN = low or open, the outputs are active. For other combinations of EN and EN, the
outputs are disabled and are high impedance.
1
2, 3, 6, 7
IN_
LVTTL/LVCMOS Driver Inputs
4
V
Power-Supply Input. Bypass V
Ground
to GND with 0.1µF and 0.001µF ceramic capacitors.
CC
CC
5
GND
EN
8
Driver Enable Input. The transmitter is disabled when EN is high. EN is internally pulled down.
Inverting LVDS Driver Outputs
9, 12, 13, 16
10, 11, 14, 15
OUT_-
OUT_+
Noninverting LVDS Driver Outputs
Termination
Detailed Description
Because the MAX9123 is a current-steering device, no
output voltage will be generated without a termination
resistor. The termination resistors should match the dif-
ferential impedance of the transmission line. Output
voltage levels depend upon the value of the termination
resistor. The MAX9123 is optimized for point-to-point
interface with 100Ω termination resistors at the receiver
inputs. Termination resistance values may range
between 90Ω and132Ω, depending on the characteris-
tic impedance of the transmission medium.
The LVDS interface standard is a signaling method
intended for point-to-point communication over a con-
trolled-impedance medium as defined by the
ANSI/TIA/EIA-644 and IEEE 1596.3 standards. The
LVDS standard uses a lower voltage swing than other
common communication standards, achieving higher
data rates with reduced power consumption while
reducing EMI emissions and system susceptibility to
noise.
The MAX9123 is an 800Mbps quad differential LVDS
driver that is designed for high-speed, point-to-point,
and low-power applications. This device accepts
LVTTL/LVCMOS input levels and translates them to
LVDS output signals.
Table 1. Input/Output Function Table
ENABLES
EN
INPUTS
OUTPUTS
EN
H
IN_
L
OUT_+
OUT_ -
The MAX9123 generates a 2.5mA to 4.0mA output cur-
rent using a current-steering configuration. This current-
steering approach induces less ground bounce and no
shoot-through current, enhancing noise margin and sys-
tem speed performance. The driver outputs are short-
circuit current limited, and enter a high-impedance state
when the device is not powered or is disabled.
L or open
L or open
L
H
L
H
H
H
All other combinations
of ENABLE pins
Don’t
care
Z
Z
Applications Information
The current-steering architecture of the MAX9123
requires a resistive load to terminate the signal and
complete the transmission loop. Because the device
switches current and not voltage, the actual output volt-
age swing is determined by the value of the termination
resistor at the input of an LVDS receiver. Logic states
are determined by the direction of current flow through
the termination resistor. With a typical 3.7mA output
current, the MAX9123 produces an output voltage of
370mV when driving a 100Ω load.
Power-Supply Bypassing
with high-frequency, surface-mount
Bypass V
CC
ceramic 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smaller valued
capacitor closest to V
.
CC
Differential Traces
Output trace characteristics affect the performance of
the MAX9123. Use controlled-impedance traces to
match trace impedance to the transmission medium.
6
_______________________________________________________________________________________
Quad LVDS Line Driver with
Flow-Through Pinout
C
L
OUT_+
OUT_ +
R /2
L
V
IN_
CC
IN_
R
L
V
OS
V
OD
GENERATOR
GND
R /2
L
OUT_ -
50Ω
C
L
OUT_-
Figure 2. Driver Propagation Delay and Transition Time Test
Circuit
Figure 1. Driver V
and V Test Circuit
OS
OD
3V
1.5V
1.5V
IN_
0
t
t
PHLD
PLHD
OUT_ -
OUT_+
V
OH
OL
0 DIFFERENTIAL
80%
0
V
80%
-)
0
V
DIFF
= (V
+) - (V
OUT_
OUT_
0
V
DIFF
20%
20%
t
t
THL
TLH
Figure 3. Driver Propagation Delay and Transition Time Waveforms
Eliminate reflections and ensure that noise couples as
common mode by running the differential trace pairs
close together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by the LVDS receiver.
Board Layout
For LVDS applications, a four-layer PC board that pro-
vides separate power, ground, LVDS signals, and input
signals is recommended. Isolate the LVTTL/LVCMOS
and LVDS signals from each other to prevent coupling.
Maintain the distance between the differential traces to
avoid discontinuities in differential impedance. Avoid
90° turns and minimize the number of vias to further
prevent impedance discontinuities.
Cables and Connectors
Transmission media should have a nominal differential
impedance of 100Ω. To minimize impedance disconti-
nuities, use cables and connectors that have matched
differential impedance.
Chip Information
TRANSISTOR COUNT: 1246
PROCESS: CMOS
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
_______________________________________________________________________________________
7
Quad LVDS Line Driver with
Flow-Through Pinout
Functional Diagram
C
L
OUT1+
OUT_+
IN1
IN2
IN3
IN4
V
CC
IN_
R
R
L/2
OUT1-
OUT2+
GND
+1.2V
EN
EN
GENERATOR
L/2
50Ω
OUT_-
1/4 MAX9123
C
L
OUT2-
OUT3+
Figure 4. Driver High-Impedance Delay Test Circuit
OUT3-
OUT4+
OUT4-
EN
EN
EN WHEN EN = 0 OR OPEN
3V
0
1.5V
1.5V
1.5V
3V
0
1.5V
PHZ
EN WHEN EN = V
CC
t
t
PZH
OUT_+ WHEN IN_ = V
CC
V
OH
OUT_- WHEN IN_ = 0
50%
50%
50%
50%
1.2V
1.2V
OUT_+ WHEN IN_ = 0
OUT_- WHEN IN_ = V
V
OL
CC
t
t
PZL
PLZ
Figure 5. Driver High-Impedance Delay Waveform
_______________________________________________________________________________________
8
Quad LVDS Line Driver with
Flow-Through Pinout
Package Information
_______________________________________________________________________________________
9
Quad LVDS Line Driver with
Flow-Through Pinout
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
©2020 ICPDF网 联系我们和版权申明