MAX9125 [MAXIM]
Quad LVDS Line Receivers with Integrated Termination; 四路LVDS线接收器，内部端接
| 型号： | MAX9125 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Quad LVDS Line Receivers with Integrated Termination |
| 文件： | 总12页 (文件大小：226K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1908; Rev 0; 5/01
Quad LVDS Line Receivers with
Integrated Termination
General Description
Features
The MAX9125/MAX9126 quad low-voltage differential
signaling (LVDS) line receivers are ideal for applica-
tions requiring high data rates, low power, and reduced
noise. The MAX9125/MAX9126 are guaranteed to
receive data at speeds up to 500Mbps (250MHz) over
controlled-impedance media of approximately 100Ω.
The transmission media may be printed circuit (PC)
board traces or cables.
ꢀ Integrated Termination Eliminates Four External
Resistors (MAX9126)
ꢀ Pin Compatible with DS90LV032A
ꢀ Guaranteed 500Mbps Data Rate
ꢀ 300ps Pulse Skew (max)
ꢀ Conform to ANSI TIA/EIA-644 LVDS Standard
ꢀ Single +3.3V Supply
The MAX9125/MAX9126 accept four LVDS differential
inputs and translate them to 3.3V CMOS outputs. The
MAX9126 features integrated parallel termination resis-
tors (nominally 115Ω), which eliminate the requirement
for four discrete termination resistors and reduce stub
length. The MAX9125 inputs are high impedance and
require an external termination resistor when used in a
point-to-point connection.
ꢀ Low 70µA Shutdown Supply Current
ꢀ Fail-Safe Circuit
Ordering Information
PART
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
16 TSSOP
16 SO
The devices support a wide common-mode input range
of 0.05V to 2.35V, allowing for ground potential differ-
ences and common-mode noise between the driver
and the receiver. A fail-safe feature sets the output high
when the inputs are open, or when the inputs are
undriven and shorted or parallel terminated. The EN
and EN inputs control the high-impedance output and
are common to all four receivers. Inputs conform to the
ANSI TIA/EIA-644 LVDS standard. The MAX9125/
MAX9126 operate from a single +3.3V supply, are
specified for operation from -40°C to +85°C, and are
available in 16-pin TSSOP and SO packages. Refer to
the MAX9124 data sheet for a quad LVDS line driver.
MAX9125EUE
MAX9125ESE
MAX9126EUE
MAX9126ESE
16 TSSOP
16 SO
Typical Application Circuit
LVDS SIGNALS
MAX9126
MAX9124
T
X
T
X
T
X
T
X
115Ω
115Ω
115Ω
115Ω
R
X
R
X
R
X
R
X
Applications
Digital Copiers
Laser Printers
Cellular Phone Base Stations
Add/Drop Muxes
LVTTL/LVCMOS
DATA INPUT
LVTTL/LVCMOS
DATA OUTPUT
Digital Cross-Connects
DSLAMs
Network Switches/Routers
Backplane Interconnect
Clock Distribution
Pin Configuration appears at end of data sheet.
100Ω SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Quad LVDS Line Receivers with
Integrated Termination
ABSOLUTE MAXIMUM RATINGS
CC
IN_+, IN_- to GND .................................................-0.3V to +4.0V
EN, EN to GND...........................................-0.3V to (V
V
to GND...........................................................-0.3V to +4.0V
Storage Temperature Range.............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Lead Temperature (soldering, 10s) .................................+300°C
ESD Protection (Human Body Model) IN_+, IN_-, OUT_............ 7.5ꢀV
+ 0.3V)
+ 0.3V)
CC
CC
OUT_ to GND .............................................-0.3V to (V
Continuous Power Dissipation (T = +70°C)
A
16-Pin TSSOP (derate 9.4mW/°C above +70°C) .........755mW
16-Pin SO (derate 8.7mW/°C above +70°C)................696mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, differential input voltage |V | = 0.1V to 1.0V, common-mode voltage V
= |V /2| to 2.4V - |V /2|, T =
A
CC
ID
CM
ID
ID
-40°C to +85°C. Typical values are at V
= +3.3V, T = +25°C, unless otherwise noted.) (Note 1)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LVDS INPUTS (IN_+, IN_-)
Differential Input High Threshold
Differential Input Low Threshold
V
100
mV
mV
TH
V
-100
-20
-25
-20
-25
35
TL
0.1V ≤V ≤ 0.6V,
20
25
20
25
ID
I
I
_+,
_-
IN
Input Current (MAX9125)
µA
µA
I
IN
0.6V <V ≤ 1.0V
ID
0.1V ≤V ≤ 0.6V, V = 0
ID
CC
Power-Off Input Current
(MAX9125)
_+,
_-
IN
I
IN
0.6V <V ≤ 1.0V, V = 0
ID CC
Input Resistor 1
Input Resistor 2
R
R
V
V
= +3.6V or 0, Figure 1
= +3.6V or 0, Figure 1
ꢀΩ
ꢀΩ
IN1
IN2
CC
CC
132
Differential Input Resistance
(MAX9126)
R
V
= +3.6V or 0, Figure 1
90
115
3.2
132
Ω
DIFF
CC
LVCMOS/LVTTL OUTPUTS (OUT_)
Open, undriven short, or
undriven 100Ω parallel
I
=
OH
2.7
-4.0mA
(MAX9125)
termination
Output High Voltage
V
V
V
= +100mV
2.7
2.7
3.2
3.2
OH
ID
I
=
Open or undriven short
= +100mV
OH
-4.0mA
(MAX9126)
V
2.7
3.2
0.1
ID
Output Low Voltage
V
I
= +4.0mA, V = -100mV
0.25
-120
+10
V
OL
OS
OZ
OL
ID
Output Short-Circuit Current
Output High-Impedance Current
I
Enabled, V = +100mV, V
_ = 0 (Note 2)
-15
-10
mA
µA
ID
OUT
I
Disabled, V
_ = 0 or V
OUT CC
2
_______________________________________________________________________________________
Quad LVDS Line Receivers with
Integrated Termination
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, differential input voltage |V | = 0.1V to 1.0V, common-mode voltage V
= |V /2| to 2.4V - |V /2|, T =
A
CC
ID
CM
ID
ID
-40°C to +85°C. Typical values are at V
= +3.3V, T = +25°C, unless otherwise noted.) (Note 1)
CC
A
PARAMETER
LOGIC INPUTS (EN, EN)
Input High Voltage
Input Low Voltage
Input Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
2.0
0
V
V
V
IH
CC
V
0.8
15
IL
I
V
= V or 0
CC
-15
µA
IN
IN
SUPPLY
Supply Current
I
Enabled, inputs open
Disabled, inputs open
9
15
mA
µA
CC
Disabled Supply Current
I
70
500
CCZ
AC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, C = 10pF, differential input voltage |V | = 0.2V to 1.0V, common-mode voltage V
= |V /2| to 2.4V
L
- |VCC /2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, T = -40°C to +85°C. Typical values are at V
=
CC
ID
CM
ID
ID
A
+3.3V, V
= 1.2V, |V | = 0.2V, T = +25°C, unless otherwise noted.) (Notes 3, 4)
CM
ID
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Differential Propagation Delay
High to Low
t
t
t
t
t
t
Figures 2 and 3
Figures 2 and 3
Figures 2 and 3
Figures 2 and 3
Figures 2 and 3
Figures 2 and 3
1.8
2.4
3.3
ns
PHLD
PLHD
SKD1
SKD2
SKD3
SKD4
Differential Propagation Delay
Low to High
1.8
2.3
3.3
300
400
0.8
1.5
ns
ps
ps
ns
ns
Differential Pulse Sꢀew
100
[t
-t
] (Note 5)
PHLD PLHD
Differential Channel-to-Channel
Sꢀew (Note 6)
Differential Part-to-Part Sꢀew
(Note 7)
Differential Part-to-Part Sꢀew
(Note 8)
Rise Time
t
t
Figures 2 and 3
Figures 2 and 3
0.34
0.32
1.2
1.2
12
12
17
17
ns
ns
ns
ns
ns
ns
TLH
THL
PHZ
Fall Time
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
t
R = 2ꢀΩ, Figures 4 and 5
L
t
R = 2ꢀΩ, Figures 4 and 5
L
PLZ
PZH
t
R = 2ꢀΩ, Figures 4 and 5
L
t
R = 2ꢀΩ, Figures 4 and 5
L
PZL
Maximum Operating Frequency
(Note 9)
f
All channels switching
250
300
MHz
MAX
_______________________________________________________________________________________
3
Quad LVDS Line Receivers with
Integrated Termination
AC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, CL = 10pF, differential input voltage |V | = 0.2V to 1.0V, common-mode voltage V
= |V /2| to 2.4V
ID
CM
ID
- |CVC /2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, T = -40°C to +85°C. Typical values are at V
=
CC
ID
A
+3.3V, V
= 1.2V, |V | = 0.2V, T = +25°C, unless otherwise noted.) (Notes 3, 4)
CM
ID
A
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V , V , and V
.
ID
TH
TL
Note 2: Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.
Note 3: AC parameters are guaranteed by design and characterization.
Note 4: C includes scope probe and test jig capacitance.
L
Note 5: t
Note 6: t
is the magnitude difference of differential propagation delays in a channel; t
= |t
- tPLHD|.
SKD1
SKD2
SKD1
PHLD
is the magnitude difference of the t
or t
of one channel and the t
or t
of any other channel on the
PLHD
PHLD
PLHD
PHLD
same part.
Note 7: t is the magnitude difference of any differential propagation delays between parts operating over rated conditions at
SKD3
the same V
and within 5°C of each other.
CC
Note 8: t
Note 9: f
is the magnitude difference of any differential propagation delays between parts operating over rated conditions.
SKD4
MAX
generator output conditions: t = t < 1ns (0% to 100%), 50% duty cycle, V = 1.1V, V = 1.3V. Receiver output
R
F
OL
OH
criteria: 60% to 40% duty cycle, V = 0.4V (max), V
= 2.7V (min), load = 10pF.
OL
OH
Typical Operating Characteristics
(V = +3.3V, |V | = 200mV, V
= +1.2V, C = 10pF, frequency = 10MHz, T = +25°C, unless otherwise noted.) (Figures 2 and 3)
CC
ID
CM
L
A
DIFFERENTIAL PROPAGATION DELAY
vs. DIFFERENTIAL INPUT VOLTAGE
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
SUPPLY CURRENT vs. SWITCHING
FREQUENCY, FOUR CHANNELS SWITCHING
100
90
80
70
60
50
40
30
20
10
0
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.8
2.6
2.4
2.2
2.0
t
PHLD
V
= +3.6V
CC
t
t
PLHD
PHLD
V
1
= +3.3V
CC
t
PLHD
V
= +3V
CC
100
500
900 1300 1700 2100 2500
-40
-15
10
35
60
85
0.01
0.1
10
100
1000
DIFFERENTIAL INPUT VOLTAGE (mV)
TEMPERATURE (°C)
SWITCHING FREQUENCY (MHz)
4
_______________________________________________________________________________________
Quad LVDS Line Receivers with
Integrated Termination
Typical Operating Characteristics (continued)
(V = +3.3V, |V | = 200mV, V
= +1.2V, C = 10pF, frequency = 10MHz, T = +25°C, unless otherwise noted (Figures 2 and 3).)
CC
ID
CM
L
A
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
DIFFERENTIAL PROPAGATION DELAY
vs. COMMON-MODE VOLTAGE
PULSE SKEW vs. SUPPLY VOLTAGE
2.6
2.5
2.4
2.3
2.2
2.6
2.5
2.4
2.3
2.2
200
175
150
125
100
75
t
PHLD
t
PHLD
t
PLHD
3.2
t
PLHD
50
3.0
3.1
3.3
3.4
3.5
3.6
0
0.5
1.0
1.5
2.0
2.5
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
SUPPLY VOLTAGE (V)
TRANSITION TIME vs. CAPACITIVE LOAD
PULSE SKEW vs. TEMPERATURE
200
175
150
125
100
75
1000
900
800
700
600
500
400
300
200
100
0
t
TLH
t
THL
50
-40
-15
10
35
60
85
5
10
15
20
25
TEMPERATURE (°C)
CAPACITIVE LOAD (pF)
Pin Description
PIN
NAME
FUNCTION
1, 7, 9, 15
2, 6, 10, 14
3, 5, 11, 13
IN_-
IN_+
OUT_
Inverting Differential Receiver Inputs
Noninverting Differential Receiver Inputs
LVCMOS/LVTTL Receiver Outputs
Receiver Enable Inputs. When EN = low and EN = high, the outputs are disabled and in high
impedance. For other combinations of EN and EN, the outputs are active.
4, 12
EN, EN
8
GND
Ground
16
V
Power Supply Input. Bypass V
to GND with 0.1µF and 0.001µF ceramic capacitors.
CC
CC
_______________________________________________________________________________________
5
Quad LVDS Line Receivers with
Integrated Termination
Table 1. Input/Output Function Table
ENABLES
INPUTS
(IN_+) - (IN_-)
X
OUTPUT
EN
EN
OUT_
L
H
Z
H
L
V
V
≥ +100mV
≤ -100mV
ID
ID
Open, undriven short, or
undriven 100Ω parallel
termination
All other combinations of ENABLE inputs
MAX9125
MAX9126
H
Open or undriven short
V
V
CC
CC
R
R
IN2
IN2
V
CC
- 0.3V
V
- 0.3V
CC
IN_+
IN_-
IN_+
R
R
R
R
IN1
IN1
IN1
IN1
OUT_
OUT_
R
DIFF
IN_-
MAX9125
MAX9126
Figure 1. Inputs with Internal Fail-Safe Circuitry
input voltage range of 0 to 2.4V. The 250mV to 400mV
differential output of an LVDS driver is nominally cen-
tered around a +1.2V offset. This offset, coupled with
the receiver’s 0 to 2.4V input voltage range, allows an
approximate 1V shift in the signal (as seen by the
receiver). This allows for a difference in ground refer-
ences of the transmitter and the receiver, the common-
mode effects of coupled noise, or both. The LVDS
standards specify an input voltage range of 0 to 2.4V
referenced to receiver ground.
Detailed Description
The LVDS interface standard is a signaling method
intended for point-to-point communication over a con-
trolled-impedance medium as defined by the ANSI
TIA/EIA-644 and IEEE 1596.3 standards. The LVDS
standard uses a lower voltage swing than other com-
mon communication standards, achieving higher data
rates with reduced power consumption while reducing
EMI emissions and system susceptibility to noise.
The MAX9125/MAX9126 are 500Mbps, four-channel
LVDS receivers intended for high-speed, point-to-point,
low-power applications. Each channel accepts an
LVDS input and translates it to an LVTTL/LVCMOS out-
put. The receiver is capable of detecting differential
signals as low as 100mV and as high as 1V within an
The MAX9126 has an integrated termination resistor
internally connected across each receiver input. The
internal termination saves board space, eases layout,
and reduces “stub length” compared to an external ter-
mination resistor. In other words, the transmission line
is terminated on the IC.
6
_______________________________________________________________________________________
Quad LVDS Line Receivers with
Integrated Termination
IN_+
PULSE**
GENERATOR
OUT_
IN_-
C
L
50Ω*
50Ω*
RECEIVER ENABLED
1/4 MAX9125/MAX9126
*50Ω REQUIRED FOR PULSE GENERATOR.
**WHEN TESTING MAX9126, ADJUST THE PULSE GENERATOR OUTPUT
TO ACCOUNT FOR INTERNAL TERMINATION RESISTOR.
Figure 2. Transition Time and Propagation Delay Test Circuit
IN_-
IN_+
V
ID
O (DIFFERENTIAL)
O (DIFFERENTIAL)
t
t
PHLD
PLHD
V
V
OH
80%
50%
80%
(V - + V _+)
IN_
IN
NOTE: V
CM =
2
50%
20%
20%
OUT_
OL
t
t
THL
TLH
Figure 3. Transition Time and Propagation Delay Timing Diagram
V
CC
S
1
R
L
IN_+
IN_-
DEVICE
UNDER
TEST
OUT_
GENERATOR
EN
EN
C
L
50Ω
1/4 MAX9125/MAX9126
C INCLUDES LOAD AND TEST JIG CAPACITANCE.
L
S = V FOR t AND t MEASUREMENTS.
1
CC
PZL
PLZ
S = GND FOR t AND t MEASUREMENTS.
1
PZH
PHZ
Figure 4. High-Z Delay Test Circuit
_______________________________________________________________________________________
7
Quad LVDS Line Receivers with
Integrated Termination
EN WHEN EN = V
3V
0
CC
1.5V
1.5V
3V
0
1.5V
1.5V
EN WHEN EN = GND
OUTPUT WHEN
t
PZL
V
CC
t
t
PLZ
50%
0.5V
V
V
OL
V
= -100mV
ID
t
PZH
PHZ
OUTPUT WHEN
= +100mV
OH
0.5V
V
ID
50%
GND
Figure 5. High-Z Delay Waveforms
Fail-Safe
Applications Information
The fail-safe feature of the MAX9125/MAX9126 sets the
output high when:
Power-Supply Bypassing
pin with high-frequency surface-mount
Bypass the V
CC
• Inputs are open.
ceramic 0.1µF and 0.001µF capacitors in parallel, as
close to the device as possible, with the smaller valued
• Inputs are undriven and shorted.
• Inputs are undriven and terminated.
capacitor closest to V
.
CC
A fail-safe circuit is important because under these
conditions, noise at the inputs may switch the receiver
and it may appear to the system that data is being
received. Open or undriven terminated input conditions
can occur when a cable is disconnected or cut, or
when the LVDS driver outputs are high impedance. A
short condition can occur because of a cable failure.
Differential Traces
Input trace characteristics affect the performance of the
MAX9125/MAX9126. Use controlled-impedance PC
board traces to match the cable characteristic imped-
ance. The termination resistor is also matched to this
characteristic impedance.
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce sꢀew by matching the electrical
length of the traces. Excessive sꢀew can result in a
degradation of magnetic field cancellation.
The fail-safe input networꢀ (Figure 1) samples the input
common-mode voltage and compares it to V
- 0.3V
CC
(nominal). When the input is driven to levels specified in
the LVDS standards, the input common-mode voltage
is less than V
- 0.3V and the fail-safe circuit is not
CC
Each channel’s differential signals should be routed
close to each other to cancel their external magnetic
field. Maintain a constant distance between the differ-
ential traces to avoid discontinuities in differential
impedance. Avoid 90° turns and vias to further prevent
impedance discontinuities.
activated. If the inputs are open or if the inputs are
undriven and shorted or undriven and parallel terminat-
ed, there is no input current. In this case, a pullup resis-
tor in the fail-safe circuit pulls both inputs above V
-
CC
0.3V, activating the fail-safe circuit and forcing the out-
put high.
Cables and Connectors
Transmission media typically have a controlled differen-
tial impedance of 100Ω. Use cables and connectors
8
_______________________________________________________________________________________
Quad LVDS Line Receivers with
Integrated Termination
that have matched differential impedance to minimize
Board Layout
Keep the LVDS and any other digital signals separated
from each other to reduce crosstalꢀ.
impedance discontinuities.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
picꢀ up noise as common mode, which is rejected by
the LVDS receiver.
For LVDS applications, use a four-layer PC board that
provides separate power, ground, LVDS signals, and
output signals. Isolate the input LVDS signals from the
output LVCMOS/LVTTL signals to prevent coupling.
Separate the input LVDS signal plane from the LVC-
MOS/LVTTL output signal plane with the power and
ground planes for best results.
Termination
The MAX9126 has an integrated termination resistor
connected across the inputs of each receiver. The
value of the integrated resistor is specified in the DC
characteristics.
Chip Information
TRANSISTOR COUNT: 940
PROCESS: CMOS
The MAX9125 requires an external termination resistor.
The termination resistor should match the differential
impedance of the transmission line. Termination resis-
tance values range between 90Ω and 132Ω, depend-
ing on the characteristic impedance of the transmission
medium.
When using the MAX9125, minimize the distance
between the input termination resistors and the MAX9125
receiver inputs. Use 1% surface-mount resistors.
_______________________________________________________________________________________
9
Quad LVDS Line Receivers with
Integrated Termination
Functional Diagram
V
V
CC
CC
I
I
+
N1+
N1
Rx
Rx
Rx
Rx
Rx
Rx
Rx
Rx
OUT1
OUT2
OUT3
OUT4
OUT1
OUT2
OUT3
OUT4
R
R
R
R
DIFF
DIFF
DIFF
DIFF
I
I
N1-
N1-
+
I
I
N2+
N2
I
I
I
N2-
N2-
I
+
N3+
N3-
N3
I
I
N3-
+
I
I
N4
N4+
I
I
N4-
N4-
EN
EN
EN
EN
MAX9125
MAX9126
GND
GND
Pin Configuration
TOP VIEW
IN1-
IN1+
OUT1
EN
1
2
3
4
5
6
7
8
16 V
CC
15 IN4-
14 IN4+
13 OUT4
12 EN
MAX9125
MAX9126
OUT2
IN2+
IN2-
GND
11 OUT3
10 IN3+
9
IN3-
TSSOP/SO
10 ______________________________________________________________________________________
Quad LVDS Line Receivers with
Integrated Termination
Package Information
______________________________________________________________________________________ 11
Quad LVDS Line Receivers with
Integrated Termination
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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