MAX8794ETB/V+T [MAXIM]
Regulator,;
| 型号： | MAX8794ETB/V+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Regulator, 稳压器 双倍数据速率 |
| 文件： | 总13页 (文件大小：386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0584; Rev 0; 8/06
Low-Voltage DDR Linear Regulator
General Description
Features
The MAX8794 DDR linear regulator sources and sinks up
to 3A peak (typ) using internal n-channel MOSFETs. This
linear regulator delivers an accurate 0.5V to 1.5V output
♦ Internal Power MOSFETs with Current Limit (3A typ)
♦ Fast Load-Transient Response
♦ External Reference Input with Reference
Output Buffer
♦ 1.1V to 3.6V Power Input
from a low-voltage power input (V = 1.1V to 3.6V). The
IN
MAX8794 uses a separate 3.3V bias supply to power the
control circuitry and drive the internal n-channel MOSFETs.
The MAX8794 provides current and thermal limits to pre-
vent damage to the linear regulator. Additionally, the
MAX8794 generates a power-good (PGOOD) signal to
indicate that the output is in regulation. During startup,
PGOOD remains low until the output is in regulation for 2ms
(typ). The internal soft-start limits the input surge current.
♦
15mV (max) Load-Regulation Error
♦ Thermal-Fault Protection
♦ Shutdown Input
♦ Power-Good Window Comparator with 2ms (typ)
Delay
♦ Small, Low-Profile, 10-Pin, 3mm x 3mm TDFN
Package
The MAX8794 powers the active-DDR termination bus
that requires a tracking input reference. The MAX8794
can also be used in low-power chipsets and graphics
processor cores that require dynamically adjustable
output voltages. The MAX8794 is available in a 10-pin,
3mm x 3mm, TDFN package.
♦ Ceramic or Polymer Output Capacitors
Applications
Ordering Information
Notebook/Desktop Computers
TEMP PIN-
RANGE PACKAGE
TOP
MARK
PKG
CODE
PART
DDR Memory Termination
Active Termination Buses
-40°C to 10 TDFN
+85°C (3mm x 3mm)
MAX8794ETB+
ABD
T1033-1
Graphics Processor Core Supplies
Chipset/RAM Supplies as Low as 0.5V
+Denotes lead-free package.
Pin Configuration
Typical Operating Circuit
V
IN
(1.1V TO 3.6V)
V
= V
TT
OUT
IN
OUT
TOP VIEW
OUTS
V
BIAS
1
2
3
4
5
10
9
MAX8794
REFOUT
IN
(2.7V TO 3.6V)
V
OUT
V
PGND
AGND
CC
CC
8
AGND
REFIN
PGND
SHDN
OUTS
SHDN
MAX8794
7
PGOOD
REFIN
6
PGOOD
V
DDQ
(2.5V OR 1.8V)
V
= V
TTR
REFOUT
REFOUT
TDFN
3mm x 3mm
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Low-Voltage DDR Linear Regulator
ABSOLUTE MAXIMUM RATINGS
IN to PGND............................................................-0.3V to +4.3V
Continuous Power Dissipation (T = +70°C)
A
OUT to PGND ..............................................-0.3V to (V + 0.3V)
10-Pin 3mm x 3mm TDFN
(derated 24.4mW/°C above +70°C)...........................1951mW
Operating Temperature Range
IN
OUTS to AGND............................................-0.3V to (V + 0.3V)
IN
V
CC
to AGND.........................................................-0.3V to +4.3V
REFIN, REFOUT, SHDN, PGOOD to AGND...-0.3V to (V + 0.3V)
MAX8794ETB...................................................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
PGND to AGND.....................................................-0.3V to +0.3V
REFOUT Short Circuit to AGND .................................Continuous
OUT Continuous RMS Current
100s ................................................................................ 1.6A
1s.................................................................................... 2.5A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = 1.8V, V
Typical values are at T = +25°C.) (Note 1)
= 3.3V, V
= V
= 1.25V, SHDN = V , circuit of Figure 1, T = -40°C to +85°C, unless otherwise noted.
OUTS CC A
IN
CC
REFIN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
1.1
TYP
MAX
3.6
3.6
1.3
600
100
10
UNITS
V
V
Power input
Bias supply
Load = 0, V
IN
Input Voltage Range
V
2.7
CC
CC
Quiescent Supply Current (V
)
I
> 0.45V
REFIN
0.7
350
50
mA
µA
CC
SHDN = GND, V
> 0.45V
REFIN
Shutdown Supply Current (V
)
I
CC(SHDN)
CC
SHDN = GND, REFIN = GND
Load = 0
Quiescent Supply Current (V
)
I
IN
0.4
0.1
0
mA
µA
IN
Shutdown Supply Current (V
)
I
SHDN = GND
10
IN
IN(SHDN)
T
T
= +25°C
-4
-6
+4
A
REFIN to OUTS,
= 200mA
Feedback-Voltage Error
V
mV
OUTS
I
OUT
= -40°C to +85°C
+6
A
Load-Regulation Error
Line-Regulation Error
OUTS Input Bias Current
OUTPUT
-1A ≤ I
≤ +1A
-15
+15
mV
mV
µA
OUT
1.4V ≤ V ≤ 3.3V, I
= 100mA
1
IN
OUT
I
-1
+1
OUTS
Output Adjust Range
0.5
1.5
0.169
0.20
V
Ω
High-side MOSFET (source) (I
= 0.1A)
0.10
0.10
3
OUT
OUT On-Resistance
Low-side MOSFET (sink) (I
= -0.1A)
OUT
Output Current Slew Rate
C
= 100µF, I
= 0.1A to 2A
A/µs
dB
kΩ
Ω
OUT
OUT
OUT Power-Supply Rejection
Ratio
10Hz < f < 10kHz, I
= 200mA,
OUT
PSRR
80
12
8
C
= 100µF
OUT
OUT to OUTS Resistance
R
OUTS
DISCHARGE
Discharge MOSFET On-
Resistance
R
SHDN = GND
2
_______________________________________________________________________________________
Low-Voltage DDR Linear Regulator
ELECTRICAL CHARACTERISTICS (continued)
(V = 1.8V, V
Typical values are at T = +25°C.) (Note 1)
= 3.3V, V
= V
= 1.25V, SHDN = V , circuit of Figure 1, T = -40°C to +85°C, unless otherwise noted.
OUTS CC A
IN
CC
REFIN
A
PARAMETER
REFERENCE
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REFIN Voltage Range
V
0.5
-1
1.5
+1
V
REFIN
REFIN Input Bias Current
I
µA
REFIN
REFIN Undervoltage-Lockout
Voltage
Rising edge, hysteresis = 75mV
= 3.3V, I = 0
0.35
0.45
V
V
V
REFIN
+ 0.01
REFIN
REFOUT Voltage
V
V
V
V
REFOUT
CC
REFOUT
REFIN
- 0.01
REFOUT Load Regulation
FAULT DETECTION
∆V
I
= 5mA
-20
+20
mV
REFOUT
REFOUT
Thermal-Shutdown Threshold
T
Rising edge, hysteresis = 15°C
Rising edge, hysteresis = 100mV
+165
2.55
°C
V
SHDN
V
Undervoltage-Lockout
CC
V
2.45
1.8
2.65
UVLO
Threshold
IN Undervoltage-Lockout
Threshold
Rising edge, hysteresis = 55mV
0.9
1.1
4.2
V
Current-Limit Threshold
Soft-Start Current-Limit Time
INPUTS AND OUTPUTS
I
3
A
LIMIT
t
200
µs
SS
With respect to feedback threshold,
hysteresis = 12mV
PGOOD Lower Trip Threshold
PGOOD Upper Trip Threshold
PGOOD Propagation Delay
-200
100
5
-150
150
10
-100
200
35
mV
mV
µs
With respect to feedback threshold,
hysteresis = 12mV
OUTS forced 25mV beyond PGOOD trip
threshold
t
I
PGOOD
Startup rising edge, OUTS within 100mV of
the feedback threshold
PGOOD Startup Delay
2
3.5
0.3
1
ms
V
PGOOD Output Low Voltage
PGOOD Leakage Current
I
= 4mA
SINK
OUTS = REFIN (PGOOD high impedance),
PGOOD = V + 0.3V
CC
µA
PGOOD
Logic high
Logic low
2.0
SHDN Logic Input Threshold
SHDN Logic Input Current
V
0.8
-1
SHDN = V
or GND
+1
µA
CC
Note 1: Limits are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed through cor-
A
relation using statistical-quality-control (SQC) methods.
_______________________________________________________________________________________
3
Low-Voltage DDR Linear Regulator
Typical Operating Characteristics
(Circuit of Figure 1. T = +25°C, unless otherwise noted.)
A
MAXIMUM OUTPUT CURRENT
vs. INPUT VOLTAGE
OUTPUT LOAD REGULATION
OUTPUT LOAD REGULATION
3.0
2.5
0.96
0.94
1.30
1.28
1.26
1.24
1.22
1.20
V
= 0.9V
V
= 1.25V
REFIN
REFIN
V
= 0.9V
OUT
V
= 1.25V
OUT
2.0
1.5
1.0
0.92
0.90
0.88
V
= 1.5V
IN
V
= 1.25V
IN
THERMALLY LIMITED
V
= 1.8V
IN
DROPOUT VOLTAGE LIMITED
V
= 1.5V
IN
0.5
0
0.86
0.84
1.0
1.5
2.0
2.5
3.0
-3
-2
-1
0
1
2
3
-3
-2
-1
0
1
2
3
INPUT VOLTAGE (V)
I
(A)
I
(A)
OUT
OUT
BIAS CURRENT (I
vs. INPUT VOLTAGE (V )
)
IN
INPUT CURRENT (I )
BIAS CURRENT (I
vs. LOAD CURRENT (I
)
CC
IN
CC
vs. INPUT VOLTAGE (V )
)
IN
OUT
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.4
250
200
150
100
50
V
= 1.5V
IN
1.2
1.0
0.8
0.6
0.4
0.2
0
V
V
= 1.25V
= 0.90V
OUT
OUT
V
= 1.25V
OUT
V
= 1.25V
OUT
V
= 0.90V
OUT
ENTERING
DROPOUT
DROPOUT
INPUT UVLO
0.5 1.0 1.5 2.0 2.5 3.0 3.5
(V)
0
0
-2
-1
0
1
2
0
0.5 1.0
1.5 2.0
(V)
2.5 3.0 3.5
V
IN
I
(A)
OUT
V
IN
INPUT CURRENT (I )
IN
vs. SINK LOAD CURRENT (I
DROPOUT VOLTAGE
vs. OUTPUT CURRENT
POWER GROUND CURRENT (I
vs. SOURCE LOAD CURRENT (I
)
)
PGND
OUT
)
OUT
7
6
5
4
3
2
1
0
0.30
0.25
0.20
0.15
0.25
0.20
0.15
0.10
0.05
0
V
= 1.5V
IN
V
= 1.5V
IN
V
= 1.25V
OUT
ENTERING
DROPOUT
V
= 0.90V
OUT
V
= 1.25V
OUT
V
= 1.25V
OUT
V
= 0.9V
OUT
0.10
0.05
0
V
= 0.90V
0.5
OUT
-2.0
-1.5
-1.0
(A)
-0.5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
1.0
(A)
1.5
2.0
I
OUTPUT CURRENT (A)
I
OUT
OUT
4
_______________________________________________________________________________________
Low-Voltage DDR Linear Regulator
Typical Operating Characteristics (continued)
(Circuit of Figure 1. T = +25°C, unless otherwise noted.)
A
REFOUT VOLTAGE ERROR
vs. REFOUT LOAD CURRENT
STARTUP WAVEFORM
MAX8794 toc11
20
5V
SHDN
15
10
5
0V
1.25V
V
OUT
0
0V
-5
4V
-10
-15
-20
PGOOD
0V
-10
-5
0
5
10
500µs/div
REFOUT LOAD CURRENT (mA)
SHUTDOWN WAVEFORM
SOURCE LOAD TRANSIENT
MAX8794 toc12
MAX8794 toc13
5V
SHDN
0V
R
= 100Ω
LOAD
2V
1V
OUT
0V
V
OUT
AC-COUPLED
1mV/div
V
4V
1A
PGOOD
0V
I
OUT
0A
100µs/div
20.0µs/div
SOURCE/SINK LOAD TRANSIENT
LINE TRANSIENT
MAX8794 toc14
MAX8794 toc15
3.3V
V
(1V/div)
V
IN
OUT
AC-COUPLED
5mV/div
1.5V
V
(10mV/div)
OUT
+1.5A
AC-COUPLED
0.9V
I
OUT
-1.5A
I
= 100mA
OUT
4.00µs/div
40µs/div
_______________________________________________________________________________________
5
Low-Voltage DDR Linear Regulator
Typical Operating Characteristics (continued)
(Circuit of Figure 1. T = +25°C, unless otherwise noted.)
A
DYNAMIC OUTPUT-VOLTAGE TRANSIENT
DYNAMIC OUTPUT-VOLTAGE TRANSIENT
MAX8794 toc17
MAX8794 toc16
V
= 1.5V
V = 1.8V
IN
2.5V
2.5V
IN
V
V
DDQ
DDQ
1.8V
1.8V
1.2V
REFOUT
1.2V
V
REFOUT
V
0.9V
1.2V
0.9V
1.2V
V
V
OUT
OUT
0.9V
0.9V
20.0µs/div
20.0µs/div
SOURCE CURRENT-LIMIT
DISTRIBUTION
SINK CURRENT-LIMIT
DISTRIBUTION
50
40
30
20
10
0
50
40
30
20
10
0
SAMPLE SIZE = 200
SAMPLE SIZE = 200
+25°C
+85°C
+25°C
+85°C
2.0
2.5
3.0
3.5
4.0
-4.0
-3.5
-3.0
-2.5
-2.0
SOURCE CURRENT LIMIT (A)
SINK CURRENT LIMIT (A)
6
_______________________________________________________________________________________
Low-Voltage DDR Linear Regulator
Pin Description
PIN
NAME
FUNCTION
Buffered Reference Output. The output of the unity-gain reference input buffer sources and sinks over
5mA. Bypass REFOUT to AGND with a 0.33µF or greater ceramic capacitor.
1
REFOUT
Analog Supply Input. Connect to the system supply voltage (+3.3V). Bypass V
greater ceramic capacitor.
to AGND with a 1µF or
CC
2
V
CC
3
4
AGND
REFIN
Analog Ground. Connect the backside pad to AGND.
External Reference Input. REFIN sets the output regulation voltage (V
= V
).
REFIN
OUTS
Open-Drain Power-Good Output. PGOOD is low when the output voltage is more than 150mV (typ) above
or below the regulation point, during soft-start, and when shut down. 2ms after the output reaches the
regulation voltage during startup, PGOOD becomes high impedance.
5
PGOOD
Output Sense Input. The OUTS regulation level is set by the voltage at REFIN. Connect OUTS to the
remote DDR termination bypass capacitors. OUTS is internally connected to OUT through a 12kΩ
resistor.
6
7
OUTS
Shutdown Control Input. Connect to V
for normal operation. Connect to analog ground to shut down the
CC
SHDN
linear regulator. The reference buffer remains active in shutdown.
Power Ground. Internally connected to the output sink MOSFET.
Output of the Linear Regulator
8
9
PGND
OUT
IN
10
Power Input. Internally connected to the output source MOSFET.
_______________________________________________________________________________________
7
Low-Voltage DDR Linear Regulator
Detailed Description
V
= V = V
TT
/ 2
DDQ
OUT
The MAX8794 is a low-voltage, low-dropout DDR termi-
V
=
IN
IN
OUT
1.1V TO 3.6V
nation linear regulator with an external bias supply
input and a buffered reference output (see Figures 1
C
C
10µF
OUT1
100µF
IN2
and 2). V
is powered by a 2.7V to 3.6V supply that is
CC
MAX8794
commonly available in laptop and desktop computers.
The 3.3V bias supply drives the gate of the internal
pass transistor, while a lower voltage input at the drain
3.3V BIAS
SUPPLY
V
PGND
AGND
CC
C1
R3
100kΩ
1.0µF
of the transistor (IN) is regulated to provide V
. By
OUT
using separate bias and power inputs, the MAX8794
can drive an n-channel high-side MOSFET and use a
lower input voltage to provide better efficiency.
POWER-GOOD
PGOOD
SHDN
OUTS
ON
OFF
The MAX8794 regulates its output voltage to the volt-
age at REFIN. When used in DDR applications as a ter-
mination supply, the MAX8794 delivers 1.25V or 0.9V at
3A peak (typ) from an input voltage of 1.1V to 3.6V. The
MAX8794 sinks up to 3A peak (typ) as required in a ter-
mination supply. The MAX8794 provides shoot-through
protection, ensuring that the source and sink MOSFETs
do not conduct at the same time, yet produces a fast
source-to-sink load transient.
R1
10kΩ
V
= V
TTR
REFOUT
C
V
DDQ
REFIN
REFOUT
C
REFIN
R2
10kΩ
REFOUT
0.33µF
1000pF
Figure 1. Standard Application Circuit
V
CC
3.3V BIAS
SUPPLY
INPUT
1.1V TO 3.6V
SOFT-
START
IN
EN
UVLO
SHDN
REFIN
OFF ON
THERMAL
SHDN
V
DDQ
OUT
V
TT
Gm
PGND
12kΩ
REFOUT
AGND
V
TTR
OUTS
REFIN
+150mV
EN
8Ω
REFIN
-150mV
PGOOD
POWER-
GOOD
DELAY
LOGIC
MAX8794
Figure 2. Functional Diagram
_______________________________________________________________________________________
8
Low-Voltage DDR Linear Regulator
The MAX8794 features an open-drain PGOOD output
connected to ceramic bypass capacitors (0.33µF to
that transitions high 2ms after the output initially reach-
es regulation. PGOOD goes low within 10µs of when
the output goes out of regulation by 150mV. The
MAX8794 features current- and thermal-limiting circuitry
to prevent damage during fault conditions.
1.0µF). REFOUT is active when V
> 0.45V and
REFIN
V
CC
is above V . REFOUT is independent of SHDN.
UVLO
Shutdown
Drive SHDN low to disable the error amplifier, gate-
drive circuitry, and pass transistor (Figure 2). In shut-
down, OUT is terminated to GND with an 8Ω MOSFET.
REFOUT is independent of SHDN. Connect SHDN to
3.3V Bias Supply (V
)
CC
The V
input powers the control circuitry and provides
CC
the gate drive to the pass transistor. This improves effi-
ciency by allowing V to be powered from a lower sup-
V
CC
for normal operation.
IN
Current Limit
ply voltage. Power V
supply. Current drawn from the V
from a well-regulated 3.3V
CC
The MAX8794 features source and sink current limits to
protect the internal n-channel MOSFETs. The source-
and-sink MOSFETs have a typical 3A current limit (1.8A
min). This current limit prevents damage to the internal
power transistors, but the device can enter thermal
shutdown if the power dissipation increases the die
temperature above +165°C (see the Thermal-Overload
Protection section).
supply remains rel-
CC
atively constant with variations in V and load current.
IN
Bypass V
with a 1µF or greater ceramic capacitor as
CC
close to the device as possible.
V
Undervoltage Lockout (UVLO)
CC
The V
input UVLO circuitry ensures that the regulator
CC
starts up with adequate voltage for the gate-drive cir-
cuitry to bias the internal pass transistor. The UVLO
Soft-Start Current Limit
Soft-start gradually increases the internal source current
limit to reduce input surge currents at startup. Full-
source current limit is available after the 200µs soft-start
timer has expired. The soft-start current limit is given by:
threshold is 2.55V (typ). V
level for proper operation.
must remain above this
CC
Power-Supply Input (IN)
IN provides the source current for the linear regulator’s
output, OUT. IN connects to the drain of the internal
n-channel power MOSFET. IN can be as low as 1.1V,
minimizing power dissipation. The input UVLO prohibits
operation below 0.8V (typ). Bypass IN with a 10µF or
greater capacitor as close to the device as possible.
I
× t
LIMIT
I
=
LIMIT(SS)
t
SS
where I
and t
are from the Electrical Charac-
SS
LIMIT
teristics. Figure 3 shows the MAX8794 PGOOD and
soft-start waveform.
Reference Input (REFIN)
The MAX8794 regulates OUTS to the voltage set at
REFIN, making the MAX8794 ideal for memory applica-
tions where the termination supply must track the sup-
ply voltage. Typically, REFIN is set by an external
resistive voltage-divider connected to the memory sup-
Thermal-Overload Protection
Thermal-overload protection prevents the linear regulator
from overheating. When the junction temperature
exceeds +165°C, the linear regulator and reference
buffer are disabled, allowing the device to cool. Normal
operation resumes once the junction temperature cools
by 15°C. Continuous short-circuit conditions result in a
pulsed output until the overload is removed. A continuous
thermal-overload condition results in a pulsed output. For
continuous operation, do not exceed the absolute maxi-
mum junction-temperature rating of +150°C.
ply (V
) as shown in Figure 1.
DDQ
The maximum output voltage of 1.5V is limited by the
gate-drive voltage of the internal n-channel power
transistor.
Buffered Reference Output (REFOUT)
REFOUT is a unity-gain transconductance amplifier that
generates the DDR reference supply. It sources and
sinks greater than 5mA. The reference buffer is typically
_______________________________________________________________________________________
9
Low-Voltage DDR Linear Regulator
200µs
SHDN
CURRENT LIMIT
OUTPUT OVERLOAD
CONDITION
POWER-GOOD
WINDOW
OUT
2ms STARTUP
DELAY
PGOOD
10µs
PROPAGATION
DELAY
10µs
PROPAGATION
DELAY
Figure 3. MAX8794 PGOOD and Soft-Start Waveforms
Power-Good (PGOOD)
The MAX8794 provides an open-drain PGOOD output
that goes high 2ms (typ) after the output initially reach-
es regulation during startup. PGOOD transitions low
10µs after the output goes out of regulation by 150mV,
or when the device enters shutdown. Connect a pullup
REFERENCE
VOLTAGE
(V
)
REF
resistor from PGOOD to V
for a logic-level output.
CC
R1
Use a 100kΩ resistor to minimize current consumption.
MAX8794
C
REFIN
Applications Information
REFIN
Dynamic Output-Voltage Transitions
By changing the voltage at REFIN, the MAX8794 can
be used in applications that require dynamic output-
voltage changes between two set points (graphics
processors). Figure 4 shows a dynamically adjustable
resistive voltage-divider network at REFIN. Using an
external signal MOSFET, a resistor can be switched in
and out of the REFIN resistor-divider, changing the volt-
age at REFIN. The two output voltages are determined
by the following equations:
R2
R3
V
OUT(LOW)
V
OUT(HIGH)
R2
V
V
=
V
REF
OUT(LOW)
OUT(HIGH)
)
(
R1 + R2
⎛
⎞
R2
R1 + R2
V
= V
REF
OUT(LOW)
⎜
⎟
(R2 + R3)
⎝
⎠
= V
REF
R1 + (R2 + R3)
⎡
⎢
⎤
⎥
R2 +R3
(
)
V
= V
REF
OUT(HIGH)
R1 + R2 +R3
(
)
⎢
⎥
⎣
⎦
Figure 4. Dynamic Output-Voltage Change
10 ______________________________________________________________________________________
Low-Voltage DDR Linear Regulator
For a step-voltage change at REFIN, the rate of change
of the output voltage is limited by the total output
capacitance, the current limit, and the load during the
transition. Adding a capacitor across REFIN and AGND
filters noise and controls the rate of change of the
REFIN voltage during dynamic transitions. With the
additional capacitance, the REFIN voltage slews
between the two set points with a time constant given
SAFE OPERATING REGION
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
DROPOUT VOLTAGE
LIMITED
MAXIMUM CURRENT LIMIT
° °
= 0 C TO +70 C
T
A
by R
x C
, where R
is the equivalent parallel
EQ
REFIN
EQ
resistance seen by the slew capacitor.
V
- V
OUT(MIN)
IN(MAX)
Operating Region and Power Dissipation
The maximum power dissipation of the MAX8794
depends on the thermal resistance of the 10-pin TDFN
package and the circuit board, the temperature differ-
ence between the die and ambient air, and the rate of
airflow. The power dissipated in the device is:
°
= +100 C
T
A
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
INPUT-OUTPUT DIFFERENTIAL VOLTAGE (V)
P
= I
SINK
x (V – V
)
SRC
P
SRC
= I
IN
OUT
x V
SINK OUT
Figure 5. Power Operating Region—Maximum Output Current
vs. Input-Output Differential Voltage
The resulting maximum power dissipation is:
V
= R
x I
DROPOUT
DS(ON) OUT
T
- T
A
J(MAX)
For low output-voltage applications, the sink current is
P
=
DIS(MAX)
limited by the output voltage and the R
MOSFET.
of the
θ
+ θ
CA
DS(ON)
JC
where T
is the maximum junction temperature
J(MAX)
Input Capacitor Selection
(+150°C), T is the ambient temperature, θ
is the
JC
A
Bypass IN to PGND with a 10µF or greater ceramic
thermal resistance from the die junction to the package
case, and θ is the thermal resistance from the case
through the PC board, copper traces, and other materi-
als to the surrounding air. For optimum power dissipa-
tion, use a large ground plane with good thermal
contact to the backside pad, and use wide input and
output traces.
capacitor. Bypass V
to AGND with a 1µF ceramic
CC
CA
capacitor for normal operation in most applications.
Typically, the LDO is powered from the output of a
step-down controller (memory supply) that has addi-
tional bulk capacitance (polymer or tantalum) and dis-
tributed ceramic capacitors.
When 1in2 of copper is connected to the device, the
maximum allowable power dissipation of a 10-pin TDFN
package is 1951mW. The maximum power dissipation is
Output Capacitor Selection
The MAX8794 output stability is independent of the out-
put capacitance for C
from 10µF to 220µF.
OUT
derated by 24.4mW/°C above T = +70°C. Extra copper
A
Capacitor ESR between 2mΩ and 50mΩ is needed to
maintain stability. Within the recommended capaci-
tance and ESR limits, the output capacitor should be
chosen to provide good transient response:
on the PC board increases thermal mass and reduces
thermal resistance of the board. Refer to the MAX8794
evaluation kit for a layout example.
The MAX8794 delivers up to 3A and operates with input
voltages up to 3.6V, but not simultaneously. High output
currents can only be achieved when the input-output
differential voltages are low (Figure 5).
∆I
x ESR = ∆V
OUT(P-P)
is the maximum peak-to-peak load-
OUT(P-P)
where ∆I
OUT(P-P)
current step (typically equal to the maximum source
load plus the maximum sink load), and ∆V is
the allowable peak-to-peak voltage tolerance.
OUT(P-P)
Dropout Operation
A regulator’s minimum input-to-output voltage differen-
tial (dropout voltage) determines the lowest usable sup-
ply voltage. Because the MAX8794 uses an n-channel
pass transistor, the dropout voltage is a function of the
Using larger output capacitance can improve efficiency
in applications where the source and sink currents
change rapidly. The capacitor acts as a reservoir for
the rapid source and sink currents, so no extra current
is supplied by the MAX8794 or discharged to ground,
improving efficiency.
drain-to-source on-resistance (R
multiplied by the load current (see the Typical
Operating Characteristics):
= 0.25Ω max)
DS(ON)
______________________________________________________________________________________ 11
Low-Voltage DDR Linear Regulator
Noise, PSRR, and Transient Response
The MAX8794 operates with low-dropout voltage and
low quiescent current in notebook computers while
maintaining good noise, transient response, and AC-
rejection specifications. Improved supply-noise rejec-
tion and transient response can be achieved by
increasing the values of the input and output capaci-
tors. Use passive filtering techniques when operating
from noisy sources.
PC Board Layout Guidelines
The MAX8794 requires proper layout to achieve the
intended output power level and low noise. Proper lay-
out involves the use of a ground plane, appropriate
component placement, and correct routing of traces
using appropriate trace widths. Refer to the MAX8794
evaluation kit for a layout example:
1) Minimize high-current ground loops. Connect the
ground of the device, the input capacitor, and the
output capacitor together at one point.
The MAX8794 load-transient response graphs (see the
Typical Operating Characteristics) show two compo-
nents of the output response: a DC shift from the output
impedance due to the load-current change and the
transient response. A typical transient response for a
step change in the load current from -1.5A to +1.5A is
10mV. Increasing the output capacitor’s value and
decreasing the ESR attenuate the overshoot.
2) To optimize performance, a ground plane is essen-
tial. Use all available copper layers in applications
where the device is located on a multilayer board.
3) Connect the input filter capacitor less than 10mm
from IN. The connecting copper trace carries large
currents and must be at least 2mm wide, preferably
5mm wide.
4) Connect the backside pad to a large ground plane.
Use as much copper as necessary to decrease the
thermal resistance of the device. In general, more
copper provides better heatsinking capabilities.
Chip Information
TRANSISTOR COUNT: 3496
PROCESS: BiCMOS
12 ______________________________________________________________________________________
Low-Voltage DDR Linear Regulator
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 6,8,10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
1
H
21-0137
2
PACKAGE VARIATIONS
COMMON DIMENSIONS
MIN. MAX.
SYMBOL
PKG. CODE
T633-1
N
6
D2
1.50±0.10 2.30±0.10 0.95 BSC
1.50±0.10 2.30±0.10
E2
e
JEDEC SPEC
MO229 / WEEA
MO229 / WEEA
MO229 / WEEC
MO229 / WEEC
MO229 / WEEC
b
[(N/2)-1] x e
1.90 REF
1.90 REF
1.95 REF
1.95 REF
1.95 REF
2.00 REF
2.00 REF
2.40 REF
2.40 REF
0.40±0.05
0.40±0.05
0.30±0.05
0.30±0.05
0.30±0.05
A
0.70
2.90
2.90
0.00
0.20
0.80
3.10
3.10
0.05
0.40
T633-2
6
D
E
0.95 BSC
T833-1
8
1.50±0.10 2.30±0.10 0.65 BSC
1.50±0.10 2.30±0.10 0.65 BSC
1.50±0.10 2.30±0.10 0.65 BSC
T833-2
8
A1
L
T833-3
8
T1033-1
T1033-2
T1433-1
T1433-2
10
10
14
14
1.50±0.10 2.30±0.10 0.50 BSC MO229 / WEED-3 0.25±0.05
k
0.25 MIN.
0.20 REF.
1.50±0.10 2.30±0.10
0.25±0.05
0.20±0.05
0.20±0.05
A2
0.50 BSC MO229 / WEED-3
1.70±0.10 2.30±0.10 0.40 BSC
1.70±0.10 2.30±0.10 0.40 BSC
- - - -
- - - -
PACKAGE OUTLINE, 6,8,10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
2
-DRAWING NOT TO SCALE-
H
21-0137
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 2006 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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