MAX8620YETD [MAXIM]
PMIC for Microprocessors or DSPs in Portable Equipment; PMIC用于便携式设备中的微处理器或DSP
| 型号： | MAX8620YETD |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | PMIC for Microprocessors or DSPs in Portable Equipment |
| 文件： | 总18页 (文件大小：409K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3564; Rev 0; 1/05
µPMIC for Microprocessors or DSPs
in Portable Equipment
General Description
Features
The MAX8620Y micro-power-management integrated
circuit (µPMIC) powers low-voltage microprocessors or
DSPs in portable devices. The µPMIC includes a high-
efficiency step-down DC-DC converter, two low-
dropout linear regulators (LDOs), a microprocessor
reset output, and power-on/off control logic. This device
maintains high efficiency at light loads with a low 115µA
supply current, and its miniature TDFN package makes
it ideal for portable devices.
♦ Three Regulators and a Reset in One Package
♦ High-Efficiency Step-Down Converter
Up to 4MHz Fixed Switching Frequency
500mA Guaranteed Output Current
0.6V to 3.3V Adjustable Output Voltage
±±2 ꢀnitial Accuracy
Fast Voltage-Positioning Transient Response
ꢀnternal Synchronous Rectifier
♦ Two 300mA LDO Regulators
The MAX8620Y’s step-down DC-DC converter utilizes a
proprietary 4MHz hysteretic-PWM control scheme that
allows for ultra-small external components. Internal syn-
chronous rectification improves efficiency and elimi-
nates the external Schottky diode that is required in
conventional step-down converters. The output voltage
is adjustable from 0.6V to 3.3V, with guaranteed output
current up to 500mA.
±00mV Dropout at ±00mA Load
Low 45µV
Output Noise
RMS
32 Accuracy over Line, Load, and Temperature
Overcurrent Protection
Nine Pin-Selectable Output-Voltage Settings
♦ 30ms (min) RESET Output Flag
♦ ±.7V to 5.5V ꢀnput
The MAX8620Y’s two LDOs offer low 45µV
output
♦ 115µA (typ) Supply Current at No Load
♦ Thermal-Overload Protection
♦ Tiny 3mm x 3mm x 0.8mm TDFN Package
RMS
noise and a low dropout of only 200mV at 200mA. Each
LDO delivers at least 300mA of continuous output cur-
rent. The output voltages are pin selectable from 1.8V
to 3.3V for flexibility.
Ordering Information
A microprocessor reset output (RESET) monitors OUT1
and warns the system of impending power loss allow-
ing safe shutdown. RESET asserts during power-up,
power-down, shutdown, and fault conditions where
PꢀN-
PACKAGE
TOP
MARK
PART
TEMP RANGE
V
is below its regulation voltage.
14 TDFN-EP
(T1433-2)
OUT1
MAX8620YETD -40°C to +85°C
AAB
Applications
Typical Operating Circuit
Cellular Handsets
Smart Phones/PDA Phones
PDAs
V
IN
1.80V, 2.60V, 2.80V, 2.85V,
3.00V, OR 3.30V*
300mA
IN2
IN1
OUT1
Wireless LAN
1.80V, 2.50V, 2.60V,
2.85V, OR 3.00V*
300mA
OUT2
Microprocessor and DSP Solutions including
MSM™, XScale™, ARM™, and OMAP™
MAX8620Y
V
LOGIC
BP
100kΩ
RESET
EN2
RESET
LX
OUT3
0.6V TO 3.3V
500mA
HF_PWR
PWR_ON
SEL1
Pin Configuration appears at end of data sheet.
FB
SEL2
MSM is a trademark of QUALCOMM, Inc.
XScale is a trademark of Intel Corp.
GND
ARM is a trademark of ARM Limited.
OMAP is a trademark of Texas Instruments, Inc.
*USE SEL1 AND SEL2 TO SET V
AND V
OUT2
OUT1
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
µPMIC for Microprocessors or DSPs
in Portable Equipment
ABSOLUTE MAXꢀMUM RATꢀNGS
IN1, IN2, PWR_ON, RESET, EN2, SEL1, SEL2,
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
HF_PWR, FB, BP to GND ..................................-0.3V to +6.0V
OUT1, OUT2 to GND .................................-0.3V to (V
+ 0.3V)
IN1
LX Current ......................................................................1.5A
RMS
Continuous Power Dissipation (T = +70°C)
A
14-Pin TDFN (derate 18.2mW/°C above +70°C) .......1454mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRꢀCAL CHARACTERꢀSTꢀCS
(V
= V
= +3.7V, C = 10µF, C = 0.01µF, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
IN1
IN2
IN
BP
A
A
(Note 1)
PARAMETER
Supply Voltage Range
SYMBOL
CONDꢀTꢀONS
MꢀN
TYP
MAX
UNꢀTS
V
2.7
5.5
V
IN1
V
= V
= 4.2V, PWR_ON = HF_PWR =
IN2
IN1
Shutdown Supply Current
I
5.5
115
430
10
µA
SHDN
GND
All outputs enabled, no load
= V = 1.8V, I
140
Supply Current
I
+ I
IN2
µA
IN1
V
= I
OUT3
=
OUT1
OUT3
OUT1
500µA, OUT2 disabled
UNDERVOLTAGE LOCKOUT
V
V
= V
= V
rising
falling
2.70
2.85
2.35
3.05
IN1
IN1
IN2
IN2
UVLO Threshold
V
V
UVLO
THERMAL PROTECTꢀON
Thermal-Shutdown Threshold
Thermal-Shutdown Hysteresis
REFERENCE (BP)
Temperature rising
+160
15
°C
°C
Reference Bypass Output
Voltage
V
0 ≤ I ≤ 1µA
1.231
1.250
1.269
0.4
V
V
BP
BP
LOGꢀC AND CONTROL ꢀNPUTS (PWR_ON, HF_PWR, EN2)
PWR_ON, HF_PWR, EN2 Input
Low Voltage
V
V
= V
= 2.7V to 4.2V (Note 2)
IL
IN1
IN2
PWR_ON, HF_PWR, EN2 Input
High Voltage
V
V
V
= V
= 2.7V to 4.2V (Note 2)
1.44
-1
V
µA
s
IH
IN1
IN2
Input Bias Current
I
= V
= V = 0V or 5.5V
EN2
+1
INB
PWR_ON
HF_PWR
From the rising edge of HF_PWR until the
one-shot timer expires (Figure 4)
HF_PWR Timer
t
1.05
1.31
1.46
HF
LꢀNEAR REGULATORS (OUT1, OUT±)
0°C to +85°C
-1.3
-1.5
+1.8
+1.8
I
= 1mA, 3.7V ≤ V
IN
LOAD
≤ 5.5V
-40°C to +85°C
OUT1, OUT2 Output-Voltage
Accuracy
V
V
,
OUT1
%
OUT2
1mA ≤ I
≤ 300mA
-1.2
0
LOAD
I
= 150mA
LOAD
OUT1, OUT2 Output Current
OUT1, OUT2 Output Current Limit
OUT1, OUT2 Dropout Voltage
I
300
310
mA
mA
mV
OUT_
I
V
= 0V
550
200
940
380
LIM_
OUT_
V
I
= 200mA, T = +85°C (Note 3)
DO
LOAD
A
±
_______________________________________________________________________________________
µPMIC for Microprocessors or DSPs
in Portable Equipment
ELECTRꢀCAL CHARACTERꢀSTꢀCS (continued)
(V
IN1
= V
= +3.7V, C = 10µF, C = 0.01µF, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
IN2 IN BP A A
(Note 1)
PARAMETER
SYMBOL
CONDꢀTꢀONS
f = 10Hz to 10kHz, C = 4.7µF,
MꢀN
TYP
MAX
UNꢀTS
OUT1, OUT2 Power-Supply
Rejection Ratio
OUT_
60
dB
I
= 30mA
LOAD_
f = 100Hz to 100kHz, C
= 4.7µF,
OUT_
45
I
= 30mA
LOAD_
Output Noise Voltage
µV
RMS
f = 100Hz to 100kHz, C
= 4.7µF,
OUT_
100
I
= 30mA, C open
BP
LOAD_
STEP-DOWN CONVERTER (OUT3)
Output Voltage Range
V
0.6
3.3
V
V
OUT3
FB Threshold Voltage
V
V
V
falling
0.6
TH
FB
FB Threshold Line Regulation
= V
= 2.7V to 5.5V (Note 2)
IN2
0.08
%/V
IN1
T
= +25°C
-2
-3
+2
+3
A
A
FB Threshold Voltage Accuracy
I
= 0mA
%
%
OUT3
(Falling) (% of V
)
TH
T
= -40°C to +85°C
FB Threshold Voltage Hysteresis
(% of V
V
2
HYS
)
TH
OUT3 disabled
= 0.5V
10
10
FB Bias Current
Current Limit
I
µA
mA
FB
V
FB
I
pFET switch
nFET rectifier
675
875
950
1000
0.65
0.35
30
1200
1200
1.5
LIM3P
I
LIM3N
R
R
pFET switch, I = -200mA
LX
ONP
On-Resistance
Ω
mA
ns
nFET rectifier, I = +200mA
0.8
ONN
LX
Rectifier-Off Current Threshold
Minimum On- and Off-Times
I
60
LXOFF
t
107
95
ON
t
OFF
OPEN-DRAꢀN, ACTꢀVE-LOW RESET OUTPUT (RESET)
RESET Output-Voltage Low
V
I
= 500µA
0.3
V
OL
SINK
RESET Output Leakage Current
V
= 5.5V
100
nA
RESET
Percent of the OUT1 regulation voltage
(Note 4)
RESET Threshold Voltage
V
84
30
87
60
90
%
THR
RESET Timeout Period
t
Figure 4
ms
RP
LDO OUTPUT-VOLTAGE SELECT ꢀNPUTS (SEL1, SEL±)
SEL_ Input Low Threshold
1
V
V
SEL_ Input High Threshold
V
- 0.2V
IN_
V
V
= V
= 4.2V, V
= 0V or V
,
IN1
IN2
SEL1
IN1
SEL_ Input Bias Current
0.1
µA
= 0V or V
SEL2
IN1
Note 1: Specifications are 100% production tested at T = +25°C. Maximum and minimum limits over temperature are guaranteed
A
by design and characterization.
Note ±: After startup.
Note 3: Guaranteed by design.
Note 4: RESET asserts low when V
drops below the specified percent of the OUT1 regulation voltage.
OUT1
_______________________________________________________________________________________
3
µPMIC for Microprocessors or DSPs
in Portable Equipment
Typical Operating Characteristics
(V
IN1
= V
= 3.7V, PWR_ON = IN1, L = 2.2µH (LQH31CN2R2M53), C = 150pF, V
= V
= 2.6V, V
= 1.867V (R1 =
OUT3
IN2
FF
OUT1
OUT2
150kΩ, R2 = 75kΩ), C = 10µF, C = 0.01µF, C
A
= C
= 4.7µF, C = 2.2µF, RESET pulled up with 100kΩ to OUT1,
OUT3
IN
BP
OUT1
OUT2
T
= +25°C, unless otherwise noted.)
INPUT QUIESCENT CURRENT
EFFICIENCY vs. LOAD CURRENT
vs. INPUT VOLTAGE
180
100
90
80
70
60
50
40
30
20
10
0
L = 4.7µH
160
140
120
100
80
L = 2.2µH
L = 1.0µH
60
40
20
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.1
1
10
100
1000
INPUT VOLTAGE (V)
LOAD CURRENT (mA)
SWITCHING FREQUENCY vs. LOAD CURRENT
EFFICIENCY vs. OUTPUT VOLTAGE
10
100
L = 1.0µH
95
L = 4.7µH
90
85
L = 2.2µH
1
80
75
70
65
60
L = 1.0µH
L = 4.7µH
L = 2.2µH
0.1
0
50 100 150 200 250 300 350 400 450 500
LOAD CURRENT (mA)
0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6
OUTPUT VOLTAGE (V)
LIGHT-LOAD SWITCHING WAVEFORMS
HEAVY-LOAD SWITCHING WAVEFORMS
MAX8620Y toc05
MAX8620Y toc06
V
LX
V
LX
2V/div
2V/div
V
OUT
V
OUT
20mV/div
20mV/div
AC-COUPLED
AC-COUPLED
I
L
200mA/div
I
L
100mA/div
200ns/div
200ns/div
4
_______________________________________________________________________________________
µPMIC for Microprocessors or DSPs
in Portable Equipment
Typical Operating Characteristics (continued)
(V
IN1
= V
= 3.7V, PWR_ON = IN1, L = 2.2µH (LQH31CN2R2M53), C = 150pF, V
= V
= 2.6V, V
= 1.867V (R1 =
OUT3
IN2
FF
OUT1
OUT2
150kΩ, R2 = 75kΩ), C = 10µF, C = 0.01µF, C
A
= C
= 4.7µF, C = 2.2µF, RESET pulled up with 100kΩ to OUT1,
OUT3
IN
BP
OUT1
OUT2
T
= +25°C, unless otherwise noted.)
LOAD TRANSIENT (50mA TO 300mA)
POWER-UP WAVEFORMS
MAX8620Y toc07
MAX8620Y toc08
2V/div
1V/div
V
OUT3
50mV/div
AC-COUPLED
V
IN
1V/div
1V/div
V
V
V
OUT3
OUT1
OUT2
200mA/div
I
L
300mA
200mA/div
50mA
I
LOAD
2µs/div
40µs/div
PWR_ON STARTUP/SHUTDOWN WAVEFORMS
RESET WAVEFORMS
MAX8620Y toc09
MAX8620Y toc10
V
2V/div
2V/div
1V/div
PWR_ON
V
PWR_ON
1V/div
1V/div
1V/div
V
V
V
OUT3
OUT1
OUT2
V
RESET
1V/div
V
OUT1
100µs/div
10ms/div
OUT2 SHUTDOWN WAVEFORMS
HF_PWR STARTUP WAVEFORMS
MAX8620Y toc11
MAX8620Y toc12
2V/div
1V/div
V
HF_PWR
1V/div
1V/div
V
EN2
V
OUT1
1V/div
V
OUT2
V
RESET
200µs/div
10ms/div
_______________________________________________________________________________________
5
µPMIC for Microprocessors or DSPs
in Portable Equipment
Typical Operating Characteristics (continued)
(V
IN1
= V
= 3.7V, PWR_ON = IN1, L = 2.2µH (LQH31CN2R2M53), C = 150pF, V
= V
= 2.6V, V
= 1.867V (R1 =
OUT3
IN2
FF
OUT1
OUT2
150kΩ, R2 = 75kΩ), C = 10µF, C = 0.01µF, C
A
= C
= 4.7µF, C = 2.2µF, RESET pulled up with 100kΩ to OUT1,
OUT3
IN
BP
OUT1
OUT2
T
= +25°C, unless otherwise noted.)
OUT1/OUT2 VOLTAGE vs. INPUT VOLTAGE
DROPOUT VOLTAGE vs. LOAD CURRENT
2.80
2.75
2.70
2.65
2.60
2.55
2.50
2.45
2.40
2.35
2.30
400
350
300
250
200
150
100
I
= 0mA
LOAD
I
= 300mA
LOAD
V
= 3V
OUT_
50
0
3.0
3.5
4.0
4.5
5.0
5.5
0
50
100
150
200
250
300
INPUT VOLTAGE (V)
LOAD CURRENT (mA)
OUT1/OUT2 POWER-SUPPLY
RIPPLE REJECTION vs. FREQUENCY
OUT1/OUT2 LOAD REGULATION vs. LOAD CURRENT
80
70
60
50
40
30
20
10
0
-0.1
-0.3
-0.5
-0.7
-0.9
-1.1
-1.3
-1.5
0.1
1
10
100
1000
0
50
100
150
200
250
300
FREQUENCY (kHz)
LOAD CURRENT (mA)
6
_______________________________________________________________________________________
µPMIC for Microprocessors or DSPs
in Portable Equipment
Pin Description
PꢀN
NAME
FUNCTꢀON
LDO Output-Voltage Select Input 1. SEL1 and SEL2 set the OUT1 and OUT2 voltages to one of nine
combinations (Table 1).
1
SEL1
LDO Output-Voltage Select Input 2. SEL1 and SEL2 set the OUT1 and OUT2 voltages to one of nine
combinations (Table 1).
2
3
SEL2
OUT2 Enable Input. Drive EN2 low to enable OUT2. Drive EN2 high to disable OUT2. If the MAX8620Y
is placed into shutdown (PWR_ON = HF_PWR = low), OUT2 does not power regardless of the status
of EN2 (Table 2, Figure 4).
EN2
Open-Drain, Active-Low Reset Output. RESET asserts low when V
drops below 87% (typ) of
OUT1
regulation. RESET remains asserted for t after V
also asserts when OUT1 is disabled (Figure 4). RESET deasserts if OUT1 is enabled and V
rises above 87% (typ) of regulation. RESET
OUT1
RP
4
RESET
is
OUT1
above 87% of regulation after t
.
RP
Reference Bypass Capacitor Node. Bypass BP with a 0.01µF capacitor to GND. BP is high
impedance when the MAX8620Y is disabled (PWR_ON = HF_PWR = low).
5
6
BP
Hands-Free Enable Input. Drive HF_PWR high or apply a pulse to enable the MAX8620Y. Power is
enabled for 1.31s (typ) following a rising edge at HF_PWR (Table 2, Figure 4).
HF_PWR
Power-Enable Input. Drive PWR_ON high to enable the MAX8620Y (Table 2, Figure 4). Drive PWR_ON
low to enter shutdown mode. In shutdown, the LX node is high impedance and both LDOs are
disabled (depending on the state of HF_PWR).
7
8
PWR_ON
FB
Step-Down Converter Output-Voltage Feedback Input. V regulates to 0.6V (typ). Connect FB to the
FB
center of an external resistor-divider between LX and GND to set V
between 0.6V and 3.3V (see
OUT3
the Setting the Step-Down Output Voltage (OUT3) section).
9
GND
LX
Ground. Connect GND to the exposed pad.
Inductor Connection. LX is internally connected to the drain of the internal p-channel power MOSFET
and the drain of the n-channel synchronous rectifier. LX is high impedance when OUT3 is disabled.
10
11
12
IN2
IN1
Power Input 2. Connect IN2 to IN1 as close to the device as possible.
Power Input 1. Connect IN1 to IN2 as close to the device as possible. Bypass IN1 to GND with a 10µF
ceramic capacitor, as close to the device as possible.
300mA LDO Output 1. Bypass OUT1 to GND with a 4.7µF ceramic capacitor for 300mA applications,
or a 2.2µF ceramic capacitor for 150mA applications. OUT1 is high impedance when disabled.
13
OUT1
300mA LDO Output 2. Bypass OUT2 to GND with a 4.7µF ceramic capacitor for 300mA applications,
or a 2.2µF ceramic capacitor for 150mA applications. OUT2 is high impedance when disabled.
14
EP
OUT2
EP
Exposed Pad. Connect EP to GND.
_______________________________________________________________________________________
7
µPMIC for Microprocessors or DSPs
in Portable Equipment
fixed frequency up to 4MHz, allowing for ultra-small
external components. The step-down converter output
current is guaranteed up to 500mA.
Detailed Description
The MAX8620Y µPMIC is designed to power low-core-
voltage microprocessors or DSPs in portable devices.
The µPMIC contains a fixed-frequency, high-efficiency
step-down converter; two low-dropout regulators
(LDOs); a 30ms (min) reset timer; and power-on/off
control logic (Figure 1).
When the step-down converter output voltage falls
below the regulation threshold, the error comparator
begins a switching cycle by turning the high-side pFET
switch on. This switch remains on until the minimum on-
time (t ) expires and the output voltage is in regula-
ON
Step-Down DC-DC Control Scheme
The MAX8620Y step-down converter is optimized for
high-efficiency voltage conversion over a wide load
range while maintaining excellent transient response,
minimizing external component size, and minimizing
output voltage ripple. The DC-DC converter (OUT3)
also features an optimized on-resistance internal
MOSFET switch and synchronous rectifier to maximize
efficiency. The MAX8620Y utilizes a proprietary hys-
teretic-PWM control scheme that switches with nearly
tion or the current-limit threshold (I
) is exceeded.
LIM3P
Once off, the high-side switch remains off until the mini-
mum off-time (t ) expires and the output voltage
OFF
again falls below the regulation threshold. During this
off period, the low-side synchronous rectifier turns on
and remains on until either the high-side switch turns
on or the inductor current reduces to the rectifier-off
current threshold (I
= 30mA (typ)). The internal
LXOFF
synchronous rectifier eliminates the need for an exter-
nal Schottky diode.
V
IN
C
IN
IN1
IN2
pFET
nFET
MAX8620Y
L
STEP-DOWN
CONVERTER
CONTROL
LX
FB
OUT3
R1
R2
C
OUT3
C
FF
CONTROL
PWR_ON
0.6V
LOGIC
ENABLE
UVLO
OUT1
OUT1
PU
LDO1
CONTROL
HF_PWR
ONE-
C
OUT1
R
SHOT
TIMER
RESET
OUT2
RESET
RESET
SEL1
SEL2
OUTPUT-
VOLTAGE
SELECT
OUT2
LDO2
CONTROL
C
OUT2
IN1
EN2
BP
EN2
REFERENCE
C
BP
GND
GND
Figure 1. Functional Diagram
_______________________________________________________________________________________
8
µPMIC for Microprocessors or DSPs
in Portable Equipment
compares the reference voltage to a feedback voltage
and amplifies the difference. If the feedback voltage is
lower than the reference voltage, the pass-transistor
gate is pulled lower, allowing more current to pass to
the outputs and increasing the output voltage. If the
feedback voltage is too high, the pass-transistor gate is
pulled up, allowing less current to pass to the output.
Voltage-Positioning Load Regulation
As seen in Figure 2, the MAX8620Y uses a unique step-
down converter feedback network. By taking feedback
from the LX node through R1, the usual phase lag due
to the output capacitor is removed, making the loop
exceedingly stable and allowing the use of a very small
ceramic output capacitor. This configuration causes the
output voltage to shift by the inductor series resistance
multiplied by the load current. This output-voltage shift
is known as voltage-positioning load regulation.
Voltage-positioning load regulation greatly reduces
overshoot during load transients, which effectively
halves the peak-to-peak output-voltage excursions
compared to traditional step-down converters. See the
Load-Transient Response graph in the Typical
Operating Characteristics section.
Table 1. MAX86±0Y Output-Voltage
Selection
SEL1
IN1
SEL±
IN1
OUT1
3.00V
2.85V
3.00V
3.30V
2.80V
3.30V
2.85V
2.60V
1.80V
OUT±
2.50V
2.85V
3.00V
2.50V
2.60V
1.80V
2.60V
2.60V
2.60V
IN1
OPEN
GND
IN1
IN1
OPEN
OPEN
OPEN
GND
GND
GND
Two low-dropout, low-quiescent-current, high-accuracy
linear regulators supply loads up to 300mA each. The
LDO output voltages are set using SEL1 and SEL2 (see
Table 1). As shown in Figure 3, the LDOs include an
internal reference, error amplifiers, p-channel pass tran-
sistors, internal-programmable voltage-dividers, and an
OUT1 power-good comparator. Each error amplifier
OPEN
GND
IN1
OPEN
GND
2.6V
300mA
I/O
IN2
IN1
OUT1
C
4.7µF
OUT1
100kΩ
C
10µF
IN
Li+
CELL
RESET IN
CORE
RESET
LX
L
OUT3,
500mA
2.2µH
MAX8620Y
BP
R1
150kΩ
C
150pF
FF
C
2.2µF
OUT3
C
BP
0.01µF
FB
DSP
OR
µP
R2
75kΩ
SEL2
SEL1
2.6V
300mA
ANALOG
OUT2
C
OUT2
POWER-ON
KEY
4.7µF
HF_PWR
EN2
V
BATT
ON/OFF
PWR_ON
1MΩ
GND
Figure 2. Typical MAX8620Y DSP or µP Application
_______________________________________________________________________________________
9
µPMIC for Microprocessors or DSPs
in Portable Equipment
IN1
MAX8620Y
P
MOS DRIVER
WITH I
LIMIT
PWR_ON
ERROR-
AMP 2
OUT2
ON/OFF
LOGIC
HF_PWR
P
OUT1
MOS DRIVER
ERROR-
AMP 1
WITH I
LIMIT
EN2
RESET
1.25V
REF
LDO THERMAL
SENSOR
POK
TIMER
87%
REGULATION
BP
GND
Figure 3. Linear-Regulator Functional Diagram
PWR_ON is high (Table 2). OUT1, OUT2, and OUT3 are
all disabled when PWR_ON is low. HF_PWR can tem-
porarily bring the MAX8620 out of power-down mode
when PWR_ON is low (see the HF_PWR section). In
power-down, the control circuitry, internal-switching p-
channel MOSFET, and the internal synchronous rectifier
(n-channel MOSFET) turn off, and LX becomes high
impedance. In addition, both LDOs are disabled.
LDO Output-Voltage
Selection (SEL1, SEL2)
As shown in Table 1, the LDO output voltages, OUT1
and OUT2, are set according to the logic states of
SEL1 and SEL2. SEL1 and SEL2 are trilevel inputs: IN1,
open, and GND. The input voltage, V , must be a
IN1
dropout voltage (V ) greater than the selected OUT1
DO
and OUT2 voltages.
OUT2 Enable (EN2)
Drive EN2 low to enable OUT2. Drive EN2 high to dis-
able OUT2. If the MAX8620Y is placed into power-
down using PWR_ON (PWR_ON = low), OUT2 does not
power regardless of the status of EN2 (Table 2).
Power-Enable Input (PWR_ON)
Drive PWR_ON low to place the MAX8620Y in power-
down mode and reduce supply current to 5.5µA (typ).
Connect PWR_ON to IN1 = IN2 or logic-high to enable
the MAX8620Y. EN2 enables and disables OUT2 when
10 ______________________________________________________________________________________
µPMIC for Microprocessors or DSPs
in Portable Equipment
Table ±. MAX86±0Y Power Modes
PWR_ON
HF_PWR*
EN2
1
0
1
0
OUT1 AND OUT3
Enabled
OUT±
1
1
0
0
0
X
X
1
1
0
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Enabled
Enabled
Disabled
X
*A rising edge at HF_PWR initiates a 1.31s one-shot timer. The status of HF_PWR shown in Table 2 indicates whether the one-shot
period has expired as follows:
1 = During t
HP
0 = t has expired
HP
Hands-Free Enable Input (HF_PWR)
A rising edge at HF_PWR generates an internal one-
shot pulse that enables the MAX8620Y for 1.31s (t ). If
Power-Supply Sequencing
The step-down converter output (OUT3) always powers
up first and powers down last (Figure 4). OUT1 powers
approximately 70µs after OUT3, and OUT2 powers
HF
HF_PWR remains high after t expires, the MAX8620Y
HF
,
reenters shutdown. During t
OUT3 and OUT1 are
approximately 50µs after V
reaches 87% (typ) of
OUT1
HF
enabled so the microprocessor (µP) can initialize and
assert a logic-high at PWR_ON. OUT2 enables during
HF
its regulation voltage. When PWR_ON goes low, OUT1
turns off, then OUT2 turns off, then OUT3 turns off 50µs
after PWR_ON goes low.
t
if EN2 is low. Once PWR_ON is high, the status of
HF_PWR is ignored. If PWR_ON remains low after t
expires, the MAX8620Y reenters shutdown.
HF
50µs
HF_PWR
PWR_ON
OUT3
t
HF
t
SU1
V
THR
OUT1
OUT2
RESET
EN2
t
SU2
t
RP
Figure 4. MAX8620Y Power-Supply Sequencing
______________________________________________________________________________________ 11
µPMIC for Microprocessors or DSPs
in Portable Equipment
event of fault conditions. For continuous operation, do
not exceed the absolute-maximum junction-tempera-
ture rating of T = +150°C.
Reset Output (RESET)
RESET is an open-drain, active-low output that indi-
cates the status of OUT1. RESET is typically pulled up
through a 100kΩ resistor to the system logic voltage.
RESET asserts at power-up. The reset timer begins
J
Applications Information
once V
reaches 87% of regulation. RESET
OUT1
Power-On Closed-Loop System
When the MAX8620Y is used in conjunction with a
microcontroller, HF_PWR and PWR_ON can implement
a short-key power-on closed-loop system (Figure 5).
The MAX8620Y detects a rising edge at HF_PWR and
generates an internal 1.31s (typ) one-shot pulse that
begins power sequencing and temporarily enables
OUT1, OUT2, and OUT3 (depending on the state of
EN2). The 1.31s of power provides time for the proces-
sor to initialize and assert a logic-high at PWR_ON.
Once PWR_ON is driven high, OUT3, OUT1, and OUT2
(depending on the state of EN2) remain enabled. If the
microcontroller does not drive PWR_ON high during
deasserts 60ms after V
rises above 87% (typ) of
OUT1
regulation (see the Typical Operating Characteristics).
RESET also asserts when OUT1 is disabled.
Reference Bypass Capacitor Node (BP)
An optional 0.01µF bypass capacitor at BP creates a
lowpass filter for LDO noise reduction. OUT1 and OUT2
exhibit 45µV
of output-voltage noise with C
OUT1
=
BP
RMS
0.01µF and C
= C
= 4.7µF.
OUT2
Undervoltage Lockout
must exceed the 2.85V typical undervolt-
V
= V
IN2
IN1
age-lockout threshold (V
) before the MAX8620Y
UVLO
t
, the MAX8620Y disables OUT1, OUT2, and OUT3,
HF
enables OUT3 to begin power-supply sequencing (see
the Power-Supply Sequencing section). The UVLO
threshold hysteresis is typically 0.5V.
and reenters shutdown.
Current Limiting
The MAX8620Y 300mA LDOs limit their output current to
I
I
= 550mA (typ). If the LDO output current exceeds
, the corresponding LDO output voltage drops. The
LIM_
LIM_
step-down converter limits I
to 675mA (min).
LIM3P
V
CORE
POWER-ON
KEY
V
I/O
µP
MAX8620Y
Thermal-Overload Protection
Thermal-overload protection limits total power dissipa-
tion in the MAX8620Y. Independent thermal-protection
circuits monitor the step-down converter and the linear-
regulator circuits. When the MAX8620Y junction temper-
V
ANA
HF_PWR
PWR_ON
PWR HOLD
1MΩ
ature exceeds T = +160°C, the thermal-overload
J
protection circuit disables the corresponding circuitry,
allowing the IC to cool. The thermal-overload protection
circuitry enables the MAX8620Y after the junction tem-
perature cools by 15°C, resulting in a pulsed output dur-
ing continuous thermal-overload conditions. Thermal-
overload protection safeguards the MAX8620Y in the
POWER-HOLD SIGNAL
Figure 5. Short-Key Power-On Closed-Loop System
1± ______________________________________________________________________________________
µPMIC for Microprocessors or DSPs
in Portable Equipment
If a long-key press is preferred, see Figure 6. PWR_ON
must remain high until a microprocessor asserts a logic-
high signal when using this circuit. If a system includes
multiple power-on sources, use a diode OR configura-
tion, as shown in Figure 7.
current, I , is typically 10nA. Select R2 so the resistor-
FB
divider bias current dominates I by a factor of 10. A
FB
wide range of resistor values is acceptable, but a good
starting point is to choose R2 = 100kΩ. R1 is given by:
⎛
⎞
V
OUT3
R1=R2
−1
⎜
⎟
V
⎝
⎠
FB
where V = 0.6V.
FB
V
CORE
V
can be set between 0.6V and 3.3V, but the step-
POWER-ON
KEY
OUT3
V
I/O
down converter dropout voltage and inductor voltage
drop impact how close V can be to V . Total
µP
MAX8620Y
V
ANA
OUT3
IN2
PWR_ON
dropout voltage is a function of the pFET on-resistance,
the DCR of the inductor, and the load as follows:
PWR HOLD
1MΩ
V
= I
× R
(
+DCR
)
OUT3(DO)
OUT3
ONP INDUCTOR
For example, with 300mA load:
POWER-HOLD SIGNAL
V
= 300mA × 0.65Ω + 50mΩ = 210mV
(
)
OUT3(DO)
Figure 6. Long-Key Power-On Closed Loop
As a result, V
OUT3
= V
must exceed the desired
IN2
IN1
V
by 210mV to maintain regulation.
Inductor Selection
The MAX8620Y step-down converter operates with induc-
tors between 1µH and 4.7µH. Low inductance values are
physically smaller but require faster switching, which
results in some efficiency loss. See the Typical Operating
Characteristics section for efficiency and switching fre-
quency versus inductor value plots. The inductor’s DC
current rating needs to be only 100mA greater than the
application’s maximum load current because the
MAX8620Y step-down converter features zero-current
overshoot during startup and load transients.
V
CORE
V
MAX8620Y
I/O
AC ADAPTER
µP
V
ANA
HF_PWR
PWR_ON
HANDS-FREE KIT
PWR HOLD
POWER-ON
KEY
1MΩ
For output voltages above 2.0V, when light-load effi-
ciency is important, the minimum recommended induc-
tor is 2.2µH. For optimum voltage-positioning load
transients, choose an inductor with DC series resis-
tance in the 50mΩ to 150mΩ range (Table 3). For high-
er efficiency at heavy loads (above 200mA) or minimal
load regulation (but some transient overshoot), the
resistance should be kept below 100mΩ. For light-load
applications up to 200mA, much higher resistance is
acceptable with very little impact on performance.
POWER-HOLD SIGNAL
Figure 7. Multiple Power-On Inputs
Setting the Step-Down Output Voltage
(OUT3)
Select a step-down converter output voltage between
0.6V and 3.3V by connecting a resistor voltage-divider
between LX, FB, and GND (see Figure 2). The FB bias
______________________________________________________________________________________ 13
µPMIC for Microprocessors or DSPs
in Portable Equipment
Table 3. Suggested ꢀnductors
ꢀNDUCTANCE
(µH)
ESR
(Ω)
CURRENT RATꢀNG
(mA)
MANUFACTURER
SERꢀES
DꢀMENSꢀONS (mm)
1.0
2.2
0.15
0.23
300
240
2.0 x 1.25 x 1.25
= 3.1mm3
LB2012
1.0
1.5
2.2
3.3
0.09
0.11
0.13
0.20
455
350
315
280
2.0 x 1.6 x 1.8
= 5.8mm3
LB2016
LB2518
1.0
1.5
2.2
3.3
0.06
0.07
0.09
0.11
500
400
340
270
2.5 x 1.8 x 2.0
= 9mm3
Taiyo Yuden
1.0
1.5
2.2
3.3
4.7
0.08
0.11
0.13
0.16
0.20
775
660
600
500
430
2.5 x 1.8 x 2.0
= 9mm3
LBC2518
2.2
4.7
0.23
0.40
410
300
2.0 x 1.25 x 1.25
= 3.1mm3
CB2012
CB2016
CB2518
2.2
4.7
0.13
0.25
510
340
2.0 x 1.6 x 1.8
= 5.8mm3
2.2
4.7
0.09
0.13
510
340
2.5 x 1.8 x 2.0
= 9mm3
1.0
2.2
4.7
0.06
0.10
0.15
1000
790
650
3.2 x 2.5 x 1.7
= 14mm3
LQH32C_53
LQM43FN
D310F
Murata
2.2
4.7
0.10
0.17
400
300
4.5 x 3.2 x 0.9
= 13mm3
1.5
2.2
3.3
0.13
0.17
0.19
1230
1080
1010
3.6 x 3.6 x 1.0
= 13mm3
TOKO
1.5
2.2
2.7
3.3
0.10
0.12
0.15
0.17
1290
1140
980
3.6 x 3.6 x 1.2
= 16mm3
D312C
900
1.5
2.2
3.3
4.7
0.05
0.08
0.10
0.14
900
780
600
500
3.2 x 3.2 x 1.2
= 12mm3
Sumida
CDRH2D11
14 ______________________________________________________________________________________
µPMIC for Microprocessors or DSPs
in Portable Equipment
lent series resistance (ESR) affects stability and output
noise. Use output capacitors with an ESR of 0.1Ω or
less to ensure stability and optimum transient response.
Surface-mount ceramic capacitors have very low ESR
and are commonly available in values up to 10µF.
Capacitor Selection
Step-Down Converter Output Capacitor
The output capacitor, C
, is required to keep the
OUT3
output voltage ripple small and to ensure regulation
loop stability. C must have low impedance at the
OUT3
Connect C
as close as possible to the MAX8620Y
OUT
switching frequency. Ceramic capacitors with X5R or
X7R dielectric are highly recommended due to their
small size, low ESR, and small temperature coefficients.
Due to the unique feedback network, the output capac-
itance can be very low. For most applications, a 2.2µF
capacitor is sufficient. For optimum load-transient per-
formance and very low output ripple, the output capaci-
tor value in µFs should be equal to or larger than the
inductor value in µHs.
to minimize the impact of PC board trace inductance.
Power Dissipation and Thermal
Considerations
The MAX8620Y total power dissipation, P , is estimat-
D
ed using the following equations:
P
= P
+ P
+ P
D
LOSS(OUT1)
LOSS(OUT2) LOSS(OUT3)
P
= I
V
− V
− V
(
)
Input Capacitor
LOSS(OUT1)
(OUT1) IN
OUT1
The input capacitor, C , reduces the current peaks
IN
P
= I
V
(
)
LOSS(OUT2)
(OUT2) IN
OUT2
drawn from the battery or input power source and
reduces switching noise in the IC. The impedance of
η
100
⎛
⎞
2
P
= P
1 −
− I
(OUT3)
⎜
⎟
⎠
LOSS(OUT3)
IN(OUT3)
C
IN
at the switching frequency should be kept very low.
⎝
Ceramic capacitors with X5R or X7R dielectrics are
highly recommended due to their small size, low ESR,
and small temperature coefficients. Use a 10µF ceram-
ic capacitor or equivalent amount of multiple capacitors
× R
DC(INDUCTOR)
`
where P
is the input power for OUT3, η is the
IN(OUT3)
step-down converter efficiency, and R
the inductor’s DC resistance.
is
DC(INDUCTOR)
in parallel between IN1 and GND. Connect C as
IN
close as possible to the MAX8620Y to minimize the
impact of PC board trace inductance.
The die junction temperature can be calculated as follows:
Feed-Forward Capacitor
The feed-forward capacitor, C , sets the feedback
FF
T
= T + P × θ
J
A
D
JA
loop response, controls the switching frequency, and is
critical in obtaining the best efficiency possible.
Choose a small ceramic C0G (NPO) or X7R capacitor
with a value given by:
where θ = 55°C/W at +70°C.
T should not exceed +150°C in normal operating con-
J
ditions.
JA
PC Board Layout and Routing
High switching frequencies and relatively large peak
currents make the PC board layout a very important
aspect of design. Good design minimizes excessive
EMI on the feedback paths and voltage gradients in the
ground plane, both of which can result in instability or
L
R1
C
=
×10S
FF
where R1 is the resistor between LX and FB (Figure 2).
Select the closest standard value to C as possible.
FF
regulation errors. Connect C close to IN1 and GND.
IN
LDO Output Capacitors
For applications that require greater than 150mA of out-
put current, connect a 4.7µF ceramic capacitor
between the LDO output and GND. For applications
that require less than 150mA of output current, connect
a 2.2µF ceramic capacitor between the LDO output
Connect the inductor and output capacitors (C
) as
OUT3
close to the IC as possible and keep the traces short,
direct, and wide.
The traces between C , C , and FB are sensitive
OUT3 FF
to inductor magnetic-field interference. Route these
traces between ground planes or keep the traces away
from the inductor.
and GND. The LDO output capacitor’s (C
) equiva-
OUT_
______________________________________________________________________________________ 15
µPMIC for Microprocessors or DSPs
in Portable Equipment
Connect GND to the ground plane. The external feed-
back network should be very close to the FB pin, within
Pin Configuration
0.2in (5mm). Keep noisy traces, such as the LX node,
TOP VIEW
as short as possible. Connect GND to the exposed
paddle directly under the IC. Figure 8 and the
MAX8620Y evaluation kit illustrate examples of PC
board layout and routing schemes.
14 13 12 11 10
9
8
MAX8620Y
SEL1
SEL2
1
2
3
4
5
6
7
IN
C1
EN2
U1
GND
R1 L1
C4
OUT3
3mm x 3mm x 0.8mm
TDFN
RESET
HF_PWR
PWR_ON
Chip Information
TRANSISTOR COUNT: 4481
Figure 8. Recommended PC Board Layout
PROCESS: BiCMOS
16 ______________________________________________________________________________________
µPMIC for Microprocessors or DSPs
in Portable Equipment
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
D2
D
A2
PIN 1 ID
N
0.35x0.35
b
[(N/2)-1] x e
REF.
PIN 1
INDEX
AREA
E
E2
DETAIL A
e
A1
k
C
C
L
L
A
L
L
e
e
PACKAGE OUTLINE, 6,8,10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
1
-DRAWING NOT TO SCALE-
21-0137
G
2
______________________________________________________________________________________ 17
µPMIC for Microprocessors or DSPs
in Portable Equipment
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
SYMBOL
MIN.
0.70
2.90
2.90
0.00
0.20
MAX.
0.80
3.10
3.10
0.05
0.40
A
D
E
A1
L
k
0.25 MIN.
0.20 REF.
A2
PACKAGE VARIATIONS
DOWNBONDS
ALLOWED
PKG. CODE
T633-1
N
6
D2
E2
e
JEDEC SPEC
MO229 / WEEA
MO229 / WEEA
MO229 / WEEC
MO229 / WEEC
MO229 / WEEC
b
[(N/2)-1] x e
1.90 REF
1.90 REF
1.95 REF
1.95 REF
1.95 REF
2.00 REF
2.40 REF
2.40 REF
1.50±0.10 2.30±0.10 0.95 BSC
1.50±0.10 2.30±0.10 0.95 BSC
1.50±0.10 2.30±0.10 0.65 BSC
1.50±0.10 2.30±0.10 0.65 BSC
1.50±0.10 2.30±0.10 0.65 BSC
0.40±0.05
0.40±0.05
0.30±0.05
0.30±0.05
0.30±0.05
NO
NO
T633-2
6
T833-1
8
NO
T833-2
8
NO
T833-3
8
YES
NO
T1033-1
T1433-1
T1433-2
10
14
14
1.50±0.10 2.30±0.10 0.50 BSC MO229 / WEED-3 0.25±0.05
1.70±0.10 2.30±0.10 0.40 BSC
1.70±0.10 2.30±0.10 0.40 BSC
- - - -
- - - -
0.20±0.05
0.20±0.05
YES
NO
PACKAGE OUTLINE, 6,8,10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
2
-DRAWING NOT TO SCALE-
21-0137
G
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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