MAX7300ATL [MAXIM]
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander; 2线接口， 2.5V至5.5V ， 20端口或28端口I / O扩展器
| 型号： | MAX7300ATL |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander |
| 文件： | 总20页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2413; Rev 7; 9/11
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
MAX730
General Description
Features
The MAX7300 compact, serial-interfaced, I/O expan-
sion peripheral provides microprocessors with up to 28
ports. Each port is individually user configurable to
either a logic input or logic output.
o 400kbps I2C-Compatible Serial Interface
o 2.5V to 5.5V Operation
o -40°C to +125°C Temperature Range
o 20 or 28 I/O Ports, Each Configurable as
Each port can be configured as either a push-pull logic
output capable of sinking 10mA and sourcing 4.5mA, or a
Schmitt logic input with optional internal pullup. Seven
ports feature configurable transition detection logic, which
generates an interrupt upon change of port logic level.
The MAX7300 is controlled through an I2C-compatible 2-
wire serial interface, and uses four-level logic to allow 16
I2C addresses from only two select pins.
Push-Pull Logic Output
Schmitt Logic Input
Schmitt Logic Input with Internal Pullup
o 11µA (max) Shutdown Current
o Logic Transition Detection for Seven I/O Ports
Ordering Information
The MAX7300AAX and MAX7300ATL have 28 ports and
are available in 36-pin SSOP and 40-pin TQFN pack-
ages, respectively. The MAX7300AAI and MAX7300ATI
have 20 ports and are available in 28-pin SSOP and
TQFN packages. For an SPI-interfaced version, refer to
the MAX7301 data sheet. For a pin-compatible port
expander with additional 24mA constant-current LED
drive capability, refer to the MAX6956 data sheet.
PART
MAX7300AAI
MAX7300ATI
MAX7300AAX
TEMP RANGE
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
PIN-PACKAGE
28 SSOP
28 TQFN-EP*
36 SSOP
MAX7300ATL
40 TQFN-EP*
*EP = Exposed pad.
Devices are also available in a lead(Pb)-free/RoHS-compliant pack-
age. Specify lead-free by adding "+" to the part number when order-
ing. Devices are also available in tape-and-reel packaging. Specify
tape and reel by adding "T" to the part number when ordering.
Applications
Industrial Controllers
White Goods
Automotive
System Monitoring
Typical Operating Circuit
Pin Configurations
32
30
28
26
3V
P4
P5
I/O 4
36
3
I/O 5
V+
GND
TOP VIEW
P6
I/O 6
47nF
39kΩ
2
1
GND
ISET
P7
I/O 7
ISET
GND
GND
AD0
P12
P13
P14
P15
P16
1
2
3
4
5
6
7
8
9
28 V+
5
P8
I/O 8
7
27 AD1
26 SCL
25 SDA
24 P31
P9
I/O 9
9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
35
11
6
AD1
AD0
SDA
SCL
4
33
34
MAX7300AAX
8
DATA
CLOCK
10
12
13
14
15
16
17
18
19
20
MAX7300
23 P30
31
29
27
25
24
23
22
21
P31
P30
P29
P28
P27
P26
P25
P24
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
22 P29
21 P28
20 P27
19 P26
18 P25
17 P24
16 P23
15 P22
P17 10
P18 11
P19 12
P20 13
P21 14
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
28 SSOP
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
ABSOLUTE MAXIMUM RATINGS
Voltage (with respect to GND)
36-Pin SSOP (derate 11.8mW/°C above +70°C) .........941mW
V+.............................................................................-0.3V to +6V
SCL, SDA, AD0, AD1................................................-0.3V to +6V
All Other Pins................................................-0.3V to (V+ + 0.3V)
P4–P31 Current ................................................................ 30mA
GND Current .....................................................................800mA
40-Pin TQFN (derate 26.3mW/°C above T = +70°C).2105mW
Operating Temperature Range
A
(T
to T
) ...............................................-40°C to +125°C
MAX
MIN
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow)
Lead (Pb)-free packages..............................................+260°C
Packages containing lead (Pb).....................................+240°C
Continuous Power Dissipation (T = +70°C)
A
28-Pin SSOP (derate 9.1mW/°C above +70°C) ...........727mW
28-Pin TQFN (derate 21.3mW/°C above +70°C) .......1702mW
MAX730
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Typical Operating Circuit, V = 2.5V to 5.5V, T = T
to T
, unless otherwise noted.) (Note 1)
MAX
V+
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
5.5
8
UNITS
Operating Supply Voltage
V+
2.5
V
T
T
T
= +25°C
5.5
A
I
All digital inputs at
V+ or GND
SHDN
Shutdown Supply Current
Operating Supply Current
= -40°C to +85°C
10
µA
µA
A
to T
11
MIN
MAX
T
= +25°C
180
170
110
240
260
A
A
All ports programmed
as outputs high, no
load, all other inputs
at V+ or GND
T
= -40°C to +85°C
I
GPOH
T
T
T
to T
280
210
230
MIN
MAX
= +25°C
A
A
All ports programmed
as outputs low, no
load, all other inputs
at V+ or GND
= -40°C to +85°C
Operating Supply Current
I
µA
µA
GPOL
T
T
T
to T
240
135
140
MIN
MAX
All ports programmed
as inputs without
pullup, ports, and all
other inputs at V+ or
GND
= +25°C
A
A
= -40°C to +85°C
Operating Supply Current
I
GPI
T
MIN
to T
145
MAX
INPUTS AND OUTPUTS
Logic High Input Voltage
Port Inputs
0.7 x
V+
V
V
V
IH
Logic Low Input Voltage
Port Inputs
0.3 x
V+
V
IL
GPIO inputs without pullup,
Input Leakage Current
I
, I
IH IL
-100
1
+100
nA
V
= V+ to GND
PORT
V
V
= 2.5V
12
80
19
120
0.3
30
V+
V+
GPIO Input Internal Pullup to V+
Hysteresis Voltage GPIO Inputs
I
µA
V
PU
= 5.5V
180
∆V
I
2
_______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
MAX730
ELECTRICAL CHARACTERISTICS (continued)
, unless otherwise noted.) (Note 1)
MAX
(Typical Operating Circuit, V = 2.5V to 5.5V, T = T
to T
V+
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GPIO outputs, I
= 2mA,
V+ -
0.7
SOURCE
T
A
= -40°C to +85°C
Output High Voltage
V
V
OH
GPIO outputs, I
= 1mA,
(Note 2)
V+ -
0.7
SOURCE
T
A
= T
to T
MIN
MAX
Port Sink Current
I
V
= 0.6V
2
10
11
18
20
mA
mA
OL
PORT
Output Short-Circuit Current
I
Port configured output low, shorted to V+
2.75
OLSC
Input High-Voltage SDA, SCL,
AD0, AD1
0.7 x
V+
V
V
V
IH
Input Low-Voltage SDA, SCL,
AD0, AD1
0.3 x
V+
V
IL
Input Leakage Current SDA, SCL
Input Capacitance
I
, I
-50
+50
10
nA
pF
V
IH IL
(Note 2)
= 6mA
Output Low-Voltage SDA
V
I
0.4
OL
SINK
TIMING CHARACTERISTICS (Figure 2)
(V = 2.5V to 5.5V, T = T
to T , unless otherwise noted.) (Note 1)
MAX
V+
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Clock Frequency
f
400
kHz
SCL
Bus Free Time Between a STOP
and a START Condition
t
1.3
0.6
0.6
µs
µs
µs
BUF
Hold Time (Repeated) START
Condition
t
HD, STA
Repeated START Condition
Setup Time
t
SU, STA
STOP Condition Setup Time
Data Hold Time
t
0.6
15
µs
ns
ns
µs
µs
SU, STO
t
(Note 3)
900
HD, DAT
Data Setup Time
t
100
1.3
0.7
SU, DAT
SCL Clock Low Period
SCL Clock High Period
t
LOW
t
HIGH
Rise Time of Both SDA and SCL
Signals, Receiving
20 +
t
(Notes 2, 4)
(Notes 2, 4)
300
300
ns
ns
R
0.1C
b
Fall Time of Both SDA and SCL
Signals, Receiving
20 +
0.1C
t
F
b
20 +
0.1C
Fall Time of SDA Transmitting
t
(Notes 2, 5)
(Notes 2, 6)
(Note 2)
250
50
ns
ns
pF
F,TX
b
Pulse Width of Spike Suppressed
t
0
SP
Capacitive Load for Each Bus
Line
C
400
b
_______________________________________________________________________________________
3
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
TIMING CHARACTERISTICS (Figure 2) (continued)
(V = 2.5V to 5.5V, T = T
to T
, unless otherwise noted.) (Note 1)
MAX
V+
A
MIN
Note 1: All parameters tested at T = +25°C. Specifications over temperature are guaranteed by design.
A
Note 2: Guaranteed by design.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V of the SCL signal) in order to
IL
bridge the undefined region of SCL’s falling edge.
Note 4: C = total capacitance of one bus line in pF. t and t measured between 0.3V+ and 0.7V+.
b
R
F
Note 5: I
≤ 6mA. C = total capacitance of one bus line in pF. t and t measured between 0.3V+ and 0.7V+.
SINK
b R F
MAX730
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
__________________________________________Typical Operating Characteristics
(R
= 39kΩ, T = +25°C, unless otherwise noted.)
ISET
A
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
OPERATING SUPPLY CURRENT
OPERATING SUPPLY CURRENT vs. V+
(OUTPUTS UNLOADED)
vs. TEMPERATURE
1
0.40
0.36
0.32
0.28
0.24
0.20
0.16
0.12
0.08
0.04
0
8
V
= 2.5V TO 5.5V
V+
NO LOAD
V
= 5.5V
V+
7
6
5
4
3
ALL PORTS
OUTPUT (0)
V
V+
= 3.3V
ALL PORTS
OUTPUT (1)
ALL PORTS OUTPUT (1)
ALL PORTS OUTPUT (0)
V
= 2.5V
V+
ALL PORTS INPUT
(PULLUPS DISABLED)
ALL PORTS INPUT HIGH
0.1
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V+ (V)
-40.0 -12.5 15.0 42.5 70.0 97.5 125.0
-40.0 -12.5 15.0 42.5 70.0 97.5 125.0
TEMPERATURE (°C)
TEMPERATURE (°C)
4
_______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
MAX730
Typical Operating Characteristics (continued)
(R
= 39kΩ, T = +25°C, unless otherwise noted.)
A
ISET
GPO SOURCE CURRENT vs. TEMPERATURE
(OUTPUT = 1)
GPO SINK CURRENT vs. TEMPERATURE
(OUTPUT = 0)
18
16
14
12
10
8
9
8
7
6
5
4
3
2
V
= 1.4V
PORT
V
= 2.5V TO 5.5V, V
= 0.6V
V+
PORT
V
= 5.5V
V+
V
= 3.3V
V+
V
= 2.5V
V+
6
4
2
-40.0 -12.5 15.0 42.5 70.0 97.5 125.0
-40.0 -12.5 15.0 42.5 70.0 97.5 125.0
TEMPERATURE (°C)
TEMPERATURE (°C)
GPI PULLUP CURRENT
vs. TEMPERATURE
GPO SHORT-CIRCUIT CURRENT
vs. TEMPERATURE
1000
100
10
100
10
1
V
= 5.5V
V+
GPO = 0, PORT
SHORTED TO V+
V
= 3.3V
V+
V
= 2.5V
V+
GPO = 1, PORT
SHORTED TO GND
-40.0 -12.5 15.0 42.5 70.0 97.5 125.0
-40.0 -12.5 15.0 42.5 70.0 97.5 125.0
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
Pin Description
PIN
NAME
FUNCTION
28 SSOP 28 TQFN-EP 36 SSOP 40 TQFN-EP
Bias Current Setting. Connect ISET to GND through a resistor
1
2, 3
4
26
27, 28
1
1
2, 3
4
36
ISET
GND
AD0
(R ) value of 39kΩ to 120kΩ.
ISET
37, 38, 39
Ground
Address Input 0. Sets device slave address. Connect to either
GND, V+, SCL, SDA to give four logic combinations. See Table 3.
7
40
—
I/O Ports. P12 to P31 can be configured as push-pull outputs,
CMOS-logic inputs, or CMOS-logic inputs with weak pullup resistor.
5–24
—
2–21
—
—
P12–P31
P4–P31
1–10, 12–19,
21–30
I/O Ports. P4 to P31 can be configured as push-pull outputs,
CMOS-logic inputs, or CMOS-logic inputs with weak pullup resistor.
5–32
11, 20, 31
—
25
26
—
22
23
—
33
34
N.C.
SDA
SCL
No Connection. Not internally connected.
I2C-Compatible Serial-Data I/O
I2C-Compatible Serial-Clock Input
32
33
Address Input 1. Sets device slave address. Connect to either
GND, V+, SCL, SDA to give four logic combinations. See Table 3.
27
28
24
25
35
36
34
35
AD1
V+
Positive Supply Voltage. Bypass V+ to GND with minimum
0.047µF capacitor.
Exposed Pad (TQFN Only). EP is internally connected to GND.
Connect to a large ground plane to maximize thermal
—
—
—
—
EP
performance. Not intended as an electrical connection point.
registers 0x09 and 0x0A. If this is not done, the eight
unused ports remain as unconnected inputs and quies-
cent supply current rises, although there is no damage
to the part.
Detailed Description
The MAX7300 general-purpose input/output (GPIO)
peripheral provides up to 28 I/O ports, P4 to P31, con-
trolled through an I2C-compatible serial interface. The
ports can be configured to any combination of logic inputs
and logic outputs, and default to logic inputs on power-up.
Register Control of I/O Ports
Across Multiple Drivers
The MAX7300 offers 20 or 28 I/O ports, depending on
package choice. Two addressing methods are avail-
able. Any single port (bit) can be written (set/cleared)
at once; or, any sequence of eight ports can be written
(set/cleared) in any combination at once. There are no
boundaries; it is equally acceptable to write P0 to P7,
P1 to P8, or P31 to P38 (P32 to P38 are nonexistent, so
the instructions to these bits are ignored).
Figure 1 is the MAX7300 functional diagram. Any I/O port
can be configured as a push-pull output (sinking 10mA,
sourcing 4.5mA), or a Schmitt-trigger logic input. Each
input has an individually selectable internal pullup resis-
tor. Additionally, transition detection allows seven ports
(P24 to P30) to be monitored in any maskable combina-
tion for changes in their logic status. A detected transi-
tion is flagged through a status register bit, as well as an
interrupt pin (port P31), if desired.
Shutdown
When the MAX7300 is in shutdown mode, all ports are
forced to inputs, and the pullup current sources are
turned off. Data in the port and control registers remain
unaltered, so port configuration and output levels are
restored when the MAX7300 is taken out of shutdown.
The MAX7300 can still be programmed while in shut-
down mode. For minimum supply current in shutdown
mode, logic inputs should be at GND or V+ potential.
Shutdown mode is exited by setting the S bit in the con-
figuration register (Table 8).
The port configuration registers individually set the 28
ports, P4 to P31, as GPIO. A pair of bits in registers
0x09 through 0x0F sets each port’s configuration
(Tables 1 and 2).
The 36-pin MAX7300AAX and 40-pin MAX7300ATL have
28 ports, P4 to P31. The 28-pin MAX7300ANI,
MAX7300AAI, and MAX7300ATI have only 20 ports avail-
able, P12 to P31. The eight unused ports should be
configured as outputs on power-up by writing 0x55 to
6
_______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
MAX730
Table 1. Port Configuration Map
REGISTER DATA
D4 D3
ADDRESS
CODE (HEX)
REGISTER
D7
D6
D5
D2
D1
D0
Port Configuration for P7, P6, P5, P4
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
P7
P6
P5
P4
Port Configuration for P11, P10, P9, P8
Port Configuration for P15, P14, P13, P12
Port Configuration for P19, P18, P17, P16
Port Configuration for P23, P22, P21, P20
Port Configuration for P27, P26, P25, P24
Port Configuration for P31, P30, P29, P28
P11
P15
P19
P23
P27
P31
P10
P14
P18
P22
P26
P30
P9
P8
P13
P17
P21
P25
P29
P12
P16
P20
P24
P28
Table 2. Port Configuration Matrix
PORT
CONFIGURATION
BIT PAIR
PORT
REGISTER
ADDRESS
CODE (HEX)
MODE
FUNCTION
PIN BEHAVIOR
(0x20–0x5F)
UPPER
LOWER
DO NOT USE THIS SETTING
Register bit = 0
0x09 to 0x0F
0x09 to 0x0F
0
0
Active-low logic output
Active-high logic output
Output
GPIO Output
0
1
Register bit = 1
GPIO Input
without Pullup
Input
Input
Schmitt logic input
0x09 to 0x0F
0x09 to 0x0F
1
1
0
1
Register bit =
input logic level
GPIO Input with Pullup
Schmitt logic input with pullup
START and STOP Conditions
Serial Interface
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
Serial Addressing
The MAX7300 operates as a slave that sends and
receives data through an I2C-compatible 2-wire inter-
face. The interface uses a serial data line (SDA) and a
serial clock line (SCL) to achieve bidirectional commu-
nication between master(s) and slave(s). A master (typ-
ically a microcontroller) initiates all data transfers to and
from the MAX7300, and generates the SCL clock that
synchronizes the data transfer (Figure 2).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
The MAX7300 SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7kΩ,
is required on SDA. The MAX7300 SCL line operates
only as an input. A pullup resistor, typically 4.7kΩ, is
required on SCL if there are multiple masters on the 2-
wire interface, or if the master in a single-master system
has an open-drain SCL output.
Acknowledge
The acknowledge bit is a clocked 9th bit, which the
recipient uses to handshake receipt of each byte of
data (Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is sta-
ble low during the high period of the clock pulse. When
the master is transmitting to the MAX7300, the
MAX7300 generates the acknowledge bit since the
Each transmission consists of a START condition
(Figure 3) sent by a master, followed by the MAX7300
7-bit slave address plus R/W bit (Figure 6), a register
address byte, one or more data bytes, and finally a
STOP condition (Figure 3).
_______________________________________________________________________________________
7
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
CONFIGURATION
PORT REGISTERS
MASK REGISTER
GPIO
P4 TO P31
CONFIGURATION
REGISTERS
PORT CHANGE
DETECTOR
MAX730
DATA
CE
R/W
8
GPIO DATA
8
R/W
COMMAND
REGISTER DECODE
AD0
AD1
ADDRESS
MATCHER
7
8
8
DATA BYTE
COMMAND BYTE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
7
TO/FROM DATA REGISTERS
DATA BYTE
TO COMMAND REGISTERS
7-BIT DEVICE ADDRESS
R/W
SDA
SCL
COMMAND BYTE
SLAVE ADDRESS BYTE
Figure 1. MAX7300 Functional Diagram
MAX7300 is the recipient. When the MAX7300 is trans-
mitting to the master, the master generates the
acknowledge bit since the master is the recipient.
addresses (Table 3), and therefore a maximum of 16
MAX7300 devices can share the same interface.
Message Format for Writing
the MAX7300
Slave Address
The MAX7300 has a 7-bit-long slave address (Figure 6).
The eighth bit following the 7-bit slave address is the
R/W bit. It is low for a write command and high for a
read command.
A write to the MAX7300 comprises the transmission of
the MAX7300’s slave address with the R/W bit set to
zero, followed by at least 1 byte of information. The first
byte of information is the command byte. The com-
mand byte determines which register of the MAX7300
is to be written by the next byte, if received. If a STOP
condition is detected after the command byte is
received, then the MAX7300 takes no further action
(Figure 7) beyond storing the command byte.
The first 3 bits (MSBs) of the MAX7300 slave address
are always 100. Slave address bits A3, A2, A1, and A0
are selected by the address inputs, AD1 and AD0.
These two input pins can be connected to GND, V+,
SDA, or SCL. The MAX7300 has 16 possible slave
8
_______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
MAX730
SDA
t
BUF
t
t
SU, STA
SU, DAT
t
HD, STA
t
LOW
t
t
SU, STO
HD, DAT
SCL
t
HIGH
t
HD, STA
t
t
F
R
REPEATED START CONDITION
START CONDITION
STOP CONDITION START CONDITION
Figure 2. 2-Wire Serial Interface Timing Details
SDA
S
P
SCL
START
STOP
CONDITION
CONDITION
Figure 3. Start and Stop Conditions
SDA
SCL
DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED
Figure 4. Bit Transfer
Any bytes received after the command byte are consid-
ered data bytes. The first data byte goes into the inter-
nal register of the MAX7300 selected by the command
byte (Figure 8). If multiple data bytes are transmitted
before a STOP condition is detected, these bytes are
generally stored in subsequent MAX7300 internal regis-
ters because the command byte address generally
autoincrements (Table 4).
a write. The pointer generally autoincrements after each
data byte is read using the same rules as for a write
(Table 4). Thus, a read is initiated by first configuring the
MAX7300’s command byte by performing a write (Figure
7). The master can now read ‘n’ consecutive bytes from
the MAX7300, with the first data byte being read from the
register addressed by the initialized command byte
(Figure 9). When performing read-after-write verification,
remember to reset the command byte’s address
because the stored control byte address generally has
been autoincremented after the write (Table 4). Table 5
is the register address map.
Message Format for Reading
The MAX7300 is read using the MAX7300’s internally
stored command byte as address pointer, the same way
the stored command byte is used as address pointer for
_______________________________________________________________________________________
9
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
START CONDITION
CLOCK PULSE FOR ACKNOWLEDGMENT
SCL
1
2
8
9
SDA
BY TRANSMITTER
MAX730
S
SDA
BY RECEIVER
Figure 5. Acknowledge
SDA
1
MSB
0
0
A3
A2
A1
A0
LSB
R/W
ACK
SCL
Figure 6. Slave Address
Operation with Multiple Masters
If the MAX7300 is operated on a 2-wire interface with
multiple masters, a master reading the MAX7300 should
use a repeated start between the write, which sets the
MAX7300’s address pointer, and the read(s) that takes
the data from the location(s). This is because it is possi-
ble for master 2 to take over the bus after master 1 has
set up the MAX7300’s address pointer, but before
master 1 has read the data. If master 2 subsequently
changes, the MAX7300’s address pointer, then master
1’s delayed read can be from an unexpected location.
Initial Power-Up
On initial power-up, all control registers are reset and
the MAX7300 enters shutdown mode (Table 6).
Transition (Port Data Change) Detection
Port transition detection allows any combination of the
seven ports P24–P30 to be continuously monitored for
changes in their logic status (Figure 10). A detected
change is flagged on the transition detection mask reg-
ister INT status bit, D7 (Table 10). If port P31 is config-
ured as an output (Tables 1 and 2), then P31 also
automatically becomes an active-high interrupt output
(INT), which follows the condition of the INT status bit.
Port P31 is set as output by writing bit D7 = 0 and bit
D6 = 1 to the port configuration register (Table 1). Note
that the MAX7300 does not identify which specific
port(s) caused the interrupt, but provides an alert that
one or more port levels have changed.
Command Address Autoincrementing
Address autoincrementing allows the MAX7300 to be
configured with the shortest number of transmissions
by minimizing the number of times the command
address needs to be sent. The command address
stored in the MAX7300 generally increments after each
data byte is written or read (Table 4).
The mask register contains 7 mask bits that select
which of the seven ports P24–P30 are to be monitored
(Table 10). Set the appropriate mask bit to enable that
port for transition detect. Clear the mask bit if transi-
10 ______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
MAX730
D15 D14 D13 D12 D11 D10 D9 D8
COMMAND BYTE IS STORED ON RECEIPT OF STOP CONDITION
ACKNOWLEDGE FROM MAX7300
SLAVE ADDRESS
S
0
A
COMMAND BYTE
A
P
ACKNOWLEDGE FROM MAX7300
R/W
Figure 7. Command Byte Received
ACKNOWLEDGE FROM MAX7300
ACKNOWLEDGE FROM MAX7300
HOW COMMAND BYTE AND DATA BYTE MAP INTO MAX7300’s REGISTER
ACKNOWLEDGE FROM MAX7300
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
S
SLAVE ADDRESS
0
A
A
DATA BYTE
A
P
COMMAND BYTE
1 BYTE
R/W
AUTOINCREMENT MEMORY WORD ADDRESS
Figure 8. Command and Single Data Byte Received
tions on that port are to be ignored. Transition detection
works regardless of whether the port being monitored is
set to input or output, but generally, it is not particularly
useful to enable transition detection for outputs.
The only way to clear INT is to access (read or write)
the transition detection mask register (Table 10). So if
the transition detection mask register is read twice in
succession after a transition event, the first time reads
with bit D7 set (identifying the event), and the second
time reads with bit D7 clear.
To use transition detection, first set up the mask regis-
ter and configure port P31 as an output, as described
above. Then enable transition detection by setting the
M bit in the configuration register (Table 9). Whenever
the configuration register is written with the M bit set,
the MAX7300 updates an internal 7-bit snapshot regis-
ter, which holds the comparison copy of the logic states
of ports P24 through P30. The update action occurs
regardless of the previous state of the M bit, so that it is
not necessary to clear the M bit and then set it again to
update the snapshot register.
Transition detection is a one-shot event. When INT has
been cleared after responding to a transition event, tran-
sition detection is automatically disabled, even though
the M bit in the configuration register remains set (unless
cleared by the user). Reenable transition detection by
writing the configuration register with the M bit set to
take a new snapshot of the seven ports P24 to P30.
External Component R
ISET
to set
The MAX7300 uses an external resistor, R
ISET,
When the configuration register is written with the M bit
set, transition detection is enabled and remains
enabled until either the configuration register is written
with the M bit clear, or a transition is detected. The INT
status bit (transition detection mask register bit D7)
goes low. Port P31 (if enabled as INT output) also goes
low, if it was not already low.
internal biasing. Use a resistor value of 39kΩ.
Applications Information
Low-Voltage Operation
The MAX7300 operates down to 2V supply voltage
(although the sourcing and sinking currents are not guar-
anteed), providing that the MAX7300 is powered up ini-
tially to at least 2.5V to trigger the device’s internal reset.
Once transition detection is enabled, the MAX7300
continuously compares the snapshot register against
the changing states of P24 through P31. If a change on
any of the monitored ports is detected, even for a short
time (like a pulse), the INT status bit (transition detec-
tion mask register bit D7) is set. Port P31 (if enabled as
INT output) also goes high. The INT output and INT sta-
tus bit are not cleared if more changes occur or if the
data pattern returns to its original snapshot condition.
Serial Interface Latency
When a MAX7300 register is written through the I2C
interface, the register is updated on the rising edge of
SCL during the data byte’s acknowledge bit (Figure 5).
The delay from the rising edge of SCL to the internal
register being updated can range from 50ns to 350ns.
______________________________________________________________________________________ 11
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
ACKNOWLEDGE FROM MAX7300
ACKNOWLEDGE FROM MAX7300
HOW COMMAND BYTE AND DATA BYTE MAP INTO MAX7300’s REGISTER
ACKNOWLEDGE FROM MAX7300
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
SLAVE ADDRESS
COMMAND BYTE
DATA BYTE
S
0
A
A
A
P
‘n’ BYTES
R/W
AUTOINCREMENT MEMORY WORD ADDRESS
Figure 9. ‘n’ Data Bytes Received
MAX730
Table 3. MAX7300 Address Map
PIN
DEVICE ADDRESS
CONNECTION
AD1
GND
GND
GND
GND
V+
AD0
GND
V+
A6
A5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SDA
SCL
GND
V+
V+
V+
SDA
SCL
GND
V+
V+
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
SDA
SCL
GND
V+
SDA
SCL
Table 4. Autoincrement Rules
COMMAND BYTE ADDRESS RANGE
x0000000 to x1111110
x1111111
AUTOINCREMENT BEHAVIOR
Command address autoincrements after byte read or written
Command address remains at x1111111 after byte written or read
PC Board Layout Considerations
Power-Supply Considerations
The MAX7300 operates with power-supply voltages of
2.5V to 5.5V. Bypass the power supply to GND with a
0.047µF capacitor as close to the device as possible.
Add a 1µF capacitor if the MAX7300 is far away from
the board’s input bulk decoupling capacitor.
Ensure that all the MAX7300 GND connections are
used. For TQFN versions, connect the underside
exposed pad to GND. A ground plane is not necessary,
but may be useful to reduce supply impedance if the
MAX7300 outputs are to be heavily loaded. Keep the
track length from the ISET pin to the R
resistor as
ISET
short as possible, and take the GND end of the register
either to the ground plane or directly to the GND pins.
12 ______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
MAX730
Table 5. Register Address Map
COMMAND ADDRESS
HEX
CODE
REGISTER
D15
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D13
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
D11
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
D10
0
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
D9
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D8
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
No-Op
0x00
0x04
0x06
0x07
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
Configuration
Transition Detect Mask
Factory Reserved; do not write to this port
Port Configuration P7, P6, P5, P4
Port Configuration P11, P10, P9, P8
Port Configuration P15, P14, P13, P12
Port Configuration P19, P18, P17, P16
Port Configuration P23, P22, P21, P20
Port Configuration P27, P26, P25, P24
Port Configuration P31, P30, P29, P28
Port 0 only (virtual port, no action)
Port 1 only (virtual port, no action)
Port 2 only (virtual port, no action)
Port 3 only (virtual port, no action)
Port 4 only (data bit D0. D7-D1 read as 0)
Port 5 only (data bit D0. D7-D1 read as 0)
Port 6 only (data bit D0. D7-D1 read as 0)
Port 7 only (data bit D0. D7-D1 read as 0)
Port 8 only (data bit D0. D7-D1 read as 0)
Port 9 only (data bit D0. D7-D1 read as 0)
Port 10 only (data bit D0. D7-D1 read as 0)
Port 11 only (data bit D0. D7-D1 read as 0)
Port 12 only (data bit D0. D7-D1 read as 0)
Port 13 only (data bit D0. D7-D1 read as 0)
Port 14 only (data bit D0. D7-D1 read as 0)
Port 15 only (data bit D0. D7-D1 read as 0)
Port 16 only (data bit D0. D7-D1 read as 0)
Port 17 only (data bit D0. D7-D1 read as 0)
Port 18 only (data bit D0. D7-D1 read as 0)
Port 19 only (data bit D0. D7-D1 read as 0)
Port 20 only (data bit D0. D7-D1 read as 0)
Port 21 only (data bit D0. D7-D1 read as 0)
Port 22 only (data bit D0. D7-D1 read as 0)
Port 23 only (data bit D0. D7-D1 read as 0)
Port 24 only (data bit D0. D7-D1 read as 0)
Port 25 only (data bit D0. D7-D1 read as 0)
______________________________________________________________________________________ 13
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
Table 5. Register Address Map (continued)
COMMAND ADDRESS
REGISTER
HEX
CODE
D15
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D14
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D13
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D12
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D11
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D10
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D9
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D8
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Port 26 only (data bit D0. D7-D1 read as 0)
Port 27 only (data bit D0. D7-D1 read as 0)
Port 28 only (data bit D0. D7-D1 read as 0)
Port 29 only (data bit D0. D7-D1 read as 0)
Port 30 only (data bit D0. D7-D1 read as 0)
Port 31 only (data bit D0. D7-D1 read as 0)
4 ports 4–7 (data bits D0–D3. D4–D7 read as 0)
5 ports 4–8 (data bits D0–D4. D5–D7 read as 0)
6 ports 4–9 (data bits D0–D5. D6–D7 read as 0)
7 ports 4–10 (data bits D0–D6. D7 reads as 0)
8 ports 4–11 (data bits D0–D7)
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
MAX730
8 ports 5–12 (data bits D0–D7)
8 ports 6–13 (data bits D0–D7)
8 ports 7–14 (data bits D0–D7)
8 ports 8–15 (data bits D0–D7)
8 ports 9–16 (data bits D0–D7)
8 ports 10–17 (data bits D0–D7)
8 ports 11–18 (data bits D0–D7)
8 ports 12–19 (data bits D0–D7)
8 ports 13–20 (data bits D0–D7)
8 ports 14–21 (data bits D0–D7)
8 ports 15–22 (data bits D0–D7)
8 ports 16–23 (data bits D0–D7)
8 ports 17–24 (data bits D0–D7)
8 ports 18–25 (data bits D0–D7)
8 ports 19–26 (data bits D0–D7)
8 ports 20–27 (data bits D0–D7)
8 ports 21–28 (data bits D0–D7)
8 ports 22–29 (data bits D0–D7)
8 ports 23–30 (data bits D0–D7)
8 ports 24–31 (data bits D0–D7)
7 ports 25–31 (data bits D0–D6. D7 reads as 0)
6 ports 26–31 (data bits D0–D5. D6–D7 read as 0)
5 ports 27–31 (data bits D0–D4. D5–D7 read as 0)
4 ports 28–31 (data bits D0–D3. D4–D7 read as 0)
3 ports 29–31 (data bits D0–D2. D3–D7 read as 0)
2 ports 30–31 (data bits D0–D1. D2–D7 read as 0)
1 port 31 only (data bits D0. D1–D7 read as 0)
Note: Unused bits read as zero.
14 ______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
MAX730
Table 6. Power-Up Configuration
ADDRESS
CODE
(HEX)
REGISTER DATA
REGISTER
FUNCTION
POWER-UP CONDITION
D7 D6
D5 D4
D3
D2 D1
D0
Port Register
Bits 4 to 31
0x24 to
0x3F
GPIO Output Low
X
X
X
X
X
X
X
0
Configuration
Register
Shutdown Enabled
Transition Detection Disabled
0x04
0
0
X
X
X
X
X
0
Input Mask
Register
All Clear (Masked Off)
0x06
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
X
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Port
Configuration
P7, P6, P5, P4: GPIO Inputs without Pullup
P11, P10, P9, P8: GPIO Inputs without Pullup
P15, P14, P13, P12: GPIO Inputs without Pullup
P19, P18, P17, P16: GPIO Inputs without Pullup
P23, P22, P21, P20: GPIO Inputs without Pullup
P27, P26, P25, P24: GPIO Inputs without Pullup
P31, P30, P29, P28: GPIO Inputs without Pullup
Port
Configuration
Port
Configuration
Port
Configuration
Port
Configuration
Port
Configuration
Port
Configuration
X = unused bits; if read, zero results.
______________________________________________________________________________________ 15
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
Table 7. Configuration Register Format
REGISTER DATA
ADDRESS CODE
(HEX)
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
Configuration Register
0x04
M
0
X
X
X
X
X
S
Table 8. Shutdown Control (S Data Bit D0) Format
MAX730
REGISTER DATA
ADDRESS CODE
FUNCTION
(HEX)
D7
M
D6
0
D5
X
D4
X
D3
X
D2
X
D1
X
D0
0
Shutdown
0x04
0x04
Normal Operation
M
0
X
X
X
X
X
1
Table 9. Transition Detection Control (M Data Bit D7) Format
REGISTER DATA
ADDRESS CODE
(HEX)
FUNCTION
D7
0
D6
0
D5
X
D4
X
D3
X
D2
X
D1
X
D0
S
Disabled
Enabled
0x04
0x04
1
0
X
X
X
X
X
S
Table 10. Transition Detection Mask Register
REGISTER
REGISTER DATA
READ/
WRITE
FUNCTION
ADDRESS
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
Port
30
mask
Port
29
mask
Port
28
mask
Port
27
mask
Port
26
mask
Port
25
mask
Port
24
mask
Read
Write
INT Status*
Unchanged
Mask
Register
0x06
*INT is automatically cleared after it is read.
16 ______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
MAX730
GPIO INPUT
GPIO IN
CONDITIONING
GPIO/PORT
GPIO/PORT OUT
OUTPUT LATCH
INT STATUS STORED AS MSB OF MASK REGISTER
P31
CLOCK PULSE AFTER EACH READ ACCESS TO MASK REGISTER
R
S
INT
OUTPUT LATCH
CONFIGURATION REGISTER M BIT = 1
GPIO IN
GPIO INPUT
D
D
Q
Q
CONDITIONING
P30
P29
GPIO/PORT OUT
MASK REGISTER BIT 6
MASK REGISTER BIT 5
GPIO/PORT OUTPUT LATCH
GPIO IN
GPIO INPUT
CONDITIONING
GPIO/PORT OUT
GPIO/PORT OUTPUT LATCH
GPIO IN
GPIO INPUT
CONDITIONING
D
D
Q
Q
P28
P27
GPIO/PORT OUT
MASK REGISTER BIT 4
GPIO/PORT OUTPUT LATCH
GPIO IN
GPIO INPUT
CONDITIONING
OR
MASK REGISTER BIT 3
GPIO/PORT OUT
GPIO/PORT OUTPUT LATCH
GPIO IN
GPIO INPUT
CONDITIONING
D
D
Q
Q
P26
P25
GPIO/PORT OUT
MASK REGISTER BIT 2
MASK REGISTER BIT 1
GPIO/PORT OUTPUT LATCH
GPIO IN
GPIO INPUT
CONDITIONING
GPIO/PORT OUT
GPIO/PORT OUTPUT LATCH
GPIO IN
GPIO INPUT
CONDITIONING
D
Q
P24
GPIO/PORT OUT
MASK REGISTER LSB
GPIO/PORT OUTPUT LATCH
CLOCK PULSE WHEN WRITING CONFIGURATION REGISTER WITH M BIT SET
Figure 10. Maskable GPIO Ports P24 to P31
______________________________________________________________________________________ 17
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
Pin Configurations (continued)
TOP VIEW
ISET
GND
GND
AD0
P8
1
2
3
4
5
6
7
8
9
36 V+
35 AD1
34 SCL
33 SDA
32 P4
31
32
33
34
35
36
37
38
39
40
N.C.
SDA
SCL
AD1
V+
20 N.C.
P25
18 P24
17
MAX730
19
P23
16 P22
15 P21
14 P20
13 P19
12 P18
MAX7300
P12
P9
31 P31
30 P5
MAX7300
ISET
GND
GND
GND
P13
P10
P30
29
28 P6
11
AD0
N.C.
P14 10
P11 11
P15 12
P16 13
P17 14
P18 15
P19 16
P20 17
P21 18
27 P29
26 P7
25 P28
24 P27
23 P26
22 P25
21 P24
20 P23
19 P22
40 TQFN-EP
TOP VIEW
SDA 22
SCL 23
AD1 24
14 P24
13 P23
12 P22
36 SSOP
V+ 25
ISET 26
GND 27
GND 28
11 P21
10 P20
MAX7300
9
8
P19
P18
28 TQFN-EP
18 ______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
MAX730
Package Information
Chip Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PROCESS: CMOS
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
28 SSOP
28 TQFN-EP
36 SSOP
A28+1
T2855+6
A36+4
21-0056
21-0140
21-0040
21-0141
90-0095
90-0026
90-0098
90-0055
40 TQFN-EP
T4066+5
______________________________________________________________________________________ 19
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
Updated Ordering Information, Absolute Maximum Ratings, Pin Description, Table
1, and Package Information sections
1
9/11
1, 2, 6, 7, 19
MAX730
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
MAX7301AAX+T
Interface Circuit, CMOS, PDSO36, 0.300 INCH, 0.80 MM PITCH, ROHS COMPLIANT, SSOP-36
MAXIM
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