MAX7301AAX+T [MAXIM]
Interface Circuit, CMOS, PDSO36, 0.300 INCH, 0.80 MM PITCH, ROHS COMPLIANT, SSOP-36;
| 型号： | MAX7301AAX+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Interface Circuit, CMOS, PDSO36, 0.300 INCH, 0.80 MM PITCH, ROHS COMPLIANT, SSOP-36 |
| 文件： | 总17页 (文件大小：277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2438; Rev 6; 4/06
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
28-Port I/O Expander
General Description
Features
The MAX7301 compact, serial-interfaced I/O expander
(or general-purpose I/O (GPIO) peripheral) provides
microprocessors with up to 28 ports. Each port is indi-
vidually user configurable to either a logic input or logic
output.
♦ High-Speed 26MHz SPI-/QSPI-™/MICROWIRE™-
Compatible Serial Interface
♦ 2.5V to 5.5V Operation
♦ -40°C to +125°C Temperature Range
Each port can be configured either as a push-pull logic
output capable of sinking 10mA and sourcing 4.5mA,
or a Schmitt logic input with optional internal pullup.
Seven ports feature configurable transition detection
logic, which generates an interrupt upon change of port
logic level. The MAX7301 is controlled through an
SPI™-compatible 4-wire serial interface.
♦ 20 or 28 I/O Ports, Each Configurable as
Push-Pull Logic Output
Schmitt Logic Input
Schmitt Logic Input with Internal Pullup
♦ 11µA (max) Shutdown Current
♦ Logic Transition Detection for Seven I/O Ports
The MAX7301AAX and MAX7301ATL have 28 ports and
are available in 36-pin SSOP and 40-pin TQFN packages,
respectively. The MAX7301AAI has 20 ports and is avail-
able in a 28-pin SSOP package.
Ordering Information
For a 2-wire I2C-interfaced version, refer to the
MAX7300 data sheet.
PIN-
PACKAGE
PKG
CODE
PART
TEMP RANGE
For a pin-compatible port expander with additional
24mA constant-current LED drive capability, refer to the
MAX6957 data sheet.
MAX7301AAI+
MAX7301AAX+
MAX7301ATL+
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
28 SSOP
36 SSOP
40 TQFN
A28-1
A36-4
T4066-5
+Denotes lead-free package.
Applications
Typical Operating Circuit
White Goods
3V
Automotive
36
32
30
28
26
V+
P4
P5
I/O 4
I/O 5
Gaming Machines
Industrial Controllerss
System Monitoring
47nF
3
2
GND
GND
P6
I/O 6
I/O 7
P7
5
39kΩ
P8
I/O 8
I/O 9
1
ISET
7
P9
9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
I/O 10
I/O 11
MAX7301
35
33
34
4
11
6
CHIP SELECT
CLOCK IN
DATA IN
CS
SCLK
DIN
I/O 12
I/O 13
8
10
12
13
14
15
16
17
18
19
20
DATA OUT
DOUT
I/O 14
I/O 15
31
29
27
25
24
P31
P30
P29
P28
P27
P26
P25
P24
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
23
22
21
I/O 22
I/O 23
SSOP
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
28-Port I/O Expander
ABSOLUTE MAXIMUM RATINGS
(Voltage with respect to GND.)
36-Pin SSOP (derate 11.8ꢀW/°C above +70°C) .........941ꢀW
40-Pin TQFN (derate 26.3ꢀW/°C above +70°C) ....2963.0ꢀW
Operating Teꢀperature Range
V+.............................................................................-0.3V to +6V
All Other Pins................................................-0.3V to (V+ + 0.3V)
P4–P31 Current ................................................................ 30ꢀA
GND Current .....................................................................800ꢀA
(T
, T
) ..................................................-40°C to +125°C
MIN MAX
Junction Teꢀperature......................................................+150°C
Storage Teꢀperature Range.............................-65°C to +150°C
Lead Teꢀperature (soldering, 10s) .................................+300°C
Continuous Power Dissipation (T = +70°C)
A
28-Pin SSOP (derate 9.5ꢀW/°C above +70°C) ...........762ꢀW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Typical Operating Circuit, V+ = 2.5V to 5.5V, T = T
to T
, unless otherwise noted.) (Note 1)
MAX
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
5.5
8
UNITS
Operating Supply Voltage
V+
2.5
V
T
T
T
T
= +25°C
5.5
A
A
A
A
All digital inputs at V+
or GND
Shutdown Supply Current
I
= -40°C to +85°C
10
µA
µA
SHDN
= T
to T
11
MIN
MAX
All ports prograꢀꢀed
as outputs high, no
load, all other inputs
at V+ or GND
= +25°C
180
170
230
Operating Supply Current
(Output High)
I
T = -40°C to +85°C
A
250
270
210
230
240
GPOH
T
A
T
A
= T
to T
MIN MAX
All ports prograꢀꢀed
as outputs low, no
load, all other inputs
at V+ or GND
= +25°C
Operating Supply Current
(Output Low)
I
T = -40°C to +85°C
A
µA
µA
GPOL
T
= T
to T
MIN MAX
A
A
All ports prograꢀꢀed
as inputs without
pullup, ports, and all
other inputs at V+ or
GND
T
= +25°C
110
135
140
145
Operating Supply Current
(Input)
I
T = -40°C to +85°C
A
GPI
T
A
= T
to T
MIN MAX
INPUTS AND OUTPUTS
Logic High Input Voltage
Port Inputs
0.7 ✕
V+
V
V
V
IH
Logic Low Input Voltage
Port Inputs
0.3 ✕
V+
V
IL
GPIO inputs without pullup,
VPORT = V+ to GND
Input Leakage Current
I
, I
IH IL
-100
1
+100
nA
V+ = 2.5V
V+ = 5.5V
12
80
19
120
0.3
30
GPIO Input Internal Pullup to V+
Hysteresis Voltage GPIO Inputs
I
µA
V
PU
180
∆V
I
GPIO outputs, I
= 2ꢀA,
= 1ꢀA,
V+ -
0.7
SOURCE
SOURCE
T
A
= -40°C to +85°C
Output High Voltage
V
V
OH
GPIO outputs, I
= T to T
V+ -
0.7
T
A
(Note 2)
MIN
MAX
2
_______________________________________________________________________________________
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
28-Port I/O Expander
ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuit, V+ = 2.5V to 5.5V, T = T
to T
, unless otherwise noted.) (Note 1)
MAX
A
MIN
PARAMETER
Port Sink Current
SYMBOL
CONDITIONS
MIN
TYP
10
MAX
18
UNITS
ꢀA
I
V
= 0.6V
2
2.75
1.6
2
OL
PORT
Output Short-Circuit Current
I
Port configured output low, shorted to V+
11
20.00
ꢀA
OLSC
V+ ≤ 3.3V
Input High-Voltage SCLK, DIN,
CS
V
V
V
IH
V+ > 3.3V
Input Low-Voltage SCLK, DIN,
CS
V
0.6
IL
Input Leakage Current SCLK,
DIN, CS
I , I
IH IL
-50
+50
nA
V+ -
0.5
Output High-Voltage DOUT
Output Low-Voltage DOUT
V
I
= 1.6ꢀA
SOURCE
V
V
OH
V
I = 1.6ꢀA
SINK
0.4
OL
TIMING CHARACTERISTICS (Figure 3)
(V+ = 2.5V to 5.5V, T = T
A
to T
, unless otherwise noted.) (Note 1)
MAX
MIN
PARAMETER
CLK Clock Period
SYMBOL
CONDITIONS
MIN
38.4
19
TYP
MAX
UNITS
ns
t
CP
CH
CLK Pulse Width High
CLK Pulse Width Low
t
ns
t
19
ns
CL
CS Fall to SCLK Rise Setup Tiꢀe
CLK Rise to CS Rise Hold Tiꢀe
DIN Setup Tiꢀe
t
9.5
0
ns
CSS
CSH
t
ns
t
9.5
0
ns
DS
DH
DO
DIN Hold Tiꢀe
t
ns
Output Data Propagation Delay
Miniꢀuꢀ CS Pulse High
t
C
= 25pF
21
ns
LOAD
t
19
ns
CSW
Note 1: All paraꢀeters tested at T = +25°C. Specifications over teꢀperature are guaranteed by design.
A
Note 2: Guaranteed by design.
_______________________________________________________________________________________
3
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
28-Port I/O Expander
__________________________________________Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
OPERATING SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
OPERATING SUPPLY CURRENT
vs. V+ (OUTPUTS UNLOADED)
0.40
8
7
6
5
4
3
1.0
V+ = 2.5V TO 5.5V
NO LOAD
0.36
0.32
V+ = 5.5V
0.28
0.24
0.20
0.16
0.12
0.08
0.04
0
ALL PORTS
OUTPUT (0)
ALL PORTS
OUTPUT (1)
ALL PORTS OUTPUT (1)
ALL PORTS OUTPUT (0)
V+ = 2.5V
V+ = 3.3V
ALL PORTS INPUT
(PULLUPS DISABLED)
ALL PORTS INPUT HIGH
0.1
-40.0 -12.5 15.0 42.5 70.0 97.5 125.0
-40.0 -12.5 15.0 42.5 70.0 97.5 125.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V+ (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
GPO SINK CURRENT vs. TEMPERATURE
(OUTPUT = 0)
GPO SOURCE CURRENT vs. TEMPERATURE
(OUTPUT = 1)
18
16
14
12
10
8
9
8
7
6
5
4
3
2
V+ = 2.5V TO 5.5V, V
= 0.6V
V
= 1.4
PORT
PORT
V+ = 5.5V
V+ = 3.3V
V+ = 2.5V
6
4
2
-40.0 -12.5 15.0 42.5 70.0 97.5 125.0
-40.0 -12.5 15.0 42.5 70.0 97.5 125.0
TEMPERATURE (°C)
TEMPERATURE (°C)
GPO SHORT-CIRCUIT CURRENT
vs. TEMPERATURE
GPI PULLUP CURRENT
vs. TEMPERATURE
1000
100
10
100
10
1
V+ = 5.5V
GPO = 0, PORT
SHORTED TO V+
V+ = 3.3V
V+ = 2.5V
GPO = 1, PORT
SHORTED TO GND
-40.0 -12.5 15.0 42.5 70.0 97.5 125.0
-40.0 -12.5 15.0 42.5 70.0 97.5 125.0
TEMPERATURE (°C)
TEMPERATURE (°C)
4
_______________________________________________________________________________________
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
28-Port I/O Expander
Pin Description
PIN
NAME
FUNCTION
to GND through a resistor (R
36 SSOP
28 SSOP
TQFN
Bias Current Setting. Connect I
39kΩ to 120kΩ.
) value of
ISET
SET
1
1
36
ISET
2, 3
4
2, 3
4
37, 38, 39
40
GND
Ground
DOUT
4-Wire Interface Serial Data Output Port
I/O Ports. P12 to P31 can be configured as push-pull outputs, CMOS logic
inputs, or CMOS logic inputs with weak pullup resistor.
—
5–24
—
P12–P31
P4–P31
1–10,
12–19,
21–30
I/O Ports. P4 to P31 can be configured as push-pull outputs, CMOS logic
inputs, or CMOS logic inputs with weak pullup resistor.
5–32
—
—
33
34
35
36
—
25
26
27
28
11, 20, 31
N.C.
SCLK
DIN
CS
No Connection. Not internally connected.
32
33
34
35
4-Wire Interface Serial Clock Input Port
4-Wire Interface Serial Data Input Port
4-Wire Interface Chip-Select Input, Active Low
Positive Supply Voltage. Bypass V+ to GND with a ꢀiniꢀuꢀ 0.047µF
V+
Exposed
Pad
—
—
PAD
Exposed Pad on Package Underside. Connect to GND.
quiescent supply current rises, although there is no
Detailed Description
daꢀage to the part.
The MAX7301 GPIO peripheral provides up to 28 I/O
ports, P4 to P31, controlled through an SPI-coꢀpatible
serial interface. The ports can be configured to any
coꢀbination of logic inputs and logic outputs, and
default to logic inputs on power-up.
Register Control of I/O Ports
Across Multiple Drivers
The MAX7301 offers 20 or 28 I/O ports, depending on
package choice.
Figure 1 is the MAX7301 functional diagraꢀ. Any I/O
port can be configured as a push-pull output (sinking
10ꢀA, sourcing 4.5ꢀA), or a Schꢀitt-trigger logic
input. Each input has an individually selectable internal
pullup resistor. Additionally, transition detection allows
seven ports (P24 through P30) to be ꢀonitored in any
ꢀaskable coꢀbination for changes in their logic status.
A detected transition is flagged through an interrupt pin
(port P31).
Two addressing ꢀethods are available. Any single port
(bit) can be written (set/cleared) at once; or, any
sequence of eight ports can be written (set/cleared) in
any coꢀbination at once. There are no boundaries; it is
equally acceptable to write P0 through P7, P1 through
P8, or P31 through P38 (P32 through P38 are nonexis-
tent, so the instructions to these bits are ignored).
Shutdown
When the MAX7301 is in shutdown ꢀode, all ports are
forced to inputs (which can be read), and the pullup
current sources are turned off. Data in the port and
control registers reꢀain unaltered so port configuration
and output levels are restored when the MAX7301 is
taken out of shutdown. The display driver can still be
prograꢀꢀed while in shutdown ꢀode. For ꢀiniꢀuꢀ
supply current in shutdown ꢀode, logic inputs should
be at GND or V+ potential. Shutdown ꢀode is exited by
setting the S bit in the configuration register (Table 6).
The port configuration registers set the 28 ports, P4 to
P31, individually as GPIO. A pair of bits in registers
0x09 through 0x0F sets each port’s configuration
(Tables 1 and 2).
The 36-pin MAX7301AAX and 40-pin MAX7301ATL
have 28 ports, P4 to P31. The 28-pin MAX7301AAI is
offered in 20 ports, P12 to P31. The eight unused ports
should be configured as outputs on power-up by writ-
ing 0x55 to registers 0x09 and 0x0A. If this is not done,
the eight unused ports reꢀain as floating inputs and
_______________________________________________________________________________________
5
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
28-Port I/O Expander
Table 1. Port Configuration Map
REGISTER DATA
D4 D3
ADDRESS
CODE (HEX)
REGISTER
D7
D6
D5
D2
D1
D0
Port Configuration for P7, P6, P5, P4
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
P7
P6
P5
P4
Port Configuration for P11, P10, P9, P8
Port Configuration for P15, P14, P13, P12
Port Configuration for P19, P18, P17, P16
Port Configuration for P23, P22, P21, P20
Port Configuration for P27, P26, P25, P24
Port Configuration for P31, P30, P29, P28
P11
P15
P19
P23
P27
P31
P10
P14
P18
P22
P26
P30
P9
P8
P13
P17
P21
P25
P29
P12
P16
P20
P24
P28
Table 2. Port Configuration Matrix
PORT
CONFIGURATION
BIT PAIR
PORT
REGISTER
(0x20–0x5F)
ADDRESS
CODE (HEX)
MODE
FUNCTION
PIN BEHAVIOR
(0xA0–0xDF)
UPPER
LOWER
DO NOT USE THIS SETTING
0x09 to 0x0F
0x09 to 0x0F
0
0
Register bit = 0
Register bit = 1
Active-low logic output
Active-high logic output
Output
GPIO Output
0
1
GPIO Input
Without Pullup
Input
Input
Schꢀitt logic input
0x09 to 0x0F
0x09 to 0x0F
1
1
0
1
Register bit =
input logic level
GPIO Input with Pullup
Schꢀitt logic input with pullup
address (Table 3), and the second byte, D7 through
D0, is the data byte (Table 4 through Table 8).
Serial Interface
The MAX7301 coꢀꢀunicates through an SPI-coꢀpati-
ble 4-wire serial interface. The interface has three
inputs, Clock (SCLK), Chip Select (CS), and Data In
(DIN), and one output, Data Out (DOUT). CS ꢀust be
low to clock data into or out of the device, and DIN
ꢀust be stable when saꢀpled on the rising edge of
SCLK. DOUT provides a copy of the bit that was input
15.5 clocks earlier, or upon a query it outputs internal
register data, and is stable on the rising edge of SCLK.
Note that the SPI protocol expects DOUT to be high
impedance when the MAX7301 is not being
accessed; DOUT on the MAX7301 is never high
impedance. See www.maxim-ic.com/an 1879 for
ways to convert DOUT to tri-state, if required.
Connecting Multiple MAX7301s
to the 4-Wire Bus
Multiple MAX7301s ꢀay be daisy-chained by connect-
ing the DOUT of one device to the DIN of the next, and
driving SCLK and CS lines in parallel (Figure 3). Data at
DIN propagates through the internal shift registers and
appears at DOUT 15.5 clock cycles later, clocked out
on the falling edge of SCLK. When sending coꢀꢀands
to ꢀultiple MAX7301s, all devices are accessed at the
saꢀe tiꢀe. An access requires (16 ✕ n) clock cycles,
where n is the nuꢀber of MAX7301s connected togeth-
er. To update just one device in a daisy-chain, the user
can send the No-Op coꢀꢀand (0x00) to the others.
SCLK and DIN ꢀay be used to transꢀit data to other
peripherals, so the MAX7301 ignores all activity on
SCLK and DIN except between the fall and subsequent
rise of CS.
Writing Device Registers
The MAX7301 contains a 16-bit shift register into which
DIN data are clocked on the rising edge of SCLK, when
CS is low. When CS is high, transitions on SCLK have
no effect. When CS goes high, the 16 bits in the Shift
register are parallel loaded into a 16-bit latch. The 16
bits in the latch are then decoded and executed.
Control and Operation Using the
4-Wire Interface
Controlling the MAX7301 requires sending a 16-bit
word. The first byte, D15 through D8, is the coꢀꢀand
6
_______________________________________________________________________________________
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
28-Port I/O Expander
CONFIGURATION
PORT REGISTERS
MASK REGISTER
CONFIGURATION
REGISTERS
PORT CHANGE
DETECTOR
GPIO
P4 TO P31
DATA
CE
R/W
8
R/W
GPIO DATA
8
COMMAND
REGISTER DECODE
8
8
DATA BYTE
COMMAND BYTE
CS
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
D8
D8
D9
D9
D10
D10
D11
D11
D12
D12
D13
D13
D14
D14
D15
D15
DOUT
DIN
SCLK
Figure 1. MAX7301 Functional Diagram
The MAX7301 is written to using the following
sequence:
Reading Device Registers
Any register data within the MAX7301 ꢀay be read by
sending a logic high to bit D15. The sequence is:
1) Take SCLK low.
1) Take SCLK low.
2) Take CS low. This enables the internal 16-bit shift
register.
2) Take CS low (this enables the internal 16-bit Shift
register).
3) Clock 16 bits of data into DIN—D15 first, D0 last—
observing the setup and hold tiꢀes (bit D15 is low,
indicating a write coꢀꢀand).
3) Clock 16 bits of data into DIN—D15 first to D0 last.
D15 is high, indicating a read coꢀꢀand and bits
D14 through D8 containing the address of the regis-
ter to be read. Bits D7–D0 contain duꢀꢀy data,
which is discarded.
4) Take CS high (either while SCLK is still high after
clocking in the last data bit, or after taking SCLK
low).
4) Take CS high (either while SCLK is still high after
clocking in the last data bit, or after taking SCLK
low), positions D7 through D0 in the Shift register
are now loaded with the register data addressed by
bits D1 through D8.
5) Take SCLK low (if not already low).
Figure 4 shows a write operation when 16 bits are
transꢀitted.
It is acceptable to clock ꢀore than 16 bits into the
MAX7301 between taking CS low and taking CS high
again. In this case, only the last 16 bits clocked into the
MAX7301 are retained.
5) Take SCLK low (if not already low).
6) Issue another read or write coꢀꢀand (which can
be a No-Op), and exaꢀine the bit streaꢀ at DOUT;
the second 8 bits are the contents of the register
addressed by bits D1 through D8 in step 3.
_______________________________________________________________________________________
7
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
28-Port I/O Expander
CS
t
t
t
CSH
CSS
CH
t
t
CL
CSH
SCLK
t
DS
t
DH
DIN
t
DO
DOUT
Figure 2. 4-Wire Interface
the configuration register is written with the M bit set,
the MAX7301 updates an internal 7-bit snapshot regis-
ter, which holds the coꢀparison copy of the logic states
of ports P24 through P30. The update action occurs
regardless of the previous state of the M bit, so that it is
not necessary to clear the M bit and then set it again to
update the snapshot register.
Initial Power-Up
On initial power-up, all control registers are reset, and
the MAX7301 enters shutdown ꢀode (Table 4).
Transition (Port Data Change) Detection
Port transition detection allows any coꢀbination of the
seven ports P24–P30 to be continuously ꢀonitored for
changes in their logic status (Figure 5). A detected
change is flagged on port P31, which is used as an
active-high interrupt output (INT). Note that the
MAX7301 does not identify which specific port(s)
caused the interrupt, but provides an alert that one or
ꢀore port levels have changed.
When the configuration register is written with the M bit
set, transition detection is enabled and reꢀains
enabled until either the configuration register is written
with the M bit clear, or a transition is detected. The INT
output port P31 goes low, if it was not already low.
Once transition detection is enabled, the MAX7301
continuously coꢀpares the snapshot register against
the changing states of P24 through P31. If a change on
any of the ꢀonitored ports is detected, even for a short
tiꢀe (like a pulse), INT output port P31 is latched high.
The INT output is not cleared if ꢀore changes occur or
if the data pattern returns to its original snapshot condi-
tion. The only way to clear INT is to access (read or
write) the transition detection ꢀask register (Table 8).
The ꢀask register contains 7 ꢀask bits that select
which of the seven ports, P24–P30 are to be ꢀonitored
(Table 8). Set the appropriate ꢀask bit to enable that
port for transition detect. Clear the ꢀask bit if transitions
on that port are to be ignored. Transition detection
works regardless of whether the port being ꢀonitored is
set to input or output, but generally it is not particularly
useful to enable transition detection for outputs.
Port P31 ꢀust be configured as an output in order to
work as the interrupt output INT when transition detec-
tion is used. Port P31 is set as output by writing bit D7
= 0 and bit D6 = 1 to the port configuration register
(Table 1).
Transition detection is a one-shot event. When INT has
been cleared after responding to a transition event,
transition detection is autoꢀatically disabled, even
though the M bit in the configuration register reꢀains
set (unless cleared by the user). Reenable transition
detection by writing the configuration register with the
M bit set, to take a new snapshot of the seven ports
P24 to P30.
To use transition detection, first set up the ꢀask regis-
ter and configure port P31 as an output, as described
above. Then enable transition detection by setting the
M bit in the configuration register (Table 7). Whenever
8
_______________________________________________________________________________________
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
28-Port I/O Expander
MICROCONTROLLER
SERIAL-DATA INPUT
CS
CS
SERIAL CS OUTPUT
SERIA-CLOCK OUTPUT
SERIAL-DATA OUTPUT
CS
MAX7301
MAX7301
MAX7301
SCLK
SCLK
DIN
SCLK
DIN
DOUT
DOUT
DOUT
DIN
Figure 3. Daisy-Chain Arrangement for Controlling Multiple MAX7301s
CS
SCLK
D15
= 0
DIN
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DOUT
D15 = 0
.
Figure 4. Transmission of a16-Bit Write to the MAX7301
External Component R
ringing for ꢀoderately long interface runs. Use line-
iꢀpedance ꢀatching terꢀinations when ꢀaking con-
nections between boards.
ISET
, to set
The MAX7301 uses an external resistor, R
ISET
internal biasing. Use a resistor value of 39kΩ.
Applications Information
PC Board Layout Considerations
For the TQFN version, connect the underside exposed
pad to GND. Ensure that all the MAX7301 GND connec-
tions are used. A ground plane is not necessary, but
ꢀay be useful to reduce supply iꢀpedance if the
MAX7301 outputs are to be heavily loaded. Keep the
Low-Voltage Operation
The MAX7301 operates down to 2V supply voltage
(although the sourcing and sinking currents are not
guaranteed), providing that the MAX7301 is powered
up initially to at least 2.5V to trigger the device’s internal
reset, and also that the serial interface is constrained to
10Mbps.
track length froꢀ the ISET pin to the R
resistor as
ISET
short as possible, and take the GND end of the resistor
either to the ground plane or directly to the ground pins.
SPI Routing Considerations
The MAX7301’s SPI interface is guaranteed to operate
at 26Mbps on a 2.5V supply, and on a 5V supply typi-
cally operates at 50Mbps. This ꢀeans that transꢀission
line issues should be considered when the interface
connections are longer than 100ꢀꢀ, particularly with
higher supply voltages. Ringing ꢀanifests itself as
coꢀꢀunication issues, often interꢀittent, typically due
to double clocking due to ringing at the SCLK input. Fit
a 1kΩ to 10kΩ parallel terꢀination resistor to either
GND or V+ at the DIN, SCLK, and CS input to daꢀp
Power-Supply Considerations
The MAX7301 operates with power-supply voltages of
2.5V to 5.5V. Bypass the power supply to GND with a
0.047µF capacitor as close to the device as possible.
Add a 1µF capacitor if the MAX7301 is far away froꢀ
the board’s input bulk decoupling capacitor.
Chip Information
TRANSISTOR COUNT: 30,316
PROCESS: CMOS
_______________________________________________________________________________________
9
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
28-Port I/O Expander
Table 3. Register Address Map
COMMAND ADDRESS
REGISTER
HEX
CODE
D15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D13
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
D11
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
D10
0
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
D9
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D8
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
No-Op
0x00
0x04
0x06
0x07
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
Configuration
Transition Detect Mask
Factory Reserved. Do not write to this.
Port Configuration P7, P6, P5, P4
Port Configuration P11, P10, P9, P8
Port Configuration P15, P14, P13, P12
Port Configuration P19, P18, P17, P16
Port Configuration P23, P22, P21, P20
Port Configuration P27, P26, P25, P24
Port Configuration P31, P30, P29, P28
Port 0 only (virtual port, no action)
Port 1 only (virtual port, no action)
Port 2 only (virtual port, no action)
Port 3 only (virtual port, no action)
Port 4 only (data bit D0. D7–D1 read as 0)
Port 5 only (data bit D0. D7–D1 read as 0)
Port 6 only (data bit D0. D7–D1 read as 0)
Port 7 only (data bit D0. D7–D1 read as 0)
Port 8 only (data bit D0. D7–D1 read as 0)
Port 9 only (data bit D0. D7–D1 read as 0)
Port 10 only (data bit D0. D7–D1 read as 0)
Port 11 only (data bit D0. D7–D1 read as 0)
Port 12 only (data bit D0. D7–D1 read as 0)
Port 13 only (data bit D0. D7–D1 read as 0)
Port 14 only (data bit D0. D7–D1 read as 0)
Port 15 only (data bit D0. D7–D1 read as 0)
Port 16 only (data bit D0. D7–D1 read as 0)
Port 17 only (data bit D0. D7–D1 read as 0)
Port 18 only (data bit D0. D7–D1 read as 0)
Port 19 only (data bit D0. D7–D1 read as 0)
Port 20 only (data bit D0. D7–D1 read as 0)
Port 21 only (data bit D0. D7–D1 read as 0)
Port 22 only (data bit D0. D7–D1 read as 0)
Port 23 only (data bit D0. D7–D1 read as 0)
Port 24 only (data bit D0. D7–D1 read as 0)
Port 25 only (data bit D0. D7–D1 read as 0)
10 ______________________________________________________________________________________
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
28-Port I/O Expander
Table 3. Register Address Map (continued)
COMMAND ADDRESS
HEX
CODE
REGISTER
D15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D14
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D13
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D12
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D11
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D10
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D9
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D8
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Port 26 only (data bit D0. D7–D1 read as 0)
Port 27 only (data bit D0. D7–D1 read as 0)
Port 28 only (data bit D0. D7–D1 read as 0)
Port 29 only (data bit D0. D7–D1 read as 0)
Port 30 only (data bit D0. D7–D1 read as 0)
Port 31 only (data bit D0. D7–D1 read as 0)
4 ports 4–7 (data bits D0–D3. D4–D7 read as 0)
5 ports 4–8 (data bits D0–D4. D5–D7 read as 0)
6 ports 4–9 (data bits D0–D5. D6–D7 read as 0)
7 ports 4–10 (data bits D0–D6. D7 reads as 0)
8 ports 4–11 (data bits D0–D7)
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
8 ports 5–12 (data bits D0–D7)
8 ports 6–13 (data bits D0–D7)
8 ports 7–14 (data bits D0–D7)
8 ports 8–15 (data bits D0–D7)
8 ports 9–16 (data bits D0–D7)
8 ports 10–17 (data bits D0–D7)
8 ports 11–18 (data bits D0–D7)
8 ports 12–19 (data bits D0–D7)
8 ports 13–20 (data bits D0–D7)
8 ports 14–21 (data bits D0–D7)
8 ports 15–22 (data bits D0–D7)
8 ports 16–23 (data bits D0–D7)
8 ports 17–24 (data bits D0–D7)
8 ports 18–25 (data bits D0–D7)
8 ports 19–26 (data bits D0–D7)
8 ports 20–27 (data bits D0–D7)
8 ports 21–28 (data bits D0–D7)
8 ports 22–29 (data bits D0–D7)
8 ports 23–30 (data bits D0–D7)
8 ports 24–31 (data bits D0–D7)
7 ports 25–31 (data bits D0–D6. D7 reads as 0)
6 ports 26–31 (data bits D0–D5. D6–D7 read as 0)
5 ports 27–31 (data bits D0–D4. D5–D7 read as 0)
4 ports 28–31 (data bits D0–D3. D4–D7 read as 0)
3 ports 29–31 (data bits D0–D2. D3–D7 read as 0)
2 ports 30–31 (data bits D0–D1. D2–D7 read as 0)
1 port 31 only (data bit D0. D1–D7 read as 0)
Note: Unused bits read as 0.
______________________________________________________________________________________ 11
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
28-Port I/O Expander
GPIO INPUT
GPIO IN
CONDITIONING
GPIO/PORT
GPIO/PORT OUT
OUTPUT LATCH
P31
CLOCK PULSE AFTER EACH READ ACCESS TO MASK REGISTER
R
S
INT
OUTPUT LATCH
CONFIGURATION REGISTER M BIT = SET
GPIO IN
GPIO INPUT
D
D
Q
Q
CONDITIONING
P30
P29
GPIO/PORT OUT
MASK REGISTER BIT 6
MASK REGISTER BIT 5
GPIO/PORT OUTPUT LATCH
GPIO IN
GPIO INPUT
CONDITIONING
GPIO/PORT OUT
GPIO/PORT OUTPUT LATCH
GPIO IN
GPIO INPUT
CONDITIONING
D
D
Q
Q
P28
P27
GPIO/PORT OUT
MASK REGISTER BIT 4
GPIO/PORT OUTPUT LATCH
GPIO IN
GPIO INPUT
CONDITIONING
OR
MASK REGISTER BIT 3
GPIO/PORT OUT
GPIO/PORT OUTPUT LATCH
GPIO IN
GPIO INPUT
CONDITIONING
D
D
Q
Q
P26
P25
GPIO/PORT OUT
MASK REGISTER BIT 2
MASK REGISTER BIT 1
GPIO/PORT OUTPUT LATCH
GPIO IN
GPIO INPUT
CONDITIONING
GPIO/PORT OUT
GPIO/PORT OUTPUT LATCH
GPIO IN
GPIO INPUT
CONDITIONING
D
Q
P24
GPIO/PORT OUT
MASK REGISTER LSB
GPIO/PORT OUTPUT LATCH
CLOCK PULSE WHEN WRITING CONFIGURATION REGISTER WITH M BIT SET
Figure 5. Maskable GPIO Ports P24 Through P31
12 ______________________________________________________________________________________
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
28-Port I/O Expander
Table 4. Power-Up Configuration
REGISTER DATA
REGISTER
FUNCTION
ADDRESS
CODE (HEX)
POWER-UP CONDITION
D7
D6
D5
D4
D3
D2
D1
D0
Port Register
Bits 4 to 31
0x24 to
0x3F
GPIO Output Low
X
X
X
X
X
X
X
0
Configuration
Register
Shutdown Enabled
Transition Detection Disabled
0x04
0x06
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0
X
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
X
0
1
1
1
1
1
1
1
X
0
0
0
0
0
0
0
0
X
0
1
1
1
1
1
1
1
X
0
0
0
0
0
0
0
0
X
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
Input Mask
Register
All Clear (Masked Off)
Port
Configuration
P7, P6, P5, P4: GPIO Inputs Without Pullup
P11, P10, P9, P8: GPIO Inputs Without Pullup
Port
Configuration
Port
Configuration
P15, P14, P13, P12: GPIO Inputs Without
Pullup
Port
Configuration
P19, P18, P17, P16: GPIO Inputs Without
Pullup
Port
Configuration
P23, P22, P21, P20: GPIO Inputs Without
Pullup
Port
Configuration
P27, P26, P25, P24: GPIO Inputs Without
Pullup
Port
Configuration
P31, P30, P29, P28: GPIO Inputs Without
Pullup
X = Unused bits; if read, zero results.
Table 5. Configuration Register Format
REGISTER DATA
ADDRESS CODE
FUNCTION
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
Configuration Register
0x04
M
0
X
X
X
X
X
S
Table 6. Shutdown Control (S Data Bit D0) Format
REGISTER DATA
ADDRESS CODE
FUNCTION
(HEX)
0x04
0x04
D7
M
D6
0
D5
X
D4
X
D3
X
D2
X
D1
X
D0
0
Shutdown
Norꢀal Operation
M
0
X
X
X
X
X
1
______________________________________________________________________________________ 13
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
28-Port I/O Expander
Table 7. Transition Detection Control (M Data Bit D7) Format
REGISTER DATA
ADDRESS CODE
(HEX)
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
Disabled
Enabled
0x04
0x04
0
0
X
X
X
X
X
S
1
0
X
X
X
X
X
S
Table 8. Transition Detection Mask Register
REGISTER
ADDRESS
(HEX)
REGISTER DATA
READ/
WRITE
FUNCTION
D7
0
D6
D5
D4
D3
D2
D1
D0
Port
30
ꢀask
Port
29
Port
28
Port
27
Port
26
ꢀask
Port
25
ꢀask
Port
24
ꢀask
Read
Write
Mask
Register
0x06
Unchanged
ꢀask
ꢀask
ꢀask
14 ______________________________________________________________________________________
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
28-Port I/O Expander
Pin Configurations
TOP VIEW
+
+
30 29 28 27 26 25 24 23 22 21
ISET
GND
GND
DOUT
P8
1
2
3
4
5
6
7
8
9
36 V+
ISET
GND
GND
DOUT
P12
1
2
3
4
5
6
7
8
9
28 V+
35 CS
34 DIN
33 SCLK
32 P4
27 CS
N.C. 31
SCLK 32
DIN 33
CS 34
20
19
18
17
16
15
14
13
12
11
N.C.
P25
P24
P23
P22
P21
P20
P19
P18
N.C.
26 DIN
25 SCLK
24 P31
23 P30
22 P29
21 P28
20 P27
19 P26
18 P25
17 P24
16 P23
15 P22
V+ 35
ISET
36
P12
P9
31 P31
30 P5
P13
MAX7301
GND 37
GND 38
GND 39
MAX7301
P14
MAX7301
P13
P10
29 P30
28 P6
P15
40
DOUT
P16
+
P14 10
P11 11
P15 12
P16 13
P17 14
P18 15
P19 16
P20 17
P21 18
27 P29
26 P7
P17 10
P18 11
P19 12
P20 13
P21 14
1
2
3
4
5
6
7
8
9 10
25 P28
24 P27
23 P26
22 P25
21 P24
20 P23
19 P22
TQFN
28 SSOP
36 SSOP
______________________________________________________________________________________ 15
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
28-Port I/O Expander
Package Information
(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation,
go to www.maxim-ic.com/packages.)
2
1
INCHES
MILLIMETERS
DIM
A
MIN
0.068
MAX
MIN
1.73
0.05
0.25
0.09
MAX
1.99
0.21
0.38
0.20
INCHES
MIN
MAX
MILLIMETERS
MIN
6.07
6.07
7.07
8.07
MAX
6.33
N
0.078
A1
B
D
D
D
D
D
0.239 0.249
0.239 0.249
0.278 0.289
0.317 0.328
14L
0.002 0.008
0.010 0.015
0.004 0.008
6.33 16L
7.33
8.33 24L
20L
C
E
H
D
SEE VARIATIONS
0.205 0.212 5.20
0.0256 BSC
0.397 0.407 10.07 10.33 28L
E
5.38
e
0.65 BSC
H
0.301 0.311 7.65
0.025 0.037 0.63
7.90
0.95
8∞
L
0∞
8∞
0∞
N
A
C
B
L
e
A1
D
NOTES:
1. D&E DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").
3. CONTROLLING DIMENSION: MILLIMETERS.
4. MEETS JEDEC MO150.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, SSOP, 5.3 MM
APPROVAL
DOCUMENT CONTROL NO.
REV.
5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
1
21-0056
C
1
36
INCHES
MILLIMETERS
DIM
A
MIN
MAX
0.104
0.011
0.017
0.013
MIN
2.44
0.10
0.30
0.23
MAX
2.65
0.29
0.44
0.32
0.096
0.004
0.012
0.009
A1
B
C
e
0.0315 BSC
0.80 BSC
E
H
E
0.291
0.398
0.020
0.598
0.299
7.40
10.11
0.51
7.60
10.51
1.02
H
0.414
0.040
0.612
L
D
15.20
15.55
1
TOP VIEW
D
A1
A
C
e
0∞-8∞
B
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 36L SSOP, 0.80 MM PITCH
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0040
E
1
16 ______________________________________________________________________________________
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
28-Port I/O Expander
Package Information (continued)
(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation,
go to www.maxim-ic.com/packages.)
(NE-1) X
e
E
E/2
k
D/2
C
(ND-1) X
e
D
D2
L
D2/2
e
b
E2/2
L
C
L
k
E2
e
L
C
C
L
L
L1
L
L
e
e
A
A1
A2
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
DOCUMENT CONTROL NO.
APPROVAL
REV.
1
F
21-0141
2
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
12. NUMBER OF LEADS SHOWN FOR REFERENCE ONLY.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
DOCUMENT CONTROL NO.
APPROVAL
REV.
2
F
21-0141
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
© 2006 Maxiꢀ Integrated Products
Printed USA
is a registered tradeꢀark of Maxiꢀ Integrated Products, Inc.
相关型号：
MAX7301ATL+T
Interface Circuit, CMOS, 6 X 6 MM, 0.80 MM PITCH, ROHS COMPLIANT, MO-220, TQFN-40
MAXIM
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