MAX7300ANI [MAXIM]
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander; 2线接口， 2.5V至5.5V ， 20端口或28端口I / O扩展器
| 型号： | MAX7300ANI |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander |
| 文件： | 总22页 (文件大小：347K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2413; Rev 1; 2/03
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
General Description
Features
ꢀ 400kbps I2C-Compatible Serial Interface
The MAX7300 compact, serial-interfaced, I/O expan-
sion peripheral provides microprocessors with up to 28
ports. Each port is individually user configurable to
either a logic input or logic output.
ꢀ 2.5V to 5.5V Operation
ꢀ -40°C to +125°C Temperature Range
Each port can be configured as either a push-pull logic
output capable of sinking 10mA and sourcing 4.5mA, or a
Schmitt logic input with optional internal pullup. Seven
ports feature configurable transition detection logic, which
generates an interrupt upon change of port logic level.
The MAX7300 is controlled through an I2C™-compatible
2-wire serial interface, and uses four-level logic to allow
16 I2C addresses from only two select pins.
ꢀ 20 or 28 I/O Ports, Each Configurable as
Push-Pull Logic Output
Schmitt Logic Input
Schmitt Logic Input with Internal Pullup
ꢀ 11µA (max) Shutdown Current
ꢀ Logic Transition Detection for Seven I/O Ports
The MAX7300AAX and MAX7300AGL have 28 ports
and are available in 36-pin SSOP and 40-pin QFN pack-
ages, respectively. The MAX7300AAI and MAX7300ANI
have 20 ports and are available in 28-pin SSOP and 28-
pin DIP packages, respectively.
Ordering Information
PART
TEMP RANGE
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
PIN-PACKAGE
28 DIP
MAX7300ANI
MAX7300AAI
MAX7300AAX
MAX7300AGL
28 SSOP
36 SSOP
40 QFN
Applications
White Goods
Automotive
Industrial Controllers
System Monitoring
Typical Operating Circuit
Pin Configurations
3V
36
3
2
1
32
30
28
26
V+
P4
P5
I/O 4
I/O 5
47nF
TOP VIEW
ISET
GND
GND
AD0
GND
GND
ISET
P6
P7
I/O 6
I/O 7
1
2
3
4
5
6
7
8
9
28 V+
5
39kΩ
P8
I/O 8
27 AD1
26 SCL
25 SDA
24 P31
7
9
P9
I/O 9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
35
11
6
AD1
AD0
SDA
SCL
4
33
34
MAX7300AAX
P12
8
DATA
CLOCK
MAX7300
10
12
13
14
15
16
17
18
19
20
P13
23 P30
22 P29
21 P28
20 P27
19 P26
18 P25
17 P24
16 P23
15 P22
P14
31
29
27
25
24
23
22
21
P31
P30
P29
P28
P27
P26
P25
P24
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
P15
P16
P17 10
P18 11
P19 12
P20 13
P21 14
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
SSOP/DIP
Pin Configurations continued at end of data sheet.
2
I C is a trademark of Philips Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
ABSOLUTE MAXIMUM RATINGS
Voltage (with respect to GND)
Operating Teꢀperature Range
(T to T ) ...............................................-40°C to +125°C
Junction Teꢀperature......................................................+150°C
Storage Teꢀperature Range.............................-65°C to +150°C
Lead Teꢀperature (soldering, 10s) .................................+300°C
V+.............................................................................-0.3V to +6V
SCL, SDA, AD0, AD1................................................-0.3V to +6V
All Other Pins................................................-0.3V to (V+ + 0.3V)
P4–P31 Current ................................................................ 30ꢀA
GND Current .....................................................................800ꢀA
MIN
MAX
Continuous Power Dissipation (T = +70°C)
A
28-Pin PDIP (derate 20.8ꢀW/°C above +70°C).........1667ꢀW
28-Pin SSOP (derate 9.5ꢀW/°C above +70°C) ...........762ꢀW
36-Pin SSOP (derate 11.8ꢀW/°C above +70°C) .........941ꢀW
40-Pin QFN (derate 23.25ꢀW/°C aboveT = +70°C)..1860ꢀW
A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Typical Operating Circuit, V+ = 2.5V to 5.5V, T = T
to T
, unless otherwise noted.) (Note 1)
MAX
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
5.5
8
UNITS
Operating Supply Voltage
V+
2.5
V
T
T
T
= +25°C
5.5
A
I
All digital inputs at
V+ or GND
SHDN
Shutdown Supply Current
Operating Supply Current
= -40°C to +85°C
10
µA
µA
A
to T
11
MIN
MAX
T
T
= +25°C
180
170
110
240
260
A
A
All ports prograꢀꢀed
as outputs high, no
load, all other inputs
at V+ or GND
= -40°C to +85°C
I
GPOH
T
T
T
to T
280
210
230
MIN
MAX
= +25°C
A
A
All ports prograꢀꢀed
as outputs low, no
load, all other inputs
at V+ or GND
= -40°C to +85°C
Operating Supply Current
I
µA
µA
GPOL
T
T
T
to T
240
135
140
MIN
MAX
All ports prograꢀꢀed
as inputs without
pullup, ports, and all
other inputs at V+ or
GND
= +25°C
A
A
= -40°C to +85°C
Operating Supply Current
I
GPI
T
to T
145
MIN
MAX
INPUTS AND OUTPUTS
Logic High Input Voltage
Port Inputs
0.7 x
V+
V
V
V
IH
Logic Low Input Voltage
Port Inputs
0.3 x
V+
V
IL
GPIO inputs without pullup,
= V+ to GND
Input Leakage Current
I , I
IH IL
-100
1
+100
nA
V
PORT
V+ = 2.5V
V+ = 5.5V
12
80
19
120
0.3
30
GPIO Input Internal Pullup to V+
Hysteresis Voltage GPIO Inputs
I
µA
V
PU
180
∆V
I
2
_______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuit, V+ = 2.5V to 5.5V, T = T
to T
, unless otherwise noted.) (Note 1)
MAX
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GPIO outputs, I
= 2ꢀA,
V+ -
0.7
SOURCE
T
= -40°C to +85°C
A
Output High Voltage
V
V
OH
GPIO outputs, I
= 1ꢀA,
V+ -
0.7
SOURCE
T
= T
to T
(Note 2)
MAX
A
MIN
Port Sink Current
I
V
= 0.6V
2
10
11
18
20
ꢀA
ꢀA
OL
PORT
Output Short-Circuit Current
I
Port configured output low, shorted to V+
2.75
OLSC
Input High-Voltage SDA, SCL,
AD0, AD1
0.7 x
V+
V
V
V
IH
Input Low-Voltage SDA, SCL,
AD0, AD1
0.3 x
V+
V
IL
Input Leakage Current SDA, SCL
Input Capacitance
I
, I
-50
+50
10
nA
pF
V
IH IL
(Note 2)
= 6ꢀA
Output Low-Voltage SDA
V
I
0.4
OL
SINK
TIMING CHARACTERISTICS (Figure 2)
(V+ = 2.5V to 5.5V, T = T
A
to T
, unless otherwise noted.) (Note 1)
MAX
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Clock Frequency
f
400
kHz
SCL
Bus Free Tiꢀe Between a STOP
and a START Condition
t
1.3
0.6
0.6
µs
µs
µs
BUF
Hold Tiꢀe (Repeated) START
Condition
t
HD, STA
Repeated START Condition
Setup Tiꢀe
t
SU, STA
STOP Condition Setup Tiꢀe
Data Hold Tiꢀe
t
0.6
15
µs
ns
ns
µs
µs
SU, STO
t
(Note 3)
900
HD, DAT
Data Setup Tiꢀe
t
100
1.3
0.7
SU, DAT
SCL Clock Low Period
SCL Clock High Period
t
LOW
t
HIGH
Rise Tiꢀe of Both SDA and SCL
Signals, Receiving
20 +
t
(Notes 2, 4)
(Notes 2, 4)
300
300
ns
ns
R
0.1C
b
Fall Tiꢀe of Both SDA and SCL
Signals, Receiving
20 +
0.1C
t
F
b
20 +
0.1C
Fall Tiꢀe of SDA Transꢀitting
t
(Notes 2, 5)
(Notes 2, 6)
(Note 2)
250
50
ns
ns
pF
F,TX
b
Pulse Width of Spike Suppressed
t
SP
0
Capacitive Load for Each Bus
Line
C
400
b
_______________________________________________________________________________________
3
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
TIMING CHARACTERISTICS (Figure 2) (continued)
(V+ = 2.5V to 5.5V, T = T
to T
, unless otherwise noted.) (Note 1)
MAX
A
MIN
Note 1: All paraꢀeters tested at T = +25°C. Specifications over teꢀperature are guaranteed by design.
A
Note 2: Guaranteed by design.
Note 3: A ꢀaster device ꢀust provide a hold tiꢀe of at least 300ns for the SDA signal (referred to V of the SCL signal) in order to
IL
bridge the undefined region of SCL’s falling edge.
Note 4: C = total capacitance of one bus line in pF. t and t ꢀeasured between 0.3V+ and 0.7V+.
b
R
F
Note 5: I
≤ 6ꢀA. C = total capacitance of one bus line in pF. t and t ꢀeasured between 0.3V+ and 0.7V+.
SINK
b R F
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
__________________________________________Typical Operating Characteristics
(R
= 39kΩ, T = +25°C, unless otherwise noted.)
ISET
A
OPERATING SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
OPERATING SUPPLY CURRENT vs. V+
(OUTPUTS UNLOADED)
1
0.40
8
V+ = 2.5V TO 5.5V
NO LOAD
0.36
0.32
0.28
0.24
0.20
0.16
0.12
0.08
0.04
0
V+ = 5.5V
7
ALL PORTS
V+ = 3.3V
ALL PORTS
OUTPUT (0)
OUTPUT (1)
6
ALL PORTS OUTPUT (1)
ALL PORTS OUTPUT (0)
5
V+ = 2.5V
4
ALL PORTS INPUT
(PULLUPS DISABLED)
ALL PORTS INPUT HIGH
0.1
3
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V+ (V)
-40.0 -12.5 15.0 42.5 70.0 97.5 125.0
-40.0 -12.5 15.0 42.5 70.0 97.5 125.0
TEMPERATURE (°C)
TEMPERATURE (°C)
4
_______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
Typical Operating Characteristics (continued)
(R
= 39kΩ, T = +25°C, unless otherwise noted.)
A
ISET
GPO SOURCE CURRENT vs. TEMPERATURE
(OUTPUT = 1)
GPO SINK CURRENT vs. TEMPERATURE
(OUTPUT = 0)
9
8
7
6
5
4
3
2
18
16
14
12
10
8
V
= 1.4V
PORT
V+ = 2.5V TO 5.5V, V
= 0.6V
PORT
V+ = 5.5V
V+ = 3.3V
V+ = 2.5V
6
4
2
-40.0 -12.5 15.0 42.5 70.0 97.5 125.0
-40.0 -12.5 15.0 42.5 70.0 97.5 125.0
TEMPERATURE (°C)
TEMPERATURE (°C)
GPO SHORT-CIRCUIT CURRENT
vs. TEMPERATURE
GPI PULLUP CURRENT
vs. TEMPERATURE
100
10
1
1000
100
10
V+ = 5.5V
GPO = 0, PORT
SHORTED TO V+
V+ = 3.3V
V+ = 2.5V
GPO = 1, PORT
SHORTED TO GND
-40.0 -12.5 15.0 42.5 70.0 97.5 125.0
-40.0 -12.5 15.0 42.5 70.0 97.5 125.0
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
Pin Description
PIN
NAME
FUNCTION
QFN
SSOP/DIP
SSOP
Bias Current Setting. Connect ISET to GND through a resistor (R
value of 39kΩ to 120kΩ.
)
ISET
1
2, 3
4
1
2, 3
4
36
ISET
GND
AD0
37, 38, 39
Ground
Address Input 0. Sets device slave address. Connect to either GND,
V+, SCL, SDA to give four logic coꢀbinations. See Table 3.
40
I/O Ports. P12 to P31 can be configured as push-pull outputs, CMOS-
logic inputs, or CMOS-logic inputs with weak pullup resistor.
5–24
—
—
P12–P31
P4–P31
1–10, 12–19,
21–30
I/O Ports. P4 to P31 can be configured as push-pull outputs, CMOS-
logic inputs, or CMOS-logic inputs with weak pullup resistor.
—
5–32
32
33
25
26
33
34
SDA
SCL
I2C-Coꢀpatible Serial Data I/O
I2C-Coꢀpatible Serial Clock Input
Address Input 1. Sets device slave address. Connect to either GND,
V+, SCL, SDA to give four logic coꢀbinations. See Table 3.
27
28
35
36
34
35
AD1
V+
Positive Supply Voltage. Bypass V+ to GND with ꢀiniꢀuꢀ 0.047µF
capacitor.
0x0A. If this is not done, the eight unused ports reꢀain
as floating inputs and quiescent supply current rises,
although there is no daꢀage to the part.
Detailed Description
The MAX7300 general-purpose input/output (GPIO)
peripheral provides up to 28 I/O ports, P4 to P31, con-
trolled through an I2C-coꢀpatible serial interface. The
ports can be configured to any coꢀbination of logic
inputs and logic outputs, and default to logic inputs on
power-up.
Register Control of I/O Ports
Across Multiple Drivers
The MAX7300 offers 20 or 28 I/O ports, depending on
package choice. Two addressing ꢀethods are avail-
able. Any single port (bit) can be written (set/cleared)
at once; or, any sequence of eight ports can be written
(set/cleared) in any coꢀbination at once. There are no
boundaries; it is equally acceptable to write P0 to P7,
P1 to P8, or P31 to P38 (P32 to P38 are nonexistent, so
the instructions to these bits are ignored).
Figure 1 is the MAX7300 functional diagraꢀ. Any I/O port
can be configured as a push-pull output (sinking 10ꢀA,
sourcing 4.5ꢀA), or a Schꢀitt-trigger logic input. Each
input has an individually selectable internal pullup resis-
tor. Additionally, transition detection allows seven ports
(P24 to P30) to be ꢀonitored in any ꢀaskable coꢀbina-
tion for changes in their logic status. A detected transi-
tion is flagged through a status register bit, as well as an
interrupt pin (port P31), if desired.
Shutdown
When the MAX7300 is in shutdown ꢀode, all ports are
forced to inputs, and the pullup current sources are
turned off. Data in the port and control registers reꢀain
unaltered, so port configuration and output levels are
restored when the MAX7300 is taken out of shutdown.
The MAX7300 can still be prograꢀꢀed while in shut-
down ꢀode. For ꢀiniꢀuꢀ supply current in shutdown
ꢀode, logic inputs should be at GND or V+ potential.
Shutdown ꢀode is exited by setting the S bit in the con-
figuration register (Table 8).
The port configuration registers individually set the 28
ports, P4 to P31, as GPIO. A pair of bits in registers
0x09 through 0x0F sets each port’s configuration
(Tables 1 and 2).
The 36-pin MAX7300AAX and 40-pin MAX7300AGL
have 28 ports, P4 to P31. The 28-pin MAX7300ANI and
MAX7300AAI have only 20 ports available, P12 to P31.
The eight unused ports should be configured as out-
puts on power-up by writing 0x55 to registers 0x09 and
6
_______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
Table 1. Port Configuration Map
REGISTER DATA
D4 D3
ADDRESS
CODE (HEX)
REGISTER
D7
D6
D5
D2
D1
D0
Port Configuration for P7, P6, P5, P4
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
P7
P6
P5
P4
Port Configuration for P11, P10, P9, P8
Port Configuration for P15, P14, P13, P12
Port Configuration for P19, P18, P17, P16
Port Configuration for P23, P22, P21, P20
Port Configuration for P27, P26, P25, P24
Port Configuration for P31, P30, P29, P28
P11
P15
P19
P23
P27
P31
P10
P14
P18
P22
P26
P30
P9
P8
P13
P17
P21
P25
P29
P12
P16
P20
P24
P28
Table 2. Port Configuration Matrix
PORT
CONFIGURATION
BIT PAIR
PORT
REGISTER
ADDRESS
CODE (HEX)
MODE
FUNCTION
PIN BEHAVIOR
UPPER
LOWER
DO NOT USE THIS SETTING
0x09 to 0x0F
0x09 to 0x0F
0
0
Written Low
Written High
Active-low logic output
Active-high logic output
Output
GPIO Output
0
1
GPIO Input
without Pullup
Input
Input
Reading Port
Reading Port
Schꢀitt logic output
0x09 to 0x0F
0x09 to 0x0F
1
1
0
1
GPIO Input with Pullup
Schꢀitt logic input with pullup
Start and Stop Conditions
Serial Interface
Serial Addressing
Both SCL and SDA reꢀain high when the interface is
not busy. A ꢀaster signals the beginning of a transꢀis-
sion with a START (S) condition by transitioning SDA
froꢀ high to low while SCL is high. When the ꢀaster
has finished coꢀꢀunicating with the slave, it issues a
STOP (P) condition by transitioning SDA froꢀ low to
high while SCL is high. The bus is then free for another
transꢀission (Figure 3).
The MAX7300 operates as a slave that sends and
receives data through an I2C-coꢀpatible 2-wire inter-
face. The interface uses a serial data line (SDA) and a
serial clock line (SCL) to achieve bidirectional coꢀꢀu-
nication between ꢀaster(s) and slave(s). A ꢀaster (typ-
ically a ꢀicrocontroller) initiates all data transfers to and
froꢀ the MAX7300, and generates the SCL clock that
synchronizes the data transfer (Figure 2).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA ꢀust reꢀain stable while SCL is high
(Figure 4).
The MAX7300 SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7kΩ,
is required on SDA. The MAX7300 SCL line operates
only as an input. A pullup resistor, typically 4.7kΩ, is
required on SCL if there are ꢀultiple ꢀasters on the 2-
wire interface, or if the ꢀaster in a single-ꢀaster systeꢀ
has an open-drain SCL output.
Acknowledge
The acknowledge bit is a clocked 9th bit, which the
recipient uses to handshake receipt of each byte of
data (Figure 5). Thus, each byte transferred effectively
requires 9 bits. The ꢀaster generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is sta-
ble low during the high period of the clock pulse. When
the ꢀaster is transꢀitting to the MAX7300, the
MAX7300 generates the acknowledge bit since the
Each transꢀission consists of a START condition
(Figure 3) sent by a ꢀaster, followed by the MAX7300
7-bit slave address plus R/W bit (Figure 6), a register
address byte, one or ꢀore data bytes, and finally a
STOP condition (Figure 3).
_______________________________________________________________________________________
7
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
CONFIGURATION
PORT REGISTERS
MASK REGISTER
GPIO
P4 TO P31
CONFIGURATION
REGISTERS
PORT CHANGE
DETECTOR
DATA
CE
R/W
8
GPIO DATA
8
R/W
COMMAND
REGISTER DECODE
AD0
AD1
ADDRESS
MATCHER
7
8
8
DATA BYTE
COMMAND BYTE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
7
TO/FROM DATA REGISTERS
DATA BYTE
TO COMMAND REGISTERS
7-BIT DEVICE ADDRESS
R/W
SDA
SCL
COMMAND BYTE
SLAVE ADDRESS BYTE
Figure 1. MAX7300 Functional Diagram
MAX7300 is the recipient. When the MAX7300 is trans-
ꢀitting to the ꢀaster, the ꢀaster generates the
acknowledge bit since the ꢀaster is the recipient.
addresses (Table 3), and therefore a ꢀaxiꢀuꢀ of 16
MAX7300 devices can share the saꢀe interface.
Message Format for Writing
the MAX7300
Slave Address
The MAX7300 has a 7-bit-long slave address (Figure 6).
The eighth bit following the 7-bit slave address is the
R/W bit. It is low for a write coꢀꢀand and high for a
read coꢀꢀand.
A write to the MAX7300 coꢀprises the transꢀission of
the MAX7300’s slave address with the R/W bit set to
zero, followed by at least 1 byte of inforꢀation. The first
byte of inforꢀation is the coꢀꢀand byte. The coꢀ-
ꢀand byte deterꢀines which register of the MAX7300
is to be written by the next byte, if received. If a STOP
condition is detected after the coꢀꢀand byte is
received, then the MAX7300 takes no further action
(Figure 7) beyond storing the coꢀꢀand byte.
The first 3 bits (MSBs) of the MAX7300 slave address
are always 100. Slave address bits A3, A2, A1, and A0
are selected by the address inputs, AD1 and AD0.
These two input pins can be connected to GND, V+,
SDA, or SCL. The MAX7300 has 16 possible slave
8
_______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
SDA
t
BUF
t
t
SU, STA
SU, DAT
t
HD, STA
t
LOW
t
t
SU, STO
HD, DAT
SCL
t
HIGH
t
HD, STA
t
t
F
R
REPEATED START CONDITION
START CONDITION
STOP CONDITION START CONDITION
Figure 2. 2-Wire Serial Interface Timing Details
SDA
S
P
SCL
START
CONDITION
STOP
CONDITION
Figure 3. Start and Stop Conditions
SDA
SCL
DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED
Figure 4. Bit Transfer
Any bytes received after the coꢀꢀand byte are consid-
ered data bytes. The first data byte goes into the inter-
nal register of the MAX7300 selected by the coꢀꢀand
byte (Figure 8). If ꢀultiple data bytes are transꢀitted
before a STOP condition is detected, these bytes are
generally stored in subsequent MAX7300 internal regis-
ters because the coꢀꢀand byte address generally
autoincreꢀents (Table 4).
a write. The pointer generally autoincreꢀents after each
data byte is read using the saꢀe rules as for a write
(Table 4). Thus, a read is initiated by first configuring the
MAX7300’s coꢀꢀand byte by perforꢀing a write (Figure
7). The ꢀaster can now read ‘n’ consecutive bytes froꢀ
the MAX7300, with the first data byte being read froꢀ the
register addressed by the initialized coꢀꢀand byte
(Figure 9). When perforꢀing read-after-write verification,
reꢀeꢀber to reset the coꢀꢀand byte’s address
because the stored control byte address generally has
been autoincreꢀented after the write (Table 4). Table 5
is the register address ꢀap.
Message Format for Reading
The MAX7300 is read using the MAX7300’s internally
stored coꢀꢀand byte as address pointer, the saꢀe way
the stored coꢀꢀand byte is used as address pointer for
__________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
START CONDITION
CLOCK PULSE FOR ACKNOWLEDGMENT
SCL
1
2
8
9
SDA
BY TRANSMITTER
S
SDA
BY RECEIVER
Figure 5. Acknowledge
SDA
1
MSB
0
0
A3
A2
A1
A0
LSB
R/W
ACK
SCL
Figure 6. Slave Address
Operation with Multiple Masters
If the MAX7300 is operated on a 2-wire interface with
ꢀultiple ꢀasters, a ꢀaster reading the MAX7300 should
use a repeated start between the write, which sets the
MAX7300’s address pointer, and the read(s) that takes
the data froꢀ the location(s). This is because it is possi-
ble for ꢀaster 2 to take over the bus after ꢀaster 1 has
set up the MAX7300’s address pointer, but before
ꢀaster 1 has read the data. If ꢀaster 2 subsequently
changes, the MAX7300’s address pointer, then ꢀaster
1’s delayed read can be froꢀ an unexpected location.
Initial Power-Up
On initial power-up, all control registers are reset and
the MAX7300 enters shutdown ꢀode (Table 6).
Transition (Port Data Change) Detection
Port transition detection allows seven ꢀaskable ports
P24 to P30 to be continuously ꢀonitored for changes in
their logic status (Figure 10). Enable transition detec-
tion by setting the M bit in the configuration register
(Table 9) after setting the ꢀask register. If port 31 is
configured as an output (Tables 1 and 2), then P31
autoꢀatically becoꢀes an interrupt request (IRQ) out-
put to flag detected transitions. Port 31 can be config-
ured and used as a general-purpose input port instead,
if not required for use as the IRQ output.
Command Address Autoincrementing
Address autoincreꢀenting allows the MAX7300 to be
configured with the shortest nuꢀber of transꢀissions
by ꢀiniꢀizing the nuꢀber of tiꢀes the coꢀꢀand
address needs to be sent. The coꢀꢀand address
stored in the MAX7300 generally increꢀents after each
data byte is written or read (Table 4).
The ꢀask register deterꢀines which of the seven ports
P24 to P30 are ꢀonitored (Table 10). Set the appropri-
ate ꢀask bit to enable that port for transition detect.
Clear the ꢀask bit if transitions on that port are to be
ignored by the transition detection logic. Ports are ꢀon-
itored regardless of their I/O configuration, both input
and output.
10 ______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
D15 D14 D13 D12 D11 D10 D9 D8
COMMAND BYTE IS STORED ON RECEIPT OF STOP CONDITION
ACKNOWLEDGE FROM MAX7300
SLAVE ADDRESS
S
0
A
COMMAND BYTE
A
P
ACKNOWLEDGE FROM MAX7300
R/W
Figure 7. Command Byte Received
ACKNOWLEDGE FROM MAX7300
ACKNOWLEDGE FROM MAX7300
HOW COMMAND BYTE AND DATA BYTE MAP INTO MAX7300’s REGISTER
ACKNOWLEDGE FROM MAX7300
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
S
SLAVE ADDRESS
0
A
A
DATA BYTE
A
P
COMMAND BYTE
1 BYTE
R/W
AUTOINCREMENT MEMORY WORD ADDRESS
Figure 8. Command and Single Data Byte Received
The MAX7300 ꢀaintains an internal 7-bit snapshot reg-
ister to hold the coꢀparison copy of the logic states of
ports P24 to P30. The snapshot register is updated with
the condition of P24 to P31 whenever the configuration
register is written with the M bit set. The update action
occurs regardless of the previous state of the M bit so
that it is not necessary to clear the M bit and then reset
it in order to update the snapshot register.
Applications Information
Low-Voltage Operation
The MAX7300 operates down to 2V supply voltage
(although the sourcing and sinking currents are not
guaranteed), providing that the MAX7300 is powered up
initially to at least 2.5V to trigger the device’s internal
reset.
When the data change detection bit is set, the MAX7300
continuously coꢀpares the snapshot register against
the changing states of P24 to P31. When a difference
occurs, the IRQ bit (ꢀask register bit D7) is set and IRQ
port P31 goes high if it is configured as an output.
Power-Supply Considerations
The MAX7300 operates with power-supply voltages of
2.5V to 5.5V. Bypass the power supply to GND with a
0.047µF capacitor as close to the device as possible.
Add a 1µF capacitor if the MAX7300 is far away froꢀ
the board’s input bulk decoupling capacitor.
The IRQ bit and IRQ output reꢀain set until the ꢀask
register is next read or written, so if the IRQ is set, then
the ꢀask register reads with bit D7 set. Writing the
ꢀask register clears the IRQ bit and resets the IRQ out-
put, regardless of the value of bit D7 written.
Chip Information
TRANSISTOR COUNT: 33,559
PROCESS: CMOS
External Component R
ISET
to set
The MAX7300 uses an external resistor, R
ISET,
internal biasing. Use a resistor value of 39kΩ.
______________________________________________________________________________________ 11
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
ACKNOWLEDGE FROM MAX7300
ACKNOWLEDGE FROM MAX7300
HOW COMMAND BYTE AND DATA BYTE MAP INTO MAX7300’s REGISTER
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
ACKNOWLEDGE FROM MAX7300
SLAVE ADDRESS
COMMAND BYTE
DATA BYTE
S
0
A
A
A
P
‘n’ BYTES
R/W
AUTOINCREMENT MEMORY WORD ADDRESS
Figure 9. ‘n’ Data Bytes Received
Table 3. MAX7300 Address Map
PIN
DEVICE ADDRESS
CONNECTION
AD1
GND
GND
GND
GND
V+
AD0
GND
V+
A6
A5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SDA
SCL
GND
V+
V+
V+
SDA
SCL
GND
V+
V+
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
SDA
SCL
GND
V+
SDA
SCL
Table 4. Autoincrement Rules
COMMAND BYTE ADDRESS RANGE
x0000000 to x1111110
x1111111
AUTOINCREMENT BEHAVIOR
Coꢀꢀand address autoincreꢀents after byte read or written
Coꢀꢀand address reꢀains at x1111111 after byte written or read
12 ______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
Table 5. Register Address Map
COMMAND ADDRESS
HEX
CODE
REGISTER
D15
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D13
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
D11
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
D10
0
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
D9
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D8
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
No-Op
0x00
0x04
0x06
0x07
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
Configuration
Transition Detect Mask
Factory Reserved; do not write to this port
Port Configuration P7, P6, P5, P4
Port Configuration P11, P10, P9, P8
Port Configuration P15, P14, P13, P12
Port Configuration P19, P18, P17, P16
Port Configuration P23, P22, P21, P20
Port Configuration P27, P26, P25, P24
Port Configuration P31, P30, P29, P28
Port 0 only (virtual port, no action)
Port 1 only (virtual port, no action)
Port 2 only (virtual port, no action)
Port 3 only (virtual port, no action)
Port 4 only
Port 5 only
Port 6 only
Port 7 only
Port 8 only
Port 9 only
Port 10 only
Port 11 only
Port 12 only
Port 13 only
Port 14 only
Port 15 only
Port 16 only
Port 17 only
Port 18 only
Port 19 only
Port 20 only
Port 21 only
Port 22 only
Port 23 only
Port 24 only
Port 25 only
______________________________________________________________________________________ 13
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
Table 5. Register Address Map (continued)
COMMAND ADDRESS
REGISTER
HEX
CODE
D15
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D14
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D13
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D12
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D11
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D10
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D9
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D8
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Port 26 only
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
Port 27 only
Port 28 only
Port 29 only
Port 30 only
Port 31 only
4 ports 4–7 (data bits D0–D3)
5 ports 4–8 (data bits D0–D4)
6 ports 4–9 (data bits D0–D5)
7 ports 4–10 (data bits D0–D6)
8 ports 4–11
8 ports 5–12
8 ports 6–13
8 ports 7–14
8 ports 8–15
8 ports 9–16
8 ports 10–17
8 ports 11–18
8 ports 12–19
8 ports 13–20
8 ports 14–21
8 ports 15–22
8 ports 16–23
8 ports 17–24
8 ports 18–25
8 ports 19–26
8 ports 20–27
8 ports 21–28
8 ports 22–29
8 ports 23–30
8 ports 24–31
7 ports 25–31
6 ports 26–31
5 ports 27–31
4 ports 28–31
3 ports 29–31
2 ports 30–31
1 port 31 only
Note: Unused bits read as zero.
14 ______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
Table 6. Power-Up Configuration
ADDRESS
CODE
(HEX)
REGISTER DATA
REGISTER
FUNCTION
POWER-UP CONDITION
D7 D6
D5 D4
D3
D2 D1
D0
Port Register
Bits 4 to 31
0x24 to
0x3F
GPIO Output Low
X
X
X
X
X
X
X
0
Configuration
Register
Shutdown Enabled
Transition Detection Disabled
0x04
0
0
X
X
X
X
X
0
Input Mask
Register
All Clear (Masked Off)
0x06
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
X
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Port
Configuration
P7, P6, P5, P4: GPIO Inputs without Pullup
P11, P10, P9, P8: GPIO Inputs without Pullup
P15, P14, P13, P12: GPIO Inputs without Pullup
P19, P18, P17, P16: GPIO Inputs without Pullup
P23, P22, P21, P20: GPIO Inputs without Pullup
P27, P26, P25, P24: GPIO Inputs without Pullup
P31, P30, P29, P28: GPIO Inputs without Pullup
Port
Configuration
Port
Configuration
Port
Configuration
Port
Configuration
Port
Configuration
Port
Configuration
X = unused bits; if read, zero results.
______________________________________________________________________________________ 15
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
Table 7. Configuration Register Format
REGISTER DATA
ADDRESS CODE
(HEX)
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
Configuration Register
0x04
M
0
X
X
X
X
X
S
Table 8. Shutdown Control (S Data Bit D0) Format
REGISTER DATA
ADDRESS CODE
FUNCTION
(HEX)
D7
M
D6
0
D5
X
D4
X
D3
X
D2
X
D1
X
D0
0
Shutdown
0x04
0x04
Norꢀal Operation
M
0
X
X
X
X
X
1
Table 9. Transition Detection Control (M Data Bit D7) Format
REGISTER DATA
ADDRESS CODE
(HEX)
FUNCTION
D7
0
D6
0
D5
X
D4
X
D3
X
D2
X
D1
X
D0
S
Disabled
Enabled
0x04
0x04
1
0
X
X
X
X
X
S
Table 10. Transition Detection Mask Register
REGISTER
ADDRESS
(HEX)
REGISTER DATA
READ/
WRITE
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
Port
30
ꢀask
Port
29
ꢀask
Port
28
ꢀask
Port
27
ꢀask
Port
26
ꢀask
Port
25
ꢀask
Port
24
ꢀask
Read
Write
IRQ Status*
Unchanged
Mask
Register
0x06
*IRQ is automatically cleared after it is read.
16 ______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
GPIO INPUT
GPIO IN
CONDITIONING
GPIO/PORT
GPIO/PORT OUT
OUTPUT LATCH
IRQ STATUS STORED AS MSB OF MASK REGISTER
P31
CLOCK PULSE AFTER EACH READ ACCESS TO MASK REGISTER
R
S
IRQ
OUTPUT LATCH
CONFIGURATION REGISTER M BIT = 1
GPIO IN
GPIO INPUT
D
D
Q
Q
CONDITIONING
P30
P29
GPIO/PORT OUT
MASK REGISTER BIT 6
MASK REGISTER BIT 5
GPIO/PORT OUTPUT LATCH
GPIO IN
GPIO INPUT
CONDITIONING
GPIO/PORT OUT
GPIO/PORT OUTPUT LATCH
GPIO IN
GPIO INPUT
D
D
Q
Q
CONDITIONING
P28
P27
GPIO/PORT OUT
MASK REGISTER BIT 4
GPIO/PORT OUTPUT LATCH
GPIO IN
GPIO INPUT
CONDITIONING
OR
MASK REGISTER BIT 3
GPIO/PORT OUT
GPIO/PORT OUTPUT LATCH
GPIO IN
GPIO INPUT
D
D
Q
Q
CONDITIONING
P26
P25
GPIO/PORT OUT
MASK REGISTER BIT 2
MASK REGISTER BIT 1
GPIO/PORT OUTPUT LATCH
GPIO IN
GPIO INPUT
CONDITIONING
GPIO/PORT OUT
GPIO/PORT OUTPUT LATCH
GPIO IN
GPIO INPUT
CONDITIONING
D
Q
P24
GPIO/PORT OUT
MASK REGISTER LSB
GPIO/PORT OUTPUT LATCH
CLOCK PULSE WHEN WRITING CONFIGURATION REGISTER WITH M BIT SET
Figure 10. Maskable GPIO Ports P24 to P31
______________________________________________________________________________________ 17
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
Pin Configurations (continued)
TOP VIEW
ISET
GND
GND
AD0
P8
1
2
3
4
5
6
7
8
9
36 V+
35 AD1
34 SCL
33 SDA
32 P4
P8
P12
P9
1
2
30
29
28
27
26
25
24
23
22
21
P4
P31
P5
3
P13
P10
P14
P11
P15
P16
P17
4
P30
P6
5
MAX7300
MAX7300
6
P29
P7
P28
P27
P26
P12
P9
31 P31
30 P5
7
8
P13
P10
P30
29
9
10
28 P6
P14 10
P11 11
P15 12
P16 13
P17 14
P18 15
P19 16
P20 17
P21 18
27 P29
26 P7
25 P28
24 P27
23 P26
22 P25
21 P24
20 P23
19 P22
QFN
SSOP
18 ______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
Package Information
(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation,
go to www.maxim-ic.com/packages.)
2
1
INCHES
MILLIMETERS
MAX
MAX
1.99
0.21
0.38
0.20
DIM
A
MIN
0.068
MIN
1.73
0.05
0.25
0.09
INCHES
MAX
MILLIMETERS
MAX
MIN
MIN
N
0.078
14L
16L
20L
A1
B
D
D
D
D
D
0.239 0.249
0.239 0.249
0.278 0.289
0.317 0.328
6.07
6.07
7.07
8.07
6.33
6.33
7.33
0.002 0.008
0.010 0.015
0.004 0.008
C
8.33 24L
E
H
SEE VARIATIONS
0.205 0.212 5.20
0.0256 BSC
D
0.397 0.407 10.07 10.33 28L
E
5.38
e
0.65 BSC
H
0.301 0.311 7.65
0.025 0.037 0.63
7.90
0.95
8∞
L
0∞
8∞
0∞
N
A
C
B
L
e
A1
D
NOTES:
1. D&E DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").
3. CONTROLLING DIMENSION: MILLIMETERS.
4. MEETS JEDEC MO150.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, SSOP, 5.3 MM
APPROVAL
DOCUMENT CONTROL NO.
REV.
5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
1
21-0056
C
1
______________________________________________________________________________________ 19
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
Package Information (continued)
(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation,
go to www.maxim-ic.com/packages.)
20 ______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
Package Information (continued)
(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation,
go to www.maxim-ic.com/packages.)
______________________________________________________________________________________ 21
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
Package Information (continued)
(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation,
go to www.maxim-ic.com/packages.)
36
INCHES
MILLIMETERS
DIM
A
MIN
MAX
0.104
0.011
0.017
0.013
MIN
2.44
0.10
0.30
0.23
MAX
2.65
0.29
0.44
0.32
0.096
0.004
0.012
0.009
A1
B
C
e
0.0315 BSC
0.291 0.299
0.80 BSC
E
H
E
7.40
10.11
0.51
7.60
10.51
1.02
H0.4140.398
L
0.020
0.598
0.040
0.612
D
15.20
15.55
1
TOP VIEW
D
A1
A
C
e
0∞-8∞
B
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 36L SSOP, 0.80 MM PITCH
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0040
E
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxiꢀ Integrated Products
Printed USA
is a registered tradeꢀark of Maxiꢀ Integrated Products.
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