MAX5854ETL+ [MAXIM]
D/A Converter, 2 Func, Parallel, Word Input Loading, 0.012us Settling Time, 6 X 6 MM, 0.8 MM HEIGHT, TQFN-40;
| 型号： | MAX5854ETL+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 2 Func, Parallel, Word Input Loading, 0.012us Settling Time, 6 X 6 MM, 0.8 MM HEIGHT, TQFN-40 转换器 |
| 文件： | 总18页 (文件大小：2205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
General Description
Features
● 10-Bit, 165Msps Dual DAC
The MAX5854 dual, 10-bit, 165Msps digital-to-analog
converter (DAC) provides superior dynamic performance
in wideband communication systems. The device inte-
grates two 10-bit DAC cores, and a 1.24V reference. The
MAX5854 supports single-ended and differential modes
of operation. The dynamic performance is maintained
over the entire 2.7V to 3.6V power-supply operating
range. The analog outputs support a -1.0V to +1.25V
compliance voltage.
● Low Power
• 190mW with I = 20mA at f
FS
= 165MHz
CLK
● 2.7V to 3.6V Single Supply
● Full Output Swing and Dynamic Performance at
2.7V Supply
● Superior Dynamic Performance
• 73dBc SFDR at f
= 40MHz
OUT
• UMTS ACLR = 65.5dB at f
= 30.7MHz
The MAX5854 can operate in interleaved data mode to
reduce the I/O pin count. This allows the converter to be
updated on a single, 10-bit bus.
OUT
● Programmable Channel Gain Matching
● Integrated 1.24V Low-Noise Bandgap Reference
● Single-Resistor Gain Control
The MAX5854 features digital control of channel gain
matching to within ±0.4dB in sixteen 0.05dB steps.
Channel matching improves sideband suppression in
analog quadrature modulation applications. The on-chip
1.24V bandgap reference includes a control amplifier that
allows external full-scale adjustments of both channels
through a single resistor. The internal reference can be
disabled and an external reference can be applied for
high-accuracy applications.
● Interleaved Data Mode
● Single-Ended and Differential Clock Input Modes
● Miniature 40-Pin TQFN Package, 6mm x 6mm
● EV Kit Available—MAX5854 EV Kit
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
The MAX5854 features full-scale current outputs of 2mA
to 20mA and operates from a 2.7V to 3.6V single supply.
The DAC supports three modes of power-control opera-
tion: normal, low-power standby, and complete power-
down. In power-down mode, the operating current is
reduced to 1μA.
MAX5854ETL
-40°C to +85°C
40 Thin QFN-EP*
*EP = Exposed paddle.
Pin Configuration
TOP VIEW
The MAX5854 is packaged in a 40-pin TQFN with
exposed paddle (EP) and is specified for the extended
(-40°C to +85°C) temperature range.
40 39 38 37 36 35 34 33
32 31
Pin-compatible, lower speed, and lower resolution ver-
sions are also available. Refer to the MAX5853 (10-
bit, 80Msps), the MAX5852 (8-bit, 165Msps), and the
MAX5851 (8-bit, 80Msps) data sheets for more informa-
tion. See Table 4 at the end of the data sheet.
30
29
DA9/PD
DA8/DACEN
DA7/IDE
DA6/REN
DA5/G3
DA4/G2
DA3/G1
DA2/G0
DA1
CV
DD
1
2
EP
CGND
3
28 CLK
4
27
26
25
24
23
22
21
CV
DD
5
CLKXN
CLKXP
DCE
MAX5854
6
Applications
● Communications
SatCom, LMDS, MMDS, HFC, DSL, WLAN,
Point-to-Point Microwave Links
● Wireless Base Stations
7
8
CW
9
DB0
10
DA0
DB1
11
16 17 18 19 20
12
15
● Quadrature Modulation
13 14
● Direct Digital Synthesis (DDS)
● Instrumentation/ATE
TQFN
19-3197; Rev 0; 2/04
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Absolute Maximum Ratings
AV , DV , CV to AGND, DGND, CGND .......-0.3V to +4V
AGND to DGND, DGND to CGND,
DD
DD
DD
DA9–DA0, DB9–DB0, CW, DCE to AGND,
DGND, CGND .....................................................-0.3V to +4V
CLKXN, CLKXP to CGND.......................................-0.3V to +4V
AGND to CGND................................................-0.3V to +0.3V
Maximum Current into Any Pin
(excluding power supplies)...........................................±50mA
OUTP_, OUTN_ to AGND....................-1.25V to (AV
CLK to DGND.........................................-0.3V to (DV
REFR, REFO to AGND ..........................-0.3V to (AV
+ 0.3V)
+ 0.3V)
+ 0.3V)
Continuous Power Dissipation (T = +70°C)
40-Pin TQFN-EP (derate 23.3mW/°C
above +70°C) ..............................................................1.860W
Operating Temperature Range........................... -40°C to +85°C
Storage Temperature Range............................ -65°C to +150°C
Junction Temperature......................................................+150°C
DD
DD
DD
A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(AV
= DV
= CV
= 3V, AGND = DGND = CGND = 0, f
= 165Msps, differential clock, external reference, V
= 1.2V,
DD
DD
DD
DAC
REF
I
= 20mA, output amplitude = 0dB FS, differential output, T = T
to T
, unless otherwise noted. T ≥ +25°C guaranteed by
FS
A
MIN
MAX
A
production test. T < +25°C guaranteed by design and characterization. Typical values are at T = +25°C.)
A
A
PARAMETER
STATIC PERFORMANCE
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
N
10
Bits
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
DNL
R = 0
-1.0
-0.5
-0.5
-11.0
-6.25
±0.25
±0.2
±0.1
±1.5
±0.7
±150
±100
+1.0
+0.5
+0.5
+6.8
+4.10
L
Guaranteed monotonic, R = 0
L
V
OS
Internal reference (Note1)
External reference
Internal reference
Gain Error (See Also Gain Error
Definition Section)
GE
%FSR
Gain-Error Temperature Drift
ppm/°C
External reference
DYNAMIC PERFORMANCE
f
f
f
f
f
f
= 10MHz
= 20MHz
= 40MHz
= 10MHz
= 20MHz
= 30MHz
69.4
78
77
73
77
77
76
OUT
OUT
OUT
OUT
OUT
OUT
f
A
= 165MHz,
CLK
= -1dBFS
OUT
Spurious-Free Dynamic Range
to Nyquist
SFDR
dBc
f
= 100MHz,
CLK
A
= -1dBFS
OUT
f
A
= 25MHz,
CLK
f
= 1MHz
79
83
84
82
74
OUT
= -1dBFS
OUT
f
A
= 165MHz, f
= 10MHz,
OUT
CLK
= -1dBFS, span = 10MHz
OUT
Spurious-Free Dynamic Range
Within a Window
f
A
= 100MHz, f
= 5MHz,
OUT
CLK
SFDR
MTPR
dBc
dBc
= -1dBFS, span = 4MHz
OUT
f
A
= 25MHz, f
= 1MHz,
CLK
OUT
= -1dBFS, span = 2MHz
OUT
8 tones at 400kHz spacing, f
f
= 78MHz,
CLK
Multitone Power Ratio to Nyquist
= 15MHz to 18.2MHz
OUT
Maxim Integrated
│ 2
www.maximintegrated.com
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Electrical Characteristics (continued)
(AV
= DV
= CV
= 3V, AGND = DGND = CGND = 0, f
= 165Msps, differential clock, external reference, V
= 1.2V,
DD
DD
DD
DAC
REF
I
= 20mA, output amplitude = 0dB FS, differential output, T = T
to T
, unless otherwise noted. T ≥ +25°C guaranteed by
FS
A
MIN
MAX
A
production test. T < +25°C guaranteed by design and characterization. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Multitone Spurious-Free
Dynamic Range Within a
Window
8 tones at 2.1MHz spacing,
f
= 165MHz, f
= 28.3MHz to 45.2MHz,
70
dBc
CLK
OUT
span = 50MHz
Adjacent Channel Power Ratio
with UMTS
f
f
= 30.72MHz, RBW = 30kHz,
= 122.88MHz
OUT
CLK
ACLR
65.5
dB
f
f
f
f
f
f
= 10MHz
= 20MHz
= 40MHz
= 10MHz
= 20MHz
= 30MHz
-76
-74
-71
-75
-74
-73
OUT
OUT
OUT
OUT
OUT
OUT
f
A
= 165MHz,
CLK
= -1dBFS
OUT
Total Harmonic Distortion to
Nyquist (2nd- Through 8th-Order
Harmonics Included)
THD
dBc
f
= 100MHz,
CLK
A
= -1dBFS
OUT
f
A
= 25MHz,
CLK
f
= 1MHz
-76
90
OUT
= -1dBFS
OUT
Output Channel-to-Channel
Isolation
f
f
f
= 10MHz
dB
dB
OUT
OUT
OUT
Channel-to-Channel Gain
Mismatch
= 10MHz, G[3:0] = 1000
= 10MHz
0.025
0.05
Channel-to-Channel Phase
Mismatch
Degrees
f
f
f
f
= 165MHz, f
= 165MHz, f
= 10MHz, I = 20mA
60.5
61
CLK
CLK
CLK
CLK
OUT
OUT
FS
= 10MHz, I = 5mA
FS
Signal-to-Noise Ratio to Nyquist
Maximum DAC Conversion Rate
SNR
dB
= 65MHz, f
= 10MHz, I = 20mA
62
OUT
OUT
FS
= 65MHz, f
= 10MHz, I = 5mA
62
FS
Interleaved mode disabled, IDE = 0
Interleaved mode enabled, IDE = 1
165
200
100
5
f
Msps
DAC
82.5
Glitch Impulse
pV-s
ns
Output Settling Time
Output Rise Time
Output Fall Time
ANALOG OUTPUT
t
To ±0.1% error band (Note 3)
10% to 90% (Note 3)
12
S
2.2
2.2
ns
90% to 10% (Note 3)
ns
Full-Scale Output Current
Range
I
2
20
mA
FS
Output Voltage Compliance
Range
-1.00
-5
+1.25
+5
V
Output Leakage Current
Shutdown or standby mode
µA
REFERENCE
Internal-Reference Output
Voltage
V
REFO
1.13
1.24
1.32
V
REN = 0
Maxim Integrated
│ 3
www.maximintegrated.com
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Electrical Characteristics (continued)
(AV
= DV
= CV
= 3V, AGND = DGND = CGND = 0, f
= 165Msps, differential clock, external reference, V
= 1.2V,
DD
DD
DD
DAC
REF
I
= 20mA, output amplitude = 0dB FS, differential output, T = T
to T
, unless otherwise noted. T ≥ +25°C guaranteed by
FS
A
MIN
MAX
A
production test. T < +25°C guaranteed by design and characterization. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Internal-Reference Supply
Rejection
AV
varied from 2.7V to 3.6V
0.5
mV/V
DD
Internal-Reference Output-
Voltage Temperature Drift
TCV
±50
50
ppm/°C
µA
REN = 0
REN = 0
REN = 1
REFO
Internal-Reference Output Drive
Capability
External-Reference Input
Voltage Range
0.10
1.2
32
1.32
V
Current Gain
I
/I
mA/mA
FS REF
LOGIC INPUTS (DA9–DA0, DB9–DB0, CW)
0.65 x
DV
Digital Input-Voltage High
V
IH
V
V
DD
0.3 x
DD
Digital Input-Voltage Low
V
IL
DV
Digital Input Current
I
-1
+1
µA
pF
IN
Digital Input Capacitance
C
3
IN
SINGLE-ENDED CLOCK INPUT/OUTPUT AND DCE INPUT (CLK, DCE)
0.65 x
Digital Input-Voltage High
V
V
V
DCE = 1
IH
CV
DD
0.3 x
CV
Digital Input-Voltage Low
V
I
DCE = 1
IL
DD
Digital Input Current
-1
+1
µA
pF
DCE = 1
DCE = 1
IN
Digital Input Capacitance
C
3
IN
0.9 x
CV
Digital Output-Voltage High
Digital Output-Voltage Low
V
V
V
DCE = 0, I
= 0.5mA, Figure 1
OH
SOURCE
DD
0.1 x
CV
V
DCE = 0, I
= 0.5mA, Figure 1
OL
SINK
DD
DIFFERENTIAL CLOCK INPUTS (CLKXP/CLKXN)
Differential Clock Input Internal
Bias
CV /2
DD
V
Differential Clock Input Swing
0.5
V
Clock Input Impedance
Measured single ended
5
kΩ
POWER REQUIREMENTS
Analog Power-Supply Voltage
Digital Power-Supply Voltage
Clock Power-Supply Voltage
AV
2.7
2.7
2.7
3
3
3
3.6
V
V
V
DD
DV
CV
3.6
3.6
DD
DD
Maxim Integrated
│ 4
www.maximintegrated.com
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Electrical Characteristics (continued)
(AV
= DV
= CV
= 3V, AGND = DGND = CGND = 0, f
= 165Msps, differential clock, external reference, V
= 1.2V,
DD
DD
DD
DAC
REF
I
= 20mA, output amplitude = 0dB FS, differential output, T = T
to T
, unless otherwise noted. T ≥ +25°C guaranteed by
FS
A
MIN
MAX
A
production test. T < +25°C guaranteed by design and characterization. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
43.2
43.2
5
MAX
UNITS
I
I
I
I
I
I
= 20mA (Note 2), single-ended clock mode
= 20mA (Note 2), differential clock mode
= 2mA (Note 2), single-ended clock mode
= 2mA (Note 2), differential clock mode
= 20mA (Note 2), single-ended clock mode
= 20mA (Note 2), differential clock mode
46
FS
FS
FS
FS
FS
FS
Analog Supply Current
I
mA
AVDD
5
6.2
6.2
13.7
24
7.5
16.5
3.7
Digital Supply Current
Clock Supply Current
I
I
mA
mA
DVDD
CVDD
Single-ended clock mode (DCE = 1) (Note 2)
Differential clock mode (DCE = 0) (Note 2)
Total Standby Current
Total Shutdown Current
I
I
+ I
+ I
DVDD CVDD
3.1
1
mA
µA
STANDBY AVDD
I
I
+ I
+ I
DVDD CVDD
SHDN
AVDD
I
I
= 20mA (Note 2)
= 2mA (Note 2)
= 20mA (Note 2)
= 2mA (Note 2)
190
75
210
Single-ended clock
mode (DCE = 1)
FS
FS
I
220
106
9.3
0.003
Differential clock mode FS
Total Power Dissipation
P
mW
TOT
(DCE = 0)
I
FS
Standby
11.1
Shutdown
TIMING CHARACTERISTICS (Figure 5, Figure 6)
Clock
cycles
Propagation Delay
1
1.2
2.7
0.8
-0.5
Single-ended clock mode (DCE = 1) (Note 4)
Differential clock mode (DCE = 0) (Note 4)
Single-ended clock mode (DCE = 1) (Note 4)
Differential clock mode (DCE = 0) (Note 4)
DAC Data to CLK Rise/Fall
Setup Time
t
ns
ns
DCS
DAC Data to CLK Rise/Fall Hold
Time
t
DCH
Control Word to CW Rise Setup
t
2.5
2.5
ns
ns
CS
Time
Control Word to CW Rise Hold
t
CW
Time
t
5
5
ns
ns
CW High Time
CW Low Time
CWH
t
CWL
DACEN = 1 to V
Stable
OUT
t
3
µs
STB
Time (Coming Out of Standby)
Maxim Integrated
│ 5
www.maximintegrated.com
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Electrical Characteristics (continued)
(AV
= DV
= CV
= 3V, AGND = DGND = CGND = 0, f
= 165Msps, differential clock, external reference, V
= 1.2V,
DD
DD
DD
DAC
REF
I
= 20mA, output amplitude = 0dB FS, differential output, T = T
to T
, unless otherwise noted. T ≥ +25°C guaranteed by
FS
A
MIN
MAX
A
production test. T < +25°C guaranteed by design and characterization. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PD = 0 to V
Stable Time
OUT
t
500
µs
SHDN
(Coming Out of Power-Down)
Maximum Clock Frequency at
CLKXP/CLKXN Input
f
165
200
MHz
CLK
Clock High Time
Clock Low Time
t
CLKXP or CLKXN input
1.5
1.5
ns
ns
CXH
t
CLKXP or CLKXN input
CXL
CLKXP Rise to CLK Output Rise
Delay
t
2.7
2.7
ns
ns
DCE = 0
CDH
CLKXP Fall to CLK Output Fall
Delay
t
DCE = 0
CDL
Note 1: Including the internal reference voltage tolerance and reference amplifier offset.
Note 2: f = 165Msps, f = 10MHz.
DAC
OUT
Note 3: Measured single-ended with 50Ω load and complementary output connected to AGND.
Note 4: Guaranteed by design, not production tested.
0.5mA
TO OUTPUT
1.6V
PIN
5pF
0.5mA
Figure 1. Load Test Circuit for CLK Outputs
Maxim Integrated
│ 6
www.maximintegrated.com
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Typical Operating Characteristics
(AV
= DV
= CV
= 3V, AGND = DGND = CGND = 0, external reference, differential clock, I
= 20mA, differential output,
DD
DD
DD
FS
T
= +25°C, unless otherwise noted.)
A
SPURIOUS-FREE DYNAMIC RANGE
SPURIOUS-FREE DYNAMIC RANGE
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
= 200MHz)
vs. OUTPUT FREQUENCY (f
= 100MHz)
vs. OUTPUT FREQUENCY (f
= 25MHz)
CLK
CLK
CLK
90
85
80
75
70
65
60
55
50
45
40
35
30
90
85
80
75
70
65
60
55
50
45
40
35
30
90
85
80
75
70
65
60
55
50
45
40
35
30
0dBFS
0dBFS
0dBFS
-6dBFS
-12dBFS
-6dBFS
-12dBFS
-6dBFS
-12dBFS
50
0
10 20 30 40 50 60 70 80 90 100
(MHz)
0
5
10 15 20 25 30 35 40 45
(MHz)
1
3
5
7
9
11
13
f
f
f (MHz)
OUT
OUT
OUT
SPURIOUS-FREE DYNAMIC RANGE
SPURIOUS-FREE DYNAMIC RANGE
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
= 200MHz)
vs. OUTPUT FREQUENCY (f
= 165MHz)
vs. OUTPUT FREQUENCY (f
= 165MHz)
CLK
CLK
CLK
90
85
80
75
70
65
60
55
50
45
40
35
30
90
90
85
80
75
70
65
60
55
50
45
40
35
30
AV = DV = CV = 3.3V
DD
DD
DD
85
80
75
70
65
60
55
50
45
40
35
30
I
= 20mA
OUT
0dBFS
I
= 5mA
OUT
AV = DV = CV = 3.6V
DD
DD
DD
AV = DV = CV = 2.7V
DD
DD
DD
I
= 10mA
OUT
-6dBFS
-12dBFS
AV = DV = CV = 3V
DD DD DD
0
10 20 30 40 50 60 70 80 90 100
(MHz)
0
10 20 30 40 50 60 70 80 90
(MHz)
0
10 20 30 40 50 60 70 80 90
(MHz)
f
f
f
OUT
OUT
OUT
SFDR vs. TEMPERATURE (f
= 165MHz,
TWO-TONE INTERMODULATION DISTORTION
CLK
f
= 10MHz, A
= 0dBFS)
(f
= 165MHz, 1MHz WINDOW)
OUT
OUT
CLK
80.0
79.5
79.0
78.5
78.0
77.5
77.0
76.5
76.0
75.5
75.0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f
f
= 4.8541MHz
= 5.0555MHz
OUT1
OUT2
f
f
OUT1
OUT2
2f
- f
OUT1 OUT2
2f
- f
OUT2 OUT1
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
(MHz)
-40
-15
10
35
60
85
f
TEMPERATURE (°C)
OUT
Maxim Integrated
│ 7
www.maximintegrated.com
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Typical Operating Characteristics (continued)
(AV
= DV
= CV
= 3V, AGND = DGND = CGND = 0, external reference, differential clock, I
= 20mA, differential output,
DD
DD
DD
FS
T
= +25°C, unless otherwise noted.)
A
8-TONE SFDR PLOT
SINGLE-TONE SFDR
SINGLE-TONE SFDR
(f
CLK
= 165MHz, 35MHz WINDOW)
(f
= 165MHz, 10MHz WINDOW)
(f
CLK
= 100MHz, 4MHz WINDOW)
CLK
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f
A
= 9.1040MHz
= -1dBFS
f
A
= 5.0533MHz
OUT1
OUT1
f
f
T4
T5
= -1dBFS
OUT
OUT
f
T6
f
T3
f
T2
f
T7
f
T1
f
T8
39.7
34.7
14
7.0
4.7 9.7 14.7
24.7 29.7
(MHz)
9
10
13
5.0 5.5
(MHz)
19.7
4
5
6
8
11 12
3.0 3.5 4.0
6.0 6.5
7
4.5
f
f
f
(MHz)
OUT
OUT
OUT
f
= 24.035MHz
= 25.087MHz
= 26.741MHz
= 27.869MHz
f
f
f
f
= 17.493MHz
= 18.997MHz
= 20.200MHz
= 21.253MHz
T5
T1
T2
T3
T4
f
f
f
T6
T7
T8
SINGLE-TONE SFDR
= 25MHz, 2MHz WINDOW)
SINGLE-TONE SFDR
= 78MHz, 20MHz WINDOW)
CLK
(f
CLK
(f
0
0
f
= 1.0152MHz
f
= 11.0333MHz
OUT
OUT
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
A
= -1dBFS
A
= -1dBFS
OUT
OUT
1.9
21.0
0.1 0.4 0.6
1.1 1.4 1.6
(MHz)
1.0
5.0
13.0
(MHz)
17.0
0.9
9.0
f
f
OUT
OUT
SINGLE-TONE FFT PLOT (f
= 165MHz,
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
CLK
f
= 10MHz, A
= 0dBFS, NYQUIST WINDOW)
OUT
OUT
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-0.1
-0.2
-0.3
-0.4
-0.5
82.5
0.5
0
150 300 450 600 750 900 1050
DIGITAL INPUT CODE
8.2MHz/div
f
(MHz)
OUT
Maxim Integrated
│ 8
www.maximintegrated.com
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Typical Operating Characteristics (continued)
(AV
= DV
= CV
= 3V, AGND = DGND = CGND = 0, external reference, differential clock, I
= 20mA, differential output,
DD
DD
DD
FS
T
= +25°C, unless otherwise noted.)
A
POWER DISSIPATION vs. SUPPLY VOLTAGES
(f = 165MHz, f = 10MHz)
POWER DISSIPATION vs. CLOCK FREQUENCY
(f = 10MHz, A = 0dBFS)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
CLK
OUT
OUT
OUT
300
280
260
240
220
200
180
160
160
230
220
210
200
190
180
170
160
150
0.5
0.4
0.3
0.2
0.1
0
DIFFERENTIAL
CLOCK DRIVE
DIFFERENTIAL
CLOCK DRIVE
-0.1
-0.2
-0.3
-0.4
-0.5
SINGLE-ENDED
CLOCK DRIVE
SINGLE-ENDED
CLOCK DRIVE
2.70 2.85 3.00 3.15 3.30 3.45 3.60
SUPPLY VOLTAGES (V)
20
45
70
95
(MHz)
120
145
170
0
150 300 450 600 750 900 1050
DIGITAL INPUT CODE
f
CLK
REFERENCE VOLTAGE vs. SUPPLY VOLTAGES
(f = 165MHz, f = 10MHz)
REFERENCE VOLTAGE vs. TEMPERATURE
DYNAMIC RESPONSE RISE TIME
CLK
OUT
MAX5854 toc21
1.22230
1.22230
1.22230
1.22200
1.22190
1.22180
1.22170
1.22160
1.22150
1.25
1.24
1.23
1.22
1.21
1.20
1.19
100mV/div
2.70 2.85 3.00 3.15 3.30 3.45 3.60
SUPPLY VOLTAGES (V)
-40
-15
10
35
60
85
10ns/div
TEMPERATURE (°C)
ACLR PLOT
SPURIOUS-FREE DYNAMIC RANGE
DYNAMIC RESPONSE FALL TIME
(f
CLK
= 122.88MHz, f
= 30.72MHz)
vs. OUTPUT FREQUENCY (f
= 165MHz)
OUT
CLK
MAX5854 toc22
-20
-30
90
85
80
75
70
65
60
55
50
45
40
35
30
ACLR = 65.5dB
0dBFS
-40
100mV/div
-50
-60
-70
-6dBFS
-80
-12dBFS
-90
-100
-110
-120
-130
-140
SINGLE-ENDED
CLOCK DRIVE
10ns/div
23.38
1.468MHz/div
(MHz)
38.06
0
10 20 30 40 50 60 70 80 90
(MHz)
f
f
OUT
OUT
Maxim Integrated
│ 9
www.maximintegrated.com
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Pin Description
PIN
1
NAME
FUNCTION
DA9/PD
Channel A Input Data Bit 9 (MSB)/Power-Down
2
DA8/DACEN Channel A Input Data Bit 8/DAC Enable Control
3
DA7/IDE
Channel A Input Data Bit 7/Interleaved Data Enable
Channel A Input Data Bit 6/Reference Enable. Setting REN = 0 enables the internal reference. Setting
REN = 1 disables the internal reference.
4
DA6/REN
5
DA5/G3
DA4/G2
DA3/G1
DA2/G0
DA1
Channel A Input Data Bit 5/Channel A Gain Adjustment Bit 3
Channel A Input Data Bit 4/Channel A Gain Adjustment Bit 2
Channel A Input Data Bit 3/Channel A Gain Adjustment Bit 1
Channel A Input Data Bit 2/Channel A Gain Adjustment Bit 0
Channel A Input Data Bit 1
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
DA0
Channel A Input Data Bit 0 (LSB)
DB9
Channel B Input Data Bit 9 (MSB)
DB8
Channel B Input Data Bit 8
DB7
Channel B Input Data Bit 7
DB6
Channel B Input Data Bit 6
DB5
Channel B Input Data Bit 5
DV
Digital Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more details.
Digital Ground
DD
DGND
DB4
DB3
DB2
DB1
DB0
CW
Channel B Input Data Bit 4
Channel B Input Data Bit 3
Channel B Input Data Bit 2
Channel B Input Data Bit 1
Channel B Input Data Bit 0 (LSB)
Active-Low Control Word Write Pulse. The control word is latched on the rising edge of CW.
Active-Low Differential Clock Enable Input. Drive DCE low to enable the differential clock inputs
CLKXP and CLKXN. Drive DCE high to disable the differential clock inputs and enable the single-
ended CLK input.
24
25
DCE
Positive Differential Clock Input. With DCE = 0, CLKXP and CLKXN are enabled. With DCE = 1, CLKXP
and CLKXN are disabled. Connect CLKXP to CGND when the differential clock is disabled.
CLKXP
CLKXN
Negative Differential Clock Input. With DCE = 0, CLKXP and CLKXN are enabled. With DCE = 1, CLKXP
26
and CLKXN are disabled. Connect CLKXN to CV
when the differential clock is disabled.
DD
27, 30
CV
Clock Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more details.
DD
Single-Ended Clock Input/Output. With the differential clock disabled (DCE = 1), CLK becomes a single-
ended conversion clock input. With the differential clock enabled (DCE = 0), CLK is a single-ended output
that mirrors the differential clock inputs CLKXP and CLKXN. See the Clock Modes section for more
information on CLK.
28
CLK
29
31
CGND
REFO
Clock Ground
Reference Input/Output. REFO serves as a reference input when the internal reference is disabled. If
the internal 1.24V reference is enabled, REFO serves as an output for the internal reference. When the
internal reference is enabled, bypass REFO to AGND with a 0.1µF capacitor
Maxim Integrated
│ 10
www.maximintegrated.com
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Pin Description (continued)
PIN
NAME
FUNCTION
Full-Scale Current Adjustment. To set the output full-scale current, connect an external resistor RSET
32
REFR
between REFR and AGND. The output full-scale current is equal to 32 x V
/R
.
REFO SET
33, 39
34
AV
Analog Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more details.
Channel B Negative Analog Current Output
DD
OUTNB
OUTPB
AGND
OUTNA
OUTPA
EP
35
Channel B Positive Analog Current Output
36, 40
37
Analog Ground
Channel A Negative Analog Current Output
38
Channel A Positive Analog Current Output
—
Exposed Paddle. Connect EP to the common point of all ground planes.
Figure 2
Detailed Description
The MAX5854 dual, high-speed, 10-bit, current-output
DV
AV
DD
DD
DIGITAL
POWER
MANAGEMENT
ANALOG
POWER
MANAGEMENT
DAC provides superior performance in communication
systems requiring low-distortion analog-signal reconstruc-
tion. The MAX5854 combines two DACs and an on-chip
1.24V reference (Figure 2). The current outputs of the
DACs can be configured for differential or single-ended
operation. The full-scale output current range is adjust-
able from 2mA to 20mA to optimize power dissipation and
gain control.
DGND
AGND
CW
MAX5854
DA0
DA1
DA2/G0
DA3/G1
DA4/G2
OUTPA
OUTNA
10-BIT
DACA
DA5/G3
DA6/REN
DA7/IDE
DA8/DACEN
DA9/PD
The MAX5854 accepts an input data and a DAC conver-
sion rate of 165MHz. The inputs are latched on the rising
edge of the clock whereas the output latches on the fol-
lowing rising edge.
G0
G1
G2
G3
CHANNEL A
GAIN
CONTROL
INPUT DATA
INTERLEAVER
IDE
The MAX5854 features three modes of operation: nor-
mal, standby, and power-down (Table 2). These modes
allow efficient power management. In power-down, the
MAX5854 consumes only 1μA of supply current. Wake-up
time from standby mode to normal DAC operation is 3μs.
OPERATING
MODE
CONTROLLER
DACEN
PD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
OUTPB
10-BIT
DACB
Programming the DAC
OUTNB
An 8-bit control word routed through channel A’s data port
programs the gain matching, reference, and the opera-
tional mode of the MAX5854. The control word is latched
on the rising edge of CW. CW is independent of the DAC
clock. The DAC clock can always remain running, when
the control word is written to the DAC. Table 1 and Table
2 represent the control word format and function.
REFO
REFR
DCE
CLKXP
CLKXN
CLK
1.24V REFERENCE
AND CONTROL
AMPLIFIER
CLOCK
DISTRIBUTION
R
CV
DD
SET
CLOCK
POWER
MANAGEMENT
The gain on channel A can be adjusted to achieve gain
matching between two channels in a user’s system. The
gain on channel A can be adjusted from -0.4dB to 0.35dB
in steps of 0.05dB by using bits G3 to G0 (Table 3).
REN
CGND
AGND
Figure 2. Simplified Diagram
Maxim Integrated
│ 11
www.maximintegrated.com
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Table 1. Control Word Format and Function
MSB
LSB
PD
DACEN
IDE
G3
G2
G1
G0
X
X
REN
CONTROL WORD
FUNCTION
PD
Power-Down. The part enters power-down mode if PD = 1.
DAC Enable. When DACEN = 0 and PD = 0, the part enters standby mode.
DACEN
Interleaved Data Mode. IDE = 1 enables the interleaved data mode. In this mode, digital data for both channels
is applied through channel A in a multiplexed fashion. Channel B data is written on the falling edge of the clock
signal and channel A data is written on the rising edge of the clock signal.
IDE
Reference Enable Bit. REN = 0 activates the internal reference. REN = 1 disables the internal reference and
requires the user to apply an external reference between 0.1V to 1.32V.
REN
G3
G2
G1
G0
Bit 3 (MSB) of Gain Adjust Word
Bit 2 of Gain Adjust Word
Bit 1 of Gain Adjust Word
Bit 0 (LSB) of Gain Adjust Word
Device Power-Up and
States of Operation
Table 2. Configuration Modes
MODE
PD DACEN IDE
REN
At power-up, the MAX5854’s default configuration is
internal reference noninterleaved input mode with a gain
of 0dB and a fully operational converter. In shutdown, the
MAX5854 consumes only 1μA of supply current, and in
standby the current consumption is 3.1mA. Wake-up time
from standby mode to normal operation is 3μs.
Normal operation;
noninterleaved inputs;
internal reference active
0
0
0
1
1
1
0
0
1
0
Normal operation;
noninterleaved inputs;
internal reference disabled
1
1
Clock Modes
Normal operation;
interleaved inputs; internal
reference disabled
The MAX5854 allows both single-ended CMOS and dif-
ferential clock mode operation, and supports update rates
of up to 165Msps. These modes are selected through an
active-low control line called DCE. In single-ended clock
mode (DCE = 1), the CLK pin functions as an input, which
accepts a user-provided single-ended clock signal. Data
is written to the converter on the rising edge of the clock.
The DAC outputs (previous data) are updated simultane-
ously on the same edge.
Standby
0
1
0
0
X
1
X
X
X
X
X
X
Power-down
Power-up
X = Don’t care.
If the DCE pin is pulled low, the MAX5854 will operate
in differential clock mode. In this mode, the clock signal
has to be applied to differential clock input pins CLKXP/
CLKXN. The differential input accepts an input range of
Table 3. Gain Difference Setting
GAIN ADJUSTMENT ON
G3
G2
G1
G0
CHANNEL A (dB)
+0.4
0
-0.35
0
1
1
0
0
1
0
0
1
0
0
1
≥0.5V
and a common-mode range of 1V to (CV
-
P-P
DD
0.5V), making the part ideal for low-input amplitude clock
drives. CLKXP/CLKXN also help to minimize the jitter,
and allow the user to connect a crystal oscillator directly
to MAX5854.
Maxim Integrated
│ 12
www.maximintegrated.com
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
AV
DD
OPTIONAL EXTERNAL BUFFER
FOR HEAVIER LOADS
10µF
0.1µF
AGND
MAX4040
1.24V
BANDGAP
REFERENCE
REN = 0
1.24V
BANDGAP
REFERENCE
AV
DD
REN = 1
REFO
MAX6520
CURRENT-
SOURCE
ARRAY
I
FS
EXTERNAL
1.2V
REFERENCE
C
COMP
*
REFO
REFR
I
REF
REFR
AGND
CURRENT-
SOURCE
ARRAY
I
FS
V
REF
I
REF
R
I
=
SET
REF
R
SET
MAX5854
AGND
AGND
R
SET
*COMPENSATION CAPACITOR (C
≈ 100nF).
COMP
MAX5854
AGND
Figure 4. MAX5854 with External Reference
Figure 3. Setting I with the Internal 1.24V Reference and the
FS
Control Amplifier
The CLK pin now becomes an output, and provides a
single-ended replica of the differential clock signal, which
can be used to synchronize the input data. Data is written
to the device on the rising edge of the CLK signal.
External Reference
To disable the internal reference of the MAX5854, set
REN = 1. Apply a temperature-stable, external refer-
ence to drive the REFO pin and set the full-scale output
(Figure 4). For improved accuracy and drift performance,
choose a fixed output voltage reference such as the 1.2V,
25ppm/°C MAX6520 bandgap reference.
Internal Reference and Control Amplifier
The MAX5854 provides an integrated 50ppm/°C, 1.24V,
low-noise bandgap reference that can be disabled and
overridden with an external reference voltage. REFO
serves either as an external reference input or an inte-
grated reference output. If REN = 0, the internal reference
is selected and REFO provides a 1.24V (50μA) output.
Buffer REFO with an external amplifier, when driving a
heavy load.
Detailed Timing
The MAX5854 accepts an input data and the DAC con-
version rate of up to 165Msps. The input latches on the
rising edge of the clock, whereas the output latches on the
following rising edge.
Figure 5 depicts the write cycle of the two DACs in non-
interleaved mode.
The MAX5854 also employs a control amplifier designed
to simultaneously regulate the full-scale output current
The MAX5854 can also operate in an interleaved data
mode. Programming the IDE bit with a high level activates
this mode (Table 1 and Table 2). In interleaved mode,
data for both DAC channels is written through input port
A. Channel B data is written on the falling edge of the
clock signal and then channel A data is written on the fol-
lowing rising edge of the clock signal. Both DAC outputs
(channel A and B) are updated simultaneously on the
next following rising edge of the clock. In interleaved data
mode, the maximum input data rate per channel is half
of the rate in noninterleaved mode. The interleaved data
mode is attractive for applications where lower data rates
are acceptable and interfacing on a single 10-bit bus is
desired (Figure 6).
(I ) for both outputs of the devices. Calculate the output
current as:
FS
I
= 32 x I
REF
FS
where I
is the reference output current (I
= V
/
REF
REF
REFO
R
SET
) and I is the full-scale output current. R
is the
FS
SET
reference resistor that determines the amplifier output cur-
rent of the MAX5854 (Figure 3). This current is mirrored
into the current-source array where I is equally distrib-
FS
uted between matched current segments and summed to
valid output current readings for the DACs.
Maxim Integrated
│ 13
www.maximintegrated.com
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
t
t
CXH
CXL
CLKXN
CLKXP
t
CDL
t
CDH
CLK
OUTPUT
t
CWL
CW
t
t
CW
t
t
DCH
CS
DCS
CONTROL
WORD
DA0–DA9
DACA - 1
DACA
DACA + 1
DACA + 2
DACA + 3
OUTNA
OUTPA
XXXX
(CONTROL WORD DATA)
DACA - 1
DACA
DACA + 1
DACA + 2
DACA + 3
t
t
DCH
DCS
DB0–DB9
DACB - 1
DACB
DACB + 1
DACB + 2
XXXX
DACB + 3
OUTNB
OUTPB
DACB - 1
DACB
DACB + 1
DACB + 2
XXXX
DACB + 3
Figure 5. Timing Diagram for Noninterleaved Data Mode (IDE = 0)
t
t
CXH
CXL
CLKXN
CLKXP
t
t
CDL
CDH
CLK
OUTPUT
t
CWL
CW
t
t
t
t
t
t
CW
DCS
DCH
DCS
DCH
CS
CONTROL
WORD
DA0–DA9
OUTNA
DACA
DACB + 1
DACA + 1
DACB + 2
DACA + 2
DACA - 1
DACA
DACB
DACA + 1
OUTPA
OUTNB
DACB - 1
DACB + 1
OUTPB
Figure 6. Timing Diagram for Interleaved Data Mode (IDE = 1)
Maxim Integrated
│ 14
www.maximintegrated.com
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
AV DV CV
DD
DD
DD
AV DV CV
DD
DD
DD
50Ω
V
,
OUTA
50Ω
SINGLE ENDED
OUTPA
OUTPA
OUTNA
DA0–DA9
DA0–DA9
1/2
MAX5854
1/2
MAX5854
100Ω
10
10
OUTNA
50Ω
50Ω
50Ω
V
OUTB
,
50Ω
SINGLE ENDED
OUTPB
OUTPB
OUTNB
DB0–DB9
DB0–DB9
1/2
MAX5854
1/2
MAX5854
100Ω
10
10
OUTNB
50Ω
50Ω
AGND DGND CGND
AGND DGND CGND
Figure 8. Application with DC-Coupled Differential Outputs
Figure 7. Application with Output Transformer Performing
Differential-to-Single-Ended Conversion
applications, information bandwidth can extend from
10MHz down to several hundred kilohertz. DC-coupling is
desirable to eliminate long discharge time constants that
are problematic with large, expensive coupling capacitors.
Analog quadrature upconverters have a DC common-
mode input requirement of typically 0.7V to 1.0V. The
MAX5854 differential I/Q outputs can maintain the desired
full-scale level at the required 0.7V to 1.0V DC common-
mode level when powered from a single 2.85V (±5%)
supply. The MAX5854 meets this low-power requirement
with minimal reduction in dynamic range while eliminating
the need for level-shifting resistor networks.
Applications Information
Differential-to-Single-Ended Conversion
The MAX5854 exhibits excellent dynamic performance to
synthesize a wide variety of modulation schemes, includ-
ing high-order QAM modulation with OFDM.
Figure 7 shows a typical application circuit with output
transformers performing the required differential-to-sin-
gle-ended signal conversion. In this configuration, the
MAX5854 operates in differential mode, which reduces
even-order harmonics, and increases the available output
power.
Power Supplies, Bypassing,
Decoupling, and Layout
Grounding and power-supply decoupling strongly influ-
ence the MAX5854 performance. Unwanted digital cross-
talk can couple through the input, reference, power-supply,
and ground connections, which can affect dynamic specifi-
cations, like signal-to-noise ratio or spurious-free dynamic
Differential DC-Coupled Configuration
Figure 8 shows the MAX5854 output operating in differ-
ential, DC-coupled mode. This configuration can be used
in communications systems employing analog quadrature
upconverters and requiring a baseband sampling, dual-
channel, high-speed DAC for I/Q synthesis. In these
Maxim Integrated
│ 15
www.maximintegrated.com
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
range. In addition, electromagnetic interference (EMI)
can either couple into or be generated by the MAX5854.
Observe the grounding and power-supply decoupling
guidelines for high-speed, high-frequency applications.
Follow the power supply and filter configuration to realize
optimum dynamic performance.
In this package, the data converter die is attached to an
EP leadframe with the back of this frame exposed at the
package bottom surface, facing the PC board side of the
package. This allows a solid attachment of the package
to the PC board with standard infrared (IR) flow soldering
techniques. A specially created land pattern on the PC
board, matching the size of the EP (4.1mm x 4.1mm),
ensures the proper attachment and grounding of the
DAC. Designing vias* into the land area and implement-
ing large ground planes in the PC board design allows for
highest performance operation of the DAC. Use an array
of 3 x 3 vias (≤ 0.3mm diameter per via hole and 1.2mm
pitch between via holes) for this 40-pin thin QFN-EP pack-
age (package code: T4066-1).
Use of a multilayer printed circuit (PC) board with sepa-
rate ground and power-supply planes is recommended.
Run high-speed signals on lines directly above the ground
plane. The MAX5854 has separate analog and digital
ground buses (AGND, CGND, and DGND, respectively).
Provide separate analog, digital, and clock ground sec-
tions on the PC board with only one point connecting
the three planes. The ground connection points should
be located underneath the device and connected to the
exposed paddle. Run digital signals above the digital
ground plane and analog/clock signals above the analog/
clock ground plane. Digital signals should be kept away
from sensitive analog, clock, and reference inputs. Keep
digital signal paths short and metal trace lengths matched
to avoid propagation delay and data skew mismatch.
Dynamic Performance Parameter Definitions
Adjacent Channel Leakage Ratio (ACLR)
Commonly used in combination with wideband code-
division multiple-access (WCDMA), ACLR reflects the
leakage power ratio in dB between the measured power
within a channel relative to its adjacent channel. ACLR
provides a quantifiable method of determining out-of-band
spectral energy and its influence on an adjacent channel
The MAX5854 includes three separate power-supply
inputs: analog (AV ), digital (DV ), and clock (CV ).
DD
DD
DD
when a bandwidth-limited RF signal passes through a
nonlinear device.
Use a single linear regulator power source to branch
out to three separate power-supply lines (AV , DV
,
DD
DD
CV ) and returns (AGND, DGND, CGND).Filter each
Total Harmonic Distortion (THD)
DD
power-supply line to the respective return line using LC
filters comprising ferrite beads and 10μF capacitors. Filter
each supply input locally with 0.1μF ceramic capacitors to
the respective return lines.
THD is the ratio of the RMS sum of all essential harmon-
ics (within a Nyquist window) of the input signal to the
fundamental itself. This can be expressed as:
2
2
2
2
Note: To maintain the dynamic performance of the
Electrical Characteristics, ensure the voltage dif-
V
+ V + V ... + ...V
3 4 N
)
(
2
THD = 20 ×log
V
ference between DV , AV , and CV does not
1
DD
DD
DD
exceed 150mV.
where V is the fundamental amplitude, and V through
1
2
Thermal Characteristics and Packaging
V
N
are the amplitudes of the 2nd through Nth order har-
Thermal Resistance
monics. The MAX5854 uses the first seven harmonics for
this calculation.
40-lead thin QFN-EP:
θ
JA
= 38°C/W
Spurious-Free Dynamic Range (SFDR)
The MAX5854 is packaged in a 40-pin thin QFN-EP
package, providing greater design flexibility, increased
thermal efficiency, and optimized AC performance of the
DAC. The EP enables the implementation of grounding
techniques, which are necessary to ensure highest per-
formance operation.
SFDR is the ratio of RMS amplitude of the carrier fre-
quency (maximum signal component) to the RMS value
of their next-largest spectral component. SFDR is usually
measured in dBc with respect to the carrier frequency
amplitude or in dBFS with respect to the DAC’s full-scale
range. Depending on its test condition, SFDR is observed
within a predefined window or to Nyquist.
*Vias connect the land pattern to internal or external copper planes.
Maxim Integrated
│ 16
www.maximintegrated.com
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Multitone Power Ratio (MTPR)
Gain Error
A series of equally spaced tones are applied to the DAC
with one tone removed from the center of the range.
MTPR is defined as the worst-case distortion (usually a
3rd-order harmonic product of the fundamental frequen-
cies), which appears as the largest spur at the frequency
of the missing tone in the sequence. This test can be per-
formed with any number of input tones; however, four and
eight tones are among the most common test conditions
for CDMA- and GSM/EDGE-type applications.
A gain error is the difference between the ideal and the
actual full-scale output current on the transfer curve, after
nullifying the offset error. This error alters the slope of the
transfer function and corresponds to the same percent-
age error in each step. The ideal current is defined by
reference voltage at V
/I
x 32.
REFO REF
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles to its new
output value to within the converter’s specified accuracy.
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc of either
output tone to the worst 3rd-order (or higher) IMD products.
Glitch Impulse
A glitch is generated when a DAC switches between two
codes. The largest glitch is usually generated around the
midscale transition, when the input pattern transitions
from 011…111 to 100…000. This occurs due to timing
variations between the bits. The glitch impulse is found
by integrating the voltage of the glitch at the midscale
transition over time. The glitch impulse is usually speci-
fied in pV-s.
Static Performance Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a line drawn between the
end points of the transfer function, once offset and gain
errors have been nullified. For a DAC, the deviations are
measured at every individual step.
Table 4. Part Selection Table
Differential Nonlinearity (DNL)
PART
SPEED (Msps)
RESOLUTION
8-bit, dual
Differential nonlinearity (DNL) is the difference between
an actual step height and the ideal value of 1 LSB. A DNL
error specification no more negative than -1 LSB guaran-
tees monotonic transfer function.
MAX5851
MAX5852
MAX5853
MAX5854
80
165
80
8-bit, dual
10-bit, dual
10-bit, dual
Offset Error
165
Offset error is the current flowing from positive DAC out-
put when the digital input code is set to zero. Offset error
is expressed in LSBs.
Chip Information
TRANSISTOR COUNT: 9,035
PROCESS: CMOS
Maxim Integrated
│ 17
www.maximintegrated.com
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2004 Maxim Integrated Products, Inc.
│ 18
相关型号：
MAX5854ETL+T
D/A Converter, 2 Func, Parallel, Word Input Loading, 0.012us Settling Time, 6 X 6 MM, 0.8 MM HEIGHT, TQFN-40
MAXIM
MAX5854ETL-T
D/A Converter, 2 Func, Parallel, Word Input Loading, 0.012us Settling Time, 6 X 6 MM, 0.8 MM HEIGHT, TQFN-40
MAXIM
MAX5855EXE
16-Bit, 4.9Gsps Wideband Interpolating and Modulating RF DAC with JESD204B Interface
MAXIM
MAX5855EXET
16-Bit, 4.9Gsps Wideband Interpolating and Modulating RF DAC with JESD204B Interface
MAXIM
MAX5856AECM-D
D/A Converter, 1 Func, Parallel, Word Input Loading, 0.011us Settling Time, PQFP48, 7 X 7 MM, 1 MM HEIGHT, MO-136AE, TQFP-48
MAXIM
©2020 ICPDF网 联系我们和版权申明