MAX5854ETL+T [MAXIM]
D/A Converter, 2 Func, Parallel, Word Input Loading, 0.012us Settling Time, 6 X 6 MM, 0.8 MM HEIGHT, TQFN-40;
| 型号： | MAX5854ETL+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 2 Func, Parallel, Word Input Loading, 0.012us Settling Time, 6 X 6 MM, 0.8 MM HEIGHT, TQFN-40 |
| 文件： | 总18页 (文件大小：446K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3197; Rev 0; 2/04
Dual, 10-Bit, 165Msps, Current-Output DAC
General Description
Features
The MAX5854 dual, 10-bit, 165Msps digital-to-analog
converter (DAC) provides superior dynamic performance
in wideband communication systems. The device inte-
grates two 10-bit DAC cores, and a 1.24V reference. The
MAX5854 supports single-ended and differential modes
of operation. The dynamic performance is maintained
over the entire 2.7V to 3.6V power-supply operating
range. The analog outputs support a -1.0V to +1.25V
compliance voltage.
♦ 10-Bit, 165Msps Dual DAC
♦ Low Power
190mW with I = 20mA at f
= 165MHz
FS
CLK
♦ 2.7V to 3.6V Single Supply
♦ Full Output Swing and Dynamic Performance at
2.7V Supply
♦ Superior Dynamic Performance
73dBc SFDR at f
= 40MHz
OUT
The MAX5854 can operate in interleaved data mode to
reduce the I/O pin count. This allows the converter to
be updated on a single, 10-bit bus.
UMTS ACLR = 65.5dB at f
= 30.7MHz
OUT
♦ Programmable Channel Gain Matching
♦ Integrated 1.24V Low-Noise Bandgap Reference
♦ Single-Resistor Gain Control
The MAX5854 features digital control of channel gain
matching to within 0.4dꢀ in siꢁteen 0.05dꢀ steps.
Channel matching improves sideband suppression in
analog quadrature modulation applications. The on-
chip 1.24V bandgap reference includes a control
amplifier that allows eꢁternal full-scale adjustments of
both channels through a single resistor. The internal ref-
erence can be disabled and an eꢁternal reference may
be applied for high-accuracy applications.
♦ Interleaved Data Mode
♦ Single-Ended and Differential Clock Input Modes
♦ Miniature 40-Pin Thin QFN Package, 6mm x 6mm
♦ EV Kit Available—MAX5854 EV Kit
The MAX5854 features full-scale current outputs of 2mA
to 20mA and operates from a 2.7V to 3.6V single sup-
ply. The DAC supports three modes of power-control
operation: normal, low-power standby, and complete
power-down. In power-down mode, the operating
current is reduced to 1µA.
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX5854ETL
*EP = Exposed paddle.
-40°C to +85°C
40 Thin QFN-EP*
The MAX5854 is packaged in a 40-pin thin QFN with
eꢁposed paddle (EP) and is specified for the eꢁtended
(-40°C to +85°C) temperature range.
Pin Configuration
TOP VIEW
Pin-compatible, lower speed, and lower resolution ver-
sions are also available. Refer to the MAX5853 (10-bit,
80Msps), the MAX5852** (8-bit, 165Msps), and the
MAX5851** (8-bit, 80Msps) data sheets for more informa-
tion. See Table 4 at the end of the data sheet.
40 39 38 37 36 35 34 33
32 31
30
29
DA9/PD
DA8/DACEN
DA7/IDE
DA6/REN
DA5/G3
DA4/G2
DA3/G1
DA2/G0
DA1
CV
DD
1
2
EP
CGND
3
28 CLK
Applications
4
27
26
25
24
23
22
21
CV
DD
5
CLKXN
CLKXP
DCE
Communications
MAX5854
6
SatCom, LMDS, MMDS, HFC, DSL, WLAN,
Point-to-Point Microwave Links
7
8
CW
Wireless ꢀase Stations
Quadrature Modulation
Direct Digital Synthesis (DDS)
Instrumentation/ATE
9
DB0
10
DA0
DB1
11
16 17 18 19 20
15
12
13 14
THIN QFN
**Future product—contact factory for availability.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual, 10-Bit, 165Msps, Current-Output DAC
ABSOLUTE MAXIMUM RATINGS
AV , DV , CV to AGND, DGND, CGND .........-0.3V to +4V
AGND to DGND, DGND to CGND,
DD
DD
DD
AGND to CGND..................................................-0.3V to +0.3V
Maximum Current into Any Pin
(excluding power supplies) ............................................ 50mA
DA9–DA0, DB9–DB0, CW, DCE to AGND,
DGND, CGND .......................................................-0.3V to +4V
CLKXN, CLKXP to CGND.........................................-0.3V to +4V
OUTP_, OUTN_ to AGND.......................-1.25V to (AV
CLK to DGND ..........................................-0.3V to (DV
REFR, REFO to AGND .............................-0.3V to (AV
Continuous Power Dissipation (T = +70°C)
+ 0.3V)
+ 0.3V)
+ 0.3V)
A
DD
DD
DD
40-Pin Thin QFN-EP (derate 23.3mW/°C
above +70°C)...............................................................1.860W
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
= DV
= CV
= 3V, AGND = DGND = CGND = 0, f
= 165Msps, differential clock, external reference, V
= 1.2V,
REF
DD
DD
DD
DAC
I
FS
= 20mA, output amplitude = 0dB FS, differential output, T = T
to T
, unless otherwise noted. T ≥ +25°C guaranteed by
MAX A
A
MIN
production test. T < +25°C guaranteed by design and characterization. Typical values are at T = +25°C.)
A
A
PARAMETER
STATIC PERFORMANCE
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
N
10
Bits
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
DNL
R = 0
L
-1.0
0.25
0.2
+1.0
+0.5
+0.5
+6.8
+4.10
Guaranteed monotonic, R = 0
L
-0.5
V
-0.5
0.1
OS
Internal reference (Note1)
External reference
Internal reference
-11.0
-6.25
1.5
Gain Error (See Also Gain Error
Definition Section)
GE
%FSR
0.7
150
100
Gain-Error Temperature Drift
ppm/°C
External reference
DYNAMIC PERFORMANCE
f
f
f
f
f
f
= 10MHz
= 20MHz
= 40MHz
= 10MHz
= 20MHz
= 30MHz
69.4
78
77
73
77
77
76
OUT
OUT
OUT
OUT
OUT
OUT
f
A
= 165MHz,
CLK
= -1dBFS
OUT
Spurious-Free Dynamic Range to
Nyquist
SFDR
dBc
f
A
= 100MHz,
CLK
= -1dBFS
OUT
f
A
= 25MHz,
CLK
f
= 1MHz
79
83
84
82
74
OUT
= -1dBFS
OUT
f
= 165MHz, f
= 10MHz,
CLK
OUT
A
= -1dBFS, span = 10MHz
OUT
Spurious-Free Dynamic Range
Within a Window
f
= 100MHz, f
= 5MHz,
CLK
OUT
SFDR
MTPR
dBc
dBc
A
= -1dBFS, span = 4MHz
OUT
f
= 25MHz, f
= 1MHz,
CLK
OUT
A
= -1dBFS, span = 2MHz
OUT
8 tones at 400kHz spacing, f
= 78MHz,
CLK
Multitone Power Ratio to Nyquist
f
= 15MHz to 18.2MHz
OUT
2
_______________________________________________________________________________________
Dual, 10-Bit, 165Msps, Current-Output DAC
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= CV
= 3V, AGND = DGND = CGND = 0, f
= 165Msps, differential clock, external reference, V
= 1.2V,
REF
DD
DD
DD
DAC
I
FS
= 20mA, output amplitude = 0dB FS, differential output, T = T
to T
, unless otherwise noted. T ≥ +25°C guaranteed by
MAX A
A
MIN
production test. T < +25°C guaranteed by design and characterization. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
8 tones at 2.1MHz spacing,
Multitone Spurious-Free Dynamic
Range Within a Window
f
= 165MHz, f
= 28.3MHz to 45.2MHz,
70
dBc
CLK
OUT
span = 50MHz
Adjacent Channel Power Ratio
with UMTS
f
f
= 30.72MHz, RBW = 30kHz,
= 122.88MHz
OUT
CLK
ACLR
65.5
dB
f
f
f
f
f
f
= 10MHz
= 20MHz
= 40MHz
= 10MHz
= 20MHz
= 30MHz
-76
-74
-71
-75
-74
-73
OUT
OUT
OUT
OUT
OUT
OUT
f
A
= 165MHz,
CLK
= -1dBFS
OUT
Total Harmonic Distortion to
Nyquist (2nd- Through 8th-Order
Harmonics Included)
THD
dBc
f
A
= 100MHz,
CLK
= -1dBFS
OUT
f
A
= 25MHz,
CLK
f
= 1MHz
-76
90
OUT
= -1dBFS
OUT
Output Channel-to-Channel
Isolation
f
f
f
= 10MHz
dB
dB
OUT
OUT
OUT
Channel-to-Channel Gain
Mismatch
= 10MHz, G[3:0] = 1000
= 10MHz
0.025
0.05
Channel-to-Channel Phase
Mismatch
Degrees
f
= 165MHz, f
= 10MHz, I = 20mA
60.5
61
CLK
OUT
FS
f
= 165MHz, f
= 10MHz, I = 5mA
OUT FS
CLK
CLK
CLK
Signal-to-Noise Ratio to Nyquist
Maximum DAC Conversion Rate
SNR
dB
f
f
= 65MHz, f
= 65MHz, f
= 10MHz, I = 20mA
62
OUT
OUT
FS
= 10MHz, I = 5mA
62
FS
Interleaved mode disabled, IDE = 0
Interleaved mode enabled, IDE = 1
165
200
100
5
f
Msps
DAC
82.5
Glitch Impulse
pV-s
ns
Output Settling Time
Output Rise Time
t
To 0.1% error band (Note 3)
10% to 90% (Note 3)
12
S
2.2
2.2
ns
Output Fall Time
90% to 10% (Note 3)
ns
ANALOG OUTPUT
Full-Scale Output Current Range
I
2
-1.00
-5
20
+1.25
+5
mA
V
FS
Output Voltage Compliance
Range
Output Leakage Current
Shutdown or standby mode
µA
REFERENCE
Internal-Reference Output
Voltage
V
REN = 0
1.13
1.24
1.32
V
REFO
_______________________________________________________________________________________
3
Dual, 10-Bit, 165Msps, Current-Output DAC
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= CV
= 3V, AGND = DGND = CGND = 0, f
= 165Msps, differential clock, external reference, V
= 1.2V,
REF
DD
DD
DD
DAC
I
FS
= 20mA, output amplitude = 0dB FS, differential output, T = T
to T
, unless otherwise noted. T ≥ +25°C guaranteed by
MAX A
A
MIN
production test. T < +25°C guaranteed by design and characterization. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Internal-Reference Supply
Rejection
AV
varied from 2.7V to 3.6V
0.5
mV/V
DD
Internal-Reference Output-
Voltage Temperature Drift
TCV
REN = 0
REN = 0
REN = 1
50
50
ppm/°C
REFO
Internal-Reference Output Drive
Capability
µA
External-Reference Input Voltage
Range
0.10
1.2
32
1.32
V
Current Gain
I
/I
mA/mA
FS REF
LOGIC INPUTS (DA9–DA0, DB9–DB0, CW)
0.65 x
Digital Input-Voltage High
Digital Input-Voltage Low
V
V
V
IH
DV
DD
0.3 x
V
IL
DV
DD
Digital Input Current
I
-1
+1
µA
pF
IN
Digital Input Capacitance
C
3
IN
SINGLE-ENDED CLOCK INPUT/OUTPUT AND DCE INPUT (CLK, DCE)
0.65 x
CV
Digital Input-Voltage High
Digital Input-Voltage Low
V
DCE = 1
DCE = 1
V
V
IH
DD
0.3 x
CV
V
IL
DD
Digital Input Current
I
DCE = 1
DCE = 1
-1
+1
µA
pF
IN
Digital Input Capacitance
C
3
IN
0.9 x
CV
Digital Output-Voltage High
Digital Output-Voltage Low
V
DCE = 0, I
= 0.5mA, Figure 1
SOURCE
V
V
OH
DD
0.1 x
CV
V
DCE = 0, I = 0.5mA, Figure 1
SINK
OL
DD
DIFFERENTIAL CLOCK INPUTS (CLKXP/CLKXN)
Differential Clock Input Internal
Bias
CV /2
DD
V
Differential Clock Input Swing
0.5
V
Clock Input Impedance
Measured single ended
5
kΩ
POWER REQUIREMENTS
Analog Power-Supply Voltage
Digital Power-Supply Voltage
Clock Power-Supply Voltage
AV
DV
CV
2.7
2.7
2.7
3
3
3
3.6
V
V
V
DD
DD
DD
3.6
3.6
4
_______________________________________________________________________________________
Dual, 10-Bit, 165Msps, Current-Output DAC
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= CV
= 3V, AGND = DGND = CGND = 0, f
= 165Msps, differential clock, external reference, V
= 1.2V,
REF
DD
DD
DD
DAC
I
FS
= 20mA, output amplitude = 0dB FS, differential output, T = T
to T
, unless otherwise noted. T ≥ +25°C guaranteed by
MAX A
A
MIN
production test. T < +25°C guaranteed by design and characterization. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
= 20mA (Note 2), single-ended clock
FS
43.2
46
mode
I
I
= 20mA (Note 2), differential clock mode
= 2mA (Note 2), single-ended clock mode
43.2
5
FS
FS
Analog Supply Current
I
mA
AVDD
I
I
= 2mA (Note 2), differential clock mode
= 20mA (Note 2), single-ended clock
5
FS
FS
6.2
7.5
mode
Digital Supply Current
Clock Supply Current
I
I
mA
mA
DVDD
I
= 20mA (Note 2), differential clock mode
6.2
13.7
24
FS
Single-ended clock mode (DCE = 1) (Note 2)
Differential clock mode (DCE = 0) (Note 2)
16.5
3.7
CVDD
Total Standby Current
Total Shutdown Current
I
I
I
+ I + I
DVDD CVDD
3.1
mA
µA
STANDBY
AVDD
AVDD
I
+ I
DVDD
+ I
CVDD
1
SHDN
I
I
I
I
= 20mA (Note 2)
= 2mA (Note 2)
= 20mA (Note 2)
= 2mA (Note 2)
190
75
210
FS
FS
FS
FS
Single-ended clock
mode (DCE = 1)
220
106
9.3
Differential clock
mode (DCE = 0)
Total Power Dissipation
P
mW
TOT
Standby
11.1
Shutdown
0.003
TIMING CHARACTERISTICS (Figure 5, Figure 6)
Propagation Delay
Clock
cycles
1
Single-ended clock mode (DCE = 1) (Note 4)
Differential clock mode (DCE = 0) (Note 4)
Single-ended clock mode (DCE = 1) (Note 4)
Differential clock mode (DCE = 0) (Note 4)
1.2
2.7
0.8
-0.5
DAC Data to CLK Rise/Fall Setup
Time
t
ns
ns
ns
ns
DCS
DAC Data to CLK Rise/Fall Hold
Time
t
DCH
Control Word to CW Rise Setup
Time
t
2.5
2.5
CS
Control Word to CW Rise Hold
Time
t
CW
CW High Time
CW Low Time
t
5
5
ns
ns
CWH
t
CWL
DACEN = 1 to V
(Coming Out of Standby)
Stable Time
OUT
t
3
µs
STB
_______________________________________________________________________________________
5
Dual, 10-Bit, 165Msps, Current-Output DAC
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= CV
= 3V, AGND = DGND = CGND = 0, f
= 165Msps, differential clock, external reference, V
= 1.2V,
REF
DD
DD
DD
DAC
I
FS
= 20mA, output amplitude = 0dB FS, differential output, T = T
to T
, unless otherwise noted. T ≥ +25°C guaranteed by
MAX A
A
MIN
production test. T < +25°C guaranteed by design and characterization. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PD = 0 to V
(Coming Out of Power-Down)
Stable Time
OUT
t
500
µs
SHDN
Maximum Clock Frequency at
CLKXP/CLKXN Input
f
165
200
MHz
CLK
Clock High Time
Clock Low Time
t
CLKXP or CLKXN input
1.5
1.5
ns
ns
CXH
t
CLKXP or CLKXN input
CXL
CLKXP Rise to CLK Output Rise
Delay
t
DCE = 0
2.7
2.7
ns
ns
CDH
CLKXP Fall to CLK Output Fall
Delay
t
DCE = 0
CDL
Note 1: Including the internal reference voltage tolerance and reference amplifier offset.
Note 2: f = 165Msps, f = 10MHz.
DAC
OUT
Note 3: Measured single-ended with 50Ω load and complementary output connected to AGND.
Note 4: Guaranteed by design, not production tested.
0.5mA
TO OUTPUT
1.6V
PIN
5pF
0.5mA
Figure 1. Load Test Circuit for CLK Outputs
6
_______________________________________________________________________________________
Dual, 10-Bit, 165Msps, Current-Output DAC
Typical Operating Characteristics
(AV
= DV
= CV
= 3V, AGND = DGND = CGND = 0, external reference, differential clock, I = 20mA, differential output, T =
DD
DD
DD FS A
+25°C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
= 25MHz)
CLK
90
85
80
75
70
65
60
55
50
45
40
35
30
90
85
80
75
70
65
60
55
50
45
40
35
30
90
85
80
75
70
65
60
55
50
45
40
35
30
0dBFS
0dBFS
0dBFS
-6dBFS
-12dBFS
-6dBFS
-6dBFS
-12dBFS
-12dBFS
1
3
5
7
9
11
13
50
0
10 20 30 40 50 60 70 80 90
(MHz)
0
5
10 15 20 25 30 35 40 45
(MHz)
f (MHz)
OUT
f
f
OUT
OUT
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
= 165MHz)
CLK
90
85
80
75
70
65
60
55
50
45
40
35
30
90
85
80
75
70
65
60
55
50
45
40
35
30
90
85
80
75
70
65
60
55
50
45
40
35
30
AV = DV = CV = 3.3V
DD
DD
DD
I
= 20mA
OUT
0dBFS
I
= 5mA
OUT
AV = DV = CV = 3.6V
DD
DD
DD
AV = DV = CV = 2.7V
I
= 10mA
DD
DD
DD
OUT
-6dBFS
AV = DV = CV = 3V
DD
-12dBFS
DD
DD
0
10 20 30 40 50 60 70 80 90
(MHz)
0
10 20 30 40 50 60 70 80 90
(MHz)
0
10 20 30 40 50 60 70 80 90 100
(MHz)
f
f
OUT
f
OUT
OUT
SFDR vs. TEMPERATURE (f
= 165MHz,
TWO-TONE INTERMODULATION DISTORTION
(f = 165MHz, 1MHz WINDOW)
CLK
f
= 10MHz, A
= 0dBFS)
OUT
OUT
CLK
80.0
79.5
79.0
78.5
78.0
77.5
77.0
76.5
76.0
75.5
75.0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f
f
= 4.8541MHz
= 5.0555MHz
OUT1
OUT2
f
f
OUT2
OUT1
2f
- f
OUT1 OUT2
2f
- f
OUT2 OUT1
-40
-15
10
35
60
85
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
(MHz)
TEMPERATURE (°C)
f
OUT
_______________________________________________________________________________________
7
Dual, 10-Bit, 165Msps, Current-Output DAC
Typical Operating Characteristics (continued)
(AV
= DV
= CV
= 3V, AGND = DGND = CGND = 0, external reference, differential clock, I = 20mA, differential output, T
A
=
DD
DD
DD
FS
+25°C, unless otherwise noted.)
8-TONE SFDR PLOT
= 165MHz, 35MHz WINDOW)
SINGLE-TONE SFDR
= 100MHz, 4MHz WINDOW)
SINGLE-TONE SFDR
= 165MHz, 10MHz WINDOW)
(f
CLK
(f
CLK
(f
CLK
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f
= 5.0533MHz
f
= 9.1040MHz
= -1dBFS
OUT1
OUT1
f
f
T4
T5
A
= -1dBFS
A
OUT
OUT
f
T6
f
T3
f
T2
f
T7
f
f
T1
T8
39.7
34.7
4.7 9.7 14.7
24.7 29.7
(MHz)
19.7
5.0
5.5 6.0 6.5
(MHz)
7.0
3.0 3.5 4.0
4.5
f
4
5
6
8
f
9
10
13 14
11 12
7
f
OUT
(MHz)
OUT
OUT
f
f
f
f
= 17.493MHz
f
= 24.035MHz
= 25.087MHz
= 26.741MHz
= 27.869MHz
T1
T2
T3
T4
T5
T6
T7
T8
= 18.997MHz
= 20.200MHz
= 21.253MHz
f
f
f
SINGLE-TONE SFDR
= 78MHz, 20MHz WINDOW)
SINGLE-TONE SFDR
= 25MHz, 2MHz WINDOW)
(f
(f
CLK
CLK
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
f
= 11.0333MHz
= -1dBFS
f
= 1.0152MHz
= -1dBFS
OUT
OUT
OUT
OUT
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
A
A
21.0
1.0
5.0
13.0
(MHz)
17.0
1.9
9.0
f
0.1 0.4 0.6 0.9 1.1 1.4 1.6
(MHz)
f
OUT
OUT
SINGLE-TONE FFT PLOT (f
= 165MHz,
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
CLK
f
= 10MHz, A
= 0dBFS, NYQUIST WINDOW)
OUT
OUT
0
0.5
0.4
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
82.5
0.5
8.2MHz/div
0
150 300 450 600 750 900 1050
DIGITAL INPUT CODE
f
(MHz)
OUT
8
_______________________________________________________________________________________
Dual, 10-Bit, 165Msps, Current-Output DAC
Typical Operating Characteristics (continued)
(AV
= DV
= CV
= 3V, AGND = DGND = CGND = 0, external reference, differential clock, I = 20mA, differential output, T =
DD
DD
DD FS A
+25°C, unless otherwise noted.)
POWER DISSIPATION vs. CLOCK FREQUENCY
(f = 10MHz, A = 0dBFS)
POWER DISSIPATION vs. SUPPLY VOLTAGES
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
(f
= 165MHz, f = 10MHz)
OUT
OUT
CLK
OUT
230
220
210
200
190
180
170
160
150
300
280
260
240
220
200
180
160
160
0.5
0.4
0.3
DIFFERENTIAL
CLOCK DRIVE
DIFFERENTIAL
CLOCK DRIVE
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
SINGLE-ENDED
CLOCK DRIVE
SINGLE-ENDED
CLOCK DRIVE
20
45
70
95
120
145
170
2.70 2.85 3.00 3.15 3.30 3.45 3.60
SUPPLY VOLTAGES (V)
0
150 300 450 600 750 900 1050
DIGITAL INPUT CODE
f
(MHz)
CLK
REFERENCE VOLTAGE vs. SUPPLY VOLTAGES
(f = 165MHz, f = 10MHz)
REFERENCE VOLTAGE vs. TEMPERATURE
DYNAMIC RESPONSE RISE TIME
CLK
OUT
MAX5854 toc21
1.25
1.24
1.23
1.22
1.21
1.20
1.19
1.22230
1.22230
1.22230
1.22200
1.22190
1.22180
1.22170
1.22160
1.22150
100mV/div
-40
-15
10
35
60
85
10ns/div
2.70 2.85 3.00 3.15 3.30 3.45 3.60
SUPPLY VOLTAGES (V)
TEMPERATURE (°C)
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
= 165MHz)
CLK
DYNAMIC RESPONSE FALL TIME
(f
= 30.72MHz)
CLK
MAX5854 toc22
90
85
80
75
70
65
60
55
50
45
40
35
30
-20
-30
ACLR = 65.5dB
0dBFS
-40
100mV/div
-50
-60
-70
-6dBFS
-80
-12dBFS
-90
-100
-110
-120
-130
-140
SINGLE-ENDED
CLOCK DRIVE
0
10 20 30 40 50 60 70 80 90
(MHz)
23.38
1.468MHz/div
(MHz)
38.06
10ns/div
f
OUT
f
OUT
_______________________________________________________________________________________
9
Dual, 10-Bit, 165Msps, Current-Output DAC
Pin Description
PIN
1
NAME
FUNCTION
Channel A Input Data Bit 9 (MSB)/Power-Down
DA9/PD
2
DA8/DACEN Channel A Input Data Bit 8/DAC Enable Control
3
DA7/IDE
Channel A Input Data Bit 7/Interleaved Data Enable
Channel A Input Data Bit 6/Reference Enable. Setting REN = 0 enables the internal reference. Setting
REN = 1 disables the internal reference.
4
DA6/REN
5
DA5/G3
DA4/G2
DA3/G1
DA2/G0
DA1
Channel A Input Data Bit 5/Channel A Gain Adjustment Bit 3
Channel A Input Data Bit 4/Channel A Gain Adjustment Bit 2
Channel A Input Data Bit 3/Channel A Gain Adjustment Bit 1
Channel A Input Data Bit 2/Channel A Gain Adjustment Bit 0
Channel A Input Data Bit 1
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
DA0
Channel A Input Data Bit 0 (LSB)
DB9
Channel B Input Data Bit 9 (MSB)
DB8
Channel B Input Data Bit 8
DB7
Channel B Input Data Bit 7
DB6
Channel B Input Data Bit 6
DB5
Channel B Input Data Bit 5
DV
Digital Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more details.
Digital Ground
DD
DGND
DB4
DB3
DB2
DB1
DB0
CW
Channel B Input Data Bit 4
Channel B Input Data Bit 3
Channel B Input Data Bit 2
Channel B Input Data Bit 1
Channel B Input Data Bit 0 (LSB)
Active-Low Control Word Write Pulse. The control word is latched on the rising edge of CW.
Active-Low Differential Clock Enable Input. Drive DCE low to enable the differential clock inputs
CLKXP and CLKXN. Drive DCE high to disable the differential clock inputs and enable the single-
ended CLK input.
24
25
DCE
Positive Differential Clock Input. With DCE = 0, CLKXP and CLKXN are enabled. With DCE = 1, CLKXP
and CLKXN are disabled. Connect CLKXP to CGND when the differential clock is disabled.
CLKXP
CLKXN
Negative Differential Clock Input. With DCE = 0, CLKXP and CLKXN are enabled. With DCE = 1, CLKXP
26
and CLKXN are disabled. Connect CLKXN to CV
when the differential clock is disabled.
DD
Clock Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more
27, 30
CV
DD
Single-Ended Clock Input/Output. With the differential clock disabled (DCE = 1), CLK becomes a
single-ended conversion clock input. With the differential clock enabled (DCE = 0), CLK is a single-
ended output that mirrors the differential clock inputs CLKXP and CLKXN. See the Clock Modes section
for more information on CLK.
28
CLK
29
31
CGND
REFO
Clock Ground
Reference Input/Output. REFO serves as a reference input when the internal reference is disabled. If the
internal 1.24V reference is enabled, REFO serves as an output for the internal reference. When the
internal reference is enabled, bypass REFO to AGND with a 0.1µF capacitor
10 ______________________________________________________________________________________
Dual, 10-Bit, 165Msps, Current-Output DAC
Pin Description (continued)
PIN
NAME
FUNCTION
Full-Scale Current Adjustment. To set the output full-scale current, connect an external resistor RSET
32
REFR
between REFR and AGND. The output full-scale current is equal to 32 x V
/R
.
REFO SET
33, 39
34
AV
Analog Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more details.
Channel B Negative Analog Current Output
DD
OUTNB
OUTPB
AGND
OUTNA
OUTPA
EP
35
Channel B Positive Analog Current Output
36, 40
37
Analog Ground
Channel A Negative Analog Current Output
38
Channel A Positive Analog Current Output
—
Exposed Paddle. Connect EP to the common point of all ground planes.
Detailed Description
DV
AV
The MAX5854 dual, high-speed, 10-bit, current-output
DAC provides superior performance in communication
systems requiring low-distortion analog-signal recon-
struction. The MAX5854 combines two DACs and an on-
chip 1.24V reference (Figure 2). The current outputs of
the DACs can be configured for differential or single-
ended operation. The full-scale output current range is
adjustable from 2mA to 20mA to optimize power dissipa-
tion and gain control.
DD
DD
DIGITAL
ANALOG
POWER
POWER
MANAGEMENT
MANAGEMENT
DGND
CW
AGND
MAX5854
DA0
DA1
DA2/G0
DA3/G1
DA4/G2
DA5/G3
DA6/REN
DA7/IDE
DA8/DACEN
DA9/PD
OUTPA
OUTNA
10-BIT
DACA
The MAX5854 accepts an input data and a DAC con-
version rate of 165MHz. The inputs are latched on the
rising edge of the clock whereas the output latches on
the following rising edge.
G0
CHANNEL A
GAIN
CONTROL
G1
G2
G3
The MAX5854 features three modes of operation: normal,
standby, and power-down (Table 2). These modes allow
efficient power management. In power-down, the
MAX5854 consumes only 1µA of supply current. Wake-up
time from standby mode to normal DAC operation is 3µs.
INPUT DATA
IDE
INTERLEAVER
OPERATING
MODE
CONTROLLER
DACEN
PD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
Programming the DAC
An 8-bit control word routed through channel A’s data
port programs the gain matching, reference, and the
operational mode of the MAX5854. The control word is
latched on the rising edge of CW. CW is independent
of the DAC clock. The DAC clock can always remain
running, when the control word is written to the DAC.
Table 1 and Table 2 represent the control word format
and function.
OUTPB
OUTNB
10-BIT
DACB
REFO
REFR
DCE
CLKXP
CLKXN
CLK
1.24V REFERENCE
AND CONTROL
AMPLIFIER
CLOCK
DISTRIBUTION
The gain on channel A can be adjusted to achieve gain
matching between two channels in a user’s system.
The gain on channel A can be adjusted from -0.4dB to
0.35dB in steps of 0.05dB by using bits G3 to G0 (see
Table 3).
R
CV
DD
SET
CLOCK
POWER
MANAGEMENT
REN
CGND
AGND
Figure 2. Simplified Diagram
______________________________________________________________________________________ 11
Dual, 10-Bit, 165Msps, Current-Output DAC
Table 1. Control Word Format and Function
MSB
LSB
PD
DACEN
IDE
REN
G3
G2
G1
G0
X
X
CONTROL WORD
FUNCTION
Power-Down. The part enters power-down mode if PD = 1.
DAC Enable. When DACEN = 0 and PD = 0, the part enters standby mode.
Interleaved Data Mode. IDE = 1 enables the interleaved data mode. In this mode, digital data for both
PD
DACEN
IDE
channels is applied through channel A in a multiplexed fashion. Channel B data is written on the falling edge
of the clock signal and channel A data is written on the rising edge of the clock signal.
Reference Enable Bit. REN = 0 activates the internal reference. REN = 1 disables the internal reference and
requires the user to apply an external reference between 0.1V to 1.32V.
REN
G3
G2
G1
G0
Bit 3 (MSB) of Gain Adjust Word
Bit 2 of Gain Adjust Word
Bit 1 of Gain Adjust Word
Bit 0 (LSB) of Gain Adjust Word
Table 2. Configuration Modes
Device Power-Up and
States of Operation
MODE
PD DACEN IDE
REN
At power-up, the MAX5854’s default configuration is
internal reference noninterleaved input mode with a gain
of 0dB and a fully operational converter. In shutdown,
the MAX5854 consumes only 1µA of supply current, and
in standby the current consumption is 3.1mA. Wake-up
time from standby mode to normal operation is 3µs.
Normal operation;
noninterleaved inputs;
internal reference active
0
1
0
0
Normal operation;
noninterleaved inputs;
internal reference disabled
0
0
1
1
0
1
1
1
Clock Modes
The MAX5854 allows both single-ended CMOS and dif-
ferential clock mode operation, and supports update
rates of up to 165Msps. These modes are selected
through an active-low control line called DCE. In single-
ended clock mode (DCE = 1), the CLK pin functions as
an input, which accepts a user-provided single-ended
clock signal. Data is written to the converter on the rising
edge of the clock. The DAC outputs (previous data) are
updated simultaneously on the same edge.
Normal operation;
interleaved inputs; internal
reference disabled
Standby
0
1
0
0
X
1
X
X
X
X
X
X
Power-down
Power-up
X = Don’t care.
If the DCE pin is pulled low, the MAX5854 will operate in
differential clock mode. In this mode, the clock signal has
to be applied to differential clock input pins
CLKXP/CLKXN. The differential input accepts an input
Table 3. Gain Difference Setting
GAIN ADJUSTMENT ON
G3
G2
G1
G0
range of ≥0.5V
and a common-mode range of 1V to
CHANNEL A (dB)
P-P
(CV
- 0.5V), making the part ideal for low- input ampli-
DD
+0.4
0
0
1
1
0
0
1
0
0
1
0
0
1
tude clock drives. CLKXP/CLKXN also help to minimize
the jitter, and allow the user to connect a crystal oscillator
directly to MAX5854.
-0.35
12 ______________________________________________________________________________________
Dual, 10-Bit, 165Msps, Current-Output DAC
AV
DD
OPTIONAL EXTERNAL BUFFER
FOR HEAVIER LOADS
10µF
0.1µF
MAX4040
1.24V
BANDGAP
REFERENCE
AGND
REN = 0
1.24V
BANDGAP
REFERENCE
AV
DD
REN = 1
REFO
MAX6520
EXTERNAL
1.2V
REFERENCE
CURRENT-
SOURCE
ARRAY
I
FS
REFO
REFR
C
*
COMP
I
REF
REFR
CURRENT-
SOURCE
ARRAY
I
FS
AGND
I
REF
V
R
REF
SET
R
SET
I
=
REF
AGND
R
SET
MAX5854
AGND
MAX5854
AGND
*COMPENSATION CAPACITOR (C
≈ 100nF).
COMP
Figure 3. Setting I with the Internal 1.24V Reference and the
FS
Figure 4. MAX5854 with External Reference
Control Amplifier
The CLK pin now becomes an output, and provides a
single-ended replica of the differential clock signal,
which may be used to synchronize the input data. Data is
written to the device on the rising edge of the CLK signal.
External Reference
To disable the internal reference of the MAX5854, set
REN = 1. Apply a temperature-stable, external reference
to drive the REFO pin and set the full-scale output
(Figure 4). For improved accuracy and drift perfor-
mance, choose a fixed output voltage reference such as
the 1.2V, 25ppm/°C MAX6520 bandgap reference.
Internal Reference and Control Amplifier
The MAX5854 provides an integrated 50ppm/°C, 1.24V,
low-noise bandgap reference that can be disabled and
overridden with an external reference voltage. REFO
serves either as an external reference input or an inte-
grated reference output. If REN =0, the internal refer-
ence is selected and REFO provides a 1.24V (50µA)
output. Buffer REFO with an external amplifier, when
driving a heavy load.
Detailed Timing
The MAX5854 accepts an input data and the DAC con-
version rate of up to 165Msps. The input latches on the
rising edge of the clock, whereas the output latches on
the following rising edge.
Figure 5 depicts the write cycle of the two DACs in non-
interleaved mode.
The MAX5854 also employs a control amplifier
designed to simultaneously regulate the full-scale out-
put current (I ) for both outputs of the devices.
FS
Calculate the output current as:
The MAX5854 can also operate in an interleaved data
mode. Programming the IDE bit with a high level activates
this mode (Tables 1 and 2). In interleaved mode, data for
both DAC channels is written through input port A.
Channel B data is written on the falling edge of the clock
signal and then channel A data is written on the following
rising edge of the clock signal. Both DAC outputs (chan-
nel A and B) are updated simultaneously on the next fol-
lowing rising edge of the clock. In interleaved data mode,
the maximum input data rate per channel is half of the
rate in noninterleaved mode. The interleaved data mode
is attractive for applications where lower data rates are
acceptable and interfacing on a single 10-bit bus is
desired (Figure 6).
I
FS
= 32 ♦ I
REF
where I
is the reference output current (I
SET FS
=
REF
REF
/ R
V
) and I is the full-scale output current.
REFO
R
is the reference resistor that determines the
SET
amplifier output current of the MAX5854 (Figure 3). This
current is mirrored into the current-source array where
I
FS
is equally distributed between matched current seg-
ments and summed to valid output current readings for
the DACs.
______________________________________________________________________________________ 13
Dual, 10-Bit, 165Msps, Current-Output DAC
t
t
CXL
CXH
CLKXN
CLKXP
t
CDL
t
CDH
CLK
OUTPUT
t
CWL
CW
t
t
CW
t
t
DCH
CS
DCS
CONTROL
WORD
DA0–DA9
DACA - 1
DACA
DACA + 1
DACA + 2
DACA + 3
OUTNA
OUTPA
XXXX
(CONTROL WORD DATA)
DACA - 1
DACA
DACA + 1
DACA + 2
DACA + 3
t
t
DCH
DCS
DB0–DB9
DACB - 1
DACB
DACB + 1
DACB + 2
XXXX
DACB + 3
OUTNB
OUTPB
DACB - 1
DACB
DACB + 1
DACB + 2
XXXX
DACB + 3
Figure 5. Timing Diagram for Noninterleaved Data Mode (IDE = 0)
t
t
CXH
CXL
CLKXN
CLKXP
t
t
CDL
CDH
CLK
OUTPUT
t
CWL
CW
t
t
t
t
t
t
CW
DCS
DCH
DCS
DCH
CS
CONTROL
WORD
DA0–DA9
DACA
DACB + 1
DACA + 1
DACB + 2
DACA + 2
OUTNA
DACA - 1
DACB - 1
DACA
DACB
DACA + 1
DACB + 1
OUTPA
OUTNB
OUTPB
Figure 6. Timing Diagram for Interleaved Data Mode (IDE = 1)
14 ______________________________________________________________________________________
Dual, 10-Bit, 165Msps, Current-Output DAC
AV
DV
CV
DD DD
DD
AV
DV
CV
DD DD
DD
50Ω
V
,
OUTA
SINGLE ENDED
50Ω
OUTPA
OUTPA
OUTNA
DA0–DA9
1/2
DA0–DA9
1/2
100Ω
MAX5854
MAX5854
10
10
OUTNA
50Ω
50Ω
50Ω
V
,
50Ω
OUTB
SINGLE ENDED
OUTPB
OUTPB
OUTNB
DB0–DB9
DB0–DB9
1/2
1/2
100Ω
MAX5854
MAX5854
10
10
OUTNB
50Ω
50Ω
AGND DGND CGND
AGND DGND CGND
Figure 7. Application with Output Transformer Performing
Differential-to-Single-Ended Conversion
Figure 8. Application with DC-Coupled Differential Outputs
extend from 10MHz down to several hundred kilohertz.
DC-coupling is desirable to eliminate long discharge
time constants that are problematic with large, expensive
coupling capacitors. Analog quadrature upconverters
have a DC common-mode input requirement of typically
0.7V to 1.0V. The MAX5854 differential I/Q outputs can
maintain the desired full-scale level at the required 0.7V
to 1.0V DC common-mode level when powered from a
single 2.85V ( 5%) supply. The MAX5854 meets this
low-power requirement with minimal reduction in dynam-
ic range while eliminating the need for level-shifting
resistor networks.
Applications Information
Differential-to-Single-Ended Conversion
The MAX5854 exhibits excellent dynamic performance
to synthesize a wide variety of modulation schemes,
including high-order QAM modulation with OFDM.
Figure 7 shows a typical application circuit with output
transformers performing the required differential-to-sin-
gle-ended signal conversion. In this configuration, the
MAX5854 operates in differential mode, which reduces
even-order harmonics, and increases the available out-
put power.
Power Supplies, Bypassing,
Decoupling, and Layout
Grounding and power-supply decoupling strongly influ-
ence the MAX5854 performance. Unwanted digital
crosstalk can couple through the input, reference,
power-supply, and ground connections, which can
affect dynamic specifications, like signal-to-noise ratio
Differential DC-Coupled Configuration
Figure 8 shows the MAX5854 output operating in differ-
ential, DC-coupled mode. This configuration can be
used in communications systems employing analog
quadrature upconverters and requiring a baseband
sampling, dual-channel, high-speed DAC for I/Q synthe-
sis. In these applications, information bandwidth can
______________________________________________________________________________________ 15
Dual, 10-Bit, 165Msps, Current-Output DAC
or spurious-free dynamic range. In addition, electro-
magnetic interference (EMI) can either couple into or
be generated by the MAX5854. Observe the grounding
and power-supply decoupling guidelines for high-
speed, high-frequency applications. Follow the power
supply and filter configuration to realize optimum
dynamic performance.
In this package, the data converter die is attached to
an EP leadframe with the back of this frame exposed at
the package bottom surface, facing the PC board side
of the package. This allows a solid attachment of the
package to the PC board with standard infrared (IR)
flow soldering techniques. A specially created land pat-
tern on the PC board, matching the size of the EP
(4.1mm ♦ 4.1mm), ensures the proper attachment and
grounding of the DAC. Designing vias* into the land
area and implementing large ground planes in the PC
board design allows for highest performance operation
of the DAC. Use an array of 3 ♦ 3 vias (≤0.3mm diame-
ter per via hole and 1.2mm pitch between via holes) for
this 40-pin thin QFN-EP package (package code:
T4066-1).
Use of a multilayer printed circuit (PC) board with sepa-
rate ground and power-supply planes is recommend-
ed. Run high-speed signals on lines directly above the
ground plane. The MAX5854 has separate analog and
digital ground buses (AGND, CGND, and DGND,
respectively). Provide separate analog, digital, and
clock ground sections on the PC board with only one
point connecting the three planes. The ground connec-
tion points should be located underneath the device
and connected to the exposed paddle. Run digital sig-
nals above the digital ground plane and analog/clock
signals above the analog/clock ground plane. Digital
signals should be kept away from sensitive analog,
clock, and reference inputs. Keep digital signal paths
short and metal trace lengths matched to avoid propa-
gation delay and data skew mismatch.
Dynamic Performance Parameter Definitions
Adjacent Channel Leakage Ratio (ACLR)
Commonly used in combination with wideband code-
division multiple-access (WCDMA), ACLR reflects the
leakage power ratio in dB between the measured
power within a channel relative to its adjacent channel.
ACLR provides a quantifiable method of determining
out-of-band spectral energy and its influence on an
adjacent channel when a bandwidth-limited RF signal
passes through a nonlinear device.
The MAX5854 includes three separate power-supply
inputs: analog (AV ), digital (DV ), and clock
DD
DD
(CV ). Use a single linear regulator power source to
DD
branch out to three separate power-supply lines (AV
,
DD
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of all essential harmon-
ics (within a Nyquist window) of the input signal to the
fundamental itself. This can be expressed as:
DV , CV ) and returns (AGND, DGND, CGND).
DD
DD
Filter each power-supply line to the respective return
line using LC filters comprising ferrite beads and 10µF
capacitors. Filter each supply input locally with 0.1µF
ceramic capacitors to the respective return lines.
Note: To maintain the dynamic performance of the
Electrical Characteristics, ensure the voltage differ-
2
2
2
2
V
+ V + V ...+...V
3 4 N
2
THD = 20 × log
V
1
ence between DV , AV , and CV does not
DD
DD
DD
exceed 150mV.
Thermal Characteristics and Packaging
where V1 is the fundamental amplitude, and V2 through
VN are the amplitudes of the 2nd through Nth order har-
monics. The MAX5854 uses the first seven harmonics
for this calculation.
Thermal Resistance
40-lead thin QFN-EP:
θ
= 38°C/W
JA
The MAX5854 is packaged in a 40-pin thin QFN-EP
package, providing greater design flexibility, increased
thermal efficiency, and optimized AC performance of
the DAC. The EP enables the implementation of
grounding techniques, which are necessary to ensure
highest performance operation.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier fre-
quency (maximum signal component) to the RMS value
of their next-largest spectral component. SFDR is usu-
ally measured in dBc with respect to the carrier fre-
quency amplitude or in dBFS with respect to the DAC’s
full-scale range. Depending on its test condition, SFDR
is observed within a predefined window or to Nyquist.
*Vias connect the land pattern to internal or external copper planes.
16 ______________________________________________________________________________________
Dual, 10-Bit, 165Msps, Current-Output DAC
Multitone Power Ratio (MTPR)
A series of equally spaced tones are applied to the DAC
with one tone removed from the center of the range.
MTPR is defined as the worst-case distortion (usually a
3rd-order harmonic product of the fundamental frequen-
cies), which appears as the largest spur at the frequency
of the missing tone in the sequence. This test can be per-
formed with any number of input tones; however, four and
eight tones are among the most common test conditions
for CDMA- and GSM/EDGE-type applications.
Gain Error
A gain error is the difference between the ideal and the
actual full-scale output current on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step. The ideal current is
defined by reference voltage at V
/ I
x 32.
REFO REF
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles to its
new output value to within the converter’s specified
accuracy.
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc of either out-
put tone to the worst 3rd-order (or higher) IMD products.
Glitch Impulse
A glitch is generated when a DAC switches between
two codes. The largest glitch is usually generated
around the midscale transition, when the input pattern
transitions from 011…111 to 100…000. This occurs due
to timing variations between the bits. The glitch impulse
is found by integrating the voltage of the glitch at the
midscale transition over time. The glitch impulse is usu-
ally specified in pV-s.
Static Performance Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. For a DAC,
the deviations are measured at every individual step.
Differential Nonlinearity (DNL)
Differential nonlinearity (DNL) is the difference between
an actual step height and the ideal value of 1 LSB. A
DNL error specification no more negative than -1 LSB
guarantees monotonic transfer function.
Table 4. Part Selection Table
PART
SPEED (Msps)
RESOLUTION
8-bit, dual
MAX5851
MAX5852
MAX5853
MAX5854
80
165
80
8-bit, dual
Offset Error
Offset error is the current flowing from positive DAC
output when the digital input code is set to zero. Offset
error is expressed in LSBs.
10-bit, dual
10-bit, dual
165
Chip Information
TRANSISTOR COUNT: 9,035
PROCESS: CMOS
______________________________________________________________________________________ 17
Dual, 10-Bit, 165Msps, Current-Output DAC
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
D
C
L
b
D/2
D2/2
k
E/2
E2/2
(NE-1) X
e
C
L
E
E2
k
L
e
(ND-1) X
e
C
C
L
L
L
L
e
e
A
A1
A2
PACKAGE OUTLINE
36,40L THIN QFN, 6x6x0.8 mm
1
D
21-0141
2
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220.
PACKAGE OUTLINE
36, 40L THIN QFN, 6x6x0.8 mm
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
2
D
21-0141
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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