MAX5585ETP+ [MAXIM]
D/A Converter, 1 Func, Serial Input Loading, 2us Settling Time, 5 X 5 MM, 0.80 MM HEIGHT, MO-220WHHC, TQFN-20;
| 型号： | MAX5585ETP+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 1 Func, Serial Input Loading, 2us Settling Time, 5 X 5 MM, 0.80 MM HEIGHT, MO-220WHHC, TQFN-20 |
| 文件： | 总34页 (文件大小：1201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3164; Rev 1; 5/04
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
General Description
Features
♦ 3µs (max) 12-Bit Settling Time to 0.5 LSB
The MAX5580–MAX5585 quad, 12-/10-/8-bit, voltage-
output, digital-to-analog converters (DACs) offer
buffered outputs and a 3µs maximum settling time at the
12-bit level. The DACs operate from a +2.7V to +5.25V
analog supply and a separate +1.8V to +5.25V digital
supply. The 20MHz, 3-wire, serial interface is compati-
ble with SPI™, QSPI™, MICROWIRE™, and digital sig-
nal processor (DSP) protocol applications. Multiple
devices can share a common serial interface in direct-
access or daisy-chained configuration. The MAX5580–
MAX5585 provide two multifunctional, user-programma-
ble, digital I/O ports. The externally selectable power-up
states of the DAC outputs are either zero scale, mid-
scale, or full scale. Software-selectable FAST and SLOW
settling modes decrease settling time in FAST mode, or
reduce supply current in SLOW mode.
♦ Quad, 12-/10-/8-Bit Serial DACs in TSSOP and
Thin QFN (5mm x 5mm x 0.8mm) Packages
♦ ±1 LSB (max) INL and DNL at 12-Bit Resolution
♦ Two User-Programmable Digital I/O Ports
♦ Single +2.7V to +5.25V Analog Supply
♦ +1.8V to AV
Digital Supply
DD
♦ 20MHz, 3-Wire, SPI-/QSPI-/MICROWIRE-/DSP-
Compatible Serial Interface
♦ Glitch-Free Outputs Power Up to Zero Scale,
Midscale, or Full Scale Controlled by PU Pin
♦ Unity-Gain or Force-Sense-Configured
Output Buffers
Ordering Information
The MAX5580/MAX5581 are 12-bit DACs, the
MAX5582/MAX5583 are 10-bit DACs, and the
MAX5584/MAX5585 are 8-bit DACs. The MAX5580/
MAX5582/MAX5584 provide unity-gain-configured out-
put buffers, while the MAX5581/MAX5583/MAX5585
provide force-sense-configured output buffers. The
MAX5580–MAX5585 operate over the extended -40°C
to +85°C temperature range and are available in
space-saving, 5mm x 5mm x 0.8mm, 20-pin, thin QFN
and TSSOP packages.
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
20 TSSOP-EP**
20 Thin QFN-EP**
MAX5580AEUP*
MAX5580AETP*
*Future product—contact factory for availability. Specifications
are preliminary.
**EP = Exposed paddle.
Ordering Information continued at end of data sheet.
Selector Guide
Applications
Portable Instrumentation
INL
(LSB
max)
OUTPUT BUFFER RESOLUTION
PART
CONFIGURATION
(BITS)
Automatic Test Equipment (ATE)
Digital Offset and Gain Adjustment
Automatic Tuning
MAX5580AEUP
MAX5580AETP
MAX5580BEUP
MAX5580BETP
MAX5581AEUP
MAX5581AETP
MAX5581BEUP
MAX5581BETP
MAX5582EUP
MAX5582ETP
MAX5583EUP
MAX5583ETP
MAX5584EUP
MAX5584ETP
MAX5585EUP
MAX5585ETP
Unity gain
Unity gain
12
12
12
12
12
12
12
12
10
10
10
10
8
1
1
Unity gain
4
Programmable Voltage and Current Sources
Programmable Attenuators
Unity gain
4
Force sense
Force sense
Force sense
Force sense
Unity gain
1
Industrial Process Controls
1
Motion Control
4
Microprocessor (µP)-Controlled Systems
Power Amplifier Control
4
1
Fast Parallel-DAC to Serial-DAC Upgrades
Unity gain
1
Force sense
Force sense
Unity gain
1
1
0.5
0.5
0.5
0.5
Pin Configurations appear at end of data sheet.
Unity gain
8
Force sense
Force sense
8
8
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
ABSOLUTE MAXIMUM RATINGS
AV
to DV ........................................................................ 6V
Maximum Current into Any Pin ......................................... 50mA
DD
DD
AGND to DGND.................................................................. 0.3V
Continuous Power Dissipation (T = +70°C)
A
AV
DV
to AGND, DGND.............................................-0.3V to +6V
to AGND, DGND ............................................-0.3V to +6V
20-Pin TSSOP (derate 21.7mW/°C above +70°C)........1739mW
20-Pin Thin QFN (derate 20.8mW/°C above +70°C) ....1667mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
DD
DD
FB_, OUT_,
REF to AGND........-0.3V to the lower of (AV + 0.3V) or +6V
DD
SCLK, DIN, CS, PU,
DSP to DGND.......-0.3V to the lower of (DV + 0.3V) or +6V
DD
UPIO1, UPIO2
to DGND...............-0.3V to the lower of (DV + 0.3V) or +6V
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
= 2.7V to 5.25V, DV
= 1.8V to AV , AGND = 0, DGND = 0, V
= 2.5V (for AV
= 2.7V to 5.25V), V
= 4.096V (for
REF
DD
DD
DD
REF
DD
AV = 4.5V to 5.25V), R = 10kΩ, C = 100pF, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
MAX A
DD
L
L
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC ACCURACY
MAX5580/MAX5581
MAX5582/MAX5583
MAX5584/MAX5585
12
10
8
Resolution
N
Bits
MAX5580A/MAX5581A (12 bit)
MAX5580B/MAX5581B (12 bit)
MAX5582/MAX5583 (10 bit)
MAX5584/MAX5585 (8 bit)
1
4
1
V
AV
V
AV
= 2.5V at
= 2.7V and
= 4.096V at
= 5.25V
REF
DD
2
Integral Nonlinearity
INL
LSB
REF
0.5
DD
(Note 2)
0.125
0.5
1
Differential Nonlinearity
Offset Error
DNL
Guaranteed monotonic (Note 2)
LSB
mV
MAX5580A/MAX5581A (12 bit), decimal code = 40
MAX5580B/MAX5581B (12 bit), decimal code = 40
MAX5582/MAX5583 (10 bit), decimal code = 20
MAX5584/MAX5585 (8 bit), decimal code = 5
5
5
5
5
25
25
25
V
OS
ppm of
FS/°C
Offset-Error Drift
Gain Error
5
MAX5580A/MAX5581A (12 bit)
4
40
10
3
MAX5580B/MAX5580B (12 bit)
Full-scale output
20
5
GE
LSB
MAX5582/MAX5583 (10 bit)
MAX5584/MAX5585 (8 bit)
2
ppm of
FS/°C
Gain-Error Drift
1
2
_______________________________________________________________________________________
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(AV
= 2.7V to 5.25V, DV
= 1.8V to AV , AGND = 0, DGND = 0, V
= 2.5V (for AV
= 2.7V to 5.25V), V
= 4.096V (for
REF
DD
DD
DD
REF
DD
AV = 4.5V to 5.25V), R = 10kΩ, C = 100pF, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
MAX A
DD
L
L
A
MIN
PARAMETER
SYMBOL
CONDITIONS
Full-scale output, AV = 2.7V to 5.25V
MIN
TYP
MAX
UNITS
Power-Supply Rejection
Ratio
PSRR
200
µV/V
DD
REFERENCE INPUT
Reference-Input Range
V
R
0.25
145
AV
V
REF
DD
Reference-Input
Resistance
Normal operation (no code dependence)
Shutdown mode
200
0.5
kΩ
REF
Reference Leakage
Current
1
µA
DAC OUTPUT CHARACTERISTICS
Unity gain
SLOW mode, full scale
Force sense
85
67
Output-Voltage Noise
µV
RMS
Unity gain
FAST mode, full scale
Force sense
140
110
Unity-gain output
0
0
AV
DD
Output-Voltage Range
(Note 3)
V
Force-sense output
AV / 2
DD
DC Output Impedance
38
57
45
30
40
Ω
AV
AV
= 5V, OUT_ to AGND, full scale, FAST mode
= 3V, OUT_ to AGND, full scale, FAST mode
DD
DD
Short-Circuit Current
mA
Power-Up Time
Wake-Up Time
From DV , applied until interface is functional
DD
60
µs
µs
Coming out of shutdown, outputs settled
Output OUT_ and FB_
Open-Circuit Leakage
Current
Programmed in shutdown mode, force-sense
outputs only
0.01
µA
DIGITAL OUTPUTS (UPIO_)
DV
0.5
-
DD
Output High Voltage
Output Low Voltage
V
I
I
= 0.5mA
SOURCE
V
V
OH
V
= 2mA
SINK
0.4
OL
DIGITAL INPUTS (SCLK, CS, DIN, DSP, UPIO_)
DV ≥ 2.7V
2.4
DD
Input High Voltage
V
V
V
IH
0.7 x
DV < 2.7V
DD
DV
DD
DV > 3.6V
DD
0.8
0.6
0.2
1
Input Low Voltage
V
2.7V ≤ DV ≤ 3.6V
IL
DD
DV < 2.7V
DD
Input Leakage Current
Input Capacitance
I
0.1
10
µA
pF
IN
C
IN
_______________________________________________________________________________________
3
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(AV
= 2.7V to 5.25V, DV
= 1.8V to AV , AGND = 0, DGND = 0, V
= 2.5V (for AV
= 2.7V to 5.25V), V
= 4.096V (for
REF
DD
DD
DD
REF
DD
AV = 4.5V to 5.25V), R = 10kΩ, C = 100pF, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
MAX A
DD
L
L
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PU INPUT
DV
200mV
-
DD
Input High Voltage
Input Low Voltage
Input Leakage Current
V
V
IH-PU
V
200
200
mV
nA
IL-PU
IN-PU
PU still considered floating when connected to a
tri-state bus
I
DYNAMIC PERFORMANCE
FAST mode
SLOW mode
3.6
1.6
Voltage-Output Slew
Rate
SR
V/µs
MAX5580/MAX5581 from code 322 to
code 4095 to 0.5 LSB
2
1.5
1
3
3
2
6
6
4
FAST
mode
MAX5582/MAX5583 from code 10 to
code 1023 to 0.5 LSB
MAX5584/MAX5585 from code 3 to
code 255 to 0.5 LSB
Voltage-Output Settling
Time (Note 4), Figure 5
t
µs
S
MAX5580/MAX5581 from code 322 to
code 4095 to 0.5 LSB
3
SLOW
mode
MAX5582/MAX5583 from code 10 to
code 1023 0.5 LSB
2.5
2
MAX5584/MAX5585 from code 3 to
code 255 to 0.5 LSB
FB_ Input Voltage
FB_ Input Current
0
V
/ 2
V
REF
0.1
µA
Unity gain
200
150
Reference -3dB
Bandwidth (Note 5)
kHz
Force sense
CS = DV , code = zero scale, any digital input
DD
Digital Feedthrough
0.1
nV-s
from 0 to DV
and DV
to 0, f = 100kHz
DD
DD
Digital-to-Analog Glitch
Impulse
Major carry transition
(Note 6)
2
nV-s
nV-s
DAC-to-DAC Crosstalk
15
4
_______________________________________________________________________________________
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(AV
= 2.7V to 5.25V, DV
= 1.8V to AV , AGND = 0, DGND = 0, V
= 2.5V (for AV
= 2.7V to 5.25V), V
= 4.096V (for
REF
DD
DD
DD
REF
DD
AV = 4.5V to 5.25V), R = 10kΩ, C = 100pF, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
MAX A
DD
L
L
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Analog Supply Voltage
Range
AV
DV
2.70
1.8
5.25
V
V
DD
Digital Supply Voltage
Range
AV
DD
DD
SLOW mode, all digital inputs
Unity gain
0.9
1.6
1.6
2.3
1.6
at DGND or DV , no load,
DD
I
AVDD
+
Force sense
Unity gain
2.4
4
V
= 4.096V
REF
Operating Supply
Current
mA
FAST mode, all digital inputs
at DGND or DV , no load,
I
DVDD
DD
Force sense
4
V
= 4.096V
REF
I
AVDD(SHDN)
+
Shutdown Supply
Current
No clocks, all digital inputs at DGND or DV , all
DD
DACs in shutdown mode
0.5
1
µA
I
DVDD(SHDN)
Note 1: For the force-sense versions, FB_ is connected to its respective OUT_, and V
(max) = V
/ 2, unless otherwise noted.
REF
OUT
Note 2: Linearity guaranteed from decimal code 40 to code 4095 for the MAX5580B/MAX5581B (12 bit, B grade), code 20 to code
1023 for the MAX5582/MAX5583 (10 bit), and code 5 to code 255 for the MAX5584/MAX5585 (8 bit).
Note 3: Represents the functional range. The linearity is guaranteed at V
= 2.5V (for AV
from 2.7V to 5.25V), and V =
REF
DD
REF
4.096V (for AV
DD
= 4.5V to 5.25V). See the Typical Operating Characteristics section for linearity at other voltages.
Note 4: Guaranteed by design.
Note 5: The reference -3dB bandwidth is measured with a 0.1V
sine wave on V and with full-scale input code.
REF
P-P
Note 6: DC crosstalk is measured as follows: outputs of DACA–DACD are set to full scale and the output of DACD is measured.
While keeping DACD unchanged, the outputs of DACA–DACC are transitioned to zero scale and the ∆V
of DACD
OUT
is measured.
_______________________________________________________________________________________
5
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V, 5V Logic) (Figure 1)
(DV
= 2.7V to 5.25V, AGND = DGND = 0, T = T
to T , unless otherwise noted.)
MAX
DD
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
ns
SCLK Frequency
f
2.7V < DV
(Note 7)
(Note 7)
< 5.25V
DD
20
SCLK
SCLK Pulse-Width High
t
20
20
10
5
CH
SCLK Pulse-Width Low
t
ns
CL
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
SCLK Rise to CS Fall Setup Time
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
t
ns
CSS
CSH
t
ns
t
10
12
5
ns
CS0
t
ns
DS
t
ns
DH
SCLK Rise to DOUTDC1 Valid
Propagation Delay
t
t
C = 20pF, UPIO_ = DOUTDC1 mode
30
30
ns
ns
DO1
DO2
L
SCLK Fall to DOUT_ Valid
Propagation Delay
C = 20pF, UPIO_ = DOUTDC0 or DOUTRB
L
mode
CS Rise to SCLK Rise Hold Time
CS Pulse-Width High
t
MICROWIRE and SPI modes 0 and 3
10
45
ns
ns
CS1
t
CSW
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when Exiting
DOUTDC0, DOUTDC1, and UPIO
Modes
C = 20pF, from end of write cycle to UPIO_
L
in high impedance
t
100
ns
DOZ
DOUTRB Tri-State Time from CS
Rise
C = 20pF, from rising edge of CS to UPIO_
in high impedance
L
t
20
20
ns
ns
DRBZ
DOUTRB Tri-State Enable Time
from 8th SCLK Rise
C = 20pF, from 8th rising edge of SCLK to
L
UPIO_ driven out of tri-state
t
ZEN
LDAC Pulse-Width Low
t
t
Figure 5
20
100
20
ns
ns
ns
ns
LDL
LDS
LDAC Effective Delay
Figure 6
CLR, MID, SET Pulse-Width Low
GPO Output Settling Time
t
Figure 5
CMS
t
Figure 6
100
100
GP
GPO Output High-Impedance
Time
t
ns
GPZ
6
_______________________________________________________________________________________
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1)
(DV
= 1.8V to 2.7V, AGND = DGND = 0, T = T
to T , unless otherwise noted.)
MAX
DD
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
ns
SCLK Frequency
f
1.8V < DV
(Note 7)
(Note 7)
< 2.7V
DD
10
SCLK
SCLK Pulse-Width High
t
40
40
20
5
CH
SCLK Pulse-Width Low
t
ns
CL
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
SCLK Rise to CS Fall Setup TIme
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
t
ns
CSS
CSH
t
ns
t
10
20
5
ns
CS0
t
ns
DS
t
ns
DH
SCLK Rise to DOUTDC1 Valid
Propagation Delay
t
t
C = 20pF, UPIO_ = DOUTDC1 mode
60
60
ns
ns
DO1
DO2
L
SCLK Fall to DOUT_ Valid
Propagation Delay
C = 20pF, UPIO_ = DOUTDC0 or DOUTRB
L
mode
CS Rise to SCLK Rise Hold Time
CS Pulse-Width High
t
MICROWIRE and SPI modes 0 and 3
20
90
ns
ns
CS1
t
CSW
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1,
and UPIO Modes
C = 20pF, from end of write cycle to UPIO_
L
in high impedance
t
200
ns
DOZ
DOUTRB Tri-State Time from CS
Rise
C = 20pF, from rising edge of CS to UPIO_
in high impedance
L
t
40
40
ns
ns
DRBZ
DOUTRB Tri-State Enable Time
from 8th SCLK Rise
C = 20pF, from 8th rising edge of SCLK to
L
UPIO_ driven out of tri-state
t
ZEN
LDAC Pulse-Width Low
t
t
Figure 5
40
200
40
ns
ns
ns
ns
LDL
LDAC Effective Delay
Figure 6
LDS
CLR, MID, SET Pulse-Width Low
GPO Output Settling Time
t
Figure 5
CMS
t
Figure 6
200
200
GP
GPO Output High-Impedance
Time
t
ns
GPZ
_______________________________________________________________________________________
7
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V, 5V Logic) (Figure 2)
(DV
= 2.7V to 5.25V, AGND = DGND = 0, T = T
to T , unless otherwise noted.)
MAX
DD
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
ns
SCLK Frequency
f
2.7V < DV
(Note 7)
(Note 7)
< 5.25V
DD
20
SCLK
SCLK Pulse-Width High
t
20
20
10
10
5
CH
SCLK Pulse-Width Low
t
ns
CL
CS Fall to SCLK Fall Setup Time
DSP Fall to SCLK Fall Setup Time
SCLK Fall to CS Rise Hold Time
SCLK Fall to CS Fall Delay
SCLK Fall to DSP Fall Delay
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
t
t
ns
CSS
DSS
CSH
ns
t
ns
t
t
10
10
12
5
ns
CS0
ns
DS0
t
ns
DS
t
ns
DH
SCLK Rise to DOUT_ Valid
Propagation Delay
C = 20pF, UPIO_ = DOUTDC1 or DOUTRB
L
mode
t
t
30
30
ns
ns
DO1
DO2
SCLK Fall to DOUT_ Valid
Propagation Delay
C = 20pF, UPIO_ = DOUTDC0 mode
L
CS Rise to SCLK Fall Hold Time
CS Pulse-Width High
t
MICROWIRE and SPI modes 0 and 3
10
45
20
20
ns
ns
ns
ns
CS1
t
t
CSW
DSW
DSP Pulse-Width High
DSP Pulse-Width Low
t
DSPWL
(Note 8)
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1,
and UPIO Modes
C = 20pF, from end of write cycle to UPIO_
L
in high impedance
t
100
ns
DOZ
DOUTRB Tri-State Time from CS
Rise
C = 20pF, from rising edge of CS to UPIO_
in high impedance
L
t
20
20
ns
ns
DRBZ
DOUTRB Tri-State Enable Time
from 8th SCLK Fall
C = 20pF, from 8th falling edge of SCLK to
L
UPIO_ driven out of tri-state
t
ZEN
LDAC Pulse-Width Low
t
t
Figure 5
20
100
20
ns
ns
ns
ns
LDL
LDAC Effective Delay
Figure 6
LDS
CLR, MID, SET Pulse-Width Low
GPO Output Settling Time
t
Figure 5
CMS
t
Figure 6
100
100
GP
GPO Output High-Impedance
Time
t
ns
GPZ
8
_______________________________________________________________________________________
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2)
(DV
= 1.8V to 2.7V, AGND = DGND = 0, T = T
MIN
to T , unless otherwise noted.)
MAX
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
ns
SCLK Frequency
f
1.8V < DV
(Note 7)
(Note 7)
< 2.7V
DD
10
SCLK
SCLK Pulse-Width High
t
40
40
20
20
5
CH
SCLK Pulse-Width Low
t
ns
CL
CS Fall to SCLK Fall Setup Time
DSP Fall to SCLK Fall Setup Time
SCLK Fall to CS Rise Hold Time
SCLK Fall to CS Fall Delay
SCLK Fall to DSP Fall Delay
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
t
t
ns
CSS
DSS
CSH
ns
t
ns
t
t
10
15
20
5
ns
CS0
DS0
ns
t
ns
DS
t
ns
DH
SCLK Rise to DOUT_ Valid
Propagation Delay
C = 20pF, UPIO_ = DOUTDC1 or DOUTRB
L
mode
t
t
60
60
ns
ns
DO1
DO2
SCLK Fall to DOUT_ Valid
Propagation Delay
C = 20pF, UPIO_ = DOUTDC0 mode
L
CS Rise to SCLK Fall Hold Time
CS Pulse-Width High
t
MICROWIRE and SPI modes 0 and 3
20
90
40
40
ns
ns
ns
ns
CS1
t
t
CSW
DSW
DSP Pulse-Width High
DSP Pulse-Width Low
t
DSPWL
(Note 8)
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1,
and UPIO Modes
C = 20pF, from end of write cycle to UPIO_
L
in high impedance
t
200
ns
DOZ
DOUTRB Tri-State Time from CS
Rise
C = 20pF, from rising edge of CS to UPIO_
in high impedance
L
t
40
40
ns
ns
DRBZ
DOUTRB Tri-State Enable Time
from 8th SCLK Fall
C = 20pF, from 8th falling edge of SCLK to
L
UPIO_ driven out of tri-state
t
ZEN
LDAC Pulse-Width Low
t
t
Figure 5
40
200
40
ns
ns
ns
ns
LDL
LDAC Effective Delay
Figure 6
LDS
CLR, MID, SET Pulse-Width Low
GPO Output Settling Time
t
Figure 5
CMS
t
Figure 6
200
200
GP
GPO Output High-Impedance
Time
t
ns
GPZ
Note 7: In some daisy-chain modes, data is required to be clocked in on one clock edge and the shifted data clocked out on the fol-
lowing edge. In the case of a 0.5 clock-period delay, it is necessary to increase the minimum high/low clock times to 25ns
(2.7V) or 50ns (1.8V).
Note 8: The falling edge of DSP starts a DSP-type bus cycle, provided that CS is also active low to select the device. DSP active low and
CS active low must overlap by a minimum of 10ns (2.7V) or 20ns (1.8V). CS can be permanently low in this mode of operation.
_______________________________________________________________________________________
9
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
Typical Operating Characteristics
(AV = DV = 5V, V
= 4.096V, R = 10kΩ, C = 100pF, speed mode = FAST, PU = floating, T = +25°C, unless otherwise noted.)
L L A
DD
DD
REF
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (12 BIT)
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (10 BIT)
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (8 BIT)
4
3
1.00
0.50
0.25
0
0.75
2
1
0.50
0.25
0
0
-1
-0.25
-2
-3
-4
-0.50
-0.75
-1.00
-0.25
-0.50
B GRADE
1024
0
2048
3072
4095
0
256
512
768
1023
0
64
128
192
255
DIGITAL INPUT CODE
DIGITAL INPUT CODE
DIGITAL INPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (8 BIT)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (12 BIT)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (10 BIT)
0.050
0.025
0
0.50
0.2
0.1
0
0.25
0
-0.025
-0.050
-0.25
-0.50
-0.1
-0.2
B GRADE
1024
0
64
128
192
255
0
2048
3072
4095
0
256
512
768
1023
DIGITAL INPUT CODE
DIGITAL INPUT CODE
DIGITAL INPUT CODE
INTEGRAL NONLINEARITY
vs. REFERENCE VOLTAGE (12 BIT)
INTEGRAL NONLINEARITY
vs. TEMPERATURE (12 BIT)
DIFFERENTIAL NONLINEARITY
vs. REFERENCE VOLTAGE (12 BIT)
4
3
0.5
0.4
4
3
0.3
2
1
2
1
0.2
0.1
0
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-1
-1
-2
-3
-4
-2
-3
-4
B GRADE
MIDSCALE
B GRADE
MIDSCALE
B GRADE
MIDSCALE
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
(V)
-40 -15
10
35
60
85
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
(V)
V
°
REF
TEMPERATURE ( C)
V
REF
10 ______________________________________________________________________________________
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
Typical Operating Characteristics (continued)
(AV = DV = 5V, V
= 4.096V, R = 10kΩ, C = 100pF, speed mode = FAST, PU = floating, T = +25°C, unless otherwise noted.)
L L A
DD
DD
REF
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE (12 BIT)
SUPPLY CURRENT
vs. DIGITAL INPUT CODE (FORCE SENSE)
SUPPLY CURRENT
vs. DIGITAL INPUT CODE (UNITY GAIN)
0.2
2.0
1.5
1.0
0.5
0
1.0
0.75
0.50
0.25
0
0.1
0
-0.1
-0.2
SLOW MODE
12 BIT
NO LOAD
SLOW MODE
12 BIT
NO LOAD
B GRADE
MIDSCALE
-40 -15
10
35
60
85
0
1024
2048
3072
4095
0
1024
2048
3072
4095
DIGITAL INPUT CODE
DIGITAL INPUT CODE
°
TEMPERATURE ( C)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(FORCE SENSE)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(UNITY GAIN)
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
100
95
90
85
80
75
70
65
60
55
50
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
FAST MODE
SLOW MODE
FAST MODE
SLOW MODE
UNITY GAIN
FORCE SENSE
AV = DV
DD
DD
I = I
+ I
AVDD DVDD
I = I
+ I
AVDD DVDD
NO LOAD
AV = DV
DD
DD
AV = DV
DD
DD
I = I
+ I
AVDD DVDD
NO LOAD
NO LOAD
2.70
3.40
4.10
4.80
5.25
2.70
3.40
4.10
4.80
5.25
2.70
3.40
4.10
4.80
5.25
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE
vs. OUTPUT SOURCE/SINK CURRENT
OFFSET ERROR vs. TEMPERATURE
GAIN ERROR vs. TEMPERATURE
7
6
0
2.5
2.0
1.5
1.0
0.5
0
CODE = 40
-1
UNITY GAIN: 1 LSB = 1mV
FORCE SENSE: 1 LSB = 0.5mV
B GRADE
MIDSCALE
-2
-3
-4
-5
-6
-7
-8
-9
FORCE SENSE
5
4
3
FORCE SENSE
2
1
0
UNITY GAIN
B GRADE
UNITY GAIN: 1 LSB = 1mV
UNITY GAIN
UNITY GAIN
V
= 4.096V
FORCE SENSE: 1 LSB = 0.5mV
REF
-10
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-15
-10
-5
0
5
10
15
°
°
TEMPERATURE ( C)
TEMPERATURE ( C)
I
(mA)
OUT
______________________________________________________________________________________ 11
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
Typical Operating Characteristics (continued)
(AV = DV = 5V, V
= 4.096V, R = 10kΩ, C = 100pF, speed mode = FAST, PU = floating, T = +25°C, unless otherwise noted.)
DD
DD
REF
L
L
A
MAJOR-CARRY TRANSITION GLITCH
SETTLING TIME POSITIVE
SETTLING TIME NEGATIVE
MAX5580-85 toc21
MAX5580-85 toc19
MAX5580-85 toc20
FULL-SCALE TRANSITION
FULL-SCALE TRANSITION
CS
2V/div
CS
2V/div
CS
2V/div
(AC COUPLED)
OUT_
10mV/div
OUT_
2V/div
OUT_
2V/div
200ns/div
400ns/div
400ns/div
REFERENCE FEEDTHROUGH AT 1kHz
REFERENCE INPUT BANDWIDTH
DAC-TO-DAC CROSSTALK
MAX5580-85 toc24
-22
5
0
-30
-40
-50
OUTA–OUTC
2V/div
-60
-5
-70
-80
-10
-15
-20
-25
-90
-100
-110
-120
-130
OUTD
2mV/div
V
= 0.1V AT 4.096V
P-P DC
REF
UNITY GAIN
-142
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
FREQUENCY (kHz)
1
10
100
FREQUENCY (Hz)
1k
10k
200µs/div
DIGITAL FEEDTHROUGH
POWER-UP GLITCH
EXITING SHUTDOWN TO MIDSCALE
MAX5580-85 toc26
MAX5580-85 toc27
MAX5580-85 toc25
SCLK
2V/div
AV
2V/div
UPIO_
2V/div
DD
OUT_
(AC-COUPLED)
5mV/div
OUT_
2V/div
OUT_
2V/div
PU = FLOAT
PU = DV
DD
1µs/div
20µs/div
10µs/div
12 ______________________________________________________________________________________
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
Pin Description
PIN
MAX5580
MAX5582
MAX5584
MAX5581
MAX5583
MAX5585
NAME
FUNCTION
TSSOP
THIN QFN
TSSOP
THIN QFN
1
2
19
20
1
2
19
20
—
1
AGND
Analog Ground
Analog Supply
AV
DD
3, 5, 17, 19 1, 3, 15, 17
—
3
N.C.
FBB
No Connection. Not internally connected.
Feedback for DACB
DACB Output
—
4
—
2
4
2
OUTB
FBA
—
6
—
4
5
3
Feedback for DACA
DACA Output
6
4
OUTA
Power-Up State Select Input. Connect PU to DV to set OUT_
DD
to full scale upon power-up. Connect PU to DGND to set OUT_
to zero scale upon power-up. Float PU to set OUT_ to midscale
upon power-up.
7
5
7
5
PU
8
6
7
8
6
7
CS
Active-Low Chip-Select Input
Serial Clock Input
9
9
SCLK
DIN
10
11
12
13
14
8
10
11
12
13
14
8
Serial Data Input
9
9
UPIO1
UPIO2
User-Programmable Input/Output 1
User-Programmable Input/Output 2
Digital Supply
10
11
12
10
11
12
DV
DD
DGND
Digital Ground
Clock Enable. Connect DSP to DV
to clock in data on the
DD
rising edge of SCLK. Connect DSP to DGND to clock in data
15
13
15
13
DSP
on the falling edge of SCLK.
16
—
18
—
20
14
—
16
—
18
16
17
18
19
20
14
15
16
17
18
OUTD
FBD
DACD Output
Feedback for DACD
DACC Output
OUTC
FBC
Feedback for DACC
Reference Input
REF
Exposed
Pad
EP
EP
EP
EP
Exposed Pad. Connect to AGND.
______________________________________________________________________________________ 13
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
Functional Diagrams
AV
DD
DV
AGND
DGND
DD
CS
SCLK
DIN
SERIAL
INTERFACE
CONTROL
MAX5580
MAX5582
MAX5584
DSP
16-BIT SHIFT
REGISTER
DOUT
REGISTER
MUX
UPIO1
UPIO2
UPIO1 AND
UPIO2
LOGIC
POWER-DOWN
LOGIC AND
REGISTER
DECODE
CONTROL
OUTA
PU
INPUT
REGISTER
A
DAC
REGISTER
A
DACA
OUTD
INPUT
REGISTER
D
DAC
REGISTER
D
DACD
REF
14 ______________________________________________________________________________________
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
Functional Diagrams (continued)
AV
DD
DV
AGND
DGND
DD
CS
SCLK
DIN
SERIAL
INTERFACE
CONTROL
MAX5581
MAX5583
MAX5585
DSP
16-BIT SHIFT
REGISTER
DOUT
REGISTER
MUX
UPIO1
UPIO2
UPIO1 AND
UPIO2
LOGIC
POWER-DOWN
LOGIC AND
REGISTER
FBA
DECODE
CONTROL
OUTA
PU
INPUT
REGISTER
A
DAC
REGISTER
A
DACA
FBD
OUTD
INPUT
REGISTER
D
DAC
REGISTER
D
DACD
REF
______________________________________________________________________________________ 15
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
Use the serial interface to set the shutdown output
Detailed Description
impedance of the amplifiers to 1kΩ or 100kΩ for the
MAX5580/MAX5582/MAX5584 and 1kΩ or high imped-
ance for the MAX5581/MAX5583/MAX5585. The DAC
outputs can drive a 10kΩ (typ) load and are stable with
up to 500pF (typ) of capacitive load.
The MAX5580–MAX5585 quad, 12-/10-/8-bit, voltage-
output DACs offer buffered outputs and a 3µs maximum
settling time at the 12-bit level. The DACs operate from a
single 2.7V to 5.25V analog supply and a separate 1.8V
to AV
digital supply. The MAX5580–MAX5585 include
DD
an input register and DAC register for each channel and
a 16-bit data-in/data-out shift register. The 3-wire serial
interface is compatible with SPI, QSPI, MICROWIRE, and
DSP applications. The MAX5580–MAX5585 provide two
user-programmable digital I/O ports, which are pro-
grammed through the serial interface. The externally
selectable power-up states of the DAC outputs are either
zero scale, midscale, or full scale.
Power-On Reset
At power-up, all DAC outputs power up to full scale,
midscale, or zero scale, depending on the configuration
of the PU input. Connect PU to DV
to set OUT_ to full
DD
scale upon power-up. Connect PU to digital ground
(DGND) at power-up to set OUT_ to zero scale. Leave
PU floating to set OUT_ to midscale.
Digital Interface
Reference Input
The reference input, REF, accepts both AC and DC val-
ues with a voltage range extending from analog ground
(AGND) to AV . The voltage at REF sets the full-scale
DD
output of the DACs. Determine the output voltage using
the following equations:
The MAX5580–MAX5585 use a 3-wire serial interface
that is compatible with SPI, QSPI, MICROWIRE, and DSP
protocol applications (Figures 1 and 2). Connect DSP to
DV
before power-up to clock data in on the rising
DD
edge of SCLK. Connect DSP to DGND before power-up
to clock data in on the falling edge of SCLK. After power-
up, the device enters DSP frame-sync mode on the first
rising edge of DSP. Refer to the MAX5580–MAX5585
Programmer’s Handbook for details.
Unity-gain versions:
V
OUT_
= (V
x CODE) / 2N
REF
Force-sense versions (FB_ connected to OUT_):
= 0.5 x (V
x CODE) / 2N
The MAX5580–MAX5585 include a 16-bit input shift
register. The data is loaded into the input shift register
through the serial interface. The 16 bits can be sent in
two serial 8-bit packets or one 16-bit word (CS must
remain low until all 16 bits are transferred). The data is
loaded MSB first. For the MAX5580/MAX5581, the 16
bits consist of 4 control bits (C3–C0) and 12 data bits
(D11–D0) (see Table 1). For the 10-bit MAX5582/
MAX5583 devices, D11–D2 are the data bits and D1
and D0 are sub-bits. For the 8-bit MAX5584/
MAX5585 devices, D11–D4 are the data bits and
D3–D0 are sub-bits. Set all sub-bits to zero for optimum
performance.
V
OUT
REF
where CODE is the numeric value of the DAC’s binary
input code and N is the bits of resolution. For the
MAX5580/MAX5581, N = 12 and CODE ranges from 0
to 4095. For the MAX5582/MAX5583, N = 10 and
CODE ranges from 0 to 1023. For the MAX5584/
MAX5585, N = 8 and CODE ranges from 0 to 255. Use
the minature MAX6126 low-dropout, ultra-low-noise ref-
erence for optimum performance.
Output Buffers
The DACA–DACD output-buffer amplifiers of the
MAX5580–MAX5585 are unity-gain stable with Rail-to-
Rail® output voltage swings and a typical slew rate
of 3.6V/µs (FAST mode). The MAX5580/MAX5582/
MAX5584 provide unity-gain outputs, while the
MAX5581/MAX5583/MAX5585 provide force-sense out-
puts. For the MAX5581/MAX5583/MAX5585, access to
the output amplifier’s inverting input provides flexibility
in output gain setting and signal conditioning (see the
Applications Information section).
Each DAC channel includes two registers: an input reg-
ister and the DAC register. At power-up, the DAC out-
put is set according to the state of PU. The DACs are
double-buffered, which allows any of the following for
each channel:
• Loading the input register without updating the DAC
register
• Loading and updating the DAC register without
updating the input register
The MAX5580–MAX5585 offer FAST and SLOW settling-
time modes. In the SLOW mode, the settling time is 6µs
(max), and the supply current is 1.6mA (max). In the
FAST mode, the settling time is 3µs (max), and the sup-
ply current is 4mA (max). See the Digital Interface section
for settling-time mode programming details.
• Updating the DAC register from the input register
• Updating the input and DAC registers simultaneously
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
16 ______________________________________________________________________________________
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
Table 1. Serial Write Data Format
MSB
CONTROL BITS
C2 C1
16 BITS OF SERIAL DATA
DATA BITS
D6 D5
LSB
C3
C0
D11
D10
D9
D8
D7
D4
D3
D2
D1
D0
t
CH
SCLK
DIN
t
CL
t
DS
C3
C2
C1
D0
t
t
t
DH
CSH
CS0
t
CSS
CS
t
CSW
t
CS1
t
DO1
DOUTDC1*
DOUT VALID
t
DO2
DOUTDC0
OR
DOUTRB*
DOUT VALID
*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT).
SEE THE DATA OUTPUT (DOUTRB, DOUTDC0, DOUTDC1) SECTION FOR DETAILS.
Figure 1. Serial-Interface Timing Diagram (DSP Mode Disabled)
t
CL
SCLK
t
CH
t
DS
DIN
C3
C2
C1
D0
t
CS0
t
DH
t
CSH
t
CCS
CS
t
CSW
t
t
CS1
DSS
t
DS0
DSP
t
D02
t
t
DSPWL
DSW
DOUTDC0*
DOUT VALID
t
D01
DOUTDC1
OR
DOUT VALID
DOUTRB*
*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT).
SEE THE DATA OUTPUT (DOUTRB, DOUTDC0, DOUTDC1) SECTION FOR DETAILS.
Figure 2. Serial-Interface Timing Diagram (DSP Mode Enabled)
______________________________________________________________________________________ 17
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
Serial-Interface Programming Commands
Tables 2a, 2b, and 2c provide all the serial-interface
programming commands for the MAX5580–MAX5585.
Table 2a shows the basic DAC programming com-
mands, Table 2b gives the advanced-feature program-
ming commands, and Table 2c provides the 24-bit
read commands. Figures 3 and 4 provide serial-inter-
face diagrams for write operations.
Loading Input and DAC Registers
The MAX5580–MAX5585 contain a 16-bit shift register
that is followed by a 12-bit input register and a 12-bit
DAC register for each channel (see the Functional
Diagrams). Tables 3, 4, and 5 highlight a few of the
commands that handle the loading of the input and
DAC registers. See Table 2a for all DAC programming
commands.
V
V
DD
DD
MICROWIRE
SPI OR QSPI
MAX5580–
MAX5585
MAX5580–
MAX5585
V
DV
V
DV
DD
DD
DD
DD
DSP
SCLK
DIN
CS
DSP
SCLK
DIN
CS
SK
SO
SCK
MOSI
I/O
SS OR I/O
MICROWIRE OR SPI (CPOL = 0, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:
COMMAND TAKES EFFECT HERE
ONLY IF SCLK COUNT = N 16
CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
♦
CS
SCLK
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SPI (CPOL = 1, CPHA = 1) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:
COMMAND TAKES EFFECT HERE
ONLY IF SCLK COUNT = N 16
♦
CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
CS
SCLK
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 3. MICROWIRE and SPI Single DAC Writes (CPOL = 0, CPHA = 0 or CPOL = 1, CPHA = 1)
DSP
SPI OR QSPI
MAX5580–
MAX5585
MAX5580–
DGND
MAX5585
V
DGND
V
SS
SS
DSP
SCLK
DSP
SCLK
TCLK, SCLK, OR CLKX
DT OR DX
SCK
DIN
CS
MOSI
DIN
CS
TFS OR FSX
SS OR I/O
DSP OR SPI (CPOL = 0, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:
COMMAND TAKES EFFECT HERE
ONLY IF SCLK COUNT = N 16
CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
♦
CS
SCLK
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DSP OR SPI (CPOL = 1, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:
COMMAND TAKES EFFECT HERE
ONLY IF SCLK COUNT = N 16
♦
CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
CS
SCLK
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4. DSP and SPI Single DAC Writes (CPOL = 0, CPHA = 1 or CPOL = 1, CPHA = 0)
18 ______________________________________________________________________________________
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
______________________________________________________________________________________ 19
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
20 ______________________________________________________________________________________
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
______________________________________________________________________________________ 21
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
D 0 / X
D 1 / X
D 2 / X
D 3 / X
D 0 / X
D 1 / X
D 2 / X
D 3 / X
D 0 / X
D 1 / X
D 2 / X
D 3 / X
D 0 /
D 1 /
D 2 /
D 3 /
D 4
D 4
D 4
D 4
D 5
D 5
D 5
D 5
D 6
D 6
D 6
D 6
D 7
D 7
D 7
D 7
D 8
D 8
D 8
D 8
D 9
D 9
D 9
D 9
D 1 0
D 1 1
D 1 0
D 1 1
D 1 0
D 1 1
D 1 0
D 1 1
E 1 2
D 1
D 1 2 / X
D 1 2 / X
E 1 2 / X
D 1 3 / X
D 1 4 / X
D 1 5 / X
D 1 6
D 1 3 / X
D 1 4 / X
D 1 5 / X
D 1 6
D 1 3 / X
D 1 4 / X
D 1 5 / X
D 1 6
D 1
D 1
D 1 6
D 1 7
D 1 8
D 1 9
D 2 0
D 2 1
D 2 2
D 2 3
D 1 7
D 1 7
D 1 7
D 1 8
D 1 8
D 1 8
D 1 9
D 1 9
D 1 9
D 2 0
D 2 0
D 2 0
D 2 1
D 2 1
D 2 1
D 2 2
D 2 2
D 2 2
D 2 3
D 2 3
D 2 3
22 ______________________________________________________________________________________
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
DAC Programming Examples:
Advanced-Feature
To load input register A from the shift register, leaving
DAC register A unchanged (DAC output unchanged),
use the command in Table 3.
Programming Commands
Select Bits (M_)
The select bits allow synchronous updating of any com-
bination of channels. The select bits command the
loading of the DAC register from the input register of
each channel. Set the select bit M_ = 1 to load the DAC
register “_” with data from the input register “_”, where
“_” is replaced with A, B, C, or D, depending on the
selected channel. Setting the select bit M_ = 0 results
in no action for that channel (Table 6).
The MAX5580–MAX5585 can load all the input registers
(A–D) simultaneously from the shift register, leaving the
DAC registers unchanged (DAC output unchanged), by
using the command in Table 4.
To load all the input registers (A–D) and all the DAC regis-
ters (A–D) simultaneously, use the command in Table 5.
For the 10-bit and 8-bit versions, set sub-bits = 0 for
best performance.
Select Bits Programming Example:
To load DAC register B from input register B while
keeping other channels (A, C, D) unchanged, set MB =
1 and M_ = 0 (Table 7).
Table 3. Load Input Register A from Shift Register
DATA
CONTROL BITS
DATA BITS
D6 D5
DIN
0
0
0
0
D11
D10
D9
D8
D7
D4
D4
D3/0 D2/0 D1/0 D0/0
Table 4. Load Input Registers (A–D) from Shift Register
DATA
CONTROL BITS
DATA BITS
DIN
1
1
0
0
D11
D10
D9
D8
D7
D6 D5
D3/0 D2/0 D1/0 D0/0
Table 5. Load Input Registers (A–D) and DAC Registers (A–D) from Shift Register
DATA
CONTROL BITS
DATA BITS
D6 D5
DIN
1
1
0
1
D11
D10
D9
D8
D7
D4
D3/0 D2/0 D1/0 D0/0
Table 6. Select Bits (M_)
DATA
CONTROL BITS
DATA BITS
MD
DIN
1
1
1
0
0
0
X
X
X
X
X
X
MC
MB
MA
X = Don’t care.
Table 7. Select Bits Programming Example
DATA
CONTROL BITS
DATA BITS
DIN
1
1
1
0
0
0
X
X
X
X
X
X
0
0
1
0
X = Don’t care.
______________________________________________________________________________________ 23
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
Shutdown-Mode Bits (PD_0, PD_1)
Use the shutdown-mode bits and control bits to
shut down each DAC independently. The shutdown-
mode bits determine the output state of the selected
channels. The shutdown-control bits put the selected
channels into shutdown mode. To select the shutdown
mode for DACA–DACD, set PD_0 and PD_1 according
to Table 8 (where “_” is replaced with one of the select-
ed channels (A–D)). The three possible states for unity-
gain versions are 1) normal operation, 2) shutdown with
1kΩ output impedance, and 3) shutdown with 100kΩ
output impedance. The three possible states for force-
sense versions are 1) normal operation, 2) shutdown with
1kΩ output impedance, and 3) shutdown with the output
in a high-impedance state. Table 9 shows the com-
mands for writing to the shutdown-mode bits. Table 10
shows an example of writing the shutdown-control bits.
This command shuts down DACA with 1kΩ to ground
and shuts down DACB–DACD with 100kΩ to ground.
Always write the shutdown-mode-bits command first and
then write the shutdown-control-bits command to proper-
ly shut down the selected channels. The shutdown-
control-bits command can be written at any time after the
shutdown-mode-bits command. It does not have to
immediately follow the shutdown-mode-bits command.
Table 8. Shutdown-Mode Bits
PD_1
PD_0
DESCRIPTION
Shutdown with 1kΩ termination to ground
on DAC_ output.
0
0
Settling-Time-Mode Bits (SPD_)
The settling-time-mode bits select the settling time (FAST
mode or SLOW mode) of the MAX5580–MAX5585.
Set SPD_ = 1 to select FAST mode or set SPD_ = 0 to
select SLOW mode, where “_” is replaced by A, B, C, or
D, depending on the selected channel (Table 11). FAST
mode provides a 3µs maximum settling time, and SLOW
mode provides a 6µs maximum settling time.
Shutdown with 100kΩ termination to
ground on DAC_ output for unity-gain
versions. Shutdown with high-impedance
output for force-sense versions.
0
1
1
1
0
1
Ignored.
DAC_ is powered up in its normal
operating mode.
Table 9. Shutdown-Mode Write Command
DATA
CONTROL BITS
DATA BITS
DIN
1
1
1
0
0
1
0
X
PDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0
X = Don’t care.
Table 10. Shutdown-Mode-Bits Write Example
DATA
CONTROL BITS
DATA BITS
DIN
1
1
1
0
0
1
0
X
0
X
1
X
0
X
1
0
1
0
0
X = Don’t care.
Table 11. Settling-Time-Mode Write Command
DATA
CONTROL BITS
DATA BITS
SPDD SPDC SPDB SPDA
DIN
1
1
1
0
1
1
0
X
X
X = Don’t care.
24 ______________________________________________________________________________________
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
Settling-Time-Mode Write Example:
ing edge of SCLK. Set the DAC’s CPOL and CPHA bits
to CPOL = 0 and CPHA = 1 or CPOL = 1 and CPHA =
0 for DSP and SPI applications, requiring the clocking
of data in on the falling edge of SCLK (refer to the
Programmer’s Handbook and see Table 14 for details).
To configure DACA and DACD into FAST mode and
DACB and DACC into SLOW mode, use the command
in Table 12.
To read back the settling-time-mode bits, use the com-
mand in Table 13.
At power-up, if DSP = DV , the default value of CPHA
DD
is zero and if DSP = DGND, the default value of CPHA
is one. The default value of CPOL is zero at power-up.
CPOL and CPHA Control Bits
The CPOL and CPHA control bits of the
MAX5580–MAX5585 are defined the same as the CPOL
and CPHA bits in the SPI standard. Set the DAC’s
CPOL and CPHA bits to CPOL = 0 and CPHA = 0 or
CPOL = 1 and CPHA = 1 for MICROWIRE and SPI
applications requiring the clocking of data in on the ris-
To write to the CPOL and CPHA bits, use the command
in Table 15.
To read back the device’s CPOL and CPHA bits, use
the command in Table 16.
Table 12. Settling-Time-Mode Write Example
DATA
CONTROL BITS
DATA BITS
DIN
1
1
1
0
1
1
0
X
X
X
X
X
1
0
0
1
X = Don’t care.
Table 13. Settling-Time-Mode Read Command
DATA
CONTROL BITS
DATA BITS
DIN
1
X
1
X
1
X
0
X
1
X
1
X
1
X
1
X
X
X
X
X
X
X
X
X
X
DOUTRB
X
X
X
SPDD SPDC SPDB SPDA
X = Don’t care.
Table 14. CPOL and CPHA Bits
CPOL
CPHA
DESCRIPTION
Default values at power-up when DSP is connected to DV . Data is clocked in on the rising edge
of SCLK.
DD
0
0
Default values at power-up when DSP is connected to DGND. Data is clocked in on the falling edge
of SCLK.
0
1
1
1
0
1
Data is clocked in on the falling edge of SCLK.
Data is clocked in on the rising edge of SCLK.
Table 15. CPOL and CPHA Write Command
DATA
CONTROL BITS
DATA BITS
DIN
1
1
1
1
0
0
0
0
X
X
X
X
X
X
CPOL CPHA
X = Don’t care.
Table 16. CPOL and CPHA Read Command
DATA
CONTROL BITS
DATA BITS
DIN
1
X
1
X
1
X
1
X
0
X
0
X
0
X
1
X
X
X
X
X
X
X
X
X
X
X
DOUTRB
X
X
X
X
CPOL CPHA
X = Don’t care.
______________________________________________________________________________________ 25
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
UPIO Bits (UPSL1, UPSL2, UP0–UP3)
The MAX5580–MAX5585 provide two user-programma-
ble input/output (UPIO) ports: UPIO1 and UPIO2. These
ports have 15 possible configurations, as shown in
Table 21. UPIO1 and UPIO2 can be programmed inde-
pendently or simultaneously by writing to the UPSL1,
UPSL2, and UP0–UP3 bits (Table 17).
UPIO Programming Example:
To set only UPIO1 as LDAC and leave UPIO2
unchanged, use the command in Table 19.
The UPIO selection and configuration bits can be read
back from the MAX5580–MAX5585 when UPIO1 or
UPIO2 is configured as a DOUTRB output. Table 20
shows the read-back data format for the UPIO bits.
Writing the command in Table 20 initiates a read opera-
tion of the UPIO bits. The data is clocked out starting on
the 9th clock cycle of the sequence. Bits UP3-2 through
UP0-2 provide the UP3–UP0 configuration bits for
UPIO2 (Table 21), and bits UP3-1 through UP0-1 pro-
vide the UP3–UP0 configuration bits for UPIO1.
Table 18 shows how UPIO1 and UPIO2 are selected for
configuration. The UP0–UP3 bits select the desired
functions for UPIO1 and/or UPIO2 (Table 21).
Table 17. UPIO Write Command
DATA
CONTROL BITS
DATA BITS
DIN
1
1
1
0
1
0
0
X
UPSL2 UPSL1 UP3
UP2
UP1
UP0
X
X
X = Don’t care.
Table 18. UPIO Selection Bits (UPSL1 and UPSL2)
UPSL2
UPSL1
UPIO PORT SELECTED
None selected
0
0
1
1
0
1
0
1
UPIO1 selected
UPIO2 selected
Both UPIO1 and UPIO2 selected
Table 19. UPIO Programming Example
DATA
CONTROL BITS
DATA BITS
DIN
1
1
1
0
1
0
0
X
0
1
0
0
0
0
X
X
X
X
X = Don’t care.
Table 20. UPIO Read Command
DATA
CONTROL BITS
DATA BITS
DIN
1
X
1
X
1
X
0
X
1
X
0
X
1
X
X
X
X
X
X
X
DOUTRB
X
X
UP3-2 UP2-2 UP1-2 UP0-2 UP3-1 UP2-1 UP1-1 UP0-1
X = Don’t care.
26 ______________________________________________________________________________________
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
UPIO Configuration
Table 21 lists the possible configurations for UPIO1 and
UPIO2. UPIO1 and UPIO2 use the selected function
when configured by the UP3–UP0 configuration bits.
Drive LDAC low to asynchronously load the DAC regis-
ters from their corresponding input registers (DACs that
are in shutdown remain shut down). The LDAC input
does not require any activity on CS, SCLK, or DIN to
take effect. If LDAC is brought low coincident with a ris-
ing edge of CS (which executes a serial command
modifying the value of either DAC input register), then
LDAC must remain asserted for at least 120ns following
the CS rising edge. This requirement applies only for
serial commands that modify the value of the DAC input
registers. See Figures 5 and 6 for timing details.
LDAC
LDAC controls the loading of the DAC registers. When
LDAC is high, the DAC registers are latched, and any
change in the input registers does not affect the con-
tents of the DAC registers or the DAC outputs. When
LDAC is low, the DAC registers are transparent, and the
values stored in the input registers are fed directly to the
DAC registers, and the DAC outputs are updated.
Table 21. UPIO Configuration Register Bits (UP3–UP0)
UPIO CONFIGURATION BITS
FUNCTION
DESCRIPTION
UP3
UP2
UP1
UP0
Active-Low Load DAC Input. Drive low to asynchronously load all DAC registers
with data from input registers.
0
0
0
0
LDAC
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
SET
MID
CLR
PDL
Active-Low Input. Drive low to set all input and DAC registers to full scale.
Active-Low Input. Drive low to set all input and DAC registers to midscale.
Active-Low Input. Drive low to set all input and DAC registers to zero scale.
Active-Low Power-Down Lockout Input. Drive low to disable software shutdown.
Reserved This mode is reserved. Do not use.
Active-Low 1kΩ Shutdown Input. Overrides PD_1 and PD_0 settings. For the
MAX5580/MAX5582/MAX5584, drive SHDN1K low to pull OUTA–OUTD to AGND
with 1kΩ. For the MAX5581/MAX5583/MAX5585, drive SHDN1K low to leave
OUTA–OUTD high impedance.
0
0
1
1
1
1
0
1
SHDN1K
Active-Low 100kΩ Shutdown Input. Overrides PD_1 and PD_0 settings. For the
MAX5580/MAX5582/MAX5584, drive SHDN100K low to pull OUTA–OUTD to
AGND with 100kΩ. For the MAX5581/MAX5583/MAX5585, drive low to leave
OUTA–OUTD high impedance.
SHDN100K
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
DOUTRB
Data Read-Back Output
DOUTDC0 Mode 0 Daisy-Chain Data Output. Data is clocked out on the falling edge of SCLK.
DOUTDC1 Mode 1 Daisy-Chain Data Output. Data is clocked out on the rising edge of SCLK.
GPI
General-Purpose Logic Input
GPOL
GPOH
General-Purpose Logic-Low Output
General-Purpose Logic-High Output
Toggle Input. Toggles DAC outputs between data in input registers and data in
DAC registers. Drive low to set all DAC outputs to values stored in input registers.
Drive high to set all DAC outputs to values stored in DAC registers.
1
1
1
1
1
1
0
1
TOGG
Fast/Slow Settling-Time-Mode Input. Drive low to select FAST (3µs) mode or drive
high to select SLOW (6µs) settling mode. Overrides the SPDA–SPDD settings.
FAST
______________________________________________________________________________________ 27
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
t
LDL
LDAC
TOGG
END OF
CYCLE*
t
GP
GPO_
LDAC
PDL
t
LDS
t
CMS
CLR,
MID, OR
SET
t
S
±0.5 LSB
* END-OF-CYCLE REPRESENTS THE RISING EDGE OF CS OR THE 16TH
ACTIVE CLOCK EDGE, DEPENDING ON THE MODE OF OPERATION.
V
OUT_
PDL AFFECTS DAC OUTPUTS (V
) ONLY IF DACS WERE PREVIOUSLY SHUT DOWN.
OUT_
Figure 6. GPO_ and LDAC Signal Timing
Figure 5. Asynchronous Signal Timing
SET, MID, CLR
SHDN1K low to select shutdown mode with OUTA–
OUTD internally terminated with 1kΩ to ground, or drive
SHDN100K low to select shutdown with an internal
100kΩ termination. For the MAX5581/MAX5583/
MAX5585, drive SHDN1K low for shutdown with 1kΩ
output termination, or drive SHDN100K low for shut-
down with high-impedance outputs.
The SET, MID, and CLR signals force the DAC outputs
to full scale, midscale, or zero scale (Figure 5). These
signals cannot be active at the same time.
The active-low SET input forces the DAC outputs to full
scale when SET is low. When SET is high, the DAC out-
puts follow the data in the DAC registers.
Data Output (DOUTRB, DOUTDC0, DOUTDC1)
UPIO1 and UPIO2 can be configured as serial data out-
puts, DOUTRB (data out for read back), DOUTDC0
(data out for daisy-chaining, mode 0), and DOUTDC1
(data out for daisy-chaining, mode 1). The differences
between DOUTRB and DOUTDC0 (or DOUTDC1) are
as follows:
The active-low MID input forces the DAC outputs to
midscale when MID is low. When MID is high, the DAC
outputs follow the data in the DAC registers.
The active-low CLR input forces the DAC outputs to
zero scale when CLR is low. When CLR is high, the
DAC outputs follow the data in the DAC registers.
If CLR, MID, or SET signals go low during a write com-
mand, reload the data to ensure accurate results.
•
The source of read-back data on DOUTRB is the
DOUT register. Daisy-chain DOUTDC_ data comes
directly from the shift register.
Power-Down Lockout (PDL)
The PDL active-low, software-shutdown lockout input
overrides (not overwrites) the PD_0 and PD_1 shutdown-
mode bits. PDL cannot be active at the same time as
SHDN1K or SHDN100K (see the Shutdown Mode
(SHDN1K, SHDN100K) section).
•
Read-back data on DOUTRB is only present after a
DAC read command. Daisy-chain data is present on
DOUTDC_ for any DAC write after the first 16 bits
are written.
•
The DOUTRB idle state (CS = high) for read back is
high impedance. Daisy-chain DOUTDC_ idles high
when inactive to avoid floating the data input in the
next device in the daisy-chain.
If the PD_0 and PD_1 bits command the DAC to
shut down prior to PDL going low, the DAC returns to
shutdown mode immediately after PDL goes high,
unless the PD_0 and PD_1 bits were modified through
the serial interface in the meantime.
See Figures 1 and 2 for timing details.
Shutdown Mode (SHDN1K, SHDN100K)
The SHDN1K and SHDN100K are active-low signals
that override (not overwrite) the PD_1 and PD_0 bit set-
tings. For the MAX5580/MAX5582/MAX5584, drive
28 ______________________________________________________________________________________
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
GPI, GPOL, GPOH
UPIO1 and UPIO2 can each be configured as a gener-
al-purpose input (GPI), a general-purpose output low
(GPOL), or a general-purpose output high (GPOH).
GPOL outputs a constant low, and GPOH outputs a
constant high. See Figure 6.
TOGG
Use the TOGG input to toggle the DAC outputs
between the values in the input registers and DAC reg-
isters. A delay of greater than 100ns from the end of the
previous write command is required before the TOGG
signal can be correctly switched between the new
value and the previously stored value. When TOGG =
0, the output follows the information in the input regis-
ters. When TOGG = 1, the output follows the informa-
tion in the DAC register (Figure 5).
The GPI can serve to detect interrupts from µPs or micro-
controllers. The GPI has three functions:
1) Sample the signal at GPI at the time of the read
(RTP1 and RTP2).
2) Detect whether a falling edge has occurred since
the last read or reset (LF1 and LF2).
3) Detect whether a rising edge has occurred since
the last read or reset (LR1 and LR2).
FAST
The MAX5580–MAX5585 have two settling-time-mode
options: FAST (3µs max) and SLOW (6µs max). To
select the FAST mode, drive FAST low, and to select
SLOW mode, drive FAST high. This overrides (not over-
writes) the SPDA–SPDD bit settings.
RTP1, LF1, and LR1 represent the data read from
UPIO1; RTP2, LF2, and LR2 represent the data read
from UPIO2.
To issue a read command for the UPIO configured as
GPI, use the command in Table 22.
Once the command is issued, RTP1 and RTP2 provide
the real-time status (0 or 1) of the inputs at UPIO1 or
UPIO2, respectively, at the time of the read. If LF2 or
LF1 is one, then a falling edge has occurred on the
respective UPIO1 or UPIO2 input since the last read or
reset. If LR2 or LR1 is one, then a rising edge has
occurred since the last read or reset.
Table 22. GPI Read Command
DATA
CONTROL BITS
DATA BITS
DIN
1
X
1
X
1
X
1
X
0
X
0
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
DOUTRB
RTP2 LF2
LR2 RTP1 LF1
LR1
X = Don’t care.
Table 23. Unipolar Code Table (Gain = +1)
DAC_
REF
DAC CONTENTS
MAX6126
ANALOG OUTPUT
MSB
1111
1000
1000
0111
0000
0000
LSB
1111
0001
0000
1111
0001
0000
OUT_
1111
0000
0000
1111
0000
0000
+V
+V
(4095 / 4096)
(2049 / 4096)
REF
REF
+V
(2048 / 4096) = V
/ 2
REF
REF
MAX5580
+V
(2047 / 4096)
(1 / 4096)
REF
V
= V
x CODE / 4096
REF_
OUT_
+V
WHERE CODE IS THE DAC INPUT
CODE (0 TO 4095 DECIMAL)
REF
0
Figure 7. Unipolar Output Circuit
______________________________________________________________________________________ 29
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
Applications Information
Unipolar Output
Figure 7 shows the unity-gain MAX5580 in a unipolar
output configuration. Table 23 lists the unipolar out-
put codes.
10kΩ
10kΩ
V+
Bipolar Output
The MAX5580 outputs can be configured for bipolar
V
DAC_
OUT_
operation, as shown in Figure 8. The output voltage is
MAX6126
REF
given by the following equation:
V-
MAX5580
MAX5582
MAX5584
V
OUT_
= V x (CODE - 2048) / 2048
REF
where CODE represents the numeric value of the
DAC’s binary input code (0 to 4095 decimal). Table 24
shows digital codes and the corresponding output volt-
age for the circuit in Figure 8.
Configurable Output Gain
The MAX5581/MAX5583/MAX5585 have force-sense
outputs, which provide a direct connection to the invert-
ing terminal of the output op amp, yielding the most
flexibility. The force-sense output has the advantage
that specific gains can be set externally for a given
application. The gain error for the MAX5581/MAX5583/
MAX5585 is specified in a unity-gain configuration (op-
amp output and inverting terminals connected), and
additional gain error results from external resistor
tolerances. The force-sense DACs allow many useful
circuits to be created with only a few simple external
components.
Figure 8. Bipolar Output Circuit
DAC_
MAX6126
REF
OUT_
FB_
R2 = 12kΩ
0.1%
25ppm
MAX5581
An example of a custom, fixed gain using the
MAX5581’s force-sense output is shown in Figure 9. In
this example, the external reference is set to 1.25V, and
the gain is set to +1.1V/V with external discrete resis-
tors to provide an approximate 0 to 1.375V DAC output
voltage range.
R1 = 10kΩ
0.1%
25ppm
V
= [(0.5 x V
x CODE) / 4096] x [1 + (R2 / R1)]
REF_
OUT
where CODE represents the numeric value of the
DAC’s binary input code (0 to 4095 decimal).
Figure 9. Configurable Output Gain
In this example, R2 = 12kΩ and R1 = 10kΩ to set the
gain = 1.1V/V:
Table 24. Bipolar Code Table (Gain = +1)
DAC CONTENTS
V
OUT
= [(0.5 x 1.25V x CODE) / 4096] x 2.2
ANALOG OUTPUT
MSB
1111
1000
1000
0111
0000
0000
LSB
1111
0001
0000
1111
0001
0000
1111
0000
0000
1111
0000
0000
+V
(2047 / 2048)
REF
+V
(1 / 2048)
0
REF
-V
-V
(1 / 2048)
REF
(2047 / 2048)
REF
-V
(2048 / 2048) = -V
REF
REF
30 ______________________________________________________________________________________
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
inductance ground plane. Wire-wrapped boards and
sockets are not recommended. For optimum system
performance, use PC boards with separate analog and
digital ground planes. Connect the two ground planes
together at the low-impedance power-supply source.
Power-Supply and Layout Considerations
Bypass the analog and digital power supplies by using a
10µF capacitor in parallel with a 0.1µF capacitor to AGND
and DGND (Figure 10). Minimize lead lengths to reduce
lead inductance. Use shielding and/or ferrite beads to fur-
ther increase isolation.
Using separate power supplies for AV
and DV
DD
DD
improves noise immunity. Connect AGND and DGND at
the low-impedance power-supply sources (Figure 11).
Digital and AC transient signals coupling to AGND can
create noise at the output. Connect AGND to the high-
est quality ground available. Use proper grounding
techniques, such as a multilayer board with a low-
AV
DV
DD
DD
10µF
0.1µF
0.1µF
10µF
ANALOG SUPPLY
AV AGND
DIGITAL SUPPLY
DV DGND
AV
DV
DD
DD
OUTA
DD
DD
REF
MAX6126
FBA*
OUTB
FBB*
0.1µF**
MAX5580–
MAX5585
1µF**
OUTC
FBC*
CS
10µF
10µF
SCLK
DIN
PU
OUTD
FBD*
0.1µF
0.1µF
DSP
UPIO1
UPIO2
AV
AGND
DV
DGND
DV
DD
DGND
DIGITAL
CIRCUITRY
DD
DD
AGND***
DGND***
MAX5580–MAX5585
*MAX5581/MAX5583/MAX5585 ONLY.
**REMOVE BYPASS CAPACITORS ON REF FOR AN AC REFERENCE INPUT.
***CONNECT ANALOG AND DIGITAL GROUND AT THE PLANES AT
THE LOW-IMPEDANCE POWER-SUPPLY SOURCE.
Figure 11. Separate Analog and Digital Power Supplies
Figure 10. Bypassing Power Supplies AV , DV , and REF
DD
DD
______________________________________________________________________________________ 31
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
Pin Configurations
TOP VIEW
AGND
AV
1
2
3
4
5
6
7
8
9
20 REF
19 N.C. (*FBC)
18 OUTC
DD
20 19 18 17 16
N.C. (*FBB)
OUTB
17 N.C. (*FBD)
16 OUTD
N.C. (*FBB)
OUTB
1
2
3
4
5
15 N.C. (*FBD)
14 OUTD
13 DSP
MAX5580–
MAX5585
N.C. (*FBA)
OUTA
15 DSP
N.C. (*FBA)
OUTA
MAX5580–
MAX5585
PU
14
DGND
12 DGND
CS
13 DV
DD
11
DV
PU
**EP
6
DD
SCLK
12 UPIO2
11 UPIO1
**EP
7
8
9
10
DIN 10
TSSOP
THIN QFN
*FOR THE MAX5581/MAX5583/MAX5585
**EXPOSED PADDLE CONNECTED TO AGND
Ordering Information (continued)
Chip Information
TRANSISTOR COUNT: 24,393
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
20 TSSOP-EP**
20 Thin QFN-EP**
20 TSSOP-EP**
20 Thin QFN-EP**
20 TSSOP-EP**
20 Thin QFN-EP**
20 TSSOP-EP**
20 Thin QFN-EP**
20 TSSOP-EP**
20 Thin QFN-EP**
20 TSSOP-EP**
20 Thin QFN-EP**
20 TSSOP-EP**
20 Thin QFN-EP**
PROCESS: BiCMOS
MAX5580BEUP
MAX5580BETP
MAX5581AEUP*
MAX5581AETP*
MAX5581BEUP
MAX5581BETP
MAX5582EUP
MAX5582ETP
MAX5583EUP
MAX5583ETP
MAX5584EUP
MAX5584ETP
MAX5585EUP
MAX5585ETP
*Future product—contact factory for availability. Specifications
are preliminary.
**EP = Exposed paddle.
32 ______________________________________________________________________________________
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
D2
0.15
C A
D
b
0.10 M
C A B
C
L
D2/2
D/2
k
PIN # 1
I.D.
0.15
C
B
PIN # 1 I.D.
0.35x45∞
E/2
E2/2
C
(NE-1) X
e
L
E2
E
k
L
DETAIL A
e
(ND-1) X
e
DETAIL B
e
L
C
L
C
L
L1
L
L
e
e
0.10
C
A
0.08
C
C
A1 A3
PACKAGE OUTLINE
16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm
1
E
21-0140
2
COMMON DIMENSIONS
20L 5x5 28L 5x5
EXPOSED PAD VARIATIONS
DOWN
BONDS
ALLOWED
PKG.
D2
E2
16L 5x5
32L 5x5
40L 5x5
PKG.
CODES
SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
MIN. NOM. MAX. MIN. NOM. MAX.
T1655-1 3.00 3.10 3.20 3.00 3.10 3.20
NO
A
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80
T1655-2 3.00 3.10 3.20 3.00 3.10 3.20 YES
NO
T2055-3 3.00 3.10 3.20 3.00 3.10 3.20 YES
A1
-
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
0
0.05
0.20 REF.
T2055-2 3.00 3.10 3.20 3.00 3.10 3.20
A3
b
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
NO
T2055-4 3.00 3.10 3.20 3.00 3.10 3.20
D
E
T2855-1 3.15 3.25 3.35 3.15 3.25 3.35
T2855-2 2.60 2.70 2.80 2.60 2.70 2.80
NO
NO
e
0.80 BSC.
0.25
0.65 BSC.
0.25
0.50 BSC.
0.25
0.50 BSC.
0.25
0.40 BSC.
T2855-3 3.15 3.25 3.35 3.15 3.25 3.35 YES
k
-
-
-
-
-
-
-
-
0.25 0.35 0.45
YES
NO
T2855-4 2.60 2.70 2.80 2.60 2.70 2.80
T2855-5 2.60 2.70 2.80 2.60 2.70 2.80
T2855-6 3.15 3.25 3.35 3.15 3.25 3.35
L
0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60
L1
-
-
-
-
-
-
-
-
-
-
-
-
0.30 0.40 0.50
NO
N
ND
16
4
4
20
5
5
28
7
7
32
8
8
40
10
10
2.80
3.20
T2855-7 2.60 2.70
T3255-2
T3255-3 3.00 3.10
2.60 2.70 2.80 YES
NO
3.00 3.10 3.20 YES
NO
3.00 3.10
3.00 3.10 3.20
NE
3.20
WHHB
WHHC
WHHD-1
WHHD-2
-
JEDEC
T3255-4 3.00 3.10 3.20 3.00 3.10 3.20
T4055-1 3.20 3.30 3.40 3.20 3.30 3.40 YES
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1,
T2855-3 AND T2855-6.
PACKAGE OUTLINE
16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
2
E
21-0140
2
______________________________________________________________________________________ 33
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, TSSOP, 4.40 MM BODY
EXPOSED PAD
1
21-0108
D
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
34 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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