MAX5590AEUG_技术文档

19-2983; Rev 0; 9/03

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

General Description

Features

♦ Octal, 12/10/8-Bit Serial DACs in TSSOP Packages

♦ 3µs (max) 12-Bit Settling Time to 1/2 LSB

The MAX5590–MAX5595 octal, 12/10/8-bit, voltage-out-

put digital-to-analog converters (DACs) offer buffered

outputs and a 3µs maximum settling time at the 12-bit

level. The DACs operate from a +2.7V to +5.25V analog

supply and a separate +1.8V to +5.25V digital supply.

The 20MHz 3-wire serial interface is compatible with

SPI™, QSPI™, MICROWIRE™, and digital signal

processor (DSP) protocol applications. Multiple devices

can share a common serial interface in direct-access or

daisy-chained configuration. The MAX5590–MAX5595

provide two multifunction, user-programmable, digital

I/O ports. The externally selectable power-up states of

the DAC outputs are either zero scale, midscale, or full

scale. Software-selectable FAST and SLOW settling

modes decrease settling time in FAST mode, or reduce

supply current in SLOW mode.

♦ Integral Nonlinearity:

1 LSB (max) MAX5590/MAX5591 A-Grade (12-Bit)

1 LSB (max) MAX5592/MAX5593 (10-Bit)

1/2 LSB (max) MAX5594/MAX5595 (8-Bit)

♦ Guaranteed Monotonic, 1 LSB (max) DNL

♦ Two User-Programmable Digital I/O Ports

♦ Single +2.7V to +5.25V Analog Supply

♦ +1.8V to AV

Digital Supply

DD

♦ 20MHz, 3-Wire, SPI-/QSPI-/MICROWIRE-/DSP-

Compatible Serial Interface

The MAX5590/MAX5591 are 12-bit DACs, the MAX5592/

MAX5593 are 10-bit DACs, and the MAX5594/

MAX5595 are 8-bit DACs. The MAX5590/MAX5592/

MAX5594 provide unity-gain-configured output buffers,

while the MAX5591/MAX5593/MAX5595 provide force-

sense-configured output buffers. The MAX5590–

MAX5595 are specified over the extended -40°C to

+85°C temperature range, and are available in space-

saving 24-pin and 28-pin TSSOP packages.

♦ Glitch-Free Outputs Power Up to Zero Scale,

Midscale, or Full Scale Controlled by PU Pin

♦ Unity-Gain or Force-Sense-Configured Output

Buffers

Applications

Portable Instrumentation

Ordering Information

PART

TEMP RANGE

-40°C to +85°C

PIN-PACKAGE

24 TSSOP

28 TSSOP

24 TSSOP

28 TSSOP

24 TSSOP

28 TSSOP

Automatic Test Equipment (ATE)

Digital Offset and Gain Adjustment

Automatic Tuning

MAX5590AEUG*

MAX5590BEUG

MAX5591AEUI*

MAX5591BEUI

MAX5592EUG

MAX5593EUI

MAX5594EUG

MAX5595EUI

Programmable Voltage and Current Sources

Programmable Attenuators

Industrial Process Controls

Motion Control

Microprocessor (µP)-Controlled Systems

Power Amplifier Control

*Future product—contact factory for availability. Specifications

are preliminary.

Fast Parallel-DAC to Serial-DAC Upgrades

Selector Guide and Pin Configurations appear at end of data

sheet.

SPI/QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

ABSOLUTE MAXIMUM RATINGS

AV

to DV ........................................................................ 6V

Maximum Current into Any Pin ......................................... 50mA

DD

AGND to DGND.................................................................. 0.3V

Continuous Power Dissipation (T = +70°C)

A

AV

DV

to AGND, DGND.............................................-0.3V to +6V

to AGND, DGND ............................................-0.3V to +6V

24-Pin TSSOP (derate 12.2mW/°C above +70°C) .......976mW

28-Pin TSSOP (derate 12.8mW/°C above +70°C) .....1026mW

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range.............................-65°C to +150°C

Maximum Junction Temperature .....................................+150°C

Lead Temperature (soldering, 10s) .................................+300°C

DD

FB_, OUT_,

REF to AGND........-0.3V to the lower of (AV + 0.3V) or +6V

DD

SCLK, DIN, CS, PU,

DSP to DGND.......-0.3V to the lower of (DV + 0.3V) or +6V

DD

UPIO1, UPIO2

to DGND...............-0.3V to the lower of (DV + 0.3V) or +6V

DD

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(AV

= 2.7V to 5.25V, DV

= 1.8V to AV , AGND = 0, DGND = 0, V

= 2.5V (for AV

= 2.7V to 5.25V), V

= 4.096V (for

REF

DD

REF

DD

AV

(Note 1)

= 4.5V to 5.25V), R = 10kΩ, C = 100pF, T = T

to T

, unless otherwise noted. Typical values are at T = +25°C.)

MAX A

DD

L

A

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STATIC ACCURACY

MAX5590/MAX5591

MAX5592/MAX5593

MAX5594/MAX5595

12

10

8

Resolution

N

Bits

MAX5590A/MAX5591A (12-bit)

MAX5590B/MAX5591B (12-bit)

MAX5592/MAX5593 (10-bit)

MAX5594/MAX5595 (8-bit)

1

4

1

V

AV

V

AV

= 2.5V at

= 2.7V and

= 4.096V at

= 5.25V

REF

DD

2

Integral Nonlinearity

INL

LSB

REF

0.5

DD

(Note 2)

0.125

0.5

1

Differential Nonlinearity

Offset Error

DNL

Guaranteed monotonic (Note 2)

LSB

mV

MAX5590A/MAX5591A (12-bit), decimal code = 40

MAX5590B/MAX5591B (12-bit), decimal code = 40

MAX5592/MAX5593 (10-bit), decimal code = 10

MAX5594/MAX5595 (8-bit), decimal code = 3

5

25

V

OS

ppm of

FS/°C

Offset-Error Drift

Gain Error

5

MAX5590A/MAX5591A (12-bit)

4

40

10

3

MAX5590B/MAX5590B (12-bit)

Full-scale output

20

5

GE

LSB

MAX5592/MAX5593 (10-bit)

MAX5594/MAX5595 (8-bit)

2

ppm of

FS/°C

Gain-Error Drift

1

2

_______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

ELECTRICAL CHARACTERISTICS (continued)

(AV

= 2.7V to 5.25V, DV

= 1.8V to AV , AGND = 0, DGND = 0, V

= 2.5V (for AV

= 2.7V to 5.25V), V

= 4.096V (for

REF

DD

REF

DD

AV

(Note 1)

= 4.5V to 5.25V), R = 10kΩ, C = 100pF, T = T

to T

, unless otherwise noted. Typical values are at T = +25°C.)

MAX A

DD

L

A

MIN

PARAMETER

SYMBOL

CONDITIONS

Full-scale output, AV = 2.7V to 5.25V

MIN

TYP

MAX

UNITS

Power-Supply Rejection

Ratio

PSRR

200

µV/V

DD

REFERENCE INPUT

Reference Input Range

V

R

0.25

145

AV

V

REF

DD

Reference Input

Resistance

Normal operation (no code dependence)

Shutdown mode

200

0.5

kΩ

REF

Reference Leakage

Current

1

µA

DAC OUTPUT CHARACTERISTICS

Unity gain

SLOW mode, full scale

Force sense

85

67

Output Voltage Noise

µV

RMS

Unity gain

FAST mode, full scale

Force sense

140

110

Unity-gain output

0

AV

DD

Output Voltage Range

(Note 3)

V

Force-sense output

AV / 2

DD

DC Output Impedance

38

57

45

30

40

Ω

AV

= 5V, OUT_ to AGND, full scale, FAST mode

= 3V, OUT_ to AGND, full scale, FAST mode

DD

Short-Circuit Current

mA

DD

Power-Up Time

Wake-Up Time

From V

applied until interface is functional

60

µs

DD

Coming out of shutdown, outputs settled

Output OUT_ and FB_

Open-Circuit Leakage

Current

Programmed in shutdown mode, force-sense

outputs only

0.01

µA

DIGITAL OUTPUTS (UPIO_)

DV

0.5

-

DD

Output High Voltage

V

I

= 2mA

SOURCE

V

OH

Output Low Voltage

V

I = 2mA

SINK

0.4

OL

DIGITAL INPUTS (SCLK, CS, DIN, DSP, UPIO_)

DV ≥ 2.7V

2.4

DD

Input High Voltage

V

IH

0.7 x

DV < 2.7V

DD

DV

DD

DV > 3.6V

DD

0.8

0.6

0.2

1

Input Low Voltage

V

2.7V ≤ DV ≤ 3.6V

IL

DD

DV < 2.7V

DD

Input Leakage Current

Input Capacitance

I

0.1

10

µA

pF

IN

C

IN

_______________________________________________________________________________________

3

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

ELECTRICAL CHARACTERISTICS (continued)

(AV

= 2.7V to 5.25V, DV

= 1.8V to AV , AGND = 0, DGND = 0, V

= 2.5V (for AV

= 2.7V to 5.25V), V

= 4.096V (for

REF

DD

REF

DD

AV

(Note 1)

= 4.5V to 5.25V), R = 10kΩ, C = 100pF, T = T

to T

, unless otherwise noted. Typical values are at T = +25°C.)

MAX A

DD

L

A

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

PU INPUT

DV

200mV

-

DD

Input High Voltage

Input Low Voltage

Input Leakage Current

V

IH-PU

V

200

mV

nA

IL-PU

IN-PU

PU still considered floating when connected to a

tri-state bus

I

DYNAMIC PERFORMANCE

FAST mode

SLOW mode

3.6

1.6

Voltage-Output Slew

Rate

SR

V/µs

MAX5590/MAX5591 from code 322 to

code 4095 to 1/2 LSB

2

1.5

1

3

2

6

4

FAST

mode

MAX5592/MAX5593 from code 10 to

code 1023 to 1/2 LSB

MAX5594/MAX5595 from code 3 to

code 255 to 1/2 LSB

Voltage-Output Settling

Time (Note 5)

µs

MAX5590/MAX5591 from code 322 to

code 4095 to 1/2 LSB

3

SLOW

mode

MAX5592/MAX5593 from code 10 to

code 1023 1/2 LSB

2.5

2

MAX5594/MAX5595 from code 3 to

code 255 to 1/2 LSB

FB_ Input Voltage

FB_ Input Current

0

V

/ 2

V

REF

0.1

µA

Unity gain

200

150

Reference -3dB

Bandwidth (Note 6)

kHz

Force sense

CS = DV , code = zero scale, any digital input

DD

Digital Feedthrough

0.1

nV-s

from 0 to DV

and DV

to 0, f = 100kHz

DD

Digital-to-Analog Glitch

Impulse

Major carry transition

(Note 4)

2

nV-s

DAC-to-DAC Crosstalk

15

4

_______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

ELECTRICAL CHARACTERISTICS (continued)

(AV

= 2.7V to 5.25V, DV

= 1.8V to AV , AGND = 0, DGND = 0, V

= 2.5V (for AV

= 2.7V to 5.25V), V

= 4.096V (for

REF

DD

REF

DD

AV

(Note 1)

= 4.5V to 5.25V), R = 10kΩ, C = 100pF, T = T

to T

, unless otherwise noted. Typical values are at T = +25°C.)

MAX A

DD

L

A

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

POWER REQUIREMENTS

Analog Supply Voltage

Range

AV

DV

2.70

1.8

5.25

V

DD

Digital Supply Voltage

Range

AV

DD

SLOW mode, all digital inputs

Unity gain

1.5

2.4

2.5

3.4

3.2

at DGND or DV , no load,

DD

I

AVDD

+

Force sense

Unity gain

4.8

8

V

= 4.096V

REF

Operating Supply

Current

mA

µA

FAST mode, all digital inputs

at DGND or DV , no load,

I

DVDD

DD

Force sense

8

V

= 4.096V

REF

I

AVDD(SHDN)

+

Shutdown Supply

Current

No clocks, all digital inputs at DGND or DV , all

DD

DACs in shutdown mode

0.5

1

I

DVDD(SHDN)

Note 1: For the force-sense versions, FB_ is connected to its respective OUT_. V

Note 2: Linearity guaranteed from decimal code 40 to code 4095 for the MAX5590B/MAX5591B (12-bit, B-grade), code 10 to code

(max) = V

/ 2, unless otherwise noted.

REF

OUT

1023 for the MAX5592/MAX5593 (10-bit), and code 3 to code 255 for the MAX5594/MAX5595 (8-bit).

Note 3: Represents the functional range. The linearity is guaranteed at V

= 2.5V (for AV

from 2.7V to 5.25V), and V

=

REF

DD

REF

= 4.5V to 5.25V). See the Typical Operating Characteristics section for linearity at other voltages.

4.096V (for AV

DD

Note 4: DC crosstalk is measured as follows: outputs of DACA–DACH are set to full scale and the output of DACH is measured.

While keeping DACH unchanged, the outputs of DACA–DACG are transitioned to zero scale and the ∆V

measured.

of DACH is

OUT

Note 5: Guaranteed by design.

Note 6: The reference -3dB bandwidth is measured with a 0.1V

sine wave on V

REF

and with full-scale input code.

P-P

_______________________________________________________________________________________

5

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V, 5V Logic) (Figure 1)

(DV

= 2.7V to 5.25V, GND = 0, T = T

MIN

to T , unless otherwise noted.)

MAX

DD

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

MHz

ns

SCLK Frequency

f

2.7V < DV

(Note 7)

< 5.25V

DD

20

SCLK

SCLK Pulse-Width High

t

20

10

5

CH

SCLK Pulse-Width Low

t

ns

CL

CS Fall to SCLK Rise Setup Time

SCLK Rise to CS Rise Hold Time

SCLK Rise to CS Fall Setup

DIN to SCLK Rise Setup Time

DIN to SCLK Rise Hold Time

t

ns

CSS

CSH

t

ns

t

10

12

5

ns

CS0

t

ns

DS

t

ns

DH

SCLK Rise to DOUTDC1 Valid

Propagation Delay

t

C = 20pF, UPIO_ = DOUTDC1 mode

30

ns

DO1

DO2

L

SCLK Fall to DOUT_ Valid

Propagation Delay

C = 20pF, UPIO_ = DOUTDC0 or DOUTRB

L

mode

t

CS Rise to SCLK Rise Hold Time

CS Pulse-Width High

t

MICROWIRE and SPI modes 0 and 3

10

45

ns

CS1

t

CSW

UPIO_ TIMING CHARACTERISTICS

DOUT Tri-State Time when Exiting

DOUTDC0, DOUTDC1, and UPIO

Modes

C = 20pF, from end of write cycle to UPIO_

L

in high impedance

t

100

ns

DOZ

DOUTRB Tri-State Time from CS

Rise

C = 20pF, from rising edge of CS to UPIO_

in high impedance

L

t

20

ns

DRBZ

DOUTRB Tri-State Enable Time

from 8th SCLK Rise

C = 20pF, from 8th rising edge of SCLK to

L

UPIO_ driven out of tri-state

t

ZEN

LDAC Pulse-Width Low

t

Figure 5

20

100

20

ns

LDL

LDS

LDAC Effective Delay

Figure 6

CLR, MID, SET Pulse-Width Low

GPO Output Settling Time

t

Figure 5

CMS

t

Figure 6

100

GP

GPO Output High-Impedance

Time

t

ns

GPZ

6

_______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1)

(DV

= 1.8V to 5.25V, GND = 0, T = T

MIN

to T , unless otherwise noted.)

MAX

DD

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

MHz

ns

SCLK Frequency

f

1.8V < DV

(Note 7)

< 5.25V

DD

10

SCLK

SCLK Pulse-Width High

t

40

20

0

CH

SCLK Pulse-Width Low

t

ns

CL

CS Fall to SCLK Rise Setup Time

SCLK Rise to CS Rise Hold Time

SCLK Rise to CS Fall Setup

DIN to SCLK Rise Setup Time

DIN to SCLK Rise Hold Time

t

ns

CSS

CSH

t

ns

t

10

20

5

ns

CS0

t

ns

DS

t

ns

DH

SCLK Rise to DOUTDC1 Valid

Propagation Delay

t

C = 20pF, UPIO_ = DOUTDC1 mode

60

ns

DO1

DO2

L

SCLK Fall to DOUT_ Valid

Propagation Delay

C = 20pF, UPIO_ = DOUTDC0 or DOUTRB

L

mode

t

CS Rise to SCLK Rise Hold Time

CS Pulse-Width High

t

MICROWIRE and SPI modes 0 and 3

20

90

ns

CS1

t

CSW

UPIO_ TIMING CHARACTERISTICS

DOUT Tri-State Time when

Exiting DOUTDC0, DOUTDC1,

and UPIO Modes

C = 20pF, from end of write cycle to UPIO_

L

in high impedance

t

200

ns

DOZ

DOUTRB Tri-State Time from CS

Rise

C = 20pF, from rising edge of CS to UPIO_

in high impedance

L

t

40

ns

DRBZ

DOUTRB Tri-State Enable Time

from 8th SCLK Rise

C = 20pF, from 8th rising edge of SCLK to

L

UPIO_ driven out of tri-state

t

ZEN

LDAC Pulse-Width Low

t

Figure 5

40

200

40

ns

LDL

LDS

LDAC Effective Delay

Figure 6

CLR, MID, SET Pulse-Width Low

GPO Output Settling Time

t

Figure 5

CMS

t

Figure 6

200

GP

GPO Output High-Impedance

Time

t

ns

GPZ

_______________________________________________________________________________________

7

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V, 5V Logic) (Figure 2)

(DV

= 2.7V to 5.25V, GND = 0, T = T

MIN

to T , unless otherwise noted.)

MAX

DD

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

MHz

ns

SCLK Frequency

f

2.7V < DV

(Note 7)

< 5.25V

DD

20

SCLK

SCLK Pulse-Width High

t

20

10

5

CH

SCLK Pulse-Width Low

t

ns

CL

CS Fall to SCLK Fall Setup Time

DSP Fall to SCLK Fall Setup Time

SCLK Fall to CS Rise Hold Time

SCLK Fall to CS Fall Delay

SCLK Fall to DSP Fall Delay

DIN to SCLK Fall Setup Time

DIN to SCLK Fall Hold Time

t

ns

CSS

DSS

CSH

ns

t

ns

t

10

12

5

ns

CS0

DS0

ns

t

ns

DS

t

ns

DH

SCLK Rise to DOUT_ Valid

Propagation Delay

C = 20pF, UPIO_ = DOUTDC1 or DOUTRB

L

mode

t

30

ns

DO1

SCLK Fall to DOUT_ Valid

Propagation Delay

t

C = 20pF, UPIO_ = DOUTDC0 mode

L

DO2

CS Rise to SCLK Fall Hold Time

CS Pulse-Width High

t

MICROWIRE and SPI modes 0 and 3

10

45

20

ns

CS1

t

CSW

DSW

DSP Pulse-Width High

DSP Pulse-Width Low

t

DSPWL

(Note 8)

UPIO_ TIMING CHARACTERISTICS

DOUT Tri-State Time when

Exiting DOUTDC0, DOUTDC1,

and UPIO Modes

C = 20pF, from end of write cycle to UPIO_

L

in high impedance

t

100

ns

DOZ

DOUTRB Tri-State Time from CS

Rise

C = 20pF, from rising edge of CS to UPIO_

in high impedance

L

t

20

ns

DRBZ

DOUTRB Tri-State Enable Time

from 8th SCLK Fall

C = 20pF, from 8th falling edge of SCLK to

L

UPIO_ driven out of tri-state

t

ZEN

LDAC Pulse-Width Low

t

Figure 5

20

100

20

ns

LDL

LDS

LDAC Effective Delay

Figure 6

CLR, MID, SET Pulse-Width Low

GPO Output Settling Time

t

Figure 5

CMS

t

Figure 6

100

GP

GPO Output High-Impedance

Time

t

ns

GPZ

8

_______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2)

(DV

= 1.8V to 5.25V, GND = 0, T = T

MIN

to T , unless otherwise noted.)

MAX

DD

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

MHz

ns

SCLK Frequency

f

1.8V < DV

(Note 7)

< 5.25V

DD

10

SCLK

SCLK Pulse-Width High

t

40

20

0

CH

SCLK Pulse-Width Low

t

ns

CL

CS Fall to SCLK Fall Setup Time

DSP Fall to SCLK Fall Setup Time

SCLK Fall to CS Rise Hold Time

SCLK Fall to CS Fall Delay

SCLK Fall to DSP Fall Delay

DIN to SCLK Fall Setup Time

DIN to SCLK Fall Hold Time

t

ns

CSS

DSS

CSH

ns

t

ns

t

10

15

20

5

ns

CS0

DS0

ns

t

ns

DS

t

ns

DH

SCLK Rise to DOUT_ Valid

Propagation Delay

C = 20pF, UPIO_ = DOUTDC1 or DOUTRB

L

mode

t

60

ns

DO1

SCLK Fall to DOUT_ Valid

Propagation Delay

t

C = 20pF, UPIO_ = DOUTDC0 mode

L

DO2

CS Rise to SCLK Fall Hold Time

CS Pulse-Width High

t

MICROWIRE and SPI modes 0 and 3

20

90

40

ns

CS1

t

CSW

DSW

DSP Pulse-Width High

DSP Pulse-Width Low

t

DSPWL

(Note 8)

UPIO_ TIMING CHARACTERISTICS

DOUT Tri-State Time when

Exiting DOUTDC0, DOUTDC1,

and UPIO Modes

C = 20pF, from end of write cycle to UPIO_

L

in high impedance

t

200

ns

DOZ

DOUTRB Tri-State Time from CS

Rise

C = 20pF, from rising edge of CS to UPIO_

in high impedance

L

t

40

ns

DRBZ

DOUTRB Tri-State Enable Time

from 8th SCLK Fall

C = 20pF, from 8th falling edge of SCLK to

L

UPIO_ driven out of tri-state

t

ZEN

LDAC Pulse-Width Low

t

Figure 5

40

200

40

ns

LDL

LDS

LDAC Effective Delay

Figure 6

CLR, MID, SET Pulse-Width Low

GPO Output Settling Time

t

Figure 5

CMS

t

Figure 6

200

GP

GPO Output High-Impedance

Time

t

ns

GPZ

Note 7: In some daisy-chain modes, data is required to be clocked in on one clock edge and the shifted data clocked out on the fol-

lowing edge. In the case of a 1/2 clock-period delay, it is necessary to increase the minimum high/low clock times to 25ns

(2.7V) or 50ns (1.8V).

Note 8: The falling edge of DSP starts a DSP-type bus cycle, provided that CS is also active low to select the device. DSP active low

and CS active low must overlap by a minimum of 10ns (2.7V) or 20ns (1.8V). CS can be permanently low in this mode of

operation.

_______________________________________________________________________________________

9

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

Typical Operating Characteristics

(AV = DV = 5V, V

= 4.096V, R = 10kΩ, C = 100pF, speed mode = FAST, PU = floating, T = +25°C, unless otherwise noted.)

L L A

DD

REF

INTEGRAL NONLINEARITY

vs. DIGITAL INPUT CODE (12-BIT)

INTEGRAL NONLINEARITY

vs. DIGITAL INPUT CODE (10-BIT)

INTEGRAL NONLINEARITY

vs. DIGITAL INPUT CODE (8-BIT)

4

3

1.00

0.50

0.25

0

0.75

0.50

0.25

0

2

1

0

-1

-2

-3

-0.25

-0.50

-0.75

-0.25

B-GRADE

-4

-1.00

-0.50

0

1024

2048

3072

4095

0

256

512

768

1023

0

64

128

192

255

DIGITAL INPUT CODE

DIFFERENTIAL NONLINEARITY

vs. DIGITAL INPUT CODE (8-BIT)

DIFFERENTIAL NONLINEARITY

vs. DIGITAL INPUT CODE (12-BIT)

DIFFERENTIAL NONLINEARITY

vs. DIGITAL INPUT CODE (10-BIT)

0.050

0.025

0

0.50

0.2

0.1

0

0.25

0

-0.025

-0.25

-0.1

B-GRADE

3072 4095

DIGITAL INPUT CODE

-0.050

-0.50

-0.2

0

64

128

192

255

0

1024

2048

0

256

512

768

1023

DIGITAL INPUT CODE

INTEGRAL NONLINEARITY

vs. REFERENCE VOLTAGE (12-BIT)

DIFFERENTIAL NONLINEARITY

vs. REFERENCE VOLTAGE (12-BIT)

INTEGRAL NONLINEARITY

vs. TEMPERATURE (12-BIT)

4

3

0.5

0.4

4

3

2

0.3

2

0.2

1

0

0.1

0

-0.1

-0.2

-0.3

-0.4

-0.5

-1

-2

-3

-4

-1

-2

-3

-4

B-GRADE

MIDSCALE

B-GRADE

MIDSCALE

1.0 1.5 20 2.5 3.0 3.5 4.0 4.5 5.0

(V)

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

(V)

-40 -15

10

35

60

85

V

REF

TEMPERATURE (°C)

REF

10 ______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

Typical Operating Characteristics (continued)

(AV = DV = 5V, V

= 4.096V, R = 10kΩ, C = 100pF, speed mode = FAST, PU = floating, T = +25°C, unless otherwise noted.)

L L A

DD

REF

DIFFERENTIAL NONLINEARITY

vs. TEMPERATURE (12-BIT)

SUPPLY CURRENT

vs. DIGITAL INPUT CODE (FORCE-SENSE)

SUPPLY CURRENT

vs. DIGITAL INPUT CODE (UNITY GAIN)

5

4

3

2

1

3

2

0.2

0.1

0

-0.1

-0.2

1

0

B-GRADE

MIDSCALE

12-BIT

NO LOAD

12-BIT

NO LOAD

0

1024

2048

3072

4095

0

1024

2048

3072

4095

-40 -15

10

35

60

85

DIGITAL INPUT CODE

TEMPERATURE (°C)

SUPPLY CURRENT

vs. SUPPLY VOLTAGE (FORCE-SENSE)

SUPPLY CURRENT

vs. SUPPLY VOLTAGE (UNITY GAIN)

SHUTDOWN SUPPLY CURRENT

vs. SUPPLY VOLTAGE

4

3

2

1

0

3.0

2.5

2.0

1.5

1.0

0.5

0

60

FAST MODE

50

40

30

20

10

0

FORCE SENSE

UNITY GAIN

SLOW MODE

AV = DV

NO LOAD

AV = DV

NO LOAD

DD

NO LOAD

2.70

3.40

4.10

4.80

5.25

2.70

3.40

4.10

4.80

5.25

3.40

4.10

4.80

5.25

SUPPLY VOLTAGE (V)

OUTPUT VOLTAGE

vs. OUTPUT SOURCE/SINK CURRENT

OFFSET ERROR vs. TEMPERATURE

GAIN ERROR vs. TEMPERATURE

2.5

2.0

1.5

1.0

0.5

0

7

6

0

-2

CODE = 40

UNITY GAIN: 1 LSB = 1mV

FORCE SENSE: 1 LSB = 0.5mV

MIDSCALE

5

4

-4

FORCE SENSE

UNITY GAIN

3

2

1

-6

UNITY GAIN

-8

UNITY GAIN

UNITY GAIN: 1 LSB = 1mV

FORCE SENSE: 1 LSB = 0.5mV

V

= 4.096V

REF

0

-10

-15

-10

-5

0

5

10

15

-40

-15

10

35

60

85

-40

-15

10

35

60

85

I

(mA)

TEMPERATURE (°C)

OUT

______________________________________________________________________________________ 11

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

Typical Operating Characteristics (continued)

(AV = DV = 5V, V

= 4.096V, R = 10kΩ, C = 100pF, speed mode = FAST, PU = floating, T = +25°C, unless otherwise noted.)

DD

REF

L

A

MAJOR-CARRY TRANSITION GLITCH

SETTLING TIME POSITIVE

SETTLING TIME NEGATIVE

MAX5590-95 toc21

MAX5590-95 toc19

MAX5590-95 toc20

FULL-SCALE

TRANSITION

CS

5V/div

CS

5V/div

OUT_

2mV/div

OUT_

2V/div

FULL-SCALE

TRANSITION

250ns/div

400ns/div

DAC-TO-DAC CROSSTALK

REFERENCE INPUT BANDWIDTH

REFERENCE FEEDTHROUGH AT 1kHz

MAX5590-95 toc24

5

0

-22

-30

-40

-50

-60

-5

OUTA–OUTG

2V/div

-70

-80

-10

-15

-20

-25

-90

-100

-110

-120

-130

OUTH

1mV/div

V

= 0.1V AT 4.096V

P-P DC

REF

UNITY GAIN

-142

200µs/div

1

10

100

FREQUENCY (kHz)

1000

10,000

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

FREQUENCY (kHz)

DIGITAL FEEDTHROUGH

POWER-UP GLITCH

EXITING SHUTDOWN TO MIDSCALE

MAX5590-95 toc25

MAX5590-95 toc26

MAX5590-95 toc27

SCLK

AV

DD

2V/div

CS

2V/div

OUT_

2V/div

OUT_

(AC-COUPLED)

2mV/div

OUT_

2V/div

PU = DV

DD

1µs/div

400µs/div

10µs/div

12 ______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

Pin Description

MAX5590

MAX5592

MAX5594

MAX5591

MAX5593

MAX5595

NAME

FUNCTION

1

2

AV

Analog Supply

DD

2

AGND Analog Ground

3

OUTA

N.C.

DACA Output

4, 8, 17, 21

—

6

No Connection. Not internally connected.

DACB Output

5

6

OUTB

OUTC

OUTD

CS

7

DACC Output

7

10

11

12

13

DACD Output

9

Active-Low Chip-Select Input

Serial Clock Input

10

11

SCLK

DIN

Serial Data Input

Clock Enable. Connect DSP to DV

at power-up to transfer data on the rising edge

DD

12

14

DSP

of SCLK. Connect DSP to GND to transfer data on the falling edge of SCLK.

Connect DSP to DGND at power-up to transfer data on the falling edge of SCLK.

13

14

15

16

18

19

20

22

15

16

17

18

19

22

23

26

DV

Digital Supply

DD

DGND Digital Ground

UPIO1 User-Programmable Input/Output 1

UPIO2 User-Programmable Input/Output 2

OUTE

OUTF

DACE Output

DACF Output

OUTG DACG Output

OUTH

PU

DACH Output

Power-Up State Select Input. Connect PU to DV to set OUTA–OUTH to full scale

DD

upon power-up. Connect PU to DGND to set OUTA–OUTH to zero upon power-up.

Leave PU floating at power-up to set OUTA–OUTH to midscale.

23

27

24

—

28

4

REF

FBA

FBB

FBC

FBD

FBE

FBF

FBG

FBH

Reference Input

Feedback for DACA

Feedback for DACB

Feedback for DACC

Feedback for DACD

Feedback for DACE

Feedback for DACF

Feedback for DACG

Feedback for DACH

5

8

9

20

21

24

25

______________________________________________________________________________________ 13

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

Functional Diagrams

AV

DV

AGND

DGND

DD

CS

SCLK

DIN

SERIAL

INTERFACE

CONTROL

MAX5590

MAX5592

MAX5594

DSP

16-BIT SHIFT

REGISTER

DOUT

REGISTER

MUX

UPIO1

UPIO2

UPIO1 AND

UPIO2

LOGIC

POWER-DOWN

LOGIC AND

REGISTER

DECODE

CONTROL

OUTA

PU

INPUT

REGISTER

A

DAC

REGISTER

A

DACA

OUTH

INPUT

REGISTER

H

DAC

REGISTER

H

DACH

REF

14 ______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

Functional Diagrams (continued)

AV

DV

AGND

DGND

DD

CS

SCLK

DIN

SERIAL

INTERFACE

CONTROL

MAX5591

MAX5593

MAX5595

DSP

16-BIT SHIFT

REGISTER

DOUT

REGISTER

MUX

UPIO1

UPIO2

UPIO1 AND

UPIO2

LOGIC

POWER-DOWN

LOGIC AND

REGISTER

FBA

DECODE

CONTROL

OUTA

PU

INPUT

REGISTER

A

DAC

REGISTER

A

DACA

FBH

OUTH

INPUT

REGISTER

H

DAC

REGISTER

H

DACH

REF

______________________________________________________________________________________ 15

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

Use the serial interface to set the shutdown output

Detailed Description

impedance of the amplifiers to 1kΩ or 100kΩ for the

MAX5590/MAX5592/MAX5594 and 1kΩ or high imped-

ance for the MAX5591/MAX5593/MAX5595. The DAC

outputs can drive a 10kΩ (typ) load and are stable with

up to 500pF (typ) of capacitive load.

The MAX5590–MAX5595 octal, 12/10/8-bit, voltage-out-

put DACs offer buffered outputs and a 3µs maximum

settling time at the 12-bit level. The DACs operate from a

single 2.7V to 5.25V analog supply and a separate 1.8V

to AV

digital supply. The MAX5590–MAX5595 include

DD

an input register and DAC register for each channel and

a 16-bit data-in/data-out shift register. The 3-wire serial

interface is compatible with SPI, QSPI, MICROWIRE, and

DSP applications. The MAX5590– MAX5595 provide two

user-programmable digital I/O ports, which are pro-

grammed through the serial interface. The externally

selectable power-up states of the DAC outputs are either

zero scale, midscale, or full scale.

Power-On Reset

At power-up, all DAC outputs power up to full scale,

midscale, or zero scale, depending on the configuration

of the PU input. Connect PU to DV

to set OUT_ to full

DD

scale upon power-up. Connect PU to digital ground

(DGND) at power-up to set OUT_ to zero scale. Leave

PU floating to set OUT_ to midscale.

Digital Interface

Reference Input

The reference input, REF, accepts both AC and DC val-

ues with a voltage range extending from analog ground

(AGND) to AV . The voltage at REF sets the full-scale

DD

output of the DACs. Determine the output voltage using

the following equations:

The MAX5590–MAX5595 use a 3-wire serial interface

that is compatible with SPI, QSPI, MICROWIRE, and DSP

protocol applications (Figures 1 and 2). Connect DSP to

DV

before power-up to clock data in on the rising

DD

edge of SCLK. Connect DSP to DGND before power-up

to clock data in on the falling edge of SCLK. After power-

up, the device enters DSP frame-sync mode on the first

rising edge of DSP. Refer to the MAX5590–MAX5595

Programmer’s Handbook for details.

Unity-gain versions:

V

OUT_

= (V

x CODE) / 2^N

REF

Force-sense versions (FB_ connected to OUT_):

= 0.5 x (V

x CODE) / 2^N

The MAX5590–MAX5595 include a 16-bit input shift

register. The data is loaded into the input shift register

through the serial interface. The 16 bits can be sent in

two serial 8-bit packets or one 16-bit word (CS must

remain low until all 16 bits are transferred). The data is

loaded MSB first. For the MAX5590/MAX5591, the 16

bits consist of 4 control bits (C3–C0) and 12 data bits

(D11–D0) (see Table 1). For the 10-bit MAX5592/

MAX5593 devices, D11–D2 are the data bits and D1

and D0 are sub-bits. For the 8-bit MAX5594/

MAX5595 devices, D11–D4 are the data bits and

D3–D0 are sub-bits. Set all sub-bits to zero for optimum

performance.

V

OUT

REF

where CODE is the numeric value of the DAC’s binary

input code and N is the bits of resolution. For the

MAX5590/MAX5591, N = 12 and CODE ranges from 0

to 4095. For the MAX5592/MAX5593, N = 10 and

CODE ranges from 0 to 1023. For the MAX5594/

MAX5595, N = 8 and CODE ranges from 0 to 255.

Output Buffers

The DACA and DACH output-buffer amplifiers of the

MAX5590–MAX5595 are unity-gain stable with Rail-to-

Rail^®output voltage swings and a typical slew rate

of 3.6V/µs (FAST mode). The MAX5590/MAX5592/

MAX5594 provide unity-gain outputs, while the

MAX5591/MAX5593/MAX5595 provide force-sense out-

puts. For the MAX5591/MAX5593/MAX5595, access to

the output amplifier’s inverting input provides flexibility

in output gain setting and signal conditioning (see the

Applications Information section).

Each DAC channel includes two registers: an input reg-

ister and the DAC register. At power-up, the DAC out-

put is set according to the state of PU. The DACs are

double-buffered, which allows any of the following for

each channel:

• Loading the input register without updating the DAC

register

The MAX5590–MAX5595 offer FAST and SLOW settling-

time modes. In the SLOW mode, the settling time is 6µs

(max), and the supply current is 3.2mA (max). In the

FAST mode, the settling time is 3µs (max), and the sup-

ply current is 8mA (max). See the Digital Interface section

for settling-time mode programming details.

• Updating the DAC register from the input register

• Updating the input and DAC registers simultaneously

Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.

16 ______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

Table 1. Serial Write Data Format

MSB

CONTROL BITS

C2 C1

16 BITS OF SERIAL DATA

DATA BITS

D6 D5

LSB

C3

C0

D11

D10

D9

D8

D7

D4

D3

D2

D1

D0

t

CH

SCLK

DIN

t

CL

t

DS

C3

C2

C1

D0

t

DH

CSH

CS0

t

CSS

CS

t

CSW

t

CS1

t

DO1

DOUTDC1*

DOUT VALID

t

DO2

DOUTDC0

OR

DOUTRB*

DOUT VALID

*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT).

SEE THE DATA OUTPUT (DOUTRB, DOUTDC0, DOUTDC1) SECTION FOR DETAILS.

Figure 1. Serial-Interface Timing Diagram (DSP Mode Disabled)

t

CL

SCLK

t

CH

t

DS

DIN

C3

C2

C1

D0

t

CS0

t

DH

t

CSH

t

CCS

CS

t

CSW

t

CS1

DSS

t

DS0

DSP

t

D02

t

DSPWL

DSW

DOUTDC0*

DOUT VALID

t

D01

DOUTDC1

OR

DOUT VALID

DOUTRB*

*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT).

SEE THE DATA OUTPUT (DOUTRB, DOUTDC0, DOUTDC1) SECTION FOR DETAILS.

Figure 2. Serial-Interface Timing Diagram (DSP Mode Enabled)

______________________________________________________________________________________ 17

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

Serial-Interface Programming Commands

Tables 2a, 2b, and 2c provide all of the serial-interface

programming commands for the MAX5590–MAX5595.

Table 2a shows the basic DAC programming com-

mands, Table 2b gives the advanced-feature program-

ming commands, and Table 2c provides the 24-bit

read commands. Figures 3 and 4 provide the serial-

interface diagrams for read and write operations.

Loading Input and DAC Registers

The MAX5590–MAX5595 contain a 16-bit shift register

that is followed by a 12-bit input register and a 12-bit

DAC register for each channel (see the Functional

Diagrams). Tables 3, 4, and 5 highlight a few of the

commands that handle the loading of the input and

DAC registers. See Table 2a for all DAC programming

commands.

V

DD

MICROWIRE

SPI OR QSPI

MAX5590–

MAX5595

MAX5590–

MAX5595

V

DV

DD

V

DV

DD

DSP

SCLK

DIN

CS

DSP

SCLK

DIN

CS

SK

SO

SCK

MOSI

I/O

SS OR I/O

MICROWIRE OR SPI (CPOL = 0, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:

COMMAND TAKES EFFECT HERE

ONLY IF SCLK COUNT = N 16

CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION

✕

CS

SCLK

DIN

C3

C2

C1

C0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SPI (CPOL = 1, CPHA = 1) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:

COMMAND TAKES EFFECT HERE

ONLY IF SCLK COUNT = N 16

✕

CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION

CS

SCLK

DIN

C3

C2

C1

C0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Figure 3. MICROWIRE and SPI Single DAC Writes (CPOL = 0, CPHA = 0 or CPOL = 1, CPHA = 1)

DSP

SPI OR QSPI

MAX5590–

MAX5595

MAX5590–

MAX5595

V

DGND

V

DGND

SS

DSP

SCLK

DSP

SCLK

TCLK, SCLK, OR CLKX

DT OR DX

SCK

DIN

CS

MOSI

DIN

CS

TFS OR FSX

SS OR I/O

DSP OR SPI (CPOL = 0, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:

COMMAND TAKES EFFECT HERE

ONLY IF SCLK COUNT = N 16

CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION

✕

CS

SCLK

DIN

C3

C2

C1

C0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

DSP OR SPI (CPOL = 1, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:

COMMAND TAKES EFFECT HERE

ONLY IF SCLK COUNT = N 16

✕

CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION

CS

SCLK

DIN

C3

C2

C1

C0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Figure 4. DSP and SPI Single DAC Writes (CPOL = 0, CPHA = 1 or CPOL = 1, CPHA = 0)

18 ______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

______________________________________________________________________________________ 19

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

20 ______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

______________________________________________________________________________________ 21

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

I D A _ 0

I D A _ 1

I D A _ 2

I D A _ 3

I D A _ 4

I D B _ 0

I D B _ 1

I D B _ 2

I D B _ 3

I D B _ 4

I D C _ 0

I D C _ 1

I D C _ 2

I D C _ 3

I D C _ 4

I D D _ 0

I D D _ 1

I D D _ 2

I D D _ 3

I D D _ 4

I D E _ 0

I D E _ 1

I D E _ 2

I D E _ 3

I D E _ 4

I D F _ 0

I D F _ 1

I D F _ 2

I D F _ 3

I D F _ 4

I D G _ 0

I D G _ 1

I D H

2 _ G I D

I D G _ 3

I D G _ 4

I D G _ 5

I D G _ 6

I D G _ 7

I D G _ 8

I D G _ 9

I D G _ 1 0

I D G _ 1 1

I D A _ 5

I D A _ 6

I D A _ 7

I D A _ 8

I D A _ 9

I D A _ 1 0

I D A _ 1 1

I D B _ 5

I D B _ 6

I D B _ 7

I D B _ 8

I D B _ 9

I D B _ 1 0

I D B _ 1 1

I D C _ 5

I D C _ 6

I D C _ 7

I D C _ 8

I D C _ 9

I D C _ 1 0

I D C _ 1 1

I D D _ 5

I D D _ 6

I D D _ 7

I D D _ 8

I D D _ 9

I D D _ 1 0

I D D _ 1 1

I D E _ 5

I D E _ 6

I D E _ 7

I D E _ 8

I D E _ 9

I D E _ 1 0

I D E _ 1 1

I D F _ 5

I D F _ 6

I D F _ 7

I D F _ 8

I D F _ 9

I D F _ 1 0

I D F _ 1 1

I D H

D D A _ 0

D D A _ 1

D D A _ 2

D D A _ 3

D D A _ 4

D D A _ 5

D D A _ 6

D D A _ 7

D D A _ 8

D D A _ 9

D D B _ 0

D D B _ 1

D D B _ 2

D D B _ 3

D D B _ 4

D D B _ 5

D D B _ 6

D D B _ 7

D D B _ 8

D D B _ 9

D D C _ 0

D D C _ 1

D D C _ 2

D D C _ 3

D D C _ 4

D D C _ 5

D D C _ 6

D D C _ 7

D D C _ 8

D D C _ 9

D D D _ 0

D D D _ 1

D D D _ 2

D D D _ 3

D D D _ 4

D D D _ 5

D D D _ 6

D D D _ 7

D D D _ 8

D D D _ 9

D D E _ 0

D D E _ 1

D D E _ 2

D D E _ 3

D D E _ 4

D D E _ 5

D D E _ 6

D D E _ 7

D D E _ 8

D D E _ 9

D D F _ 0

D D F _ 1

D D F _ 2

D D F _ 3

D D F _ 4

D D F _ 5

D D F _ 6

D D F _ 7

D D F _ 8

D D F _ 9

D D G _ 0

D D G _ 1

D D G _ 2

D D G _ 3

D D G _ 4

D D G _ 5

D D G _ 6

D D G _ 7

D D G _ 8

D D G _ 9

D D

D D A _ 1 0

D D A _ 1 1

D D B _ 1 0

D D B _ 1 1

D D C _ 1 0

D D C _ 1 1

D D D _ 1 0

D D D _ 1 1

D D E _ 1 0

D D E _ 1 1

D D F _ 1 0 0 1 _

D D F _ 1 1

D D G

D D

D D G _ 1 1

SC

22 ______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

DAC Programming Examples:

Advanced-Feature

To load input register A from the shift register, leaving

DAC register A unchanged (DAC output unchanged),

use the command in Table 3.

Programming Commands

Select Bits (M_)

The select bits allow synchronous updating of any com-

bination of channels. The select bits command the

loading of the DAC register from the input register of

each channel. Set the select bit M_ = 1 to load the DAC

register “_” with data from the input register “_”, where

“_” is replaced with A, B, or C and so on through H,

depending on the selected channel. Setting the select

bit M_ = 0 results in no action for that channel (Table 6).

The MAX5590–MAX5595 can load all of the input regis-

ters (A–H) simultaneously from the shift register, leaving

the DAC registers unchanged (DAC output unchanged),

by using the command in Table 4.

To load all of the input registers (A–H) and all of the DAC

registers (A–H) simultaneously, use the command in

Table 5.

For the 10-bit and 8-bit versions, set sub-bits = 0 for

best performance.

Select Bits Programming Example:

To load DAC register B from input register B while

keeping other channels (A, C–H) unchanged, set MB =

1 and M_ = 0 (Table 7).

Table 3. Load Input Register A from Shift Register

DATA

CONTROL BITS

DATA BITS

D6 D5

DIN

0

D11

D10

D9

D8

D7

D4

D3/0 D2/0 D1/0 D0/0

Table 4. Load Input Registers (A–H) from Shift Register

DATA

CONTROL BITS

DATA BITS

D6 D5

DIN

1

0

1

D11

D10

D9

D8

D7

D4

D3/0 D2/0 D1/0 D0/0

Table 5. Load Input Registers (A–H) and DAC Registers (A–H) from Shift Register

DATA

CONTROL BITS

DATA BITS

DIN

1

0

1

0

D11

D10

D9

D8

D7

D6

D5

D4

D3/0 D2/0 D1/0 D0/0

Table 6. Select Bits (M_)

DATA

CONTROL BITS

DATA BITS

ME MD

DIN

1

0

X

MH

MG

MF

MC

MB

MA

X = Don’t care.

Table 7. Select Bits Programming Example

DATA

CONTROL BITS

DATA BITS

DIN

1

0

X

0

1

0

X = Don’t care.

______________________________________________________________________________________ 23

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

Shutdown-Mode Bits (PD_0, PD_1)

Use the shutdown-mode bits and control bits to

shut down each DAC independently. The shutdown-

mode bits determine the output state of the selected

channels. The shutdown-control bits put the selected

channels into shutdown-mode. To select the shutdown

mode for DACA–DACH, set PD_0 and PD_1 according

to Table 8 (where “_” is replaced with one of the select-

ed channels (A–H)). The three possible states for unity-

gain versions are 1) normal operation, 2) shutdown with

1kΩ output impedance, and 3) shutdown with 100kΩ

output impedance. The three possible states for force-

sense versions are 1) normal operation, 2) shutdown

with 1kΩ output impedance, and 3) shutdown with the

output in a high-impedance state. Tables 9 and 10

show the commands for writing to the shutdown-mode

bits. Table 11 shows the commands for writing the

shutdown-control bits. This command is required to put

the selected channels into shutdown.

Always write the shutdown-mode-bits command first

and then write the shutdown-control-bits command to

properly shut down the selected channels. The shut-

down-control-bits command can be written at any time

after the shutdown-mode-bits command. It does not

have to immediately follow the shutdown-mode-bits

command.

Table 8. Shutdown-Mode Bits

PD_1

PD_0

DESCRIPTIONS

Shutdown with 1kΩ termination to ground

on DAC_ output.

0

Settling-Time-Mode Bits (SPD_)

The settling-time-mode bits select the settling time (FAST

mode or SLOW mode) of the MAX5590–MAX5595.

Set SPD_ = 1 to select FAST mode or set SPD_ = 0 to

select SLOW mode, where “_” is replaced by A, B, or C

and so on through H, depending on the selected chan-

nel (Table 12). FAST mode provides a 3µs maximum set-

tling time, and SLOW mode provides a 6µs maximum

settling time.

Shutdown with 100kΩ termination to

ground on DAC_ output for unity-gain

versions. Shutdown with high-impedance

output for force-sense versions.

0

1

0

1

Ignored.

DAC_ is powered up in its normal

operating mode.

Table 9. Shutdown-Mode Write Command (DACA–DACD)

DATA

CONTROL BITS

DATA BITS

DIN

1

0

1

0

PDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0

X = Don’t care.

Table 10. Shutdown-Mode Write Command (DACE–DACH)

DATA

CONTROL BITS

DATA BITS

DIN

1

0

1

0

1

0

PDH1 PDH0 PDG1 PDG0 PDF1 PDF0 PDE1 PDE0

X = Don’t care.

Table 11. Shutdown-Control-Bits Write Command

DATA

CONTROL BITS

DATA BITS

DIN

1

0

1

0

1

0

PDCH PDCG PDCF PDCE PDCD PDCC PDCB PDCA

X = Don’t care.

Table 12. Settling-Time-Mode Write Command

DATA

CONTROL BITS

DATA BITS

DIN

1

0

1

0

SPDH SPDG SPDF SPDE SPDD SPDC SPDB SPDA

24 ______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

Settling-Time-Mode Write Example:

ing edge of SCLK. Set the DAC’s CPOL and CPHA bits

to CPOL = 0 and CPHA = 1 or CPOL = 1 and CPHA =

0 for DSP and SPI applications, requiring the clocking

of data in on the falling edge of SCLK (refer to the

Programmer’s Handbook and see Table 15 for details).

To configure DACA and DACD into FAST mode and

DACB and DACC into SLOW mode, use the command

in Table 13.

To read back the settling-time-mode bits, use the com-

mand in Table 14.

At power-up, if DSP = DV , the default value of CPHA

DD

is zero and if DSP = DGND, the default value of CPHA

is one. The default value of CPOL is zero at power-up.

CPOL and CPHA Control Bits

The CPOL and CPHA control bits of the

MAX5590–MAX5595 are defined the same as the CPOL

and CPHA bits in the SPI standard. Set the DAC’s

CPOL and CPHA bits to CPOL = 0 and CPHA = 0 or

CPOL = 1 and CPHA = 1 for MICROWIRE and SPI

applications requiring the clocking of data in on the ris-

To write to the CPOL and CPHA bits, use the command

in Table 16.

To read back the device’s CPOL and CPHA bits, use

the command in Table 17.

Table 13. Settling-Time-Mode Write Example

DATA

CONTROL BITS

DATA BITS

DIN

1

0

1

0

X

1

0

1

X = Don’t care.

Table 14. Settling-Time-Mode Read Command

DATA

DIN

CONTROL BITS

DATA BITS

1

X

0

X

1

X

1

X

1

X

0

X

0

X

1

X

DOUTRB

SPDH SPDG SPDF SPDE SPDD SPDC SPDB SPDA

X = Don’t care.

Table 15. CPOL and CPHA Bits

CPOL

CPHA

DESCRIPTION

Default values at power-up when DSP is connected to DV . Data is clocked in on the rising edge

of SCLK.

DD

0

Default values at power-up when DSP is connected to DGND. Data is clocked in on the falling edge

of SCLK.

0

1

0

1

Data is clocked in on the falling edge of SCLK.

Data is clocked in on the rising edge of SCLK.

Table 16. CPOL and CPHA Write Command

DATA

CONTROL BITS

DATA BITS

DIN

1

0

X

CPOL CPHA

X = Don’t care.

Table 17. CPOL and CPHA Read Command

DATA

DIN

CONTROL BITS

DATA BITS

1

X

1

X

0

X

0

X

0

X

0

X

0

X

1

X

DOUTRB

X

CPOL CPHA

X = Don’t care.

______________________________________________________________________________________ 25

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

UPIO Bits (UPSL1, UPSL2, UP0–UP3)

The MAX5590–MAX5595 provide two user-programma-

ble input/output (UPIO) ports: UPIO1 and UPIO2. These

ports have 15 possible configurations, as shown in

Table 22. UPIO1 and UPIO2 can be programmed inde-

pendently or simultaneously by writing to the UPSL1,

UPSL2, and UP0–UP3 bits (Table 18).

UPIO Programming Example:

To set only UPIO1 as LDAC and leave UPIO2

unchanged, use the command in Table 20.

The UPIO selection and configuration bits can be read

back from the MAX5590–MAX5595 when UPIO1 or

UPIO2 is configured as a DOUTRB output. Table 21

shows the read-back data format for the UPIO bits.

Writing the command in Table 21 initiates a read opera-

tion of the UPIO bits. The data is clocked out starting on

the ninth clock cycle of the sequence. Bits UP3-2

through UP0-2 provide the UP3–UP0 configuration bits

for UPIO2 (Table 22), and bits UP3-1 through UP0-1

provide the UP3–UP0 configuration bits for UPIO1.

Table 19 shows how UPIO1 and UPIO2 are selected for

configuration. The UP0–UP3 bits select the desired

functions for UPIO1 and/or UPIO2 (Table 22).

Table 18. UPIO Write Command

DATA

CONTROL BITS

DATA BITS

DIN

1

0

1

0

1

0

UPSL2 UPSL1 UP3

UP2

UP1

UP0

X

X = Don’t care.

Table 19. UPIO Selection Bits (UPSL1 and UPSL2)

UPSL2

UPSL1

UPIO PORT SELECTED

None selected

0

1

0

1

0

1

UPIO1 selected

UPIO2 selected

Both UPIO1 and UPIO2 selected

Table 20. UPIO Programming Example

DATA

CONTROL BITS

DATA BITS

DIN

1

0

1

0

1

0

1

0

X

X = Don’t care.

Table 21. UPIO Read Command

DATA

DIN

CONTROL BITS

DATA BITS

1

X

0

X

1

X

1

X

0

X

1

X

1

X

DOUTRB

X

UP3-2 UP2-2 UP1-2 UP0-2 UP3-1 UP2-1 UP1-1 UP0-1

X = Don’t care.

26 ______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

UPIO Configuration

Table 22 lists the possible configurations for UPIO1 and

UPIO2. UPIO1 and UPIO2 use the selected function

when configured by the UP3–UP0 configuration bits.

Drive LDAC low to asynchronously load the DAC regis-

ters from their corresponding input registers (DACs that

are in shutdown remain shut down). The LDAC input

does not require any activity on CS, SCLK, or DIN to

take effect. If LDAC is brought low coincident with a ris-

ing edge of CS (which executes a serial command

modifying the value of either DAC input register), then

LDAC must remain asserted for at least 120ns following

the CS rising edge. This requirement applies only for

serial commands that modify the value of the DAC input

registers. See Figures 5 and 6 for timing details.

LDAC

LDAC controls the loading of the DAC registers. When

LDAC is high, the DAC registers are latched, and any

change in the input registers does not affect the con-

tents of the DAC registers or the DAC outputs. When

LDAC is low, the DAC registers are transparent, and the

values stored in the input registers are fed directly to the

DAC registers, and the DAC outputs are updated.

Table 22. UPIO Configuration Register Bits (UP3–UP0)

UPIO CONFIGURATION BITS

FUNCTION

DESCRIPTION

UP3

UP2

UP1

UP0

Active-Low Load DAC Input. Drive low to asynchronously load all DAC registers

with data from input registers.

0

LDAC

0

1

0

1

0

1

0

1

0

1

SET

MID

CLR

PDL

Active-Low Input. Drive low to set all input and DAC registers to full scale.

Active-Low Input. Drive low to set all input and DAC registers to midscale.

Active-Low Input. Drive low to set all input and DAC registers to zero scale.

Active-Low Power-Down Lockout Input. Drive low to disable software shutdown.

Reserved This mode is reserved. Do not use.

Active-Low 1kΩ Shutdown Input. Overrides PD_1 and PD_0 settings. For the

MAX5590/MAX5592/MAX5594, drive SHDN1K low to pull OUTA–OUTH to AGND

with 1kΩ. For the MAX5591/MAX5593/MAX5595, drive SHDN1K low to leave

OUTA–OUTH high impedance.

0

1

0

1

SHDN1K

Active-Low 100kΩ Shutdown Input. Overrides PD_1 and PD_0 settings. For the

MAX5590/MAX5592/MAX5594, drive SHDN100K low to pull OUTA–OUTH to

AGND with 100kΩ. For the MAX5591/MAX5593/MAX5595, drive low to leave

OUTA–OUTH high impedance.

SHDN100K

1

0

1

0

1

0

1

0

1

0

1

DOUTRB

Data Read-Back Output

Mode 0 Daisy-Chain Data Output. Data is clocked out on the falling edge of

DOUTDC0

DOUTDC1 Mode 1 Daisy-Chain Data Output. Data is clocked out on the rising edge of SCLK.

GPI

General-Purpose Logic Input

GPOL

GPOH

General-Purpose Logic-Low Output

General-Purpose Logic-High Output

Toggle Input. Toggles DAC outputs between data in input registers and data in

DAC registers. Drive low to set all DAC outputs to values stored in input registers.

Drive high to set all DAC outputs to values stored in DAC registers.

1

0

1

TOGG

Fast/Slow Settling-Time-Mode Input. Drive low to select FAST (3µs) mode or drive

high to select SLOW (6µs) settling mode. Overrides the SPDA–SPDH settings.

FAST

______________________________________________________________________________________ 27

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

t

LDL

LDAC

TOGG

END OF

CYCLE*

t

GP

PDL

GPO_

LDAC

t

CMS

t

LDS

CLR,

MID, OR

SET

t

S

0.5 LSB

V

OUT_

* END-OF-CYCLE REPRESENTS THE RISING EDGE OF CS OR THE 16TH

ACTIVE CLOCK EDGE, DEPENDING ON THE MODE OF OPERATION.

PDL AFFECTS DAC OUPTUTS (V

) ONLY IF DACS WERE PREVIOUSLY SHUT DOWN.

OUT_

Figure 6. GPO_ and LDAC Signal Timing

Figure 5. Asynchronous Signal Timing

SET, MID, CLR

SHDN1K low to select shutdown mode with OUTA–

OUTH internally terminated with 1kΩ to ground, or drive

SHDN100K low to select shutdown with an internal

100kΩ termination. For the MAX5591/MAX5593/

MAX5595, drive SHDN1K low for shutdown with 1kΩ

output termination, or drive SHDN100K low for shut-

down with high-impedance outputs.

The SET, MID, and CLR signals force the DAC outputs

to full scale, midscale, or zero scale (Figure 5). These

signals cannot be active at the same time.

The active-low SET input forces the DAC outputs to full

scale when SET is low. When SET is high, the DAC out-

puts follow the data in the DAC registers.

For proper shutdown, first select a shutdown mode

(Table 8), then use the shutdown-control bits as listed

in Table 2b.

The active-low MID input forces the DAC outputs to

midscale when MID is low. When MID is high, the DAC

outputs follow the data in the DAC registers.

Data Output (DOUTRB, DOUTDC0, DOUTDC1)

UPIO1 and UPIO2 can be configured as serial data out-

puts, DOUTRB (data out for read back), DOUTDC0

(data out for daisy-chaining, mode 0), and DOUTDC1

(data out for daisy-chaining, mode 1). The differences

between DOUTRB and DOUTDC0 (or DOUTDC1) are

as follows:

The active-low CLR input forces the DAC outputs to

zero scale when CLR is low. When CLR is high, the

DAC outputs follow the data in the DAC registers.

If CLR, MID, or SET signals go low during a write com-

mand, reload the data to ensure accurate results.

Power-Down Lockout (PDL)

The PDL active-low, software-shutdown lockout input

overrides (not overwrites) the PD_0 and PD_1 shutdown-

mode bits. PDL cannot be active at the same time as

SHDN1K or SHDN100K (see the Shutdown Mode

(SHDN1K, SHDN100K) section).

•

The source of read-back data on DOUTRB is the

DOUT register. Daisy-chain DOUTDC_ data comes

directly from the shift register.

•

Read-back data on DOUTRB is only present after a

DAC read command. Daisy-chain data is present on

DOUTDC_ for any DAC write after the first 16 bits

are written.

If the PD_0 and PD_1 bits command the DAC to

shut down prior to PDL going low, the DAC returns to

shutdown mode immediately after PDL goes high,

unless the PD_0 and PD_1 bits were modified through

the serial interface in the meantime.

•

The DOUTRB idle state (CS = high) for read back is

high impedance. Daisy-chain DOUTDC_ idles high

when inactive to avoid floating the data input in the

next device in the daisy-chain.

Shutdown Mode (SHDN1K, SHDN100K)

The SHDN1K and SHDN100K are active-low signals

that override (not overwrite) the PD_1 and PD_0 bit set-

tings. For the MAX5590/MAX5592/MAX5594, drive

See Figures 1 and 2 for timing details.

28 ______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

GPI, GPOL, GPOH

UPIO1 and UPIO2 can each be configured as a gener-

al-purpose input (GPI), a general-purpose output low

(GPOL), or a general-purpose output high (GPOH).

GPOL outputs a constant low, and GPOH outputs a

constant high. See Figure 6.

TOGG

Use the TOGG input to toggle the DAC outputs

between the values in the input registers and DAC reg-

isters. A delay of greater than 100ns from the end of the

previous write command is required before the TOGG

signal can be correctly switched between the new

value and the previously stored value. When TOGG =

0, the output follows the information in the input regis-

ters. When TOGG = 1, the output follows the informa-

tion in the DAC register (Figure 5).

The GPI can serve to detect interrupts from µPs or micro-

controllers. The GPI has three functions:

1) Sample the signal at GPI at the time of the read

(RTP1 and RTP2).

2) Detect whether or not a falling edge has occurred

since the last read or reset (LF1 and LF2).

3) Detect whether or not a rising edge has occurred

since the last read or reset (LR1 and LR2).

FAST

The MAX5590–MAX5595 have two settling-time-mode

options: FAST (3µs max) and SLOW (6µs max). To

select the FAST mode, drive FAST low, and to select

SLOW mode, drive FAST high. This overrides (not over-

writes) the SPDA–SPDH bit settings.

RTP1, LF1, and LR1 represent the data read from

UPIO1; RTP2, LF2, and LR2 represent the data read

from UPIO2.

To issue a read command for the UPIO configured as

GPI, use the command in Table 23.

Once the command is issued, RTP1 and RTP2 provide

the real-time status (0 or 1) of the inputs at UPIO1 or

UPIO2, respectively, at the time of the read. If LF2 or

LF1 is one, then a falling edge has occurred on the

respective UPIO1 or UPIO2 input since the last read or

reset. If LR2 or LR1 is one, then a rising edge has

occurred since the last read or reset.

Table 23. GPI Read Command

DATA

DIN

CONTROL BITS

DATA BITS

1

X

0

X

1

X

1

X

1

X

0

X

1

X

DOUTRB

RTP2 LF2

LR2 RTP1 LF1

LR1

X = Don’t care.

Table 24. Unipolar Code Table (Gain = +1)

DAC CONTENTS

ANALOG OUTPUT

DAC_

REF_

MSB

1111

1000

0111

0000

LSB

1111

0001

0000

1111

0001

0000

OUT_

1111

0000

1111

0000

+V

(4095 / 4096)

(2049 / 4096)

REF

V

= V

x CODE / 4096

REF_

OUT_

CODE IS THE DAC_ INPUT

CODE (0 TO 4095 DECIMAL).

+V

(2048 / 4096) = V

/ 2

REF

+V

(2047 / 4096)

MAX5590

REF

+V

(1 / 4096)

0

REF

Figure 7. Unipolar Output Circuit

______________________________________________________________________________________ 29

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

Applications Information

Unipolar Output

Figure 7 shows the unity-gain MAX5590 in a unipolar

output configuration. Table 24 lists the unipolar out-

put codes.

10kΩ

V+

Bipolar Output

The MAX5590 outputs can be configured for bipolar

operation, as shown in Figure 8. The output voltage is

given by the following equation:

V

OUT

DAC_

REF

OUT_

V-

V

OUT_

= V

x (CODE - 2048) / 2048

REF

MAX5590

where CODE represents the numeric value of the

DAC’s binary input code (0 to 4095 decimal). Table 25

shows digital codes and the corresponding output volt-

age for the Figure 8 circuit.

Configurable Output Gain

The MAX5591/MAX5593/MAX5595 have force-sense

outputs, which provide a direct connection to the invert-

ing terminal of the output op amp, yielding the most

flexibility. The force-sense output has the advantage

that specific gains can be set externally for a given

application. The gain error for the MAX5591/MAX5593/

MAX5595 is specified in a unity-gain configuration (op-

amp output and inverting terminals connected), and

additional gain error results from external resistor

tolerances. The force-sense DACs allow many useful

circuits to be created with only a few simple external

components.

Figure 8. Bipolar Output Circuit

DAC_

REF

OUT_

FB_

R2 = 12kΩ

0.1%

25ppm

MAX5591

An example of a custom, fixed gain using the

MAX5591’s force-sense output is shown in Figure 9. In

this example, the external reference is set to 1.25V, and

the gain is set to +1.1V/V with external discrete resis-

tors to provide an approximate 0 to 1.375V DAC output

voltage range.

R1 = 10kΩ

0.1%

25ppm

V

= [(0.5 x V

x CODE) / 4096] x [1 + (R2 / R1)]

OUT

REF_

where CODE represents the numeric value of the

DAC’s binary input code (0 to 4095 decimal).

Figure 9. Configurable Output Gain

In this example, R2 = 12kΩ and R1 = 10kΩ to set the

gain = 1.1V/V.

Table 25. Bipolar Code Table (Gain = +1)

DAC CONTENTS

ANALOG OUTPUT

V

OUT

= [(0.5 x 1.25V x CODE) / 4096] x 2.2

MSB

1111

1000

0111

0000

LSB

1111

0001

0000

1111

0001

0000

1111

0000

1111

0000

+V

(2047 / 2048)

REF

+V

(1 / 2048)

0

REF

-V

(1 / 2048)

REF

(2047 / 2048)

REF

-V

(2048 / 2048) = -V

REF

30 ______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

inductance ground plane. Wire-wrapped boards and

sockets are not recommended. For optimum system

performance, use PC boards with separate analog and

digital ground planes. Connect the two ground planes

together at the low-impedance power-supply source.

Power-Supply and Layout Considerations

Bypass the analog and digital power supplies by using a

10µF capacitor in parallel with a 0.1µF capacitor to AGND

and DGND (Figure 10). Minimize lead lengths to reduce

lead inductance. Use shielding and/or ferrite beads to fur-

ther increase isolation.

Using separate power supplies for AV

and DV

DD

improves noise immunity. Connect AGND and DGND at

the low-impedance power-supply sources (Figure 11).

Digital and AC transient signals coupling to AGND can

create noise at the output. Connect AGND to the high-

est quality ground available. Use proper grounding

techniques, such as a multilayer board with a low-

AV

DV

DD

ANALOG SUPPLY

AV AGND

DIGITAL SUPPLY

DV DGND

0.1µF

10µF

DV

0.1µF

10µF

V

REF

DD

AV

DD

REF

0.1µF*

10µF*

OUTA

MAX5590–MAX5595

CS

SCLK

DIN

10µF

OUTH

FBA

0.1µF

PU

MAX5591

MAX5593

MAX5595

ONLY

DSP

UPIO1

UPIO2

AV

DD

AGND

DV

DGND

DV

DD

DGND

DIGITAL

CIRCUITRY

DD

FBH

MAX5590–MAX5595

AGND**

DGND**

*REMOVE BYPASS CAPACITORS ON REF FOR AC-REFERENCE INPUTS.

**CONNECT ANALOG AND DIGITAL GROUND PLANES AT THE

LOW-IMPEDANCE POWER-SUPPLY SOURCE.

Figure 11. Separate Analog and Digital Power Supplies

Figure 10. Bypassing Power Supplies AV , DV , and REF

DD

______________________________________________________________________________________ 31

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

Pin Configurations

TOP VIEW

AV

1

2

3

4

5

6

7

8

9

28 REF

DD

AV

1

2

3

4

5

6

7

8

9

24 REF

DD

AGND

OUTA

FBA

27 PU

AGND

OUTA

N.C.

23 PU

26 OUTH

25 FBH

24 FBG

23 OUTG

22 OUTF

21 FBF

22 OUTH

21 N.C.

20 OUTG

19 OUTF

18 OUTE

17 N.C.

16 UPIO2

15 UPIO1

14 DGND

FBB

MAX5590

MAX5592

MAX5594

MAX5591

MAX5593

MAX5595

OUTB

OUTC

OUTD

N.C.

OUTB

OUTC

FBC

FBD

20 FBE

CS

OUTD 10

CS 11

19 OUTE

18 UPIO2

17 UPIO1

16 DGND

SCLK 10

DIN 11

SCLK 12

DIN 13

DSP 14

DSP 12

13 DV

DD

15 DV

DD

TSSOP

Selector Guide

Chip Information

TRANSISTOR COUNT: 38,513

OUTPUT

BUFFER

INL

RESOLUTION

(LSBs

PROCESS: BiCMOS

PART

(BITS)

CONFIGURATION

MAX)

MAX5590AEUG*

MAX5590BEUG

MAX5591AEUI*

MAX5591BEUI

MAX5592EUG

MAX5593EUI

Unity Gain

12

10

8

1

4

Force Sense

Unity Gain

1

4

1

Force Sense

Unity Gain

1

MAX5594EUG

MAX5595EUI

0.5

Force Sense

8

*Future product. Contact factory for availability. Specifications

are preliminary.

32 ______________________________________________________________________________________

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information

go to www.maxim-ic.com/packages.)

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 33

Printed USA

is a registered trademark of Maxim Integrated Products.


型号：	MAX5590AEUG
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs 缓冲，快速建立，八通道12 /10/ 8位，电压输出DAC
文件：	总33页 (文件大小：1111K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX5590AEUG [MAXIM]

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MAX5591AEUI+

MAX5591BEUI

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