MAX522ESA+ [MAXIM]
D/A Converter, 2 Func, Serial Input Loading, 70us Settling Time, PDSO8, 0.150 INCH, SOP-8;
| 型号： | MAX522ESA+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 2 Func, Serial Input Loading, 70us Settling Time, PDSO8, 0.150 INCH, SOP-8 |
| 文件： | 总12页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0403; Rev 0; 6/95
Du a l, 8 -Bit , Vo lt a g e -Ou t p u t
S e ria l DAC in 8 -P in S O P a c k a g e
MAX52
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ Operates from a Single +2.7V to +5.5V Supply
♦ Dual Buffered Voltage Output
The MAX522 contains two 8-bit, buffered, voltage-output
digital-to-analog converters (DAC A and DAC B) in small
8-pin SO and DIP packages. DAC A’s buffer can source
and sink 5mA, and DAC B’s output can source and sink
♦ Low Power Consumption:
1mA Operating Current
<1µA Shutdown Current
500µA, both to within 0.5V of ground and V . The
DD
MAX522 operates with a single +2.7V to +5.5V supply.
The device utilizes a 3-wire serial interface, which oper-
ates at clock rates up to 5MHz and is compatible with
SPI™, QSPI™, and Microwire™ interface standards.
The serial input shift register is 16 bits long and con-
sists of eight bits of DAC input data and eight bits for
DAC selection and shutdown control. DAC registers
can be loaded independently or in parallel at the posi-
tive edge of CS.
♦ Independently Programmable Shutdown Mode
♦ 5MHz, 3-Wire Serial Interface
♦ SPI™, QSPI™, and Microwire™ Compatible
♦ Space-Saving 8-Pin SO Package
______________Ord e rin g In fo rm a t io n
The MAX522’s ultra-low power consumption and small
8-pin SO package make it ideal for portable and bat-
tery-powered applications. Supply current is less than
1mA and drops below 1µA in shutdown mode. In addi-
tion, the reference input is disconnected from the REF
pin during shutdown, further reducing the system’s total
power consumption. The software format is compatible
with the MAX512/MAX513 triple 8-bit DACs.
PART
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
8 Plastic DIP
8 SO
MAX522CPA
MAX522CSA
MAX522EPA
MAX522ESA
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
8 Plastic DIP
8 SO
________________Fu n c t io n a l Dia g ra m
________________________Ap p lic a t io n s
Digital Gain and Offset Adjustment
Programmable Current Source
Programmable Voltage Source
Power-Amp Bias Control
VCO Tuning
0.22µF
8 DIN
0.1µF
(OPTIONAL)
V
3
DD 7 REF
SCLK
2
OUTA
5
V
OUTA
__________________P in Co n fig u ra t io n
DAC
0.1µF
DAC A
DAC B
LATCH
A
TOP VIEW
OUTB
6
V
OUTB
DAC
LATCH
B
0.01µF
1
2
3
4
8
7
6
5
CS
DIN
CS
1
MAX522
SCLK
REF
MAX522
V
DD
OUTB
OUTA
GND
4
GND
DIP/SO
SPI and QSPI are trademarks of Motorola Inc.
Microwire is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
Ca ll t o ll fre e 1 -8 0 0 -9 9 8 -8 8 0 0 fo r fre e s a m p le s o r lit e ra t u re .
Du a l, 8 -Bit , Vo lt a g e -Ou t p u t
S e ria l DAC in 8 -P in S O P a c k a g e
ABSOLUTE MAXIMUM RATINGS
VDD to GND ................................................................ -0.3V, +6V
Digital Inputs and Outputs to GND............... -0.3V, (VDD + 0.3V)
REF ................................................................-0.3V, (VDD + 0.3V)
OUTA, OUTB (Note 1)............................................................VDD
Continuous Power Dissipation (TA = +70°C)
Operating Temperature Ranges
MAX522C_ A.......................................................0°C to +70°C
MAX522E_ A....................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +165°C
Lead Temperature (soldering, 10sec) .............................+300°C
Plastic DIP (derate 9.09mW/°C above +70°C) ..............727mW
SO (derate 5.88mW/°C above +70°C)...........................471mW
MAX52
Note 1: The outputs may be shorted to VDD or GND if the package power dissipation is not exceeded. Typical short-circuit current to
GND is 50mA.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.5V, REF = VDD, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
STATIC PERFORMANCE
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
N
8
Bits
LSB
LSB
LSB
Differential Nonlinearity
Integral Nonlinearity
Total Unadjusted Error
DNL
INL
TUE
Guaranteed monotonic
±1
(Note 2)
(Note 2)
±1.5
±1
Zero-Code Temperature
Coefficient
100
µV/°C
%/%
4.5V ≤ V ≤ 5.5V, REF = 4.096V
0.01
DD
Power-Supply Rejection Ratio
PSRR
2.7V ≤ V ≤ 3.6V, REF = 2.4V
0.015
DD
REFERENCE INPUTS
Reference Input Voltage Range
Reference Input Capacitance
Reference Input Resistance
GND
8
V
DD
V
25
2
pF
kΩ
RREF
(Note 3)
Reference Input Resistance
(shutdown mode)
MΩ
DAC OUTPUTS
Output Voltage Range
0
REF
V
DAC A
DAC B
DAC A
DAC B
0.1
Capacitive Load at OUT_
Output Resistance
µF
0.01
50
Ω
500
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
V
(0.7)(V
)
V
V
IH
DD
V
IL
(0.3)(V
)
DD
IIN
V
IN = 0V or VDD
0.1
±10
10
µA
pF
CIN
Input Capacitance
(Notes 4, 5)
2
_______________________________________________________________________________________
Du a l, 8 -Bit , Vo lt a g e -Ou t p u t
S e ria l DAC in 8 -P in S O P a c k a g e
MAX52
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.5V, REF = VDD, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
SR
C
= 0.1µF (DAC A), C = 0.01µF (DAC B)
0.1
70
70
V/µs
µs
L
L
C
C
= 0.1µF (DAC A)
= 0.01µF (DAC B)
L
L
1
Voltage-Output Settling Time
To ± ⁄ LSB
2
Digital Feedthrough
and Crosstalk
All 0s to all 1s
10
nV-s
POWER SUPPLIES
Supply Voltage Range
V
2.7
5.5
2.8
2.5
V
DD
V
= 5.5V
= 3.6V
1.3
0.9
0.1
DD
Supply Current
I
DD
All inputs = 0V
mA
µA
V
DD
Shutdown Supply Current
V
= 5.5V
DD
TIMING CHARACTERISTICS (Note 4)
(VDD = +2.7V to +5.5V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
SERIAL INTERFACE TIMING
–—–
CS Fall to SCLK Rise Setup Time
t
150
150
50
ns
ns
ns
ns
ns
ns
ns
CSS
–—–
SCLK Rise to CS Rise Setup Time
t
CSH
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
SCLK Pulse Width High
t
DS
DH
CH
t
t
50
100
100
200
SCLK Pulse Width Low
t
CL
t
CSPWH
–—–
CS Pulse Width High
Note 2: Reduced digital code range (code 24 through code 232) is due to swing limitations of the output amplifiers. See Typical
Operating Characteristics.
Note 3: Reference input resistance is code dependent. The lowest input resistance occurs at code 55hex. Refer to the Reference
Input section in the Detailed Description.
Note 4: Guaranteed by design. Not production tested.
Note 5: Input capacitance is code dependent. The highest capacitance occurs at code 00hex.
_______________________________________________________________________________________
3
Du a l, 8 -Bit , Vo lt a g e -Ou t p u t
S e ria l DAC in 8 -P in S O P a c k a g e
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(T = +25°C, unless otherwise noted.)
A
OUTPUT VOLTAGE vs.
OUTPUT VOLTAGE vs.
OUTPUT VOLTAGE vs.
OUTPUT SOURCE CURRENT (V = 3V)
DD
OUTPUT SOURCE CURRENT (V = 5V)
DD
OUTPUT SINK CURRENT
5.2
5.0
4.8
4.6
4.4
4.2
900
800
700
600
500
400
300
3.5
3.0
2.5
2.0
1.5
REF = V = 3V
DD
DAC A
DAC B
DAC A
DAC B
5
CODE = ALL 1s
DAC A
DAC B
1.0
200
REF = V = 3V
DD
CODE = ALL 1s
REF = V = 5V
DD
CODE = ALL 1s
4.0
3.8
0.5
0
100
0
0.0001 0.001 0.01
0.1
1
10
100
0.0001 0.001 0.01
0.1
1
10
100
0.0001 0.001 0.01
0.1
1
10
100
OUTPUT SOURCE CURRENT (mA)
OUTPUT SOURCE CURRENT (mA)
OUTPUT SINK CURRENT (mA)
TOTAL UNADJUSTED ERROR
vs. DIGITAL CODE
POSITIVE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
POSITIVE SUPPLY CURRENT
vs. TEMPERATURE
0
-5
1.5
1.4
1.370
DAC A LOADED WITH 5mA
DAC B LOADED WITH 0.5mA
REF = V
DD
ALL LOGIC INPUTS GROUNDED
1.365
1.360
1.3
1.2
-10
-15
1.1
1.0
0.9
0.8
1.355
1.350
-20
-25
-30
-35
0.7
0.6
REF = V = 5V
DD
ALL LOGIC INPUTS = 5V
ALL DACs SET TO ALL 1s
1.345
1.340
REF = V = 3V
DD
0.5
0
32 64 96 128 160 192 224 255
DIGITAL CODE
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
-60 -40 -20
0
20 40 60 80 100 120 140
V
TEMPERATURE (°C)
DD
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
REFERENCE FEEDTHROUGH
vs. FREQUENCY
REFERENCE LARGE-SIGNAL
FREQUENCY RESPONSE
4.5
4.0
0
5
0
REF = V = 5V
DD
ALL LOGIC INPUTS = 5V
ALL DACs SET TO ALL 1s
V
= 3V
DD
V
= 0V TO 2.9V SINE WAVE
REF
-20
NO LOAD
CODE = ALL 0s
3.5
3.0
-5
-40
-60
2.5
2.0
1.5
1.0
-10
-15
-80
DAC A, B
V
DD
= 3V
-20
-25
-100
-120
V
REF
= 0V TO V SINE WAVE
DD
0.5
0
-60 -40 -20
0
20 40 60 80 100 120 140
0.01
0.1
1
10
100
1000
0.001 0.01 0.1
1
10
100 1000
TEMPERATURE (°C)
FREQUENCY (kHz)
FREQUENCY (kHz)
4
_______________________________________________________________________________________
Du a l, 8 -Bit , Vo lt a g e -Ou t p u t
S e ria l DAC in 8 -P in S O P a c k a g e
MAX52
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(T = +25°C, unless otherwise noted.)
A
REFERENCE SMALL-SIGNAL
FREQUENCY RESPONSE
0
DAC A
-20
DAC B
-40
-60
-80
V
= 3V
DD
V
= 1.5V DC WITH ±40mV
REF
P-P
SINE WAVE SUPERIMPOSED
0.1k
100k 1M
10M
1k
10k
FREQUENCY (Hz)
LINE-TRANSIENT RESPONSE (OUTA)
CLOCK FEEDTHROUGH (OUTA)
A
B
3.14V
A
2.86V
B
20µs/div
1µs/div
REF = 2.56V, NO LOAD, CODE = ALL 1s
CS = HIGH
A : V 100mV/div
DD,
B : OUTA, 500µV/div
A: SCLK, 333kHz, 0V TO 2.9V, 2V/div
B: OUTA, 2mV/div
_______________________________________________________________________________________
5
Du a l, 8 -Bit , Vo lt a g e -Ou t p u t
S e ria l DAC in 8 -P in S O P a c k a g e
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(T = +25°C, unless otherwise noted).
A
POSITIVE SETTLING TIME (DAC A)
POSITIVE SETTLING TIME (DAC B)
MAX52
A
B
A
B
20µs/div
20µs/div
V
DD
= 3V, REF = V R = 1Ωk , C = 0.1µF,
V
DD
= 3V, REF = V R = 10Ωk , C = 0.01µF,
DD,
L
L
DD,
L
L
ALL BITS OFF TO ALL BITS ON
ALL BITS OFF TO ALL BITS ON
A: CS, 2V/div
A: CS, 2V/div
B: OUTA, 20mV/div
B: OUTB, 20mV/div
TIME EXITING SHUTDOWN MODE
OUTPUT VOLTAGE NOISE (DC TO 1MHz)
A
OUTA
200µV/div
B
20µs/div
2ms/div
V
DD
= 3V, REF = V R = 1Ωk , C = 0.1µF,
DD, L L
DIGITAL CODE = 80, REF = V NO LOAD
DD,
DAC LOADED WITH ALL 1s
A: CS, 2V/div
B: OUTA, 1V/div
6
_______________________________________________________________________________________
Du a l, 8 -Bit , Vo lt a g e -Ou t p u t
S e ria l DAC in 8 -P in S O P a c k a g e
MAX52
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
Chip Select (active low). Enables data to be shifted into the 16-bit shift register. Programming commands
are executed at the rising edge of CS.
–—–
CS
1
–—–
2
3
4
5
6
7
8
SCLK
Serial Clock Input. Data is clocked in on the rising edge of SCLK.
Positive Power Supply (2.7V to 5.5V). Bypass with 0.22µF to GND.
Ground
V
DD
GND
OUTA
OUTB
REF
DAC A Output Voltage (Buffered). Connect 0.1µF capacitor or greater to GND.
DAC B Output Voltage (Buffered). Connect 0.01µF capacitor or greater to GND.
Reference Input for DAC A and DAC B
DIN
Serial Data Input of the 16-bit shift register. Data is clocked into the register on the rising edge of SCLK.
The reference voltage on REF can range anywhere from
_______________De t a ile d De s c rip t io n
GND to V . See the Output Buffer Amplifier section for
DD
An a lo g S e c t io n
The MAX522 contains two 8-bit, voltage-output digital-
to-analog converters (DACs). The DACs are “inverted”
R-2R ladder networks using complementary switches
that convert 8-bit digital inputs into equivalent analog
output voltages in proportion to the applied reference
voltage.
more information.
Output Buffer Amplifiers
DAC A a nd DAC B volta g e outp uts a re inte rna lly
b uffe re d . The b uffe r a mp lifie rs ha ve a ra il-to-ra il
(GND to V ) output voltage range.
DD
The DAC outputs are internally divided by two and the
buffer is set to a gain of two, eliminating the need for a
buffer input voltage range to the positive supply rail.
The MAX522 has one reference input which is shared
by DAC A and DAC B. The device includes output
buffer amplifiers for both DACs and input logic for sim-
ple microprocessor (µP) and CMOS interfaces. The
power-supply range is from +5.5V down to +2.7V.
DAC A’s output amplifier can source and sink up to
5mA of current (0.5mA for DAC B’s buffer). See the
Total Unadjusted Error vs. Digital Code graph in the
Typ ic a l Op e ra ting Cha ra c te ris tic s . The a mp lifie r is
unity-g a in s ta b le with a c a p a c itive loa d of 0.1µF
(0.01µF for DAC B’s buffer) or greater. The slew rate is
limited by the load capacitor and is typically 0.1V/µs
with a 0.1µF load (0.01µF for DAC B’s buffer).
Reference Input and DAC Output Range
The voltage at REF sets the full-scale output of the
DACs. The input impedance of the REF input is code
d e p e nd e nt. The lowe s t va lue , a p p roxima te ly 8kΩ,
occurs when the input code is 01010101 (55hex). The
maximum value of infinity occurs when the input code
is zero.
Shutdown Mode
When programmed to shutdown mode, the outputs of
DAC A and DAC B go into a high-impedance state.
Virtually no current flows into or out of the buffer ampli-
fiers in that state. In shutdown mode, the REF inputs
are high impedance (2MΩ typical) to conserve current
drain from the system reference; therefore, the system
reference does not have to be powered down.
In shutdown mode, the selected DAC output is set to
zero while the value stored in the DAC register remains
unchanged. This removes the load from the reference
input to save power. Bringing the MAX522 out of shut-
down mode restores the DAC output voltage. Because
the input resistance at REF is code dependent, the
DAC’s re fe re nc e s ourc e s s hould ha ve a n outp ut
impedance of no more than 5Ω. The input capacitance
at the REF pin is also code dependent and typically
does not exceed 25pF.
Coming out of shutdown, the DAC outputs return to the
values kept in the registers. The recovery time is equiv-
alent to the DAC settling time.
_______________________________________________________________________________________
7
Du a l, 8 -Bit , Vo lt a g e -Ou t p u t
S e ria l DAC in 8 -P in S O P a c k a g e
Table 1. Input Shift Register
B0*
B1
DAC Data Bit 0 (LSB)
DAC Data Bit 1
B2
DAC Data Bit 2
R
R
R
B3
DAC Data Bit 3
OUT
B4
DAC Data Bit 4
MAX52
B5
DAC Data Bit 5
2R
2R
2R
2R
2R
B6
DAC Data Bit 6
B7
DAC Data Bit 7 (MSB)
Load Reg DAC A, Active High
Load Reg DAC B, Active High
Uncommitted Bit 4
LA
REF
GND
LB
UB4
SA
SHOWN FOR ALL 1s ON DAC
Shut Down DAC A, Active High
Shut Down DAC B, Active High
Uncommitted Bit 3
SB
UB3
UB2
UB1**
Uncommitted Bit 2
Figure 1. DAC Simplified Circuit Diagram
Uncommitted Bit 1
**Clocked in last.
**Clocked in first.
Serial-Input Data Format and Control Codes
Table 2 lists the serial-input data format. The 16-bit
input word consists of an 8-bit control byte and an 8-bit
data byte. The 8-bit control byte is not decoded inter-
nally. Every control bit performs one function. Data is
clocked in starting with UB1 (Uncommitted Bit), fol-
lowed by the remaining control bits and the data byte.
The LSB of the data byte (B0) is the last bit clocked into
the shift register (Figure 2).
S e ria l In t e rfa c e
–—–
An active-low chip select (CS) enables the shift register
to re c e ive d a ta from the s e ria l d a ta inp ut. Da ta is
clocked into the shift register on every rising edge of
the serial clock signal (SCLK). The clock frequency can
be as high as 5MHz.
Data is sent MSB first and can be transmitted in one 16-
–—–
bit word. The write cycle can be segmented when CS is
kept active (low) to allow, for example, two 8-bit-wide
Table 3 is an example of a 16-bit input word. It per-
forms the following functions:
transfers. After clocking all 16 bits into the input shift
register, the rising edge of CS updates the DAC outputs
–—–
a nd the s hutd own s ta tus . Be c a us e of the ir s ing le
buffered structure, DACs cannot be simultaneously
updated to different digital values.
• 80hex (128 decimal) loaded into DAC registers
A and B.
• DAC A and DAC B are active.
8
_______________________________________________________________________________________
Du a l, 8 -Bit , Vo lt a g e -Ou t p u t
S e ria l DAC in 8 -P in S O P a c k a g e
MAX52
CS
INSTRUCTION
EXECUTED
SCLK
OPTIONAL
DIN
UB1 UB2 UB3 SB SA UB4 LB LA
(CONTROL BYTE)
D7 D6 D5 D4 D3 D2 D1 D0
(DATA BYTE)
Figure 2. MAX522 3-Wire Serial-Interface Timing Diagram
Table 2. Serial-Interface Programming Commands
CONTROL
DATA
FUNCTION
B7
MSB
B0
LSB
UB1 UB2 UB3 SB SA UB4 LB LA
B6 B5 B4 B3 B2 B1
*
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
*
*
*
*
*
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
*
*
*
*
*
0
0
0
1
1
*
*
*
*
*
X
X
X
X
X
X
X
X
No Operation to DAC Registers
Unassigned Command
Load Register to DAC B
Load Register to DAC A
Load Both DAC Registers
All DACs Active
*
*
*
*
0
0
1
0
1
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Unassigned Command
Shut Down DAC B
Shut Down DAC A
Shut Down All DACs
X = Don’t care.
* = Not shown, for the sake of clarity. The functions of loading and shutting down the DACs and programming the logic can be combined in a single
command.
Table 3. Example of a 16-Bit Input Word
Loaded
in First
Loaded
in Last
UB1
UB2
UB3
SB
SA
UB4
LB
LA
B7
B6
B5
B4
B3
B2
B1
B0
X
X
1
0
0
0
1
1
1
0
0
0
0
0
0
0
_______________________________________________________________________________________
9
Du a l, 8 -Bit , Vo lt a g e -Ou t p u t
S e ria l DAC in 8 -P in S O P a c k a g e
CS
t
CSPWH
t
t
CSH
CSS
t
CH
MAX52
SCLK
t
CL
t
DS
t
DH
DIN
Figure 3. MAX522 Detailed Serial-Interface Timing Diagram
Digital Inputs
The digital inputs are compatible with CMOS logic.
Supply current increases slightly when toggling the
log ic inp uts throug h the tra ns ition zone b e twe e n
Table 4. Code Table
DAC CONTENTS
ANALOG
OUTPUT
B7 B6 B5 B4 B3 B2 B1 B0
(0.3)(V ) and (0.7)(V ).
DD
DD
255
256
Microprocessor Interfacing
+REF ×
+REF ×
1
1
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
The MAX522 s e ria l inte rfa c e is c omp a tib le with
Microwire, SPI, and QSPI. For SPI, clear the CPOL and
CPHA bits (CPOL = 0 and CPHA = 0). CPOL = 0 sets
the inactive clock state to zero and CPHA = 0 changes
data at the falling edge of SCLK. This setting allows SPI
to run at full clock speeds (0.5MHz). If a serial port is
not available on your µP, three bits of a parallel port can
be used to emulate a serial port by bit manipulation.
Minimize digital feedthrough at the voltage outputs by
operating the serial clock only when necessary.
129
256
128
= +
REF
2
+REF
×
256
127
256
+REF ×
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
+REF ×
256
0V
Note:
1
−8
1LSB
=
REF × 2
= REF ×
256
D
where D = Decimal
Value of Digital Input
ANALOG OUTPUT = REF ×
256
10 ______________________________________________________________________________________
Du a l, 8 -Bit , Vo lt a g e -Ou t p u t
S e ria l DAC in 8 -P in S O P a c k a g e
MAX52
______________Ap p lic a t io n s In fo rm a t io n
The MAX522 is specified for single-supply operation
with V ranging from 2.7V to 5.5V, covering all com-
DD
monly used supply voltages in 3V and 5V systems.
In it ia liza t io n
The re is no inte rna l p owe r-on re s e t. The re fore , a t
power-up, perform an initial write operation to set the
outputs to the desired voltage.
P o w e r-S u p p ly a n d
Gro u n d Ma n a g e m e n t
GND s hould b e c onne c te d to the hig he s t q ua lity
ground available. Bypass V with a 0.1µF to 0.22µF
DD
capacitor to GND. The reference input can be used
without b yp a s s ing . For op timum line /loa d -tra ns ie nt
response and noise performance, bypass the refer-
ence input with 0.1µF to 4.7µF to GND. Careful PC
board layout minimizes crosstalk among DAC outputs,
the reference, and digital inputs. Separate analog lines
with ground traces between them. Make sure that high-
frequency digital lines are not routed in parallel to ana-
log lines.
______________________________________________________________________________________ 11
Du a l, 8 -Bit , Vo lt a g e -Ou t p u t
S e ria l DAC in 8 -P in S O P a c k a g e
________________________________________________________P a c k a g e In fo rm a t io n
INCHES
MILLIMETERS
DIM
E
MIN
MAX
0.200
–
MIN
–
MAX
5.08
–
A
–
E1
D
A1 0.015
A2 0.125
A3 0.055
0.38
3.18
1.40
0.41
1.14
0.20
0.13
7.62
6.10
2.54
7.62
–
0.175
0.080
0.022
0.065
0.012
0.080
0.325
0.310
–
4.45
2.03
0.56
1.65
0.30
2.03
8.26
7.87
–
A3
A2
A1
MAX52
A
L
B
0.016
B1 0.045
0.008
D1 0.005
0.300
E1 0.240
0.100
eA 0.300
C
0° - 15°
E
C
e
e
B1
eA
eB
–
–
B
eB
L
–
0.400
0.150
10.16
3.81
0.115
2.92
D1
INCHES
MILLIMETERS
PKG. DIM
PINS
Plastic DIP
PLASTIC
DUAL-IN-LINE
PACKAGE
(0.300 in.)
MIN
MAX MIN
MAX
8
P
P
P
P
P
N
D
D
D
D
D
D
0.348 0.390 8.84
9.91
14
16
18
20
24
0.735 0.765 18.67 19.43
0.745 0.765 18.92 19.43
0.885 0.915 22.48 23.24
1.015 1.045 25.78 26.54
1.14 1.265 28.96 32.13
21-0043A
INCHES
MILLIMETERS
DIM
MIN
0.053
MAX
0.069
0.010
0.019
0.010
0.157
MIN
1.35
0.10
0.35
0.19
3.80
MAX
1.75
0.25
0.49
0.25
4.00
A
D
A1 0.004
B
C
E
e
0.014
0.007
0.150
0°-8°
A
0.101mm
0.004in.
0.050
1.27
e
H
L
0.228
0.016
0.244
0.050
5.80
0.40
6.20
1.27
A1
C
B
L
INCHES
MILLIMETERS
DIM PINS
Narrow SO
SMALL-OUTLINE
PACKAGE
MIN MAX
MIN
MAX
5.00
8.75
8
0.189 0.197 4.80
D
D
D
E
H
14 0.337 0.344 8.55
16 0.386 0.394 9.80 10.00
21-0041A
(0.150 in.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1995 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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