MAX5231AEEE+ [MAXIM]
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| 型号： | MAX5231AEEE+ |
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MAXIM INTEGRATED PRODUCTS |
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19-2332; Rev 1; 9/03
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
General Description
Features
The MAX5230/MAX5231 low-power, dual 12-bit voltage-
output digital-to-analog converters (DACs) feature an
internal 3ppm/°C precision bandgap voltage reference
and precision output amplifiers. The MAX5231 operates
on a single 5V supply with an internal 2.5V reference and
features a 4.095V full-scale output range. The MAX5230
operates on a single 3V supply with an internal 1.25V ref-
erence and features a 2.0475V full-scale output range.
The MAX5231 consumes only 470µA while the MAX5230
consumes only 420µA of supply current. Both devices
feature low-power (2µA) software- and hardware-
enabled shutdown modes.
ꢀ Internal 3ppm/°C Precision Bandgap Reference
2.465V (MAX5231)
1.234V (MAX5230)
ꢀ 10ppm/°C (max) Full-Scale Output Range
4.095V (MAX5231)
2.0475V (MAX5230)
ꢀ Single-Supply Operation
5V (MAX5231)
3V (MAX5230)
ꢀ Low Supply Current
470µA (MAX5231)
420µA (MAX5230)
The MAX5230/MAX5231 feature a 13.5MHz SPI™-,
QSPI™-, and MICROWIRE™-compatible 3-wire serial
interface. An additional data output (DOUT) allows for
daisy-chaining and read back. Each DAC has a double-
buffered digital input. The MAX5230/MAX5231 feature
two software-selectable shutdown output impedances:
1kΩ or 200kΩ. A power-up reset feature sets DAC out-
puts at ground or at the midscale DAC code.
ꢀ 13.5MHz SPI/QSPI/MICROWIRE-Compatible,
3-Wire Serial Interface
ꢀ Pin-Programmable Power-Up Reset State to Zero
or Midscale Output Voltage
ꢀ Programmable Shutdown Modes with 1kΩ or
200kΩ Internal Output Loads
The MAX5230/MAX5231 are specified over the extended
temperature range (-40°C to +85°C) and are available in
16-pin QSOP packages.
ꢀ Recalls Output State Prior to Shutdown or Reset
ꢀ Buffered Output Drives 5kΩ || 100pF Loads
ꢀ Space-Saving 16-Pin QSOP Package
Applications
Industrial Process Controls
Automatic Test Equipment
Digital Offset and Gain Adjustment
Motion Control
Ordering Information
PIN-
PACKAGE
INL
(LSB)
PART
TEMP RANGE
µP-Controlled Systems
MAX5230AEEE
MAX5230BEEE
MAX5231AEEE
MAX5231BEEE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
16 QSOP
16 QSOP
16 QSOP
16 QSOP
0.5
1
Pin Configuration
0.5
1
TOP VIEW
OSA
OUTA
RSTV
LDAC
CLR
1
2
3
4
5
6
7
8
16 OSB
15 OUTB
14
V
DD
Functional Diagram appears at end of data sheet.
MAX5230
MAX5231
13 AGND
12 REF
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor, Corp.
CS
11 PDL
10 DOUT
DIN
SCLK
9
DGND
QSOP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
ABSOLUTE MAXIMUM RATINGS
DD
V
to AGND, DGND...............................................-0.3V to +6V
Maximum Current into Any Pin............................................50mA
AGND to DGND.....................................................-0.3V to +0.3V
Digital Inputs to DGND.............................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Digital Output (DOUT) to DGND...................-0.3V to V
OUT_ to AGND .............................................-0.3V to V
OS_ to AGND...................................................-4V to V
+ 0.3V
+ 0.3V
+ 0.3V
DD
DD
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX5231
(V
= +4.5V to +5.5V, OS_ = AGND = DGND = 0, R = 5kΩ, C = 100pF, T = T
A
to T , unless otherwise noted. Typical values
MAX
DD
L
L
A
MIN
are at T = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
N
12
Bits
MAX5231A
MAX5231B
0.5
1
Integral Nonlinearity (Note 1)
INL
LSB
Differential Nonlinearity
Offset Error (Note 2)
DNL
1
LSB
mV
V
3
OS
Offset-Temperature Coefficient (Note 3)
Full-Scale Voltage
TCV
8
4.095
3
µV/°C
V
OS
V
Code = FFF hex, T = +25°C
4.070
4.120
10
FS
A
MAX5231A
Full-Scale Temperature Coefficient
(Note 3)
TCV
ppm/°C
FS
MAX5231B (Note 6)
10
30
Power-Supply Rejection
DC Crosstalk (Note 4)
REFERENCE
PSR
4.5V ≤ V ≤ 5.5V
175
500
100
µV
µV
DD
Output Voltage
V
2.465
3
V
REF
MAX5231A
MAX5231B
Output-Voltage Temperature
Coefficient (Note 3)
TCV
ppm/°C
REF
10
0.1
4
Reference External Load Regulation
Reference Short-Circuit Current
DIGITAL INPUTS
V
/I
0 ≤ I
≤ 100µA (sourcing)
2
µV/µA
mA
OUT OUT
OUT
Input High Voltage
V
0.7 x V
V
V
IH
DD
Input Low Voltage
V
0.3 x V
1
IL
DD
Input Hysteresis
V
200
8
mV
µA
pF
HYS
Input Leakage Current
Input Capacitance
I
Digital inputs = 0 or V
DD
IN
C
IN
DIGITAL OUTPUTS
Output High Voltage
V
I
= 2mA
SOURCE
4.25
V
V
OH
Output Low Voltage
V
I = 2mA
SINK
0.2
OL
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
SR
0.6
V/µs
2
_______________________________________________________________________________________
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX5231 (continued)
(V
= +4.5V to +5.5V, OS_ = AGND = DGND = 0, R = 5kΩ, C = 100pF, T = T
A
to T , unless otherwise noted. Typical values
MAX
DD
L
L
A
MIN
are at T = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
To 0.5LSB, V
MIN
TYP
MAX
UNITS
=
4V
≥ 0.25V
STEP
Voltage-Output Settling Time
10
µs
(V
DD
- 0.25V) ≥ V
OUT
Output-Voltage Swing (Note 5)
OS_ Input Resistance
0 to V
V
DD
R
83
121
kΩ
OS
Time Required for Output to Settle After
Turning on V (Note 6)
DD
95
400
400
160
µs
µs
µs
Time Required for Output to Settle After
Exiting Full Power-Down (Note 6)
95
12
Time Required for Output to Settle After
Exiting DAC Power-Down (Note 6)
CS = V , f
= 100kHz,
DD SCLK
Digital Feedthrough
5
nV-s
nV-s
V
= 5V
P-P
SCLK
Major-Carry Glitch Energy
POWER SUPPLIES
90
Power-Supply Voltage
V
4.5
5.5
525
5
V
DD
Power-Supply Current (Note 7)
I
470
1.4
µA
DD
Full power-down mode
Power-Supply Current in Power-Down
and Shutdown Modes (Note 7)
One DAC shutdown mode
Both DACs shutdown mode
350
235
390
260
µA
ELECTRICAL CHARACTERISTICS—MAX5230
(V
= +2.7V to +3.6V, OS_ = AGND = DGND = 0, R = 5kΩ, C = 100pF, T = T
A
to T , unless otherwise noted. Typical values
MAX
DD
L
L
A
MIN
are at T = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
N
12
Bits
MAX5230A
MAX5230B
0.5
1
Integral Nonlinearity (Note 1)
INL
LSB
Differential Nonlinearity
Offset Error (Note 2)
DNL
1
LSB
mV
V
3
OS
Offset-Temperature Coefficient (Note 3)
Full-Scale Voltage
TCV
8
2.0475
3
µV/°C
V
OS
V
Code = FFF hex, T = +25°C
2.0350
2.0600
10
FS
A
MAX5230A
Full-Scale Temperature Coefficient
(Note 3)
TCV
ppm/°C
FS
MAX5230B (Note 6)
10
30
Power-Supply Rejection
DC Crosstalk (Note 4)
REFERENCE
PSR
2.7V ≤ V ≤ 3.6V
175
500
100
µV
µV
DD
Output Voltage
V
1.234
3
V
REF
MAX5230A
MAX5230B
Output-Voltage Temperature
Coefficient (Note 3)
TCV
ppm/°C
REF
10
_______________________________________________________________________________________
3
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX5230 (continued)
(V
= +2.7V to +3.6V, OS_ = AGND = DGND = 0, R = 5kΩ, C = 100pF, T = T
A
to T , unless otherwise noted. Typical values
MAX
DD
L
L
A
MIN
are at T = +25°C.)
PARAMETER
SYMBOL
/I
CONDITIONS
≤ 100µA (sourcing)
OUT
MIN
TYP
0.1
4
MAX
UNITS
µV/µA
mA
Reference External Load Regulation
Reference Short-Circuit Current
DIGITAL INPUTS
V
0 ≤ I
2
OUT OUT
Input High Voltage
V
0.7 x V
V
V
IH
DD
Input Low Voltage
V
0.3 x V
1
IL
DD
Input Hysteresis
V
200
8
mV
µA
pF
HYS
Input Leakage Current
Input Capacitance
I
Digital inputs = 0 or V
DD
IN
C
IN
DIGITAL OUTPUTS
Output High Voltage
V
I
= 2mA
SOURCE
2.3
V
V
OH
Output Low Voltage
V
I = 2mA
SINK
0.25
OL
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
SR
0.6
10
V/µs
µs
To 0.5 LSB, V
=
2V
≥ 0.25V
STEP
Voltage-Output Settling Time
(V
DD
- 0.25V) ≥ V
OUT
Output-Voltage Swing (Note 5)
OS_ Input Resistance
0 to V
V
DD
R
83
121
kΩ
OS
Time Required for Output to Settle After
Turning on V (Note 6)
DD
95
400
400
160
µs
µs
µs
Time Required for Output to Settle After
Exiting Full Power-Down (Note 6)
95
12
Time Required for Output to Settle After
Exiting DAC Power-Down (Note 6)
CS =V , f
= 100kHz,
DD SCLK
Digital Feedthrough
5
nV-s
nV-s
V
= 3V
P-P
SCLK
Major-Carry Glitch Energy
90
4
_______________________________________________________________________________________
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX5230 (continued)
(V
= +2.7V to +3.6V, OS_ = AGND = DGND = 0, R = 5kΩ, C = 100pF, T = T
A
to T , unless otherwise noted. Typical values
MAX
DD
L
L
A
MIN
are at T = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
Power-Supply Voltage
Power-Supply Current (Note 7)
V
2.7
3.6
475
5
V
DD
I
420
0.9
µA
DD
Full power-down mode
Power-Supply Current in Power-Down
and Shutdown Modes (Note 7)
µA
One DAC shutdown mode
320
220
360
245
Both DACs shutdown mode
Note 1: Accuracy is guaranteed as shown in the following table:
ACCURACY GUARANTEED
V
DD
(V)
FROM CODE
TO CODE
4095
3
5
20
10
4095
Note 2: Offset is measured at the code closest to 10mV.
Note 3: Temperature coefficient is determined by the box method in which the maximum ∆V
over the temperature range is
OUT
divided by ∆T.
Note 4: DC crosstalk is measured as follows: set DAC A to midscale, and DAC B to zero, and measure DAC A output; then change
DAC B to full scale, and measure ∆V for DAC A. Repeat the same measurement with DAC A and DAC B interchanged.
OUT
DC crosstalk is the maximum ∆V
measured.
OUT
Note 5: Accuracy is better than 1LSB for V
= 10mV to V
- 180mV.
DD
OUT_
Note 6: Guaranteed by design, not production tested.
Note 7: R = ∞ and digital inputs are at either V
or DGND.
DD
LOAD
TIMING CHARACTERISTICS—MAX5231
(V
= +4.5V to +5.5V, AGND = DGND = 0, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
DD
A
MIN
(Figures 1 and 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
74
30
30
30
0
TYP
MAX
UNITS
ns
SCLK Clock Period
t
CP
CH
SCLK Pulse Width High
SCLK Pulse Width Low
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
DIN Setup Time
t
ns
t
CL
ns
t
ns
CSS
CSH
t
ns
t
30
0
ns
DS
DIN Hold Time
t
ns
DH
C
C
C
C
= 200pF
= 100pF
= 200pF
= 100pF
45
30
45
30
100
100
SCLK Rise to DOUT Valid
Propagation Delay Time
LOAD
LOAD
LOAD
LOAD
t
t
ns
ns
DO1
DO2
SCLK Fall to DOUT Valid
Propagation Delay Time
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold Time
CS Pulse Width High
t
t
10
30
75
30
40
ns
ns
ns
ns
ns
CS0
CS1
t
CSW
LDAC Pulse Width Low
t
LDL
CS Rise to LDAC Rise Hold Time
t
(Note 8)
CSLD
_______________________________________________________________________________________
5
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
TIMING CHARACTERISTICS—MAX5230
(V
= +2.7V to +3.6V, AGND = DGND = 0, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
DD
A
MIN
(Figures 1 and 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
74
30
30
30
0
TYP
MAX
UNITS
ns
SCLK Clock Period
t
CP
CH
SCLK Pulse Width High
SCLK Pulse Width Low
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
DIN Setup Time
t
ns
t
ns
CL
t
ns
CSS
CSH
t
ns
t
30
0
ns
DS
DIN Hold Time
t
ns
DH
C
C
C
C
= 200pF
= 100pF
= 200pF
= 100pF
60
45
60
45
200
200
SCLK Rise to DOUT Valid
Propagation Delay Time
LOAD
LOAD
LOAD
LOAD
t
ns
ns
DO1
DO2
SCLK Fall to DOUT Valid
Propagation Delay Time
t
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold Time
CS Pulse Width High
t
t
10
30
75
30
75
ns
ns
ns
ns
ns
CS0
CS1
t
CSW
LDAC Pulse Width Low
t
LDL
CS Rise to LDAC Rise Hold Time
t
(Note 8)
CSLD
Note 8: This timing requirement applies only to CS rising edges, which execute commands modifying the DAC input register
contents.
Typical Operating Characteristics
(V
DD
= +3V (MAX5230), V
= +5V (MAX5231), R = 5kΩ, C = 100pF, OS_ = AGND, both DACs enabled with full-scale output code,
DD
L
L
T
A
= +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (MAX5230)
0.15
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (MAX5231)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (MAX5230)
0.208
0.086
0.15
0.10
0.05
0
0.10
0.05
0
-0.037
-0.160
-0.283
-0.05
-0.10
-0.15
-0.05
-0.10
-0.15
0
500 1000 1500 2000 2500 3000 3500 4000
DIGITAL INPUT CODE
0
500 1000 1500 2000 2500 3000 3500 4000
DIGITAL INPUT CODE
0
500 1000 1500 2000 2500 3000 3500 4000
DIGITAL INPUT CODE
6
_______________________________________________________________________________________
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
Typical Operating Characteristics (continued)
(V
DD
= +3V (MAX5230), V
= +5V (MAX5231), R = 5kΩ, C = 100pF, OS_ = AGND, both DACs enabled with full-scale output code,
DD
L
L
T
A
= +25°C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (MAX5231)
0.15
SUPPLY CURRENT vs. TEMPERATURE
(MAX5230)
SUPPLY CURRENT vs. TEMPERATURE
(MAX5231)
450
440
430
420
410
400
450
440
430
420
410
400
0.10
0.05
0
-0.05
-0.10
-0.15
0
500 1000 1500 2000 2500 3000 3500 4000
DIGITAL INPUT CODE
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX5230)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX5231)
FULL POWER-DOWN SUPPLY CURRENT
vs. TEMPERATURE (MAX5230)
430
425
420
415
410
405
400
490
485
480
475
470
465
460
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
NO LOAD
2.7
3.0
3.3
3.6
4.50
4.75
5.00
5.25
5.50
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TWO-DACs SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE (MAX5230)
ONE-DAC SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE (MAX5230)
FULL POWER-DOWN SUPPLY CURRENT
vs. TEMPERATURE (MAX5231)
230
225
220
215
210
205
200
330
325
320
315
310
305
300
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
NO LOAD
NO LOAD
NO LOAD
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
Typical Operating Characteristics (continued)
(V
DD
= +3V (MAX5230), V
= +5V (MAX5231), R = 5kΩ, C = 100pF, OS_ = AGND, both DACs enabled with full-scale output code,
DD
L
L
T
A
= +25°C, unless otherwise noted.)
FULL-SCALE OUTPUT VOLTAGE
vs. TEMPERATURE (MAX5230)
TWO-DACs SHUTDOWN SUPPLY CURRENT
ONE-DAC SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE (MAX5231)
vs. TEMPERATURE (MAX5231)
2.0480
2.0475
2.0470
2.0465
2.0460
255
380
375
370
365
360
355
350
250
245
240
235
230
NO LOAD
-15
NO LOAD
225
NO LOAD
-40
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
FULL-SCALE OUTPUT VOLTAGE
vs. TEMPERATURE (MAX5231)
FULL-SCALE ERROR vs. RESISTIVE LOAD
(MAX5230)
FULL-SCALE ERROR vs. RESISTIVE LOAD
(MAX5231)
4.0940
4.0935
4.0930
4.0925
4.0920
4.0915
4.0910
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.25
0.20
0.15
0.10
0.05
0
CHANGE FROM
NO LOAD
CHANGE FROM
NO LOAD
NO LOAD
-15
-40
10
35
60
85
2.5
3.5
4.5
5.5
6.5
7.5
2.5
3.5
4.5
5.5
6.5
7.5
TEMPERATURE (°C)
RESISTIVE LOAD (kΩ)
RESISTIVE LOAD (kΩ)
DYNAMIC RESPONSE RISE TIME
(MAX5230)
DYNAMIC RESPONSE RISE TIME
(MAX5231)
DYNAMIC RESPONSE FALL TIME
(MAX5230)
MAX5230/MAX5231 toc21
MAX5230/MAX5231 toc19
MAX5230/MAX5231 toc20
3V
3V
V
CS
2V/div
V
5V
CS
2V/div
V
CS
5V/div
0
0
0
2.048V
4.096V
2.048V
V
V
V
OUT
500mV/div
OUT
500mV/div
OUT
1V/div
10mV
10mV
10mV
2µs/div
2µs/div
2µs/div
8
_______________________________________________________________________________________
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
Typical Operating Characteristics (continued)
(V
DD
= +3V (MAX5230), V
= +5V (MAX5231), R = 5kΩ, C = 100pF, OS_ = AGND, both DACs enabled with full-scale output code,
DD L L
T
A
= +25°C, unless otherwise noted.)
DYNAMIC RESPONSE FALL TIME
ANALOG CROSSTALK
(MAX5230)
ANALOG CROSSTALK
(MAX5231)
MAX5230/MAX5231 toc24
(MAX5231)
MAX5230/MAX5231 toc22
MAX5230/MAX5231 toc23
5V
V
OUTA
2V/div
OUTA
5V/div
CS
5V/div
0
4.096V
OUTB
5mV/div
AC-COUPLED
OUTB
5mV/div
AC-COUPLED
V
OUT
1V/div
10mV
2µs/div
400µs/div
400µs/div
DIGITAL FEEDTHROUGH
(MAX5230)
DIGITAL FEEDTHROUGH
(MAX5231)
MAJOR-CARRY TRANSITION
(MAX5230)
MAX5230/MAX5231 toc27
MAX5230/MAX5231 toc25
MAX5230/MAX5231 toc26
SCLK
2V/div
SCLK
5V/div
CS
5V/div
OUTA
100mV/div
AC-COUPLED
OUTA
1mV/div
AC-COUPLED
OUTA
1mV/div
AC-COUPLED
10µs/div
10µs/div
2µs/div
MAJOR-CARRY TRANSITION
(MAX5231)
REFERENCE VOLTAGE
vs. TEMPERATURE (MAX5230)
REFERENCE VOLTAGE
vs. TEMPERATURE (MAX5231)
MAX5230/MAX5231 toc28
1.2350
1.2345
1.2340
1.2335
1.2330
2.4630
2.4625
2.4620
2.4615
2.4610
CS
5V/div
OUTA
100mV/div
AC-COUPLED
NO LOAD
-15
NO LOAD
-15
2µs/div
-40
10
35
60
85
-40
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
9
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
Pin Description
PIN
1
NAME
OSA
FUNCTION
DAC A Offset Adjust
DAC A Output
2
OUTA
Reset Value Input
3
RSTV
1: Connect to V
to select midscale as the reset value.
DD
0: Connect to DGND to select zero as the reset value.
4
5
LDAC
CLR
Load DACs A and B
Clear Input. Both DAC outputs go to zero or midscale. Clears both DAC internal registers (input
register and DAC register) to its predetermined (RSTV) state.
6
7
CS
Chip-Select Input
DIN
Serial Data Input. Data is clocked in on the rising edge of SCLK.
8
SCLK
DGND
DOUT
PDL
Serial Clock Input
9
Digital Ground
10
11
12
13
Serial Data Output
Power-Down Lockout. Disables shutdown of both DACs when low.
Reference Output. Reference provides a 2.465V (MAX5231) or 1.234V (MAX5230) nominal output.
Analog Ground
REF
AGND
Positive Power Supply. Bypass V
with a 0.1µF capacitor in parallel with a 4.7µF capacitor to
DD
14
V
DD
AGND, and bypass V
with a 0.1µF capacitor to DGND.
DD
15
16
OUTB
OSB
DAC B Output
DAC B Offset Adjust
COMMAND EXECUTED
CS
SCLK
1
8
9
16
D5 D4 D3 D2 D1 D0 S0
(1)
DIN
C1 C0
D10 D9
D11
C2
D8 D7
D6
DOUT
(MODE 0)
C2
C1
DOUT
C2
C1
(MODE 1)
Figure 1. Serial Interface Timing
10 ______________________________________________________________________________________
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
t
LDL
t
CSLD
LDAC
t
CSW
CS
t
t
CSS
CSO
t
CSH
t
CS1
SCLK
t
t
CL
CH
t
CP
DIN
t
t
DS
DH
t
t
D02
D01
DOUT
Figure 2. Detailed Serial Interface Timing
0.6V/µs and settle to 1/2LSB within 10µs with a load of
5kΩ in parallel with 100pF. Use the serial interface to
set the shutdown output impedance of the amplifiers to
1kΩ or 200kΩ.
OS_ can be used to produce an offset voltage at the
output. For instance, to achieve a 1V offset, apply -1V
to OS_ to produce an output range from 1V to (1V +
Detailed Description
The MAX5230/MAX5231 12-bit, voltage-output DACs
are easily configured with a 3-wire SPI-, QSPI-,
MICROWIRE-compatible serial interface. The devices
include a 16-bit data-in/data-out shift register and have
an input consisting of an input register and a DAC reg-
ister. In addition, these devices employ precision
trimmed internal resistors to produce a gain of
1.6384V/V, maximizing the output voltage swing, and a
programmable-shutdown output impedance of 1kΩ or
200kΩ The full-scale output voltage is 4.095V for the
MAX5231 and 2.0475V for the MAX5230. These
devices produce a weighted output voltage proportion-
V /V ). Note that the DAC’s output range is still lim-
FS REF
ited by the maximum output voltage specification.
OS_
121kΩ
®
al to the digital input code with an inverted Rail-to-Rail
ladder network (Figure 3).
77.25kΩ
Internal Reference
The MAX5230/MAX5231 use an on-board precision
bandgap reference to generate an output voltage of
1.234V (MAX5230) or 2.465V (MAX5231). With a low
temperature coefficient of only 3ppm/°C, REF can
source up to 100µA and is stable for capacitive loads
less than 35pF.
OUT_
R
R
R
2R
D0
2R
D9
2R
D10
2R
2R
D11
1kΩ
REF
Output Amplifiers
The output amplifiers have internal resistors that pro-
AGND
vide for a gain of 1.6384V/V when OS_ is connected to
AGND. The output amplifiers have a typical slew rate of
SHOWN FOR ALL ONES ON DAC
Figure 3. Simplified DAC Circuit Diagram
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
______________________________________________________________________________________ 11
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
ously. The control bits and D11–D8 allow the DACs to
operate independently.
Table 1. Serial Data Format
MSB <------------16-bits of serial data ------------> LSB
Send the 16-bit data as one 16-bit word (QSPI) or two
3 Control Bits
MSB .. 12 Data Bits... LSB
D11 ..............................D0
Sub-Bit
S0
8-bit packets (SPI, MICROWIRE), with CS low during
this period. The control bits and D11–D8 determine
which registers update and the state of the registers
when exiting shutdown. The 3-bit control and D11–D8
determine the following:
C2…C0
Serial Interface
The 3-wire serial interface (SPI, QSPI, MICROWIRE
compatible) used in the MAX5230/MAX5231 allows for
complete control of DAC operations (Figures 4 and 5).
Figures 1 and 2 show the timing for the serial interface.
The serial word consists of 3 control bits followed by 12
data bits (MSB first) and 1 sub-bit as described in
Tables 1, 2, and 3. When the 3 control bits are all zero
or all 1, D11–D8 are used as additional control bits,
allowing for greater DAC functionality.
• Registers to be updated
• Selection of the power-down and shutdown modes
The general timing diagram of Figure 1 illustrates data
acquisition. Driving CS low enables the device to
receive data. Otherwise the interface control circuitry is
disabled. With CS low, data at DIN is clocked into the
register on the rising edge of SCLK. As CS goes high,
data is latched into the input and/or DAC registers,
depending on the control bits and D11–D8. The maxi-
mum clock frequency guaranteed for proper operation
is 13.5MHz. Figure 2 depicts a more detailed timing
diagram of the serial interface.
The digital inputs allow any of the following: loading the
input register(s) without updating the DAC register(s),
updating the DAC register(s) from the input register(s),
or updating the input and DAC register(s) simultane-
Table 2. Serial-Interface Programming Commands
16-BIT SERIAL WORD
FUNCTION
C2
0
C1
0
C0
1
D11..............D0
12-bit DAC data
12-bit DAC data
S0*
0
Load input register A; DAC registers are unchanged.
Load input register A; all DAC registers are updated.
0
1
0
0
Load all DAC registers from the shift register (start up both DACs
with new data, and load the input registers).
0
1
1
0
1
0
12-bit DAC data
0
0
Update both DAC registers from their respective input registers (start
up both DACs with data previously stored in the input registers).
X X X X X X X X X X X X
1
1
0
1
1
0
12-bit DAC data
12-bit DAC data
0
0
Load input register B; DAC registers are unchanged.
Load input register B; all DAC registers are updated.
Shut down both DACs, respectively, according to bits P1A and P1B
(see Table 3). Internal bias and reference remain active.
1
0
1
0
1
0
P1A P1B X X X X X X X X X X
0 0 1 X X X X X X X X X
0
0
Update DAC register A from input register A (start up DAC A with
data previously stored in input register A).
Full Power-Down. Power down the main bias generator and shut
down both DACs, respectively, according to bits P1A and P1B (see
Table 3).
0
0
0
0 1 1 P1A P1B X X X X X X X
0
Update DAC register B from input register B (start up DAC B with
data previously stored in input register B).
0
0
0
1 0 1 X X X X X X X X X
0
0
0
0
0
0
0
0
0
0
0
0
0
1 1 0 P1A X X X X X X X X
1 1 1 P1B X X X X X X X X
1 0 0 0 X X X X X X X X
1 0 0 1 X X X X X X X X
0
0
0
0
Shut down DAC A according to bit P1A (see Table 3).
Shut down DAC B according to bit P1B (see Table 3).
Mode 0. DOUT clocked out on SCLK falling edge (default).
Mode 1. DOUT clocked out on SCLK rising edge.
X = Don’t care.
* S0 must be zero for proper operation.
12 ______________________________________________________________________________________
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
Power-Down and Shutdown Modes
5V
As described in Tables 2 and 3, several serial interface
commands put one or both of the DACs into shutdown
mode. Shutdown modes are completely independent
for each DAC. In shutdown, the amplifier output be-
SS
comes high impedance, and OUT_ terminates to OS_
MOSI
SCK
I/O
DIN
SCLK
CS
through the 200kΩ (typ) gain resistors. Optionally (see
Tables 2 and 3), OUT_ can have an additional termina-
tion of 1kΩ to AGND.
Full power-down mode shuts down the main bias gene-
rator, reference, and both DACs. The shutdown impe-
dance of the DAC outputs can still be controlled
independently, as described in Tables 2 and 3.
SPI/QSPI
PORT
MAX5230
MAX5231
A serial interface command exits shutdown mode and
updates a DAC register. Each DAC can exit shutdown
at the same time or independently (see Tables 2 and
3). For example, if both DACs are shut down, updating
the DAC A register causes DAC A to power up, while
DAC B remains shut down. In full power-down mode,
powering up either DAC also powers up the main bias
generator and reference. To change from full power-
down to both DACs shutdown requires the waking of at
least one DAC between states.
Figure 4. SPI/QSPI Interface Connections
SK
SO
I/O
SCLK
DIN
CS
MICROWIRE
PORT
MAX5230
MAX5231
When powering up the MAX5230/MAX5231 (powering
V
), allow 400µs (max) for the output to stabilize. When
DD
exiting full power-down mode, also allow 400µs (max) for
the output to stabilize. When exiting DAC shutdown
mode, allow 160µs (max) for the output to stabilize.
Reset Value (RSTV) and
Clear (CLR) Inputs
Figure 5. Connections for MICROWIRE
Driving CLR low asynchronously forces both DAC out-
puts and all the internal registers (input registers and
DAC registers) for both DACs to either zero or midscale,
depending on the level at RSTV. RSTV = DGND sets the
Load DAC Input (LDAC)
Asserting LDAC asynchronously loads the DAC registers
from their corresponding input registers (DACs that are
shut down remain shut down). The LDAC input is totally
asynchronous and does not require any activity on CS,
SCLK, or DIN in order to take effect. If LDAC is asserted
coincident with a rising edge of CS, which executes a
serial command modifying the value of either DAC input
register, then LDAC must remain asserted for at least
30ns following the CS rising edge. This requirement
applies only for serial commands that modify the value of
the DAC input registers.
zero value, and RSTV, = V
sets the midscale value.
DD
The internal power-on reset circuit sets the DAC out-
puts and internal registers to either zero or midscale
when power is first applied to the device, depending on
the level at RSTV as described in the preceding para-
graph. The DAC outputs are enabled after power is first
applied. In order to obtain the midscale value on
power-up (RSTV = V ), the voltage on RSTV must rise
DD
simultaneously with the V
supply.
DD
Power-Down Lockout Input (PDL)
Driving PDL low disables shutdown of either DAC. When
PDL is low, serial commands to shut down either DAC are
ignored. When either DAC is in shutdown mode, a high-
to-low transition on PDL brings the DACs and the refer-
ence out of shutdown with DAC outputs set to the state
prior to shutdown.
Table 3. P1 Shutdown Modes
P1 (A/B)
SHUTDOWN MODE
0
1
Shut down with internal 1kΩ load to GND
Shut down with internal 200kΩ load to GND
______________________________________________________________________________________ 13
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
Offset Error
Applications Information
The offset error (Figure 6c) is the difference between
the ideal and the actual offset point. For a DAC, the off-
set point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated for by trimming.
Definitions
Integral Nonlinearity (INL)
Integral nonlinearity (Figure 6a) is the deviation of the val-
ues on an actual transfer function from a straight line.
This straight line can be either a best-straight-line fit
(closest approximation to the actual transfer curve) or a
line drawn between the endpoints of the transfer func-
tion, once offset and gain errors have been nullified. For
a DAC, the deviations are measured at every single step.
Gain Error
Gain error (Figure 6d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve, after nullifying the offset error. This error
alters the slope of the transfer function and corre-
sponds to the same percentage error in each step.
Differential Nonlinearity (DNL)
Differential nonlinearity (Figure 6b) is the difference
between an actual step height and the ideal value of
1LSB. If the magnitude of the DNL is less than 1LSB, the
DAC guarantees no missing codes and is monotonic.
Settling Time
The settling time is the amount of time required from the
start of a transition, until the DAC output settles to its new
output value within the converter’s specified accuracy.
7
6
6
1LSB
5
4
5
DIFFERENTIAL LINEARITY
ERROR (-1/4LSB)
4
AT STEP
011 (1/2LSB )
3
2
3
2
1
0
1LSB
DIFFERENTIAL
LINEARITY ERROR (+1/4LSB)
AT STEP
001 (1/4LSB )
1
0
000
001
010
011
100
101
000 001 010 011 100 101 110 111
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 6a. Integral Nonlinearity
Figure 6b. Differential Nonlinearity
IDEAL FULL-SCALE OUTPUT
7
6
5
ACTUAL
3
2
1
0
DIAGRAM
GAIN ERROR
(-1 1/4LSB)
IDEAL DIAGRAM
IDEAL DIAGRAM
ACTUAL
FULL-SCALE
OUTPUT
ACTUAL
OFFSET
POINT
OFFSET ERROR
(+1 1/4LSB)
4
0
IDEAL OFFSET
POINT
000 100
101
110
111
000
001
010
011
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 6d. Gain Error
Figure 6c. Offset Error
14 ______________________________________________________________________________________
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
Table 4. Unipolar Code Table
V+
DAC CONTENTS
ANALOG OUTPUT (V)
5V/3V
REF
PHOTODIODE
MSB
LSB
MAX5230
MAX5231
V
DD
OS_
1111 1111 1
1000 0000 0
1000 0000 0
0111 1111 1
0000 0000
111 (0)
001 (0)
000 (0)
111 (0)
001 (0)
000 (0)
2.04750
1.02425
1.02375
1.02325
0.00050
0
4.0950
2.0485
2.0475
2.0465
0.0010
0
REF
121kΩ
V+
V-
77.25kΩ
0000 0000 0
V
OUT
OUT_
DAC_
Digital Feedthrough
Digital feedthrough is noise generated on the DAC’s
output when any digital input transitions. Proper board
layout and grounding significantly reduce this noise,
but there is always some feedthrough caused by the
DAC itself.
MAX5230
MAX5231
1kΩ
R
PULLDOWN
AGND
DGND
Unipolar Output
Figure 7 shows the MAX5230/MAX5231 configured for
unipolar, rail-to-rail operation. The MAX5231 produces
a 0 to 4.095V output, while the MAX5230 produces 0 to
2.0475V output. Table 4 lists the unipolar output codes.
Figure 8. Digital Calibration
Digital Calibration and
Threshold Selection
Figure 8 shows the MAX5230/MAX5231 in a digital cali-
bration application. With a bright light value applied to
the photodiode (on), the DAC is digitally ramped until it
trips the comparator. The microprocessor (µP) stores
this “high” calibration value. Repeat the process with a
dim light (off) to obtain the dark current calibration. The
µP then programs the DAC to set an output voltage at
the midpoint of the two calibrated values. Applications
include tachometers, motion sensing, automatic read-
ers, and liquid clarity analysis.
5V/3V
REF
V
DD
OS_
REF
121kΩ
77.25kΩ
OUT_
DAC_
Sharing a Common DIN Line
Several MAX5230/MAX5231s may share one common
DIN signal line (Figure 9). In this configuration, the data
bus is common to all devices; data is not shifted through
a daisy-chain. The SCLK and DIN lines are shared by all
devices, but each IC needs its own dedicated CS line.
MAX5230
MAX5231
1kΩ
AGND
GAIN = 1.6384V/V
DGND
Daisy-Chaining Devices
Any number of MAX5230/MAX5231s can be daisy-
chained by connecting the serial data output (DOUT) of
one device to the digital input (DIN) of the following
device in the chain (Figure 10).
Figure 7. Unipolar Output Circuit (Rail-to-Rail)
______________________________________________________________________________________ 15
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
DIN
SCLK
CS1
CS2
CS3
TO OTHER
SERIAL DEVICES
CS
CS
CS
MAX5230
MAX5231
MAX5230
MAX5231
MAX5230
MAX5231
SCLK
DIN
SCLK
DIN
SCLK
DIN
Figure 9. Multiple MAX5230/MAX5231s Sharing a Common DIN Line
SCLK
CS
CS
CS
CS
TO OTHER
SERIAL DEVICES
MAX5230
MAX5231
MAX5230
MAX5231
MAX5230
MAX5231
SCLK
SCLK
SCLK
DIN
DIN
DIN
DOUT
DOUT
DOUT
DIN
Figure 10. Daisy-Chaining MAX5230/MAX5231 Devices
grounding techniques, such as a multilayer board with a
low-inductance ground plane or star connect all ground
return paths back to the MAX5230/MAX5231 AGND.
Carefully lay out the traces between channels to reduce
AC cross-coupling and crosstalk. Wire-wrapped boards
and sockets are not recommended. If noise becomes
an issue, shielding may be required.
Power-Supply and Bypassing
Considerations
On power-up, the input and DAC registers are cleared
to either zero (RSTV = DGND) or midscale (RSTV =
DD
V
). Bypass V
with a 4.7µF capacitor in parallel
DD
with a 0.1µF capacitor to AGND, and bypass V
with
DD
a 0.1µF capacitor to DGND. Minimize lead lengths to
reduce lead inductance.
Chip Information
TRANSISTOR COUNT: 4745
Grounding and Layout Considerations
Digital and AC transient signals on AGND or DGND can
create noise at the output. Connect AGND and DGND
to the highest quality ground available. Use proper
PROCESS: BiCMOS
16 ______________________________________________________________________________________
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
Functional Diagram
DOUT
CS DIN SCLK
V
DD
AGND
DGND
121kΩ
OSA
77.25kΩ
AMP A
OUTA
DAC A
SR
CONTROL
16-BIT
SHIFT REGISTER
PDL
1kΩ
1kΩ SHUTDOWN
LDAC
RSTV
CLR
DECODE
CONTROL
121kΩ
OSB
1
77.25kΩ
INPUT
REGISTERS
DAC
REGISTER
AMP B
OUTB
DAC B
1kΩ SHUTDOWN
2.5V (1.25V)
2X
(1X)
1.25V
BANDGAP
REFERENCE
REFERENCE
BUFFER
MAX5230
MAX5231
( ) FOR MAX5230 ONLY
REF
______________________________________________________________________________________ 17
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
1
21-0055
E
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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