MAX4718EUB [MAXIM]
4.5 з/20 з, 300MHz Bandwidth, Dual SPDT Analog Switches in UCSP; 4.5 з / 20 з ， 300MHz的带宽，双路SPDT模拟开关，UCSP封装
| 型号： | MAX4718EUB |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 4.5 з/20 з, 300MHz Bandwidth, Dual SPDT Analog Switches in UCSP |
| 文件： | 总15页 (文件大小：349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2627; Rev 0; 10/02
4.5 /20 , 300MHz Bandwidth, Dual SPDT
Analog Switches in UCSP
General Description
Features
The MAX4717/MAX4718 low-voltage, low on-resistance
ꢀ USB 1.1 Signal Switching Compliant
(R ), dual single-pole/double throw (SPDT) analog
ON
ꢀ 2ns (max) Differential Skew
switches operate from a single +1.8V to +5.5V supply.
These devices are designed for USB 1.1 and audio
switching applications.
ꢀ -3dB Bandwidth: >300MHz
ꢀ Low 15pF On-Channel Capacitance
The MAX4717 features two 4.5
switches with 1.2 flatness and 0.3 matching between
channels. The MAX4718 features one 4.5 (max)
SPDT switch and one 20 (max) SPDT switch. The
R
(max) SPDT
ꢀ Single-Supply Operation from +1.8V to +5.5V
ꢀ 4.5 (max) Switches (MAX4717/MAX4718)
0.3 (max) R
ON
R
ON
R
ON
Match (+3.0V Supply)
ON
R
ON
1.2 (max) Flatness (+3.0V Supply)
ꢀ 20 (max) Switch (MAX4718)
0.4 (max) R
20 switch has a guaranteed matching and flatness of
0.4 and 1.2 , respectively. These switches offer break-
R
ON
Match (+3.0V Supply)
ON
before-make switching (1ns) with t
<80ns and t
OFF
ON
1.2 (max) Flatness (+3.0V Supply)
<40ns at +2.7V. The digital logic inputs are +1.8V logic
compatible with a +2.7V to +3.6V supply.
®
ꢀ Rail-to-Rail Signal Handling
ꢀ High Off-Isolation: -55dB (10MHz)
ꢀ Low Crosstalk: -80dB (10MHz)
ꢀ Low Distortion: 0.03%
These switches are packaged in a chip-scale package
(UCSP™), significantly reducing the required PC board
area. The chip occupies only a 2.0mm ✕ 1.50mm area
and has a 4 ✕ 3 bump array with a bump pitch of
0.5mm. These switches are also available in a 10-pin
µMAX package.
ꢀ +1.8V CMOS-Logic Compatible
ꢀ <0.5nA Leakage Current at +25°C
Applications
Ordering Information
USB 1.1 Signal Switching Circuits
Battery-Operated Equipment
Audio/Video-Signal Routing
Headphone Switching
Low-Voltage Data-Acquisition Systems
Sample-and-Hold Circuits
Cell Phones
PIN/BUMP-
PACKAGE
TOP
MARK
PART
TEMP RANGE
MAX4717EUB
MAX4717EBC-T*
MAX4718EUB
MAX4718EBC-T*
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
10 µMAX
—
ABH
—
12 UCSP-12
10 µMAX
12 UCSP-12
ABI
Note: UCSP package requires special solder temperature pro-
file described in the Absolute Maximum Ratings section.
PDAs
*UCSP reliability is integrally linked to the user’s assembly meth-
ods, circuit board material, and environment. See the UCSP reli-
ability notice in the UCSP Reliability section of this data sheet for
more information.
UCSP is a trademark of Maxim Integrated Products, Inc.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
Pin Configurations/Functional Diagrams/Truth Tables
TOP VIEW
MAX4717/MAX4718
(BUMP SIDE DOWN)
PART
SPDT1
4.5
SPDT2
4.5
MAX4717/MAX4718
GND
MAX4717
MAX4718
C1
B1
A1
NC1
IN1
NC2
IN2
1
2
3
4
5
10 NO2
V+
NO1
4.5
20
9
COM2
C2
A2
MAX4717/MAX4718
IN2
8
7
COM1
IN1
IN_
0
NO_
OFF
ON
NC_
ON
COM1 C3
A3 COM2
NC2
GND
NO1
C4
NO2
A4
1
OFF
B4
NC1
6
SWITCHES SHOWN FOR LOGIC "0" INPUT
V+
MAX
UCSP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
4.5 /20 , 300MHz Bandwidth, Dual SPDT
Analog Switches in UCSP
ABSOLUTE MAXIMUM RATINGS
(All Voltages Referenced to GND)
ESD Method 3015.7.............................................................>2kV
V+, IN_...................................................................-0.3V to +6.0V
COM_, NO_, NC_ (Note 1) ...........................-0.3V to (V+ + 0.3V)
Continuous Current COM_, NO_, NC_ ........................... 100ꢀA
Peak Current COM_, NO_, NC_
Operating Teꢀperature Range ...........................-40°C to +85°C
Junction Teꢀperature......................................................+150°C
Storage Teꢀperature Range.............................-65°C to +150°C
Lead Teꢀperature (soldering, 10s) .................................+300°C
Buꢀp Teꢀperature (soldering) (Note 2)
(pulsed at 1ꢀs, 10% duty cycle)................................ 200ꢀA
Continuous Power Dissipation (T = +70°C)
10-Pin µMAX (derate 5.6ꢀW/°C above +70°C)...........444ꢀW
12-Buꢀp UCSP (derate 11.4ꢀW/°C above +70°C) ....909ꢀW
Infrared (15s) ...............................................................+220°C
Vapor Phase (60s) .......................................................+215°C
A
Note 1: Signals on COM_, NO_, or NC_ exceeding V+ or GND are claꢀped by internal diodes. Liꢀit forward-diode current to ꢀaxi-
ꢀuꢀ current rating.
Note 2: This device is constructed using a unique set of packaging techniques that iꢀpose a liꢀit on the therꢀal profile the device
can be exposed to during board level solder attach and rework. This liꢀit perꢀits only the use of the solder profiles recoꢀ-
ꢀended in the industry standard specification, JEDEC 020A, paragraph 7.6, table 3 for IR/VPR and convection reflow.
Preheating is required. Hand or wave soldering is not allowed.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—Single +3V Supply
(V+ = +2.7V to +3.6V, V = +1.4V, V = +0.5V, T = T
to T
, unless otherwise noted. Typical values are at V+ = +3.0V,
MAX
IH
IL
A
MIN
T
A
= +25°C, unless otherwise noted.) (Notes 3, 4)
PARAMETER
Analog Signal Range
ANALOG SWITCH (Low R —MAX4717/MAX4718 SPDT 1)
SYMBOL
CONDITIONS
T
MIN
TYP
MAX
UNITS
A
V
,
T
to
MIN
T
MAX
COM_
0
V+
V
V
, V
NO_ NC_
ON
+25°C
to
3.0
0.1
4.5
5
On-Resistance
(Note 5)
V+ = 2.7V, I
= 10ꢀA;
= 1.5V
COM_
COM_
COM_
R
ON
T
MIN
V
or V
NO_
NC_
T
MAX
+25°C
0.3
0.4
1.2
1.5
+0.5
+1
On-Resistance Match Between
Channels (Notes 5, 6)
V+ = 2.7V, I
or V
= 10ꢀA;
= 1.5V
R
ON
T
to
MIN
V
NO_
NC_
T
MAX
+25°C
0.6
On-Resistance Flatness
(Note 7)
V+ = 2.7V, I
or V
= 10ꢀA;
R
FLAT(ON)
T
to
MIN
V
= 1.0V, 1.5V, 2.0V
NC_
NO_
T
MAX
+25°C
-0.5
-1
+0.01
+0.01
NO_, NC_ Off-Leakage Current
(Note 8)
I
I
V+ = 3.6V, V
= 0.3V, 3.3V;
NO_(OFF),
COM_
nA
nA
T
to
MIN
V
or V
= 3.3V, 0.3V
NC_(OFF)
NO_
NC_
T
MAX
+25°C
T to
MIN
-1
+1
V+ = 3.6V, V
or V
= 0.3V, 3.3V;
COM_
COM_ On-Leakage Current
(Note 8)
I
V
= 0.3V, 3.3V, or
COM_(ON)
NO_
NC_
-2
+2
floating
T
MAX
ANALOG SWITCH (High R —MAX4718 SPDT 2)
ON
+25°C
to
15
20
25
V+ = 2.7V, I
= 10ꢀA;
COM_
On-Resistance (Note 5)
R
ON
T
MIN
V
or V
= 1.5V
NC_
NO_
T
MAX
2
_______________________________________________________________________________________
4.5 /20 , 300MHz Bandwidth, Dual SPDT
Analog Switches in UCSP
ELECTRICAL CHARACTERISTICS—Single +3V Supply (continued)
(V+ = +2.7V to +3.6V, V = +1.4V, V = +0.5V, T = T
to T
, unless otherwise noted. Typical values are at V+ = +3.0V,
MAX
IH
IL
A
MIN
T
A
= +25°C, unless otherwise noted.) (Notes 3, 4)
PARAMETER
SYMBOL
CONDITIONS
T
MIN
TYP
MAX
UNITS
A
+25°C
0.15
0.4
On-Resistance Match Between
Channels (Notes 5, 6)
V+ = 2.7V, I
= 10ꢀA;
= 1.5V
COM_
R
ON
T
to
MIN
V
or V
NO_
NC_
0.5
1.2
1.5
+0.5
+1
T
MAX
+25°C
0.6
On-Resistance Flatness
(Note 7)
V+ = 2.7V, I
or V
= 10ꢀA;
COM_
R
FLAT(ON)
T
to
MIN
V
= 1.0V, 1.5V, 2.0V
NC_
NO_
T
MAX
+25°C
-0.5
-1
+0.01
+0.01
NO_, NC_ Off-Leakage Current
(Note 8)
I
I
V+ = 3.6V, V
= 0.3V, 3.3V;
NO_(OFF),
COM_
nA
nA
T
to
MIN
V
or V
= 3.3V, 0.3V
NC_(OFF)
NO_
NC_
T
MAX
+25°C
-1
+1
V+ = 3.6V, V
or V
= 0.3V, 3.3V;
COM_
COM_ On-Leakage Current
(Note 8)
I
V
= 0.3V, 3.3V, or
NC_
COM_(ON)
NO_
T
MIN
to
-2
+2
floating
T
MAX
DYNAMIC CHARACTERISTICS
+25°C
to
40
20
8
80
100
40
V
, V
= 1.5V;
NO_ NC_
Turn-On Tiꢀe
t
ns
ns
ns
R = 300 , C = 35pF, Figure 1;
V
ON
L
L
T
MIN
= 1.5V, V = 0V
IL
IH
T
MAX
+25°C
V
, V
NO_ NC_
= 1.5V;
Turn-Off Tiꢀe
t
R = 300 , C = 35pF, Figure 1;
V
OFF
L
L
T
MIN
to
50
= 1.5V, V = 0V
IL
IH
T
MAX
+25°C
Break-Before-Make Tiꢀe Delay
(Note 8)
V
, V
NO_ NC_
= 1.5V;
L
t
BBM
T
to
MIN
R = 300 , C = 35pF, Figure 2
L
1
T
MAX
T
T
to
MIN
Skew (Note 8)
t
R = 39 , C = 50pF, Figure 3
0.15
5
2
ns
SKEW
S
L
MAX
V
= 1.5V, R
= 0 ,
GEN
GEN
Charge Injection
Q
+25°C
+25°C
pC
C = 1.0nF, Figure 4
L
f = 10MHz; V
, V
NO_ NC_
= 1V
;
;
P-P
-55
-80
-80
-110
R = 50 , C = 5pF, Figure 5
L
L
Off-Isolation
V
dB
dB
ISO
f = 1MHz; V
, V
NO_ NC_
= 1V
;
P-P
R = 50 , C = 5pF, Figure 5
L
L
f = 10MHz; V
, V
= 1V
NO_ NC_ P-P
R = 50 , C = 5pF, Figure 5
L
L
Crosstalk (Note 9)
V
+25°C
CT
f = 1MHz; V
, V
NO_ NC_
= 1V
;
P-P
R = 50 , C = 5pF, Figure 5
L
L
Signal = 0dBꢀ, R = 50 ,
C = 5pF, Figure 5
L
L
On-Channel -3dB Bandwidth
Total Harꢀonic Distortion
NO_, NC_ Off-Capacitance
BW
+25°C
+25°C
+25°C
>300
0.03
9
MHz
%
THD
V
= 2V , R = 600
COM P-P L
C
C
NO_(OFF),
f = 1MHz, Figure 6
pF
NC_(OFF)
_______________________________________________________________________________________
3
4.5 /20 , 300MHz Bandwidth, Dual SPDT
Analog Switches in UCSP
ELECTRICAL CHARACTERISTICS—Single +3V Supply (continued)
(V+ = +2.7V to +3.6V, V = +1.4V, V = +0.5V, T = T
to T
, unless otherwise noted. Typical values are at V+ = +3.0V,
MAX
IH
IL
A
MIN
T
A
= +25°C, unless otherwise noted.) (Notes 3, 4)
PARAMETER
SYMBOL
CONDITIONS
f = 1MHz, Figure 6
T
MIN
TYP
MAX
UNITS
A
Switch On-Capacitance
C
+25°C
15
pF
(ON)
DIGITAL I/O
T
T
to
MAX
MIN
Input Logic High Voltage
Input Logic Low Voltage
V
1.4
V
V
IH
T
T
to
MAX
MIN
V
0.5
IL
T
T
to
MAX
MIN
Input Leakage Current
POWER SUPPLY
I
V+ = +3.6V, V
V+ = +5.5V, V
= 0 or 5.5V
= 0V or V+
-100
1.8
+100
nA
IN
IN_
IN_
T
T
to
MIN
Power-Supply Range
V+
I+
5.5
1
V
MAX
T
T
to
MIN
Supply Current
µA
MAX
ELECTRICAL CHARACTERISTICS—Single +5V Supply
(V+ = +4.2V to +5.5V, V = +2.0V, V = +0.8V, T = T
to T
, unless otherwise noted. Typical values are at V+ = +5.0V,
MAX
IH
IL
A
MIN
T
A
= +25°C, unless otherwise noted.) (Notes 3, 4)
PARAMETER
Analog Signal Range
ANALOG SWITCH (Low R —MAX4717/MAX4718 SPDT 1)
SYMBOL
CONDITIONS
T
MIN
TYP
MAX
UNITS
A
V
,
T
to
MIN
T
MAX
COM_
0
V+
V
V
, V
NO_ NC_
ON
+25°C
to
1.7
0.1
3
3.5
0.3
0.4
1.2
1.5
+0.5
+1
V+ = 4.2V, I
= 10ꢀA;
= 3.5V
COM_
COM_
COM_
On-Resistance (Note 5)
R
ON
T
MIN
V
or V
NO_
NC_
T
MAX
+25°C
On-Resistance Match Between
Channels (Notes 5, 6)
V+ = 4.2V, I
or V
= 10ꢀA;
= 3.5V
R
ON
T
to
MIN
V
NO_
NC_
T
MAX
+25°C
0.4
On-Resistance Flatness
(Note 7)
V+ = 4.2V, I
or V
= 10ꢀA;
R
FLAT(ON)
T
to
MIN
V
= 1.0V, 2.0V, 3.5V
NC_
NO_
T
MAX
+25°C
-0.5
-1
+0.01
+0.01
NO_, NC_ Off-Leakage Current
(Note 8)
I
I
V+ = 5.5V; V
= 1.0V, 4.5V;
NO_(OFF),
COM_
nA
nA
T
to
MIN
V
or V
= 1.0V, 4.5V
NC_(OFF)
NO_
NC_
T
MAX
+25°C
T to
MIN
-1
+1
V+ = 5.5V; V
or V
= 1.0V, 4.5V;
COM_
COM_ On-Leakage Current
(Note 8)
I
V
= 1.0V, 4.5V, or
COM_(ON)
NO_
NC_
-2
+2
floating
T
MAX
4
_______________________________________________________________________________________
4.5 /20 , 300MHz Bandwidth, Dual SPDT
Analog Switches in UCSP
ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)
(V+ = +4.2V to +5.5V, V = +2.0V, V = +0.8V, T = T
to T
, unless otherwise noted. Typical values are at V+ = +5.0V,
MAX
IH
IL
A
MIN
T
A
= +25°C, unless otherwise noted.) (Notes 3, 4)
PARAMETER
SYMBOL
CONDITIONS
T
MIN
TYP
MAX
UNITS
A
ANALOG SWITCH (High R —MAX4718 SPDT 2)
ON
+25°C
to
12
20
25
V+ = 4.2V, I
= 10ꢀA;
= 3.5V
COM_
COM_
COM_
On-Resistance (Note 5)
R
ON
T
MIN
V
or V
NO_
NC_
T
MAX
+25°C
0.15
0.4
0.4
0.5
1.2
1.5
+0.5
+1
On-Resistance Match Between
Channels (Notes 5, 6)
V+ = 4.2V, I
or V
= 10ꢀA;
= 3.5V
R
ON
T
to
MIN
V
NO_
NC_
T
MAX
+25°C
On-Resistance Flatness
(Note 7)
V+ = 4.2V, I
or V
= 10ꢀA;
R
FLAT(ON)
T
to
MIN
V
= 1.0V, 2.0V, 4.5V
NC_
NO_
T
MAX
+25°C
-0.5
-1
+0.01
+0.01
NO_, NC_ Off-Leakage Current
(Note 8)
I
I
V+ = 5.5V; V
= 1.0V, 4.5V;
COM_
NO_(OFF),
nA
nA
T
to
MIN
V
or V
= 1.0V, 4.5V
NC_
NC_(OFF)
NO_
T
MAX
+25°C
-1
+1
V+ = 5.5V, V
= 1.0V, 4.5V;
COM_
COM_ On-Leakage Current
(Note 8)
I
V
or V
= 1.0V, 4.5V, or
NC_
COM_(ON)
NO_
T
MIN
to
-2
+2
floating
T
MAX
DYNAMIC CHARACTERISTICS
+25°C
to
30
20
8
80
100
40
V
, V
= 3.0V;
NO_ NC_
Turn-On Tiꢀe
t
ns
ns
ON
T
MIN
R = 300 , C = 35pF, Figure 1
L
L
T
MAX
+25°C
V
, V
NO_ NC_
= 3.0V;
Turn-Off Tiꢀe
t
OFF
T
MIN
to
R = 300 , C = 35pF, Figure 1
L
L
50
T
MAX
+25°C
Break-Before-Make Tiꢀe Delay
(Note 8)
V
, V
NO_ NC_
= 3.0V;
L
t
ns
ns
BBM
T
MIN
to
R = 300 , C = 35pF, Figure 2
L
1
T
MAX
T
to
MIN
Skew (Note 8)
t
R = 39 , C = 50pF, Figure 3
0.15
2
SKEW
S
L
T
MAX
DIGITAL I/O
T
T
to
MAX
MIN
MIN
MIN
Input Logic High Voltage
V
2.0
V
V
IH
T
T
to
MAX
Input Logic Low Voltage
Input Leakage Current
V
0.8
IL
T
T
to
I
IN
V+ = 5.5V, V _ = 0V or V+
-100
+100
nA
IN
MAX
_______________________________________________________________________________________
5
4.5 /20 , 300MHz Bandwidth, Dual SPDT
Analog Switches in UCSP
ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)
(V+ = +4.2V to +5.5V, V = +2.0V, V = +0.8V, T = T
to T
, unless otherwise noted. Typical values are at V+ = +5.0V,
MAX
IH
IL
A
MIN
T
A
= +25°C, unless otherwise noted.) (Notes 3, 4)
PARAMETER
SYMBOL
CONDITIONS
T
MIN
TYP
MAX
UNITS
A
POWER SUPPLY
T
T
to
MAX
MIN
MIN
Power-Supply Range
V+
I+
1.8
5.5
1
V
T
T
to
MAX
Supply Current
V+ = 5.5V, V
= 0V or V+
µA
IN_
Note 3: UCSP parts are 100% tested at +25°C only, and guaranteed by design over the specified teꢀperature range. µMAX parts
are 100% tested at T and guaranteed by design over the specified teꢀperature range.
MAX
Note 4: The algebraic convention used in this data sheet is where the ꢀost negative value is a ꢀiniꢀuꢀ and the ꢀost positive
value is a ꢀaxiꢀuꢀ.
Note 5: Guaranteed by design for UCSP parts.
Note 6:
R
ON
= R
- R
.
ON(MAX)
ON(MIN)
Note 7: Flatness is defined as the difference between the ꢀaxiꢀuꢀ and ꢀiniꢀuꢀ value of on-resistance as ꢀeasured over the
specified analog signal ranges.
Note 8: Guaranteed by design.
Note 9: Between any two switches.
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
ON-RESISTANCE vs. V
ON-RESISTANCE vs. V
ON-RESISTANCE vs. V
COM
COM
COM
10
8
6
5
4
3
2
1
5
4
3
2
1
0
LOW R SWITCH
V+ = 5V
LOW R SWITCH
V+ = 3V
LOW R SWITCH
ON
ON
ON
V+ = 1.8V
V+ = 2.5V
6
T
= +85 C
A
T
= +85 C
T
= +25 C
A
A
T
= +25 C
A
V+ = 3V
4
V+ = 4.2V
V+ = 5V
2
T = -40 C
A
T
= -40 C
A
0
0
1
2
3
4
5
0
0.5
1.0
1.5
2.0
(V)
2.5
3.0
0
1
2
3
(V)
4
5
V
(V)
V
V
COM
COM
COM
6
_______________________________________________________________________________________
4.5 /20 , 300MHz Bandwidth, Dual SPDT
Analog Switches in UCSP
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
ON-RESISTANCE vs. V
ON-RESISTANCE vs. V
ON-RESISTANCE vs. V
COM
COM
COM
T = +85 C
A
20
18
16
14
12
10
15
14
13
12
11
10
15
14
13
12
11
10
HIGH R SWITCH
ON
V+ = 5V
HIGH R SWITCH
V+ = 3V
HIGH R SWITCH
V+ = 1.8V
ON
ON
T
= +85 C
A
V+ = 2.5V
V+ = 4.2V
V+ = 5V
T
= -40 C
A
T
= +25 C
1.0
A
T
= +25 C
A
T
= -40 C
A
0
1
2
3
4
5
0
0.5
1.5
2.0
2.5
3.0
0
1
2
3
4
5
V
(V)
V
(V)
V
(V)
COM
COM
COM
LEAKAGE CURRENT vs. TEMPERATURE
LEAKAGE CURRENT vs. TEMPERATURE
LEAKAGE CURRENT vs. TEMPERATURE
500
400
300
200
100
0
1000
800
600
400
200
0
700
500
300
100
-100
V+ = 3V
V+ = 3V
V+ = 5V
LOW R SWITCH
HIGH R SWITCH
LOW R SWITCH
ON
ON
ON
COM ON-LEAKAGE
COM ON-LEAKAGE
COM OFF-LEAKAGE
COM ON-LEAKAGE
COM OFF-LEAKAGE
COM OFF-LEAKAGE
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE ( C)
TEMPERATURE ( C)
TEMPERATURE ( C)
LEAKAGE CURRENT vs. TEMPERATURE
CHARGE INJECTION vs. V
SUPPLY CURRENT vs. TEMPERATURE
COM
900
700
500
300
100
50
40
30
20
10
0
6
5
4
3
2
1
0
V+ = 5V
HIGH R SWITCH
ON
C = 1nF
L
V+ = 5V
COM ON-LEAKAGE
V+ = 5V
C = 1nF
L
V+ = 3V
COM OFF-LEAKAGE
V+ = 3V
-100
-40
-15
10
35
60
85
0
1
2
3
4
5
-40
-15
10
35
60
85
TEMPERATURE ( C)
V
(V)
TEMPERATURE ( C)
COM
_______________________________________________________________________________________
7
4.5 /20 , 300MHz Bandwidth, Dual SPDT
Analog Switches in UCSP
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
TURN-ON/OFF TIME
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. LOGIC LEVEL
LOGIC THRESHOLD vs. SUPPLY VOLTAGE
100
2.0
1.6
1.2
0.8
0.4
0
100
80
60
40
20
0
LOW R SWITCH
ON
80
V
TH+
V+ = 5V
60
40
V
t
TH-
ON
t
OFF
V+ = 3V
20
0
0
1
2
3
4
5
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
1.5
2.5
3.5
4.5
5.5
LOGIC LEVEL (V)
SUPPLY VOLTAGE (V)
TURN-ON/OFF TIME
vs. SUPPLY VOLTAGE
TURN-ON/OFF TIME
vs. TEMPERATURE
TURN-ON/OFF TIME
vs. TEMPERATURE
100
80
60
40
20
0
60
50
40
30
60
50
HIGH R SWITCH
ON
LOW R SWITCH
HIGH R SWITCH
ON
ON
t
, V+ = 3.0V
ON
t
, V+ = 3.0V
ON
t
, V+ = 5.0V
ON
t
, V+ = 5.0V
ON
40
30
20
10
0
t
ON
20
10
0
t
, V+ = 5.0V
t
OFF
OFF
t
, V+ = 5.0V
t
, V+ = 3.0V
-15
OFF
OFF
t
, V+ = 3.0V
OFF
1.5
2.5
3.5
4.5
5.5
-40
-15
10
35
60
85
-40
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE ( C)
TEMPERATURE ( C)
RISE/FALL-TIME DELAY
vs. TEMPERATURE
RISE TIME TO FALL TIME MISMATCH
vs. SUPPLY VOLTAGE
RISE/FALL-TIME DELAY
vs. SUPPLY VOLTAGE
3.0
2.5
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
400
300
200
100
0
INPUT RISE/FALL TIME = 15ns
INPUT RISE/FALL TIME = 15ns
INPUT RISE/FALL TIME = 15ns
FIGURE 4, C = 50pF
FIGURE 4, C = 50pF
FIGURE 4, C = 50pF
L
L
L
V+ = 4.2V
LOW R SWITCH
ON
LOW R SWITCH
ON
LOW R SWITCH
ON
RISE DELAY
RISE DELAY
FALL DELAY
FALL DELAY
1.5
2.5
3.5
4.5
5.5
-40
-15
10
35
60
85
1.5
2.5
3.5
4.5
5.5
SUPPLY VOLTAGE (V)
TEMPERATURE ( C)
SUPPLY VOLTAGE (V)
8
_______________________________________________________________________________________
4.5 /20 , 300MHz Bandwidth, Dual SPDT
Analog Switches in UCSP
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
RISE TIME TO FALL TIME MISMATCH
vs. TEMPERATURE
SKEW vs. SUPPLY VOLTAGE
SKEW vs. TEMPERATURE
200
150
100
50
400
300
200
100
0
200
150
100
50
INPUT RISE/FALL TIME = 15ns
INPUT RISE/FALL TIME = 15ns
INPUT RISE/FALL TIME = 15ns
FIGURE 4, C = 50pF
L
FIGURE 4, C = 50pF
FIGURE 4, C = 50pF
L
L
V+ = 4.2V
MAX4717 ONLY
V+ = 4.2V
LOW R SWITCH
ON
MAX4717 ONLY
0
0
-40
-15
10
35
60
85
1.5
2.5
3.5
4.5
5.5
-40
-15
10
35
60
85
TEMPERATURE ( C)
SUPPLY VOLTAGE (V)
TEMPERATURE ( C)
FREQUENCY RESPONSE
FREQUENCY RESPONSE
20
0
20
0
LOW R SWITCH
ON
V+ = 3V/5V
HIGH R SWITCH
V+ = 3V/5V
ON
-20
-40
-60
-80
-100
-120
-140
-20
-40
ON-LOSS
ON-LOSS
-60
OFF-ISOLATION
OFF-ISOLATION
-80
-100
-120
-140
CROSSTALK
100
CROSSTALK
100
0.0001
0.01
1
0.0001
0.01
1
FREQUENCY (MHz)
FREQUENCY (MHz)
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
1
1
V+ = 3V
V+ = 3V
HIGH R SWITCH
LOW R SWITCH
ON
ON
R = 600
L
R = 600
L
0.1
0.1
0.01
0.01
10
100
1k
FREQUENCY (Hz)
10k
100k
10
100
1k
FREQUENCY (Hz)
10k
100k
_______________________________________________________________________________________
9
4.5 /20 , 300MHz Bandwidth, Dual SPDT
Analog Switches in UCSP
+5V supply voltage, the logic thresholds are 0.8V (low)
and 2.0V (high).
Pin Description
PIN
NAME
NC2
FUNCTION
Analog Signal Levels
UCSP µMAX
The on-resistance of the MAX4717/MAX4718 changes
very little for analog input signals across the entire supply
voltage range (see the Typical Operating Characteristics).
The switches are bidirectional, so the NO_, NC_, and
COM_ pins can be either inputs or outputs.
Analog Switch 2—Norꢀally Closed
Terꢀinal
A1
A2
A3
A4
7
8
Digital Control Input for Analog
Switch 2
IN2
Power-Supply Sequencing and
Overvoltage Protection
Caution: Do not exceed the absolute maximum rat-
ings because stresses beyond the listed ratings
may cause permanent damage to the device.
Analog Switch 2—Coꢀꢀon
Terꢀinal
9
COM2
NO2
Analog Switch 2—Norꢀally Open
Terꢀinal
10
B1
B4
6
1
GND Ground
Proper power-supply sequencing is recoꢀꢀended for
all CMOS devices. Always apply V+ before applying
analog signals, especially if the analog signal is not
current-liꢀited.
V+
Positive-Supply Voltage Input
Analog Switch 1—Norꢀally Closed
Terꢀinal
C1
C2
C3
C4
5
4
3
2
NC1
Digital Control Input for Analog
Switch 1
UCSP Package Considerations
For general UCSP package inforꢀation and PC layout
considerations, please refer to the Maxiꢀ Application
Note (Wafer-Level Chip-Scale Package).
IN1
COM1
NO1
Analog Switch 1—Coꢀꢀon
Terꢀinal
UCSP Reliability
The chip-scale package (UCSP) represents a unique
packaging forꢀ factor that ꢀay not perforꢀ equally to a
packaged product through traditional ꢀechanical relia-
bility tests. UCSP reliability is integrally linked to the
user’s asseꢀbly ꢀethods, circuit board ꢀaterial, and
usage environꢀent. The user should closely review
these areas when considering use of a UCSP package.
Perforꢀance through Operating Life Test and Moisture
Resistance reꢀains uncoꢀproꢀised as it is priꢀarily
deterꢀined by the wafer-fabrication process.
Analog Switch 1—Norꢀally Open
Terꢀinal
Detailed Description
The MAX4717/MAX4718 high-speed, low-voltage, low on-
resistance (R ), dual SPDT analog switches operate
ON
froꢀ a single +1.8V to +5.5V supply. The switches feature
break-before-ꢀake switching operation and fast switch-
ing speeds (t
= 80ns (ꢀax), t
= 40ns (ꢀax)).
ON
OFF
These switches have low 15pF on-channel capaci-
tance, which allows for 12Mbps switching of the data
signals for USB 1.0/1.1 applications. The MAX4717 is
designed to switch D+ and D- USB signals with a guar-
anteed skew of less than 2ns (see Figure 4) as ꢀea-
sured froꢀ 50% of the input signal to 50% of the output
signal.
Mechanical stress perforꢀance is a greater considera-
tion for a UCSP package. UCSPs are attached through
direct solder contact to the user’s PC board, foregoing
the inherent stress relief of a packaged product lead
fraꢀe. Solder joint contact integrity ꢀust be consid-
ered. Inforꢀation on Maxiꢀ’s qualification plan, test
data, and recoꢀꢀendations are detailed in the UCSP
application note, which can be found on Maxiꢀ’s web-
site at www.ꢀaxiꢀ-ic.coꢀ.
Applications Information
Digital Control Inputs
The MAX4717/MAX4718 logic inputs accept up to
+5.5V regardless of supply voltage. For exaꢀple, with
a +3.3V supply, IN_ can be driven low to GND and high
to +5.5V allowing for ꢀixing of logic levels in a systeꢀ.
Driving the control logic inputs rail-to-rail ꢀiniꢀizes
power consuꢀption. For a +3V supply voltage, the
logic thresholds are 0.5V (low) and 1.4V (high); for a
Chip Information
TRANSISTOR COUNT: 235
PROCESS: BiCMOS
10 ______________________________________________________________________________________
4.5 /20 , 300MHz Bandwidth, Dual SPDT
Analog Switches in UCSP
Test Circuits/Timing Diagrams
MAX4717/
MAX4718
V+
t < 5ns
t < 5ns
f
r
V
IH
LOGIC
INPUT
50%
V+
COM_
V
IL
NO_
V
N_
V
OUT
OR NC_
t
OFF
R
L
C
L
IN_
V
OUT
0.9 x V
0.9 x V
OUT
0UT
GND
LOGIC
INPUT
SWITCH
OUTPUT
0V
t
ON
C INCLUDES FIXTURE AND STRAY CAPACITANCE.
L
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
R
L
V
OUT
= V
N_
(
)
ON
R + R
L
Figure 1. Switching Time
V+
V+
MAX4717/
MAX4718
V
V
IH
LOGIC
INPUT
50%
IL
NC_
NO_
V
V
OUT
N_
COM_
R
L
300
C
L
35pF
IN_
LOGIC
INPUT
GND
0.9 x V
OUT
V
OUT
t
BBM
C INCLUDES FIXTURE AND STRAY CAPACITANCE.
L
Figure 2. Break-Before-Make Interval
______________________________________________________________________________________ 11
4.5 /20 , 300MHz Bandwidth, Dual SPDT
Analog Switches in UCSP
Test Circuits/Timing Diagrams (continued)
RISE TIME DELAY = |t
- t
|
INRISE OUTRISE
MAX4717
NC1 OR
NO1
R
R
S
S
FALL TIME DELAY = |t
- t
|
INFALL OUTFALL
COM1
COM2
IN+
IN-
OUT+
OUT-
RISE TIME TO FALL TIME MISMATCH = |t
- t
|
OUTFALL OUTRISE
C
C
L
L
NC2 OR
NO2
IN1
IN2
V
TO V
IH
IL
t
INFALL
t
INRISE
10%
V+
90%
90%
V
IN+
50%
10%
0V
V+
V
50%
IN-
0V
V+
t
OUTFALL
t
OUTRISE
90%
90%
V
OUT+
50%
10%
10%
0V
V+
50%
V
OUT-
0V
t
SKEW
Figure 3. Output Signal Skew
12 ______________________________________________________________________________________
4.5 /20 , 300MHz Bandwidth, Dual SPDT
Analog Switches in UCSP
Test Circuits/Timing Diagrams (continued)
V+
V
OUT
MAX4717/
MAX4718
V+
V
OUT
R
GEN
NC_
COM_
V
OUT
IN
OR NO_
OFF
OFF
OFF
OFF
C
L
ON
ON
V
GEN
GND
IN_
V
TO V
IH
IL
IN
Q = (
V
)(C )
OUT L
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
Figure 4. Charge Injection
+5V 10nF
V+
V
V
OUT
OFF-ISOLATION = 20log
ON-LOSS = 20log
V
IN
NETWORK
ANALYZER
50
50
OUT
V
V
0V OR V+
IN
IN_
V
IN
COM1
V
OUT
MAX4717/
MAX4718
CROSSTALK = 20log
NC1
V
IN
MEAS
50
REF
OUT
NO1*
50
GND
50
*FOR CROSSTALK THIS PIN IS NO2.
NC2 AND COM2 ARE OPEN.
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN COM_ AND "OFF" NO_ OR NC_ TERMINAL ON EACH SWITCH.
ON-LOSS IS MEASURED BETWEEN COM_ AND "ON" NO_ OR NC_ TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
Figure 5. On-Loss, Off-Isolation, and Crosstalk
V+
V+
10nF
COM_
MAX4717/
MAX4718
IN
V
OR V
IH
IL
CAPACITANCE
METER
NC_ or
NO_
f = 1MHz
GND
Figure 6. Channel Off/On-Capacitance
______________________________________________________________________________________ 13
4.5 /20 , 300MHz Bandwidth, Dual SPDT
Analog Switches in UCSP
Package Information
(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation,
go to www.maxim-ic.com/packages.)
14 ______________________________________________________________________________________
4.5 /20 , 300MHz Bandwidth, Dual SPDT
Analog Switches in UCSP
Package Information (continued)
(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation,
go to www.maxim-ic.com/packages.)
e
4X S
10
10
INCHES
MAX
MILLIMETERS
MAX
1.10
0.15
0.95
3.05
3.00
3.05
3.00
5.05
0.70
DIM MIN
MIN
-
A
-
0.043
0.006
0.037
0.120
0.118
0.120
0.118
0.199
A1
A2
D1
D2
E1
E2
H
0.002
0.030
0.116
0.114
0.116
0.114
0.187
0.05
0.75
2.95
2.89
2.95
2.89
4.75
0.40
H
ÿ 0.50±0.1
0.6±0.1
L
0.0157 0.0275
0.037 REF
L1
b
0.940 REF
0.007
0.0106
0.177
0.270
0.200
1
1
e
0.0197 BSC
0.500 BSC
0.6±0.1
c
0.0035 0.0078
0.0196 REF
0.090
BOTTOM VIEW
0.498 REF
S
TOP VIEW
0∞
6∞
0∞
6∞
D2
E2
GAGE PLANE
A2
c
A
E1
b
L
A1
D1
L1
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0061
I
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2002 Maxiꢀ Integrated Products
Printed USA
is a registered tradeꢀark of Maxiꢀ Integrated Products.
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