MAX4719EUB+ [MAXIM]
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| 型号： | MAX4719EUB+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 暂无描述 开关 光电二极管 |
| 文件： | 总11页 (文件大小：282K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2626; Rev 0; 10/02
20 , 300MHz Bandwidth, Dual SPDT Analog
Switch in UCSP
General Description
Features
The MAX4719 low-voltage, low on-resistance (R ),
ON
ꢀ -3dB Bandwidth: >300MHz
dual single-pole/double throw (SPDT) analog switch
operates from a single +1.8V to +5.5V supply. The
ꢀ Low 15pF On-Channel Capacitance
MAX4719 features 20
and 0.4 matching between channels. The switch offers
break-before-make switching (1ns) with t <80ns and
R
(max) with 1.2 flatness
ꢀ Single-Supply Operation from +1.8V to +5.5V
ON
ꢀ 20
R
ON
(max) Switch
ON
0.4 (max) R
1.2 (max) R
Match (+3.0V Supply)
Flatness (+3.0V Supply)
ON
ON
t
<40ns at +2.7V. The digital logic inputs are +1.8V
logic compatible with a +2.7V to +3.6V supply.
OFF
®
ꢀ Rail-to-Rail Signal Handling
ꢀ High Off-Isolation: -55dB (10MHz)
ꢀ Low Crosstalk: -80dB (10MHz)
ꢀ Low Distortion: 0.03%
The switch is packaged in a chip-scale package
(UCSP™), significantly reducing the required PC board
area. The chip occupies only a 2.0mm ✕ 1.50mm area
and has a 4 ✕ 3 bump array with a bump pitch of
0.5mm. The MAX4719 is also available in a 10-pin
µMAX package.
ꢀ +1.8V CMOS-Logic Compatible
ꢀ <0.5nA Leakage Current at +25°C
Applications
Cell Phones
Battery-Operated Equipment
Audio/Video-Signal Routing
Low-Voltage Data-Acquisition Systems
Sample-and-Hold Circuits
PDAs
Ordering Information
PIN/BUMP-
PACKAGE
TOP
MARK
PART
TEMP RANGE
MAX4719EUB
-40°C to +85°C
-40°C to +85°C
10 µMAX
—
MAX4719EBC-T*
12 UCSP-12
ABJ
Note: UCSP package requires special solder temperature pro-
file described in the Absolute Maximum Ratings section.
*UCSP reliability is integrally linked to the user’s assembly meth-
ods, circuit board material, and environment. See the UCSP reli-
ability notice in the UCSP Reliability section of this data sheet for
more information.
UCSP is a trademark of Maxim Integrated Products, Inc.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
Pin Configurations/Functional Diagrams/Truth Table
TOP VIEW
MAX4719
GND
(BUMP SIDE
DOWN)
MAX4719
MAX4719
C1
C2
B1
A1
NC1
IN1
NC2
IN2
1
2
3
4
5
10
9
NO2
COM2
IN2
V+
NO1
IN_
0
NO_
OFF
ON
NC_
ON
A2
1
OFF
8
7
COM1
IN1
COM1 C3
A3 COM2
SWITCHES SHOWN FOR LOGIC "0" INPUT
NC2
GND
NO1
NO2
C4
B4
A4
NC1
6
V+
UCSP
MAX
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
20 , 300MHz Bandwidth, Dual SPDT Analog
Switch in UCSP
ABSOLUTE MAXIMUM RATINGS
(All Voltages Referenced to GND)
ESD Method 3015.7 ...............................................................2kV
Operating Teꢀperature Range ...........................-40°C to +85°C
Junction Teꢀperature......................................................+150°C
Storage Teꢀperature Range.............................-65°C to +150°C
Lead Teꢀperature (soldering, 10s) .................................+300°C
Buꢀp Teꢀperature (soldering) (Note 2)
V+, IN_...................................................................-0.3V to +6.0V
COM_, NO_, NC_ (Note 1) ...........................-0.3V to (V+ + 0.3V)
Continuous Current COM_, NO_, NC_ ........................... 100ꢀA
Peak Current COM_, NO_, NC_
(pulsed at 1ꢀs, 10% duty cycle)................................ 200ꢀA
Continuous Power Dissipation (T = +70°C)
10-Pin µMAX (derate 5.6ꢀW/°C above +70°C)...........444ꢀW
12-Buꢀp UCSP (derate 11.4ꢀW/°C above +70°C) ....909ꢀW
Infrared (15s) ...............................................................+220°C
Vapor Phase (60s) .......................................................+215°C
A
Note 1: Signals on COM_, NO_, or NC_ exceeding V+ or GND are claꢀped by internal diodes. Liꢀit forward-diode current to ꢀaxi-
ꢀuꢀ current rating.
Note 2: This device is constructed using a unique set of packaging techniques that iꢀpose a liꢀit on the therꢀal profile the device
can be exposed to during board level solder attach and rework. This liꢀit perꢀits only the use of the solder profiles recoꢀ-
ꢀended in the industry standard specification, JEDEC 020A, paragraph 7.6, table 3 for IR/VPR and convection reflow.
Preheating is required. Hand or wave soldering is not allowed.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—Single +3V Supply
(V+ = +2.7V to +3.6V, V = +1.4V, V = +0.5V, T = T
to T
, unless otherwise noted. Typical values are at V+ = +3.0V,
MAX
IH
IL
A
MIN
T
A
= +25°C, unless otherwise noted.) (Notes 3, 4)
PARAMETER
SYMBOL
CONDITIONS
T
MIN
TYP
MAX
UNITS
A
V
,
T
to
MIN
COM_
, V
Analog Signal Range
0
V+
V
V
T
MAX
NO_ NC_
ANALOG SWITCH
+25°C
to
14
20
25
V+ = 2.7V, I
= 10ꢀA;
= 1.5V
COM_
COM_
COM_
On-Resistance (Note 5)
R
ON
T
MIN
V
or V
NO_
NC_
T
MAX
+25°C
0.15
0.6
0.4
0.5
1.2
1.5
+0.5
+1
On-Resistance Match Between
Channels (Notes 5, 6)
V+ = 2.7V, I
or V
= 10ꢀA;
= 1.5V
R
ON
T
to
MIN
V
NO_
NC_
T
MAX
+25°C
On-Resistance Flatness
(Note 7)
V+ = 2.7V, I
or V
= 10ꢀA;
R
FLAT(ON)
T
to
MIN
V
= 1.0V, 1.5V, 2.0V
NC_
NO_
T
MAX
+25°C
-0.5
-1
0.01
0.01
NO_, NC_ Off-Leakage Current
(Note 8)
I
I
V+ = 3.6V, V
= 0.3V, 3.3V;
NO_(OFF),
COM_
nA
nA
T
to
MIN
V
or V
= 3.3V, 0.3V
NC_(OFF)
NO_
NC_
T
MAX
+25°C
T to
MIN
-1
+1
V+ = 3.6V, V
or V
= 0.3V, 3.3V;
COM_
COM_ On-Leakage Current
(Note 8)
I
V
= 0.3V, 3.3V, or
COM_(ON)
NO_
NC_
-2
+2
floating
T
MAX
DYNAMIC CHARACTERISTICS
+25°C
to
40
80
V
, V
= 1.5V;
L
NO_ NC_
Turn-On Tiꢀe
t
ns
ON
T
MIN
R = 300 , C = 35pF, Figure 1
L
100
T
MAX
2
_______________________________________________________________________________________
20 , 300MHz Bandwidth, Dual SPDT Analog
Switch in UCSP
ELECTRICAL CHARACTERISTICS—Single +3V Supply (continued)
(V+ = +2.7V to +3.6V, V = +1.4V, V = +0.5V, T = T
to T
, unless otherwise noted. Typical values are at V+ = +3.0V,
MAX
IH
IL
A
MIN
T
A
= +25°C, unless otherwise noted.) (Notes 3, 4)
PARAMETER
SYMBOL
CONDITIONS
, V = 1.5V;
T
MIN
TYP
MAX
UNITS
A
+25°C
20
40
V
NO_ NC_
Turn-Off Tiꢀe
t
ns
OFF
T
to
MIN
R = 300 , C = 35pF, Figure 1
L
L
50
T
MAX
+25°C
8
Break-Before-Make Tiꢀe Delay
(Note 8)
V
, V
= 1.5V;
L
NO_ NC_
t
ns
BBM
Q
T
to
MIN
R = 300 , C = 35pF, Figure 2
L
1
T
MAX
V
= 2V, R
= 0 ;
GEN
GEN
Charge Injection
Off-Isolation
+25°C
+25°C
18
-55
-80
-80
-110
pC
C = 1.0nF, Figure 3
L
f = 10MHz; V
R = 50 , C = 5pF, Figure 4
, V
NO_ NC_
L
= 1V
;
;
P-P
L
V
dB
dB
ISO
f = 1MHz; V
R = 50 , C = 5pF, Figure 4
, V
NO_ NC_
L
= 1V
;
P-P
L
f = 10MHz; V
R = 50 , C = 5pF, Figure 4
, V
= 1V
NO_ NC_ P-P
L
L
Crosstalk (Note 9)
V
+25°C
CT
f = 1MHz; V
R = 50 , C = 5pF, Figure 4
, V
NO_ NC_
L
= 1V
;
P-P
L
Signal = 0dBꢀ, R = 50 ;
C = 5pF, Figure 4
L
L
On-Channel -3dB Bandwidth
Total Harꢀonic Distortion
NO_, NC_ Off-Capacitance
BW
+25°C
+25°C
+25°C
+25°C
300
0.03
9
MHz
%
THD
V
= 2V , R = 600
COM P-P L
C
C
NO_(OFF)
NC_(OFF)
f = 1MHz, Figure 5
f = 1MHz, Figure 5
pF
Switch On-Capacitance
C
20
pF
ON
DIGITAL I/O
T
T
to
MAX
MIN
Input Logic High Voltage
Input Logic Low Voltage
V
1.4
V
V
IH
T
T
to
MAX
MIN
V
0.5
IL
T
T
to
MAX
MIN
Input Leakage Current
POWER SUPPLY
I
V+ = +3.6V, V
V+ = +5.5V, V
= 0V or 5.5V
= 0V or V+
-100
1.8
+100
nA
IN
IN_
IN_
T
T
to
MAX
MIN
Power-Supply Range
V+
I+
5.5
1
V
T
T
to
MAX
MIN
Supply Current
µA
_______________________________________________________________________________________
3
20 , 300MHz Bandwidth, Dual SPDT Analog
Switch in UCSP
ELECTRICAL CHARACTERISTICS—Single +5V Supply
(V+ = +4.2V to +5.5V, V = +2.0V, V = +0.8V, T = T
to T
, unless otherwise noted. Typical values are at V+ = +5.0V,
MAX
IH
IL
A
MIN
T
A
= +25°C, unless otherwise noted.) (Notes 3, 4)
PARAMETER
SYMBOL
CONDITIONS
T
MIN
TYP
MAX
UNITS
A
V
,
T
to
MIN
COM_
, V
Analog Signal Range
0
V+
V
V
T
MAX
NO_ NC_
ANALOG SWITCH
+25°C
T to
MIN
12
20
25
V+ = 4.2V, I
= 10ꢀA;
= 3.5V
COM_
COM_
COM_
On-Resistance (Note 5)
R
ON
V
or V
NO_
NC_
T
MAX
+25°C
0.15
0.4
0.4
0.5
1
On-Resistance Match Between
Channels (Notes 5, 6)
V+ = 4.2V, I
or V
= 10ꢀA;
= 3.5V
R
ON
T
to
MIN
V
NO_
NC_
T
MAX
+25°C
On-Resistance Flatness
(Note 7)
V+ = 4.2V, I
or V
= 10ꢀA;
R
FLAT(ON)
T
to
MIN
V
= 1.0V, 2.0V, 4.5V
NC_
NO_
1.2
+0.5
+1
+1
+2
T
MAX
+25°C
-0.5
-1
+0.01
+0.01
NO_, NC_ Off-Leakage Current
(Note 8)
I
I
V+ = 5.5V; V
= 1.0V, 4.5V;
NO_(OFF),
COM_
nA
nA
T
to
MIN
V
or V
= 4.5V, 1.0V
NC_(OFF)
NO_
NC_
T
MAX
+25°C
T to
MIN
-1
V+ = 5.5V, V
or V
= 1.0V, 4.5V;
COM_
COM_ On-Leakage Current
(Note 8)
I
V
= 1.0V, 4.5V, or
COM_(ON)
NO_
NC_
-2
floating
T
MAX
DYNAMIC CHARACTERISTICS
+25°C
to
30
20
8
80
100
40
V
, V
= 3.0V;
L
NO_ NC_
Turn-On Tiꢀe
t
ns
ns
ns
ON
T
MIN
R = 300 , C = 35pF, Figure 1
L
T
MAX
+25°C
V
, V
NO_ NC_
= 3.0V;
Turn-Off Tiꢀe
t
OFF
T
MIN
to
R = 300 , C = 35pF, Figure 1
L
L
50
T
MAX
+25°C
Break-Before-Make Tiꢀe Delay
(Note 8)
V
, V
NO_ NC_
= 3.0V;
L
t
BBM
T
MIN
to
R = 300 , C = 35pF, Figure 2
L
1
T
MAX
DIGITAL I/O
T
T
to
MIN
MIN
MIN
Input Logic High Voltage
V
2.0
V
V
IH
MAX
T
T
to
Input Logic Low Voltage
Input Leakage Current
V
0.8
IL
MAX
T
T
to
I
IN
V+ = 5.5V, V _ = 0V or V+
-0.1
+0.1
µA
IN
MAX
4
_______________________________________________________________________________________
20 , 300MHz Bandwidth, Dual SPDT Analog
Switch in UCSP
ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)
(V+ = +4.2V to +5.5V, V = +2.0V, V = +0.8V, T = T
to T
, unless otherwise noted. Typical values are at V+ = +5.0V,
MAX
IH
IL
A
MIN
T
A
= +25°C, unless otherwise noted.) (Notes 3, 4)
PARAMETER
SYMBOL
CONDITIONS
T
MIN
TYP
MAX
UNITS
A
POWER SUPPLY
T
T
to
MAX
MIN
MIN
Power-Supply Range
V+
I+
1.8
5.5
1
V
T
T
to
Supply Current
V+ = 5.5V, V
= 0V or V+
µA
IN_
MAX
Note 3: UCSP parts are 100% tested at +25°C only, and guaranteed by design over the specified teꢀperature range. µMAX parts
are 100% tested at T and guaranteed by design over the specified teꢀperature range.
MAX
Note 4: The algebraic convention used in this data sheet is where the ꢀost negative value is a ꢀiniꢀuꢀ and the ꢀost positive
value is a ꢀaxiꢀuꢀ.
Note 5: Guaranteed by design for UCSP parts.
Note 6:
R
ON
= R
- R
.
ON(MAX)
ON(MIN)
Note 7: Flatness is defined as the difference between the ꢀaxiꢀuꢀ and ꢀiniꢀuꢀ value of on-resistance as ꢀeasured over the
specified analog signal ranges.
Note 8: Guaranteed by design.
Note 9: Between any two switches.
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
ON-RESISTANCE vs. V
ON-RESISTANCE vs. V
ON-RESISTANCE vs. V
COM
COM
COM
T = +85 C
A
20
18
16
14
12
10
15
14
13
12
11
10
15
14
13
12
11
10
V+ = 5V
V+ = 3V
V+ = 1.8V
T
= +85 C
A
V+ = 2.5V
V+ = 4.2V
T
= -40 C
A
T
= +25 C
1.0
A
T
= +25 C
A
T
= -40 C
A
V+ = 5V
0
1
2
3
4
5
0
0.5
1.5
2.0
2.5
3.0
0
1
2
3
4
5
V
(V)
V
(V)
V
(V)
COM
COM
COM
_______________________________________________________________________________________
5
20 , 300MHz Bandwidth, Dual SPDT Analog
Switch in UCSP
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
LEAKAGE CURRENT vs. TEMPERATURE
LEAKAGE CURRENT vs. TEMPERATURE
CHARGE INJECTION vs. V
COM
800
600
400
200
0
700
50
40
30
20
10
0
V+ = 5V
V+ = 3V
500
300
COM ON-LEAKAGE
COM ON-LEAKAGE
C = 1nF
L
V+ = 5V
COM OFF-LEAKAGE
COM OFF-LEAKAGE
C = 1nF
L
V+ = 3V
100
-200
-100
-40
-15
10
35
60
85
-40
-15
10
35
60
85
0
1
2
3
4
5
TEMPERATURE ( C)
TEMPERATURE ( C)
V
COM
(V)
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. LOGIC LEVEL
6
5
4
3
2
1
0
100
80
60
40
20
0
V+ = 5V
V+ = 5V
V+ = 3V
V+ = 3V
-40
-15
10
35
60
85
0
1
2
3
4
5
TEMPERATURE ( C)
LOGIC LEVEL (V)
TURN-ON/OFF TIME
vs. SUPPLY VOLTAGE
LOGIC THRESHOLD vs. SUPPLY VOLTAGE
100
80
60
40
20
0
2.0
1.6
1.2
0.8
0.4
0
V
TH+
V
TH-
t
ON
t
OFF
1.5
2.5
3.5
4.5
5.5
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
6
_______________________________________________________________________________________
20 , 300MHz Bandwidth, Dual SPDT Analog
Switch in UCSP
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
TURN-ON/OFF TIME
vs. TEMPERATURE
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
FREQUENCY RESPONSE
60
50
40
30
20
10
20
0
1
V+ = 3V/5V
V+ = 3V
R = 600
L
t
, V+ = 3.0V
t , V+ = 5.0V
ON
ON
-20
-40
-60
-80
-100
-120
-140
ON-LOSS
0.1
OFF-ISOLATION
CROSSTALK
100
t
, V+ = 3.0V
OFF
t
, V+ = 5.0V
OFF
0
0.01
-40
-15
10
35
60
85
0.0001
0.01
1
10
100
1k
10k
100k
TEMPERATURE ( C)
FREQUENCY (MHz)
FREQUENCY (Hz)
Detailed Description
Pin Description
The MAX4719 high-speed, low-voltage, 20
R
, dual
ON
PIN
SPDT analog switch operates froꢀ a single +1.8V to
+5.5V supply. The switch features break-before-ꢀake
NAME
FUNCTION
UCSP µMAX
switching operation and fast switching speeds (t
=
Analog Switch 2—Norꢀally Closed
ON
A1
A2
A3
A4
7
8
NC2
IN2
80ns (ꢀax), t
= 40ns (ꢀax)).
Terꢀinal
OFF
Digital Control Input for Analog
Switch 2
Applications Information
Digital Control Inputs
Analog Switch 2—Coꢀꢀon
The MAX4719 logic inputs accept up to +5.5V regard-
less of supply voltage. For exaꢀple, with a +3.3V sup-
ply, IN_ can be driven low to GND and high to +5.5V
allowing for ꢀixing of logic levels in a systeꢀ. Driving
the control logic inputs rail-to-rail ꢀiniꢀizes power con-
suꢀption. For a +3V supply voltage, the logic thresh-
olds are 0.5V (low) and 1.4V (high); for a +5V supply
voltage, the logic thresholds are 0.8V (low) and 2.0V
(high).
9
COM2
NO2
Terꢀinal
Analog Switch 2—Norꢀally Open
10
Terꢀinal
B1
B4
6
1
GND Ground
V+
Positive-Supply Voltage Input
Analog Switch 1—Norꢀally Closed
C1
C2
C3
C4
5
4
3
2
NC1
Terꢀinal
Digital Control Input for Analog
Switch 1
Analog Signal Levels
The on-resistance of the MAX4719 changes very little for
analog input signals across the entire supply voltage
range (see the Typical Operating Characteristics). The
switches are bidirectional, so the NO_, NC_, and COM_
pins can be either inputs or outputs.
IN1
COM1
NO1
Analog Switch 1—Coꢀꢀon
Terꢀinal
Analog Switch 1—Norꢀally Open
Terꢀinal
_______________________________________________________________________________________
7
20 , 300MHz Bandwidth, Dual SPDT Analog
Switch in UCSP
usage environꢀent. The user should closely review
these areas when considering use of a UCSP package.
Perforꢀance through Operating Life Test and Moisture
Resistance reꢀains uncoꢀproꢀised as it is priꢀarily
deterꢀined by the wafer-fabrication process.
Power-Supply Sequencing and
Overvoltage Protection
Caution: Do not exceed the absolute maximum rat-
ings because stresses beyond the listed ratings
may cause permanent damage to the device.
Mechanical stress perforꢀance is a greater considera-
tion for a UCSP package. UCSPs are attached through
direct solder contact to the user’s PC board, foregoing
the inherent stress relief of a packaged product lead
fraꢀe. Solder joint contact integrity ꢀust be consid-
ered. Inforꢀation on Maxiꢀ’s qualification plan, test
data, and recoꢀꢀendations are detailed in the UCSP
application note, which can be found on Maxiꢀ’s web-
site at www.ꢀaxiꢀ-ic.coꢀ.
Proper power-supply sequencing is recoꢀꢀended for
all CMOS devices. Always apply V+ before applying
analog signals, especially if the analog signal is not
current-liꢀited.
UCSP Package Considerations
For general UCSP package inforꢀation and PC layout
considerations, please refer to the Maxiꢀ Application
Note (Wafer-Level Chip-Scale Package).
UCSP Reliability
The chip-scale package (UCSP) represents a unique
packaging forꢀ factor that ꢀay not perforꢀ equally to a
packaged product through traditional ꢀechanical relia-
bility tests. UCSP reliability is integrally linked to the
user’s asseꢀbly ꢀethods, circuit board ꢀaterial, and
Chip Information
TRANSISTOR COUNT: 235
PROCESS: BiCMOS
Test Circuits/Timing Diagrams
MAX4719
V+
t
t
< 5ns
< 5ns
r
f
V
IH
LOGIC
INPUT
50%
V+
COM_
V
IL
NO_
V
N_
V
OUT
OR NC_
R
C
L
300
L
t
OFF
35pF
IN_
V
OUT
0.9 x V
0.9 x V
OUT
0UT
GND
LOGIC
INPUT
SWITCH
OUTPUT
0V
t
ON
C
V
INCLUDES FIXTURE AND STRAY CAPACITANCE.
L
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
R
L
= V
OUT
N_
(
)
ON
R
+ R
L
Figure 1. Switching Time
V+
V+
MAX4719
V
IH
LOGIC
INPUT
50%
V
IL
NC_
NO_
V
V
OUT
N_
COM_
R
L
300
C
L
35pF
IN_
LOGIC
INPUT
GND
0.9 x V
OUT
V
OUT
t
BBM
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
Figure 2. Break-Before-Make Interval
_______________________________________________________________________________________
8
20 , 300MHz Bandwidth, Dual SPDT Analog
Switch in UCSP
Test Circuits/Timing Diagrams (continued)
V+
V
OUT
MAX4719
V+
V
OUT
R
GEN
NC_
COM_
V
OUT
IN
OR NO_
OFF
OFF
OFF
OFF
C
L
ON
ON
V
GEN
GND
IN_
IN
V
TO V
IH
Q = (
V
)(C )
OUT L
IL
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
Figure 3. Charge Injection
+5V 10nF
V+
V
V
OUT
OFF-ISOLATION = 20log
ON-LOSS = 20log
V
IN
NETWORK
ANALYZER
50
50
OUT
V
V
0V OR V+
IN
IN_
V
IN
COM1
V
OUT
MAX4719
CROSSTALK = 20log
NC1
V
IN
MEAS
50
REF
OUT
NO1*
50
GND
50
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
*FOR CROSSTALK THIS PIN IS NO2.
NC2 AND COM2 ARE OPEN.
OFF-ISOLATION IS MEASURED BETWEEN COM_ AND "OFF" NO_ OR NC_ TERMINAL ON EACH SWITCH.
ON-LOSS IS MEASURED BETWEEN COM_ AND "ON" NO_ OR NC_ TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
Figure 4. On-Loss, Off-Isolation, and Crosstalk
V+
V+
10nF
COM_
MAX4719
V
IL
OR
IN
CAPACITANCE
METER
V
IH
NC_ or
NO_
f = 1MHz
GND
Figure 5. Channel Off/On-Capacitance
_______________________________________________________________________________________
9
20 , 300MHz Bandwidth, Dual SPDT Analog
Switch in UCSP
Package Information
(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation,
go to www.maxim-ic.com/packages.)
10 ______________________________________________________________________________________
20 , 300MHz Bandwidth, Dual SPDT Analog
Switch in UCSP
Package Information (continued)
(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation,
go to www.maxim-ic.com/packages.)
e
4X S
10
10
INCHES
MAX
MILLIMETERS
MAX
1.10
0.15
0.95
3.05
3.00
3.05
3.00
5.05
0.70
DIM MIN
MIN
-
A
-
0.043
0.006
0.037
0.120
0.118
0.120
0.118
0.199
A1
A2
D1
D2
E1
E2
H
0.002
0.030
0.116
0.114
0.116
0.114
0.187
0.05
0.75
2.95
2.89
2.95
2.89
4.75
0.40
H
ÿ 0.50±0.1
0.6±0.1
L
0.0157 0.0275
0.037 REF
L1
b
0.940 REF
0.007
0.0106
0.177
0.270
0.200
1
1
e
0.0197 BSC
0.500 BSC
0.6±0.1
c
0.0035 0.0078
0.0196 REF
0.090
BOTTOM VIEW
0.498 REF
S
TOP VIEW
0∞
6∞
0∞
6∞
D2
E2
GAGE PLANE
A2
c
A
E1
b
L
A1
D1
L1
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0061
I
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
© 2002 Maxiꢀ Integrated Products
Printed USA
is a registered tradeꢀark of Maxiꢀ Integrated Products.
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