MAX3831UCB-T [MAXIM]
ATM/SONET/SDH Mux/Demux, 1-Func, PQFP64, 10 X 10 MM, 1 MM HEIGHT, MO-136AJ, TQFP-64;
| 型号： | MAX3831UCB-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ATM/SONET/SDH Mux/Demux, 1-Func, PQFP64, 10 X 10 MM, 1 MM HEIGHT, MO-136AJ, TQFP-64 时钟发生器 |
| 文件： | 总16页 (文件大小：285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1534; Rev 1; 10/99
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
General Description
Features
ꢀ +3.3V Single Supply
The MAX3831/MAX3832 are 4:1 multiplexers (muxes)
and 1:4 demultiplexers (demuxes) with automatic chan-
nel assignment. Operating from a single +3.3V supply,
the mux receives four parallel, 622Mbps SDH/SONET
channels. These channels are bit interleaved to gener-
ate a serial data stream of 2.488Gbps for interfacing to
an optical or an electrical driver. A 10-bit-wide elastic
buffer tolerates up to ±±.ꢀns sꢁew between any parallel
data input and the reference clocꢁ. An external
1ꢀꢀMHz reference clocꢁ is required for the on-chip PLL
to synthesize a high-frequency 2.488GHz clocꢁ for tim-
ing the outgoing data streams.
ꢀ 1.45W Power Dissipation (MAX3831)
ꢀ 4-Channel Mux/Demux with Fully Integrated
2.488GHz Clock Generator
ꢀ Frame Detection Maintains Channel Assignment
ꢀ ±±.5ns ꢀlastic Store ꢁange
ꢀ 2.5ps ꢁMS Serial-Data Output ꢁandom Jitter
ꢀ 8ps Serial-Data Output Deterministic Jitter
ꢀ 622Mbps LVDS Parallel Input/Output
ꢀ 2.488Gbps Serial CML Input/Output
The MAX3831/MAX3832’s demux receives 2.488Gbps
serial data and the 2.488GHz clocꢁ from an external
clocꢁ/data recovery device (MAX38±6), converting it to
four 622Mbps LVDS outputs. The MAX3831 provides a
622MHz LVDS clocꢁ output, and the MAX3832 pro-
vides a 1ꢀꢀMHz LVDS clocꢁ output. An internal frame
detector looꢁs for a 622Mbps SDH/SONET framing pat-
tern and rolls the demux to maintain proper channel
assignment at the outputs.
ꢀ On-Chip Pattern Generator Provides
High-Speed BIST
ꢀ System Test Flexibility: System Loopback,
Line Loopback
ꢀ Loss-of-Frame Indicator
Applications
ATM Switching Networꢁs
SDH/SONET Bacꢁplanes
High-Speed Parallel Linꢁs Line Extenders
These devices also include an embedded pattern gen-
erator that enables a full-speed, built-in self-test (BIST).
Two different loopbacꢁ modes provide system test flexi-
bility. A TTL loss-of-frame monitor is included. The
MAX3831/MAX3832 are available in 64-pin TQFP-EP
(exposed paddle) pacꢁages and are specified over the
upper commercial (0°C to +8ꢀ°C) temperature range.
Intraracꢁ/Subracꢁ
Interconnects
Dense Digital Cross-
Connects
Ordering Information
PAꢁT
TꢀMP. ꢁANGꢀ
0°C to +8ꢀ°C
0°C to +8ꢀ°C
PIN-PACKAGꢀ
64 TQFP-EP
MAX3831UCB
MAX3832UCB
Pin Configuration appears at end of data sheet.
64 TQFP-EP
Typical Application Circuit
+3.3V
0.33µF
TTL
TTL
TTL
TTL
0.1µF
RSETES
RCLKI+
RCLKI-
FIL+ FIL- TEST
LOF PLBEN
V
CC
155MHz REF
SCLKI-
SCLKI+
SDI-
LVDS
LVDS
CML
CLOCK INPUT
MAX3876
2.5Gbps
CDR
4
4
PDI1+ TO PDI4+
2.5Gbps
OPTICAL
TRANSCEIVER
CML
PDI1- TO PDI4-
SDI+
MAX3831
MAX3832
4
4
CMOS
OVERHEAD
PDO1+ TO PDO4+
PDO1- TO PDO4-
PCLKO+
SDO+
SDO-
LVDS
LVDS
TTL
TTL
LBEN
PCLKO-
GND
RSETFR
TRIEN
TTL
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
ABSOLUTꢀ MAXIMUM ꢁATINGS
Positive Supply Voltage (V )...............................-0.ꢀV to +ꢀ.0V
Continuous Power Dissipation (T = +8ꢀ°C) (Note 1)
A
CC
Input Voltage (LVDS, TTL)..........................-0.ꢀV to (V
+ 0.ꢀV)
+ 0.ꢀV)
+ 0.ꢀV)
+ 0.ꢀV)
+0.ꢀV)
64-Pin TQFP-EP (derate 40.0mW/°C above +8ꢀ°C).........2.6W
Operating Temperature Range...............................0°C to +8ꢀ°C
Storage Temperature Range.............................-60°C to +1ꢀ0°C
Lead Temperature (soldering, 10sec) .............................+300°C
CC
CC
CC
CC
CML Input Voltage ..........................(V
- 0.8V) to (V
CC
FIL+, FIL- Voltage.......................................-0.ꢀV to (V
TTL Output Voltage ....................................-0.ꢀV to (V
LVDS Output Voltage ..................................-0.ꢀV to (V
CC
CML Output Currents..........................................................22mA
Note 1: Based on empirical data from the MAX3831/MAX3832 evaluation ꢁit.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ꢀLꢀCTꢁICAL CHAꢁACTꢀꢁISTICS
CC
(V
= +3.0V to +3.6V, LVDS differential load = 100Ω ±1ꢂ, CML load = ꢀ0Ω ±1ꢂ to V , all TTL inputs are open, T = 0°C to
CC A
+8ꢀ°C, unless otherwise noted. Typical values are at T = +2ꢀ°C and V
= +3.3V.)
A
CC
PAꢁAMꢀTꢀꢁ
SYMBOL
CONDITIONS
MIN
TYP
440
480
MAX
ꢀ80
UNITS
MAX3831
MAX3832
CML inputs and outputs open,
Supply Current
I
mA
CC
LVDS input V = 1.2V (Note 2)
OS
614
LVDS INPUTS AND OUTPUTS
Input Voltage Range
V
0
2400
+100
mV
mV
mV
Ω
IN
Differential Input Threshold
Threshold Hysteresis
V
IDTH
HYST
-100
V
90
Input Impedance
R
8ꢀ
100
2±0
11ꢀ
1.4±ꢀ
400
IN
Input Common-Mode Current
Output Voltage High
I
LVDS input, V = 1.2V
OS
µA
V
OS
V
OH
Output Voltage Low
V
OL
0.92ꢀ
2ꢀ0
V
Differential Output Voltage
Figure 1
mV
V
OD
Change in Magnitude of
Differential Output Voltage for
Complementary States
∆V
±2ꢀ
mV
V
OD
OS
Output Offset Voltage
V
1.12ꢀ
1.2±ꢀ
±2ꢀ
Change in Magnitude of Output
Offset Voltage for Complementary
States
∆V
mV
OS
>1
MΩ
Ω
TRIEN = GND
Differential Output Impedance
80
120
12
TRIEN = V
CC
Output Current
Short outputs together (Note 3)
mA
CML INPUTS AND OUTPUTS
Differential Output Voltage
Differential Output Impedance
Output Common-Mode Voltage
V
640
8ꢀ
800
100
1000
11ꢀ
mVp-p
ODp-p
Ω
V
- 0.2
V
CC
V
-
V
+
CC
CC
0.4
Single-Ended Input Voltage Range
V
IS
V
0.6
400
8ꢀ
Differential Input Voltage Swing
Differential Input Impedance
Figure 2
1200
11ꢀ
mVp-p
100
Ω
2
_______________________________________________________________________________________
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
DC ꢀLꢀCTꢁICAL CHAꢁACTꢀꢁISTICS (continued)
(V
= +3.0V to +3.6V, LVDS differential load = 100Ω ±1ꢂ, CML load = ꢀ0Ω ±1ꢂ to V , all TTL inputs are open, T = 0°C to
CC
CC A
+8ꢀ°C, unless otherwise noted. Typical values are at T = +2ꢀ°C and V
= +3.3V.)
A
CC
PAꢁAMꢀTꢀꢁ
TTL INPUTS AND OUTPUTS
Input Voltage High
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
IH
2.0
V
V
Input Voltage Low
V
IL
0.8
-ꢀ0
Input Current High
I
IH
V
V
= 2.0V
= 0
-2ꢀ0
-ꢀꢀ0
2.4
µA
µA
V
IH
Input Current Low
I
IL
-100
IL
Output Voltage High
Output Voltage Low
Output Impedance
V
OH
I
I
= 20µA
= 2mA
OH
OL
V
OL
0.4
V
6
ꢁΩ
TRIEN = GND
Note 2: When TEST = GND, the pattern generator will consume an additional 30mA.
Note 3: Guaranteed by design and characterization.
AC ꢀLꢀCTꢁICAL CHAꢁACTꢀꢁISTICS
CC
(V
= +3.0V to +3.6V, LVDS differential load = 100Ω ±1ꢂ, CML load = ꢀ0Ω ±1ꢂ to V , all TTL inputs are open, T = 0°C to
CC A
= +3.3V.) (Note 4)
+8ꢀ°C, unless otherwise noted. Typical values are at T = +2ꢀ°C and V
A
CC
PAꢁAMꢀTꢀꢁ
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
4:1 MULTIPLꢀXꢀꢁ WITH CLOCK GꢀNꢀꢁATOꢁ
Parallel Input Data Rate
622.08
±±.ꢀ
Mbps
ns
Maximum Parallel Input Sꢁew
Serial-Data Output Rate
t
(Note ꢀ)
es
2.48832
Gbps
ps
Serial-Data Output Rise/Fall Time
t , t
r
20ꢂ to 80ꢂ
(Note 6)
120
3.ꢀ
40
f
ps
RMS
Serial-Data Output Random Jitter
SRJ
SDJ
ps
p-p
Serial-Data Output Deterministic
Jitter
(Note ±)
8
18
ps
p-p
1:4 DꢀMULTIPLꢀXꢀꢁ
Serial-Data Input Rate
Serial-Data Setup Time
Serial-Data Hold Time
Parallel-Data Output Rate
2.48832
Gbps
ps
t
Figure 3
Figure 3
100
100
SU
t
ps
H
PDO±
622.08
622.08
1ꢀꢀ.ꢀ2
90
Mbps
MAX3831
MAX3832
Parallel-Clocꢁ Output Frequency
PCLKO±
MHz
PCLKO to PDO_ Delay
t
MAX3831, Figure 3
20ꢂ to 80ꢂ
-100
300
3ꢀ0
6ꢀ
ps
ps
ps
ps
ns
CLK-Q
LVDS Output Rise/Fall Time
LVDS Differential Sꢁew
t
t
Any differential pair
PDO1± to PDO4±
SKEW1
LVDS Channel-to-Channel Sꢁew
LVDS Three-State Enable Time
<100
30
SKEW2
Note 4: AC characteristics are guaranteed by design and characterization.
Note 5: Relative to the positive edge of the 1ꢀꢀMHz reference clocꢁ. PDI1 to PDI4 aligned to RCLKI at reset.
Note 6: Measured with a reference clocꢁ jitter of <1ps
.
RMS
Note ±: Deterministic jitter is the arithmetic sum of pattern-dependent jitter and pulse-width distortion.
_______________________________________________________________________________________
3
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
PDO+
V
V
R = 100Ω
L
OD
D
PDO-
V
V
V
PDO-
OH
SINGLE-ENDED OUTPUT
V
OS
OL
| OD|
V
V
PDO+
+V
OD
0V
0V (DIFF)
V
= V
- V
PDO+ PDO-
ODp-p
DIFFERENTIAL OUTPUT
-V
OD
Figure 1. Definition of the LVDS Output
SDI+
200mV MIN
600mV MAX
SDI-
(SDI+) - (SDI-)
400mVp-p MIN
1200mVp-p MAX
V
ID
Figure 2. Definition of the CML Input
t
= 1 / f
SCLK
SCLK
SCLKI
t
t
H
SU
SDI
PCLKO
t
CLK-Q
PDO1–PDO4
NOTE: SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLKI = (SCLKI+) - (SCLKI-).
Figure 3. Timing Parameters
4
_______________________________________________________________________________________
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
Typical Operating Characteristics
(V
= +3.3V, T = +2ꢀ°C, unless otherwise noted.)
A
CC
SERIAL-DATA OUTPUT JITTER
SUPPLY CURRENT vs. TEMPERATURE
SERIAL-DATA OUTPUT EYE DIAGRAM
600
500
400
300
200
100
0
MAX3832
MAX3831
23
2
-1 PRBS PATTERN
WIDEBAND RMS
JITTER = 2.48ps
5ps/div
50ps/div
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
SERIAL-DATA HOLD TIME
ELASTIC STORE RANGE
10
8
100
80
60
40
20
0
6
4
2
ERROR-FREE OPERATION
0
-2
-4
-6
-8
-10
CHANNEL ALIGNED TO RCLKI
-20
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
DATA TO RCLKI DELAY AT RESET (ns)
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
MAX3831
PARALLEL CLOCK-TO-DATA OUTPUT
PROPAGATION DELAY vs. TEMPERATURE
SERIAL-DATA SETUP TIME
300
250
200
150
100
50
100
80
60
40
20
0
0
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
Pin Description
PIN
NAMꢀ
FUNCTION
1, 16, 2ꢀ, 28,
29, 32, 43, 48,
49, 60, 63
GND
Supply Ground
2, ꢀ, 10, 13,
1±, 24, 38, ꢀꢀ,
ꢀ9, 64
V
CC
+3.3V Supply Voltage
3
4
SDO-
Negative CML Serial-Data Output, 2.488Gbps
Positive CML Serial-Data Output, 2.488Gbps
SDO+
Line Loopbacꢁ Enable. When this TTL input is forced low, the CML serial-data inputs (SDI±)
route directly to the CML serial-data outputs (SDO±). No other inputs or outputs are affected.
An internal 1ꢀꢁΩ pull-up resistor pulls LBEN high for normal operation. See Test Loopbacks.
6
LBEN
TEST
Self-Test Enable. When this TTL input is forced low, the built-in pattern generator generates
a standard OC-12 SONET-liꢁe frame of 12 A1s, 12 A2s, and 9696 bytes of 2± - 1 pseudo-
random bits. This also enables an internal serial-system-loopbacꢁ path. The CML inputs
(SDI± and the SCLK±) and the LVDS inputs are ignored in this mode. An internal 1ꢀꢁΩ pull-
up resistor pulls TEST high for normal operation.
±
8
SDI+
SDI-
Positive CML Serial-Data Input, 2.488Gbps
9
Negative CML Serial-Data Input, 2.488Gbps
11
12
14
1ꢀ
SCLKI+
SCLKI-
PCLKO-
PCLKO+
N.C.
Positive CML Serial-Clocꢁ Input, 2.488GHz
Negative CML Serial-Clocꢁ Input, 2.488GHz
Negative LVDS Parallel-Clocꢁ Output, 622.08MHz (MAX3831); 1ꢀꢀ.ꢀ2MHz (MAX3832)
Positive LVDS Parallel-Clocꢁ Output, 622.08MHz (MAX3831); 1ꢀꢀ.ꢀ2MHz (MAX3832)
No Connection
–
18 23, 26, 2±
Frame Reset. When this TTL input is forced low, the frame detector and pattern generator
are reset. The LOF output is also asserted low. An internal 1ꢀꢁΩ pull-up resistor pulls
RSETFR high for normal operation.
30
RSETFR
31
33
TTL Loss-of-Frame Output. Asserts low in a loss-of-frame condition.
LOF
TRIEN
3-State Enable. When this TTL input is forced low, all TTL and LVDS outputs go into a high-
impedance state. An internal 1ꢀꢁΩ pull-up resistor pulls TRIEN high for normal operation.
34, 36, 39, 41
PDO4- to PDO1-
Negative LVDS Parallel-Data Output, 622Mbps
Positive LVDS Parallel-Data Output, 622Mbps
Negative LVDS Parallel-Data Input, 622Mbps
Positive LVDS Parallel-Data Input, 622Mbps
3ꢀ, 3±, 40, 42 PDO4+ to PDO1+
44, 46, ꢀ0, ꢀ2
4ꢀ, 4±, ꢀ1, ꢀ3
PDI4- to PDI1-
PDI4+ to PDI1+
Parallel System Loopbacꢁ Enable. When this TTL input is forced low, the LVDS parallel
inputs route through the elastic store to the LVDS parallel outputs. This bypasses the high-
speed mux and demux. An internal 1ꢀꢁΩ pull-up resistor pulls PLBEN high for normal oper-
ation.
ꢀ4
PLBEN
ꢀ6
ꢀ±
RCLKI-
Negative LVDS Reference Clocꢁ Input, 1ꢀꢀ.ꢀ2MHz
Positive LVDS Reference Clocꢁ Input, 1ꢀꢀ.ꢀ2MHz
RCLKI+
6
_______________________________________________________________________________________
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
Pin Description (continued)
PIN
NAMꢀ
FUNCTION
Elastic Store Reset. The elastic buffer is centered on a rising edge of RSETES, maximizing
the elastic store range. Data must be present for 10µs before applying a pulse of at least
10ns. An internal 1ꢀꢁΩ pull-up resistor pulls RSETES high for normal operation.
ꢀ8
RSETES
61
62
FIL-
Negative PLL Filter Capacitor Input. Connect a 0.33µF capacitor between FIL+ and FIL-.
Positive PLL Filter Capacitor Input. Connect a 0.33µF capacitor between FIL+ and FIL-.
FIL+
Ground. This must be soldered to a circuit board for proper thermal performance (see
Package Information).
EP
Exposed Paddle
Due to the inherent uncertainty of the data transitions
_______________Detailed Description
between the parallel-data inputs there is no bit or frame
alignment between these inputs. However, the demux
ensures proper channel assignment is maintained.
The MAX3831/MAX3832 use a 4:1 mux and 1:4 demux
with an elastic store buffer to simplify SDH/SONET
interconnect I/O routing. The 622Mbps low-voltage dif-
ferential signal (LVDS) parallel inputs pass through the
10-bit elastic store buffer, which accommodates ±±.ꢀns
sꢁew on any single input relative to the 1ꢀꢀMHz refer-
ence clocꢁ input RCLKI. This reference clocꢁ is
required to synthesize the internal 2.488GHz clocꢁ
used to drive the elastic store and 4:1 multiplexer. All
TTL and LVDS outputs can be placed in a high-imped-
ance state. See Figure 4 for a functional diagram.
Bit-Interleaved Multiplexer/
Demultiplexer
The MAX3831/MAX3832 use a bit interleave/deinterleave
mux/demux. To guarantee channel assignment, one of
the four channels is inverted before multiplexing to pro-
vide a reference for the frame detector during demulti-
plexing. After demultiplexing, the same channel is
inverted bacꢁ to the original data format.
The 4:1 mux bit-interleaves the parallel data, providing
a 2.488Gbps CML serial output to the optical or electri-
cal driver. The CML serial input receives the
2.488Gbps data, the demux deinterleaves it to
622Mbps and sends the data to the frame detector.
The frame detector monitors one 622Mbps channel and
rolls the demux into the proper channel assignment.
The MAX3831/MAX3832 include high-speed, built-in
self-test (BIST), which also allows testing of the
622Mbps parallel-system loopbacꢁ and the 2.488Gbps
line loopbacꢁ.
Frame Detector
After a 2.ꢀGbps serial data is bit deinterleaved into four
622Mbps channels, an SDH/SONET frame detector
monitors the fourth channel, looꢁing for the 32-bit pat-
tern (A1A1A2A2) in the OC-12 header. To maintain cor-
rect channel assignment, the demux outputs rotate until
this 32-bit overhead pattern is reliably detected. A loss-
of-frame output, LOF, indicates when the received data
is in or out of frame. When LOF goes high, the frame
pattern is detected and the demux outputs are correct-
ly assigned. When LOF is low, the frame detection cir-
cuitry is searching for the correct frame. A RSETFR
(TTL, active low) is included to reset the frame detector
when necessary.
Elastic Store Buffer
Each parallel-data input, PDI1 to PDI4, passes through
its respective 10-bit elastic store buffer. Following an
elastic store reset, this buffer accommodates ±±.ꢀns of
sꢁew on any input relative to the 1ꢀꢀMHz reference
clocꢁ. Figure ꢀ illustrates the elastic store buffer rela-
tionship with RCLKI. The Elastic Store Range graph in
the Typical Operating Characteristics shows the
amount of data sꢁew tolerated.
The frame detector uses an algorithm to detect an in-
frame condition and a loss-of-frame condition; this algo-
rithm is implemented to meet the SONET in-frame and
false-frame specs. The frame_search state will occur
upon start-up or reset. In this state, the frame detector
scans through the incoming serial data searching for the
framing pattern in the channel 4 output of the demux.
While in this state, if the framing pattern is not found
within 2ꢀ0µs, the demux channels are shifted (rolled)
and the frame search continues (Figure 6).
Following a 10µs power-up period, the locations of the
individual data-channel bit transitions are acquired,
guaranteeing data preservation. The output of this
blocꢁ passes directly into the 4:1 mux. After power-up,
the elastic store buffer must be reset by applying a low
pulse on RSETES for at least 10ns.
In-frame will be declared if two consecutive framing
patterns are found at the correct byte locations within
the SONET frame (9±20 bytes). If this pattern is not pre-
________________________________________________________________________________________
±
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
TRIEN
TEST
FIL+
FIL-
RSETES
155MHz
(155MHz)
RCLKI+
MAX3831
MAX3832
LVDS
FREQUENCY
GENERATOR
RCLKI-
622MHz
PATTERN
GENERATOR
2.488GHz
LBEN
CK
PDI1+
PDI1-
ES
ES
LVDS
LVDS
SDO+
SDO-
4:1
MUX
PDI2+
PDI2-
LINE LOOPBACK
PDI3+
PDI3-
ES
ES
2.488Gbps
SYSTEM LOOPBACK
LVDS
LVDS
TEST
PDI4+
PDI4-
622Mbps PARALLEL LOOPBACK
D
PDO1+
PDO1-
LVDS
LVDS
2.488Gbps
SDI+
SDI-
PDO2+
PDO2-
1:4
DEMUX
PDO3+
PDO3-
LVDS
LVDS
2.488GHz
CK
SCLKI+
SCLKI-
PDO4+
PDO4-
ROTATE
FRAME
CLOCK
GENERATOR
PLBEN
PCLKO+
622MHz
DETECTOR
LVDS
*
PCLKO-
RSETFR
LOF
*MAX3831: f
= 622MHz, MAX3832: f
= 155MHz
PCLKO
PCLKO
Figure 4. Functional Diagram
sent at the correct location (false frame), the state
machine will return to the frame_search state described
above. While in the in_frame state, each frame will be
checꢁed for a framing pattern at the correct location.
Four consecutive false frames will cause the state
machine to return to the frame_search state described
above. The false-frame counter is reset with three or
fewer consecutive false frames.
DATA INPUT
DATA OUTPUT OF ELASTIC STORE
AT t = t
o
PDI1
A0
A1
A0
B0
B1
B2
B1
C0
D1
PDI2
C0
C1
PDI3
PDI4
D0
D1
RSETES
≥10ns
+t
Built-In Self-Test
with On-Chip Serial Loopback
RCLKI
es
DATA OUTPUT OF ELASTIC STORE
AT t > t
An on-chip pattern generator can be enabled to pro-
duce a 622Mbps SDH/SONET-liꢁe transport overhead
followed by a pseudorandom bit sequence. This consists
of 12 A1s, 12 A2s, and a pseudorandom bit stream
(PRBS = 2± - 1). When TEST is low, this pattern is distrib-
uted to all parallel inputs, bypassing the LVDS input
buffers. Note, this pattern is sꢁewed by one 622MHz
o
A0
A1
A0
PDI1
PDI2
PDI3
PDI4
-t
es
B1
B2
B1
C0
D1
C0
C1
D0
D1
Figure 5. Example of Elastic Store Function
_______________________________________________________________________________________
8
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
FRAME DETECT
START-UP OR RESET
START 250µs TIMER
FRAME_SEARCH
NO
YES
TIMER
TIMED OUT?
ROLL DATA
LOF = 0
FRAME
PATTERN
DETECTED?
NO
YES
1 FRAME DETECTED
RESET BYTE
AND FRAME
FRAME
PATTERN
DETECTED?
NO
NO
YES
FRAME
PATTERN
DETECTED?
YES
YES
YES
IN_FRAME
NO
FRAME
PATTERN
DETECTED?
LOF = 1
NO
FRAME
PATTERN
DETECTED?
FRAME
PATTERN
DETECTED?
NO
YES
Figure 6. Frame Detection Flow Diagram
_______________________________________________________________________________________
9
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
clocꢁ cycle between each channel. In this test mode, ser-
ial data is internally looped bacꢁ to the demux. All frame
V
CC
V
CC
detect logic is exercised using this mode. The CML
inputs (SDI± and SCLKI±) and LVDS inputs (PDI_±) are
ignored in this mode. After the BIST mode is enabled, the
loss-of-frame flag LOF goes high, indicating that the self-
test has passed. In normal operation, TEST is left open
(internally pulled high), disabling the pattern generator
and accepting data from the parallel input channels.
50Ω
50Ω
50Ω
50Ω
SDO+ SDI+
SDO- SDI-
Test Loopbacks
Two additional test loopbacꢁs are provided: parallel
system loopbacꢁ and serial line loopbacꢁ.
Parallel System Loopback
In parallel system loopbacꢁ, four 622Mbps parallel
input channels are phase aligned by an associated 10-
bit elastic store and routed to the output LVDS buffers.
This loopbacꢁ is controlled by setting PLBEN low.
Normal data transmission is resumed when PLBEN
goes high (internally pulled high).
MAX3831
MAX3832
MAX3876
Serial Line Loopback
Serial line loopbacꢁ is used for testing the performance
of the optical transceiver and the transmission linꢁ. The
received 2.488Gbps data stream is routed to the trans-
mit CML output buffer. Line loopbacꢁ is enabled when
LBEN is asserted low. When LBEN is left open (internally
pulled high), normal serial-data transmission resumes.
Figure 7. CML-to-CML Interface
__________Applications Information
Low-Voltage Differential
Signal Inputs/Outputs
The MAX3831/MAX3832 have LVDS inputs and outputs
for interfacing with high-speed digital circuitry. All LVDS
inputs and outputs are compatible with the IEEE-1ꢀ96.3
LVDS specification. This technology uses 2ꢀ0mV to
400mV differential low-voltage amplitudes to achieve
fast transition times, minimize power dissipation, and
improve noise immunity.
LVDS Parallel Interface
The MAX3831 parallel interface includes four OC-12
data inputs, a 1ꢀꢀMHz reference clocꢁ input, four
622Mbps parallel-data outputs, and a 622MHz parallel-
clocꢁ output (MAX3832, f
= 1ꢀꢀMHz). All parallel
PCLKO
inputs and outputs are LVDS compatible to minimize
power dissipation, speed transition time, and improve
noise immunity. The 1ꢀꢀMHz input signal at RCLKI
requires a duty cycle between 40ꢂ and 60ꢂ.
For proper operation, the parallel clocꢁ and data LVDS
outputs (PCLKO+, PCLKO-, PDO_+, PDO_-) require
100Ω differential DC termination between the inverting
and noninverting outputs. Do not terminate these out-
puts to ground. The parallel-data LVDS inputs (PDI_+,
PDI_-) are internally terminated with 100Ω differential
input resistance and therefore do not require external
termination.
The LVDS outputs go into a high-impedance state when
TRIEN is forced low. This simplifies system checꢁs by
allowing vectors to be forced on the LVDS outputs.
CML Serial Interface
The MAX3831/MAX3832 provide a 2.488Gbps serial-
data stream to a driver and accept 2.488Gbps serial
data and a 2.488GHz clocꢁ signal from an external
clocꢁ and data recovery device (MAX38±6). The high-
speed interface is CML compatible, resulting in lower
system power dissipation and excellent performance
(Figure ±).
Interfacing with PECL/ECL
Input Levels
When interfacing with differential PECL input levels, it is
important to attenuate the signal while still maintaining
ꢀ0Ω termination (Figures 8 and 9). Observe the com-
mon-mode input voltage specifications. AC-coupling is
required if a V
other than 3.3V is used to maintain the
CC
input common-mode level (Figure 8).
10 ______________________________________________________________________________________
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
V
CC
V
= 3.3V
CC
V
= 3.3V
CC
50Ω
50Ω
0.1µF
0.1µF
50Ω
50Ω
25Ω
SDI+
SDI-
PECL
LEVELS
82Ω
82Ω
SDI+
SDI-
R *
T
82Ω
82Ω
100Ω
PECL
OUTPUT
25Ω
R *
T
MAX3831
MAX3832
MAX3831
MAX3832
*SELECT R SUCH THAT THE CORRECT PECL COMMON-MODE LEVEL
T
IS ACHIEVED (TYPICAL PECL OUTPUT CURRENT = 14mA).
Figure 8. PECL-to-CML Interface
Figure 9. Direct Coupling of a PECL Output into the MAX3831/
MAX3832
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies, ꢁeep ground con-
nections short, and use multiple vias where possible.
Use controlled-impedance transmission lines to inter-
face with the MAX3831/MAX3832 high-speed inputs
and outputs.
Place power-supply decoupling as close to V
as
CC
possible. To reduce feedthrough, taꢁe care to isolate
the input signals from the output signals.
______________________________________________________________________________________ 11
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
Pin Configuration
TOP VIEW
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GND
1
2
48 GND
V
CC
47 PDI3+
46 PDI3-
45 PDI4+
44 PDI4-
43 GND
SDO-
SDO+
3
4
V
5
CC
6
LBEN
TEST
SDI+
SDI-
7
42 PDO1+
41 PDO1-
40 PDO2+
39 PDO2-
8
MAX3831
MAX3832
9
V
10
CC
SCLKI+ 11
SCLKI- 12
38 V
CC
37 PDO3+
36 PDO3-
35 PDO4+
34 PDO4-
33 TRIEN
V
CC
13
PCLKO- 14
PCLKO+ 15
GND 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TQFP-ꢀP
___________________Chip Information
TRANSISTOR COUNT: 14,134
12 ______________________________________________________________________________________
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
Package Information
______________________________________________________________________________________ 13
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
Package Information (continued)
14 ______________________________________________________________________________________
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
NOTꢀS
______________________________________________________________________________________ 15
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
NOTꢀS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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+3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator
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