MAX3264CUE+ [MAXIM]
Telecom Circuit, 1-Func, Bipolar, PDSO16, 4.40 MM, LEAD FREE, EXPOSED PAD, MO-153ABT, TSSOP-16;
| 型号： | MAX3264CUE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Telecom Circuit, 1-Func, Bipolar, PDSO16, 4.40 MM, LEAD FREE, EXPOSED PAD, MO-153ABT, TSSOP-16 放大器 |
| 文件： | 总17页 (文件大小：345K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1523; Rev 6, 5/04
+3 .0 V t o +5 .5 V, 1 .2 5 Gb p s /2 .5 Gb p s
Lim it in g Am p lifie rs
Ge n e ra l De s c rip t io n
Fe a t u re s
The 1.25Gbps MAX3264/MAX3268/MAX3768 and the
2.5Gbps MAX3265/MAX3269/MAX3765 limiting ampli-
fie rs a re d e s ig ne d for Gig a b it Ethe rne t a nd Fib re
Channel optical receiver systems. The amplifiers accept
a wide range of input voltages and provide constant-
le ve l output volta ge s with c ontrolle d e dge spe e ds.
Additional features include RMS power detectors with
p rog ra mma b le los s -of-s ig na l (LOS) ind ic a tion, a n
optional squelch function that mutes the data output sig-
nal when the input voltage falls below a programmable
threshold, and excellent jitter performance.
♦ +3.0V to +5.5V Supply Voltage
♦ Low Deterministic Jitter
14ps (MAX3264)
11ps (MAX3265/MAX3765)
♦ 150ps (max) Edge Speed (MAX3265/MAX3765)
300ps (max) Edge Speed (MAX3264)
♦ Programmable Signal-Detect Function
♦ Choice of CML or PECL Output Interface
♦ 10-Pin µMAX or 16-Pin TSSOP Package
Ord e rin g In fo rm a t io n
The MAX3264/MAX3265/MAX3765 feature current-mode
logic (CML) data outputs that are tolerant of inductive
connectors and a 16-pin TSSOP package, making these
c irc uits id e a l for GBIC re c e ive rs . The MAX3268/
MAX3269/MAX3768 feature standards-compliant posi-
tive-referenced emitter-coupled logic (PECL) data out-
puts and are available in a tiny 10-pin µMAX package
that is ideal for small-form-factor (SFF) receivers.
PART
TEMP RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
PIN-PACKAGE
16 TSSOP-EP*
16 TSSOP-EP*
Dice**
MAX3264CUE
MAX3264CUE+
MAX3264C/D
MAX3265CUE
MAX3265CUE+
MAX3265CUB
MAX3265CUB+
MAX3265EUE
MAX3265EUE+
MAX3265C/D
16 TSSOP-EP*
16 TSSOP-EP*
10 µMAX-EP*
10 µMAX-EP*
16 TSSOP-EP*
16 TSSOP-EP*
Dice**
Ap p lic a t io n s
Gigabit Ethernet Optical Receivers
Fibre Channel Optical Receivers
System Interconnect
ATM Optical Receivers
+Denotes lead-free package.
*EP = Exposed paddle.
**Dice are designed to operate from 0°C to +70°C, but are tested
and guaranteed only at T = +25°C.
A
Selector Guide appears at end of data sheet.
Pin Configurations appear at end of data sheet.
Ordering Information continued at end of data sheet.
Typ ic a l Op e ra t in g Circ u it s
C
AZ
V
CC
V
CC
V
CC
CAZ1
CAZ2
MAX3264CUE
MAX3265CUE
MAX3265EUE
R
TERM
C
IN
0.01µF
0.01µF
OUT+
OUT-
IN+
IN-
R
100Ω
L
100Ω
0.01µF
MAX3266
MAX3267
C
IN
0.01µF
R
TERM
LOS
N.C.
TH SQUELCH
N.C.
LOS
LEVEL
N.C.
V
CC
R
TH
LOSS
OF
SIGNAL
Typical Operating Circuits continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+3 .0 V t o +5 .5 V, 1 .2 5 Gb p s /2 .5 Gb p s
Lim it in g Am p lifie rs
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V ) ............................................-0.5V to +6.0V
Continuous Current at PECL Outputs (OUT+, OUT-) .........50mA
CC
Voltage at IN+, IN- ..........................(V - 2.4V) to (V + 0.5V)
Continuous Power Dissipation (T = +70°C)
CC
CC
A
Voltage at SQUELCH, CAZ1,
CAZ2, LOS, LOS, TH..................................-0.5V to (V + 0.5V)
Voltage at LEVEL...................................................-0.5V to +2.0V
Current into LOS, LOS ..........................................-1mA to +9mA
Differential Input Voltage (IN+ - IN-) .....................................2.5V
Continuous Current at
16-Pin TSSOP (derate 27mW/°C above +70°C) .........2162mW
10-Pin µMAX (derate 20mW/°C above +70°C) ...........1600mW
Operating Ambient Temperature Range .............-40°C to +85°C
Storage Temperature Range .............................-55°C to +150°C
Processing Temperature (dice) .......................................+400°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
CML Outputs (OUT+, OUT-)..........................-25mA to +25mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Data outputs terminated per Figure 1, V = +3.0V to +5.5V, T = 0°C to +70°C. Typical values are at V = +3.3V, T = +25°C,
CC
A
CC
A
unless otherwise noted.) (Note 1)
PARAMETER
CONDITIONS
MIN
TYP
1.25
2.5
MAX UNITS
MAX3264/MAX3268/MAX3768
MAX3265/MAX3269/MAX3765
MAX3264/MAX3268/MAX3768
MAX3265/MAX3269/MAX3765
MAX3264/MAX3268/MAX3768 (Notes 2, 3)
MAX3265/MAX3269/MAX3765 (Notes 2, 3)
MAX3264/MAX3268/MAX3768 (Notes 2, 4)
MAX3265/MAX3269/MAX3765 (Notes 2, 4)
MAX3264 (Note 5)
Data Rate
Gbps
5
1200
mV
Input Voltage Range
Deterministic Jitter
Random Jitter
10
1200
14
11
30
psp-p
25
15
ps
RMS
8
80
80
175
100
150
100
4.4
1
300
150
300
150
MAX3265/MAX3765 (Note 6)
MAX3268/MAX3768 (Note 5)
MAX3269 (Note 6)
Data Output Edge Speed
ps
LOS Hysteresis
(Notes 2, 7)
2.5
dB
µs
LOS Assert/Deassert Time
(Notes 7, 8)
MAX3264/MAX3268/MAX3768
MAX3265/MAX3269/MAX3765
MAX3264/MAX3268/MAX3768
MAX3265/MAX3269/MAX3765
1.20
2.20
2.6
4.8
4.5
8.5
Low LOS Assert Level
R
R
= 2.5kΩ
= 2.5kΩ
mV
mV
TH
TH
Low LOS Deassert Level
2
_______________________________________________________________________________________
+3 .0 V t o +5 .5 V, 1 .2 5 Gb p s /2 .5 Gb p s
Lim it in g Am p lifie rs
ELECTRICAL CHARACTERISTICS (continued)
(Data outputs terminated per Figure 1, V = +3.0V to +5.5V, T = 0°C to +70°C. Typical values are at V = +3.3V, T = +25°C,
CC
A
CC
A
unless otherwise noted.) (Note 1)
PARAMETER
CONDITIONS
MIN
5.6
TYP
MAX
UNITS
MAX3264/MAX3268/MAX3768
MAX3265/MAX3269/MAX3765
MAX3264/MAX3268/MAX3768
MAX3265/MAX3269/MAX3765
MAX3264/MAX3268/MAX3768
MAX3265/MAX3269/MAX3765
MAX3264/MAX3268/MAX3768
MAX3265/MAX3269/MAX3765
9
Medium LOS Assert Level
Medium LOS Deassert Level
High LOS Assert Level
R
R
R
R
= 7kΩ
mV
TH
TH
TH
TH
9.9
16
15
19.8
40.5
= 7kΩ
mV
mV
mV
27
9.4
21.6
41.5
35
= 20kΩ
= 20kΩ
18.0
High LOS Deassert Level
67
Squelch Input Current
0
80
400
103
µA
Differential Input Resistance
IN+ to IN-
97
100
150
230
Ω
MAX3264/MAX3268/MAX3768
MAX3265/MAX3269/MAX3765
Input-Referred Noise
CML Output Voltage
µV
RMS
LEVEL = open, R
LEVEL = GND, R
Referenced to V
= 50Ω
= 75Ω
550
1100
-1.025
-1.810
2.4
1200
1800
LOAD
LOAD
mV
1270
-0.880
+1.620
V
V
PECL Output High Voltage
PECL Output Low Voltage
LOS Output High Voltage
LOS Output Low Voltage
CC
Referenced to V
CC
I
= -30µA
V
LOS
I
= +1.2mA
0.4
V
LOS
Outputs AC-coupled
f < 2MHz
20
20
2
mV
dB
MHz
kHz
Output Signal When Squelched
Power-Supply Rejection Ratio
C
C
= open
= 0.1µF
AZ
AZ
Low-Frequency Cutoff
2
MAX3264/MAX3265/MAX3765
MAX3268/MAX3269/MAX3768
85
100
4
115
Output Resistance (Single Ended)
Ω
MAX3268
MAX3269
MAX3264
MAX3265
MAX3765
MAX3768
MAX3765
39
48
38
50
50
39
64
62
78
62
76
76
62
90
Power-Supply Current
Figure 2
mA
Output not
squelched
Output squelched
_______________________________________________________________________________________
3
+3 .0 V t o +5 .5 V, 1 .2 5 Gb p s /2 .5 Gb p s
Lim it in g Am p lifie rs
ELECTRICAL CHARACTERISTICS—MAX3265EUE
(Data outputs terminated per Figure 1, V = +3.0V to +5.5V, T = -40°C to +85°C. Typical values are at V = +3.3V, T = +25°C,
CC
A
CC
A
unless otherwise noted.) (Note 1)
PARAMETER
Data Rate
CONDITIONS
MIN
TYP
MAX UNITS
2.5
Gbps
Input Voltage Range
Deterministic Jitter
10
1200
25
mV
(Notes 2, 3)
(Notes 2, 4)
(Note 6)
11
8
ps
p-p
Random Jitter
ps
RMS
Data Output Edge Speed
LOS Hysteresis
100
4.4
1
155
ps
(Notes 2, 7)
(Notes 7, 8)
2.2
2.20
9.9
dB
µs
LOS Assert/Deassert Time
Low LOS Assert Level
Low LOS Deassert Level
Medium LOS Assert Level
Medium LOS Deassert Level
High LOS Assert Level
High LOS Deassert Level
Squelch Input Current
Differential Input Resistance
Input-Referred Noise
R
R
R
R
R
R
= 2.5kΩ
= 2.5kΩ
= 7kΩ
4.8
8.5
16
mV
mV
mV
mV
mV
mV
µA
Ω
TH
TH
TH
TH
TH
TH
13.6
43.0
= 7kΩ
27
= 20kΩ
= 20kΩ
18.0
41.5
67
111
400
103
0
80
IN+ to IN-
97
100
230
µV
RMS
LEVEL = open, R
LEVEL = GND, R
= 50Ω
550
1100
2.4
1200
1800
LOAD
CML Output Voltage
mV
= 75Ω
1270
LOAD
LOS Output High Voltage
LOS Output Low Voltage
I
= -30µA
V
V
LOS
I
= +1.2mA
0.450
LOS
Output Signal When Squelched
Power-Supply Rejection Ratio
Outputs AC-coupled
f < 2MHz
20
20
2
mV
dB
MHz
kHz
Ω
C
C
= open
= 0.1µF
AZ
AZ
Low-Frequency Cutoff
2
Output Resistance (single ended)
Power-Supply Current
85
100
50
115
76
Figure 2
mA
Note 1: Specifications for Input Voltage Range, LOS Assert/Deassert Levels, and CML Output Voltage refer to the total differential
peak-to-peak signal applied or measured. PECL output voltages are absolute (single-ended) voltages measured at a single
output.
Note 2: Input edge speed is controlled using four-pole, lowpass Bessel filters with bandwidth approximately 75% of the maximum
data rate.
Note 3: Deterministic jitter is measured with a K28.5 pattern (0011 1110 1011 0000 0101). Deterministic jitter is the peak-to-peak
deviation from ideal time crossings, measured at the zero-level crossings of the differential output per ANSI X3.230,
Annex A.
Note 4: Random jitter is measured with the minimum input signal applied after filtering with a four-pole, lowpass, Bessel filter (fre-
quency bandwidth at 75% of the maximum data rate). For Fibre Channel and Gigabit Ethernet applications, the peak-to-
peak random jitter is 14.1-times the RMS random jitter.
Note 5: Input signal applied after a 933MHz Bessel filter.
Note 6: Input signal applied after a 1.8GHz Bessel filter.
Note 7: Input for LOS assert/deassert and hysteresis tests is a repeating K28.5 pattern. Hysteresis is defined as:
20log (V
/ V
).
LOS-DEASSERT
LOS-ASSERT
Note 8: Response time to a 10dB change in input power.
4
_______________________________________________________________________________________
+3 .0 V t o +5 .5 V, 1 .2 5 Gb p s /2 .5 Gb p s
Lim it in g Am p lifie rs
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(T = +25°C, unless otherwise noted.)
A
MAX3265EUE
LOS HYSTERESIS vs. TEMPERATURE
OUTPUT VOLTAGE
vs. INPUT VOLTAGE
1700
MAX3264
LOS HYSTERESIS vs. TEMPERATURE
6.5
6.0
5.5
5.0
4.5
4.0
3.5
6.5
6.0
5.5
5.0
4.5
4.0
3.5
1500
MAX3264/MAX3268
1300
1100
R
= 4.6kΩ
TH
MAX3265/MAX3269/MAX3765
900
R
TH
= 7kΩ
700
500
300
R
TH
= 25kΩ
R
TH
= 16kΩ
-40
-15
10
35
60
85
0
2
4
6
8
10
12
0
10
20
30
40
50
60
70
TEMPERATURE (°C)
INPUT VOLTAGE (mV)
TEMPERATURE (°C)
MAX3265/MAX3269/MAX3765
DETERMINISTIC JITTER
vs. INPUT AMPLITUDE
MAX3264/MAX3268/MAX3768
RANDOM JITTER
MAX3264/MAX3268/MAX3768
DETERMINISTIC JITTER
vs. INPUT AMPLITUDE
vs. INPUT AMPLITUDE
30
16
14
12
10
8
30
25
20
15
10
5
25
20
15
10
5
6
4
2
0
0
0
0
200
400
600
800 1000 1200
0
10
20
30
40
50
0
200
400
600
800 1000 1200
INPUT AMPLITUDE (mV)
INPUT AMPLITUDE (mV)
INPUT AMPLITUDE (mV)
MAX3268/MAX3768
DATA OUTPUT EYE DIAGRAM
(MINIMUM INPUT)
MAX3265/MAX3269/MAX3765
RANDOM JITTER
LOSS OF SIGNAL WITH SQUELCH
vs. INPUT AMPLITUDE
8
7
6
5
4
3
2
1
0
V
IN
V
OUT
300mV/div
V
LOS
200ps/div
0
10
20
30
40
50
500ns/div
INPUT AMPLITUDE (mV)
_______________________________________________________________________________________
5
+3 .0 V t o +5 .5 V, 1 .2 5 Gb p s /2 .5 Gb p s
Lim it in g Am p lifie rs
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(T = +25°C, unless otherwise noted.)
A
MAX3265/MAX3765
MAX3264
MAX3264
DATA OUTPUT EYE DIAGRAM
2.5Gbps (MINIMUM INPUT)
DATA OUTPUT EYE DIAGRAM AT
1.25Gbps (MINIMUM INPUT)
DATA OUTPUT EYE DIAGRAM AT
1.25Gbps (MAXIMUM INPUT)
150mV/div
50mV/div
150mV/div
100ps/div
200ps/div
200ps/div
MAX3265/MAX3765
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
DATA OUTPUT EYE DIAGRAM
2.5Gbps (MAXIMUM INPUT)
OUTPUT VSWR vs. FREQUENCY
4.0
3.5
3.0
2.5
2.0
1.5
1.0
25
20
15
10
5
150mV/div
0
100ps/div
100k
1M
10M
100M
1G
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (Hz)
FREQUENCY (GHz)
COMMON-MODE REJECTION RATIO
vs. FREQUENCY
MAX3264
LOSS-OF-SIGNAL THRESHOLD vs. R
MAX3265/MAX3765
LOSS-OF-SIGNAL THRESHOLD vs. R
TH
TH
60
50
40
30
20
10
0
40
35
30
25
20
15
10
5
55
50
45
40
35
30
25
20
15
10
5
MAX3268/MAX3768
MAX3265/MAX3765
0
1M
10M
100M
1G
10G
0
5
10
15
R
20
25
30
35
0
5
10
15
(kΩ)
20
25
30
FREQUENCY (Hz)
(kΩ)
R
TH
TH
6
_______________________________________________________________________________________
+3 .0 V t o +5 .5 V, 1 .2 5 Gb p s /2 .5 Gb p s
Lim it in g Am p lifie rs
P in De s c rip t io n
PIN
NAME
FUNCTION
µMAX
TSSOP
1, 4
2
3, 6
4
GND
IN+
IN-
Supply Ground
Noninverted Input Signal
Inverted Input Signal
3
5
Loss-of-Signal Threshold. A resistor connected from this pin to ground sets the
input signal level at which the loss-of-signal (LOS) output(s) is asserted. Refer to
Typical Operating Characteristics and Design Procedure.
5
6
8
9
TH
Inverted Loss-of-Signal Output. LOS is high when the level of the input signal is
above the preset threshold set by the TH input. LOS is asserted low when the
signal level drops below the threshold.
LOS
7, 10
11, 14
12
V
Supply Voltage
CC
8
9
OUT-
OUT+
Inverted Data Output
Noninverted Data Output
13
Offset-Correction-Loop Capacitor. A capacitor connected between this pin and
CAZ2 extends the time constant of the offset correction loop.
—
—
1
2
CAZ1
CAZ2
Offset-Correction-Loop Capacitor. A capacitor connected between this pin and
CAZ1 extends the time constant of the offset correction loop. Refer to Design
Procedure.
Output Current Level. When this pin is not connected, the CML output current is
approximately 16mA. When this pin is connected to ground, the output current
increases to approximately 20mA. (In the MAX3265CUB/MAX3765CUB, LEVEL is
internally connected to ground.)
—
—
7
LEVEL
LOS
Noninverted Loss-of-Signal Output. LOS is low when the level of the input signal
is above the preset threshold set by the TH input. LOS asserts high when the sig-
nal level drops below the threshold.
10
Squelch Input. The squelch function is disabled when SQUELCH is not connected
or is set to a TTL low level. When SQUELCH is set to a TTL high level and LOS is
asserted, the data outputs, OUT+, and OUT-, are forced to static levels. See sec-
tions PECL Output Buffer and CML Output Buffer for more information. (In the
MAX3265/MAX3268/MAX3269 10-pin µMAX, SQUELCH is not connected. In the
—
15
SQUELCH
N.C.
MAX3765/MAX3768, SQUELCH is internally connected to V .)
CC
—
16
No Connection
Exposed
Paddle
Ground. The exposed paddle must be soldered to the circuit–board ground for
proper thermal performance.
EP
EP
_______________________________________________________________________________________
7
+3 .0 V t o +5 .5 V, 1 .2 5 Gb p s /2 .5 Gb p s
Lim it in g Am p lifie rs
V
CC
V
CC
V
CC
V
CC
R
300Ω
R
100Ω
TERM
TERM
300Ω
100Ω
100Ω
100Ω
100Ω
100Ω
C
OUT
C
OUT
2 x R
2 x R
LOAD
LOAD
150Ω
100Ω
C
OUT
C
OUT
MAX3264
MAX3265
MAX3765
MAX3264
MAX3265
MAX3765
(b) MAX3264/MAX3265/MAX3765 WITH 75Ω TERMINATION
(a) MAX3264/MAX3265/MAX3765 WITH 50Ω TERMINATION
V
CC
MAX3268
MAX3269
MAX3768
OUT-
OUT+
R
50Ω
TERM
50Ω
V
CC
- 2V
(c) MAX3268/MAX3269/MAX3768 OUTPUT TERMINATION
Figure 1. Data Output Termination
8
_______________________________________________________________________________________
+3 .0 V t o +5 .5 V, 1 .2 5 Gb p s /2 .5 Gb p s
Lim it in g Am p lifie rs
V
CC
I
CC
I
OUT
100Ω
100Ω
MAX3264CUE: OPEN
MAX3265CUE: OPEN
SQUELCH MAX3265CUB: GND (INTERNAL)
MAX3765CUB: V (INTERNAL)
CC
CONTROL
MAX3264CUE: OPEN
MAX3265CUE: OPEN
MAX3265CUB: GND (INTERNAL)
MAX3765CUB: GND (INTERNAL)
MAX3264
MAX3265
MAX3765
LEVEL
R
TH
2.5kΩ
(a) CML SUPPLY CURRENT (I
)
CC
V
CC
I
CC
OUT+
OUT-
OPEN
OPEN
MAX3268
MAX3269
MAX3768
R
TH
2.5kΩ
(b) PECL SUPPLY CURRENT (I
)
CC
Figure 2. Power-Supply Current Measurement
_______________________________________________________________________________________
9
+3 .0 V t o +5 .5 V, 1 .2 5 Gb p s /2 .5 Gb p s
Lim it in g Am p lifie rs
RMS P o w e r De t e c t w it h
Lo s s -o f-S ig n a l In d ic a t o r
_______________De t a ile d De s c rip t io n
Fig ure 3 is a func tiona l d ia g ra m of the MAX3264/
An RMS power detector looks at the signal from the
input buffer and compares it to a threshold set by the
TH resistor (see Typical Operating Characteristics for
appropriate resistor values). The signal-detect informa-
tion is provided to the LOS outputs, which are internally
terminated with 8kΩ (MAX3265/MAX3269/MAX3765) or
16kΩ (MAX3264/MAX3268/MAX3768) pullup resistors.
The LOS outputs meet TTL voltage specifications when
loaded with a resistor ≥ 4.7kΩ.
MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 lim-
iting amplifiers. A linear input buffer drives a multistage
limiting amplifier and an RMS power-detection circuit.
Offset correction with lowpass filtering ensures low
deterministic jitter. The output buffer produces a limited
output signal. The MAX3264/MAX3265/MAX3765 pro-
duc e a CML output, while the MAX3268/MAX3269/
MAX3768 produce a PECL-compatible output signal.
Schematics of these input/output circuits are shown in
Figures 4 through 7.
TH
V
CC
R
R
LOS
= 8kΩ (MAX3265/MAX3269/MAX3765)
= 16kΩ (MAX3264/MAX3268/MAX3768)
LOS
MAX3264
MAX3265
MAX3268
MAX3269
MAX3765
MAX3768
R
LOS
LOS
LOS
TTL
TTL
V
CC
POWER DETECT
WITH
COMPARATOR
R
LOS
GAIN
IN+
IN-
OUT+
OUT-
INPUT
BUFFER
OUTPUT
BUFFER
100Ω
SQUELCH
LEVEL
LOW-
PASS
CONTROL
OFFSET
100pF
CORRECTION
CAZ1
CAZ2
TOTAL GAIN = 55dB (MAX3264/MAX3268/MAX3768)
TOTAL GAIN = 49dB (MAX3265/MAX3269/MAX3765)
Figure 3. Functional Diagram
10 ______________________________________________________________________________________
+3 .0 V t o +5 .5 V, 1 .2 5 Gb p s /2 .5 Gb p s
Lim it in g Am p lifie rs
In p u t Bu ffe r
The input buffer is designed to accept input signals
from the MAX3266/MAX3267 transimpedance ampli-
fiers. The input buffer provides a 100Ω input imped-
ance between IN+ and IN-. Input VSWR is typically less
than 2.0 for frequencies less than 2GHz. DC-coupling
the inputs is not recommended; this prevents the DC
offset-correction circuitry from functioning properly.
CML Ou t p u t Bu ffe r
The MAX3264/MAX3265/MAX3765 CML output circuits
(Figure 7) provide high tolerance to impedance mis-
matches and inductive connectors. The output current
can be set to two levels. When the LEVEL pin is left
unconnected, output current is approximately 16mA.
Connecting LEVEL to ground sets the output current to
approximately 20mA.
The squelch function is enabled when the SQUELCH pin
Ga in S t a g e a n d Offs e t Co rre c t io n
The limiting amplifier provides approximately 55dB
(MAX3264/MAX3268/MAX3768) or 49dB (MAX3265/
MAX3269/MAX3765) of gain. This large gain makes the
amplifier susceptible to small DC offsets in the input sig-
nal. DC offsets as low as 1mV reduce the accuracy of
the power-detection circuit and may cause deterministic
jitter. A low-frequency feedback loop is integrated into
the limiting amplifier to reduce input offset, typically to
less than 100µV.
is set to a TTL-high level or connected to V . The
CC
squelch function holds OUT+ and OUT- at a static volt-
age whenever the input signal power drops below the
loss-of-signal threshold. In the 10-pin µMAX package of
the MAX3265/MAX3268/MAX3269, the SQUELCH func-
tion is left internally unconnected. In the MAX3765/
MAX3768, the SQUELCH function is always enabled by
internally connecting it to V . SQUELCH operation for
CC
the MAX3264/MAX3265 is described in Table 1.
An external capacitor connected between CAZ1 and
CAZ2, in parallel with internal capacitance, determines
the time constant of the offset-correction circuit. The off-
set-correction circuit requires an average data-input
mark density of 50% to prevent an increase in duty-
cycle distortion and to ensure low deterministic jitter.
Table 1.
VOLTAGE WHEN SQUELCHED
LEVEL PIN
OUT-
OUT+
Open
GND
V
- 100mV
- 100mV
V
CC
CC
V
V
- 100mV
CC
CC
In t e rn a l In p u t /Ou t p u t S c h e m a t ic s
V
CC
V
CC
500Ω
500Ω
0.25pF
IN+
110Ω
IN-
R
T
0.25pF
LOS
ESD
STRUCTURES
ESD
STRUCTURE
GND
R = 8kΩ (MAX3265/MAX3269/MAX3765)
T
R = 16kΩ (MAX3264/MAX3268/MAX3768)
T
GND
Figure 4. Input Circuit
Figure 5. LOS Output Circuit
______________________________________________________________________________________ 11
+3 .0 V t o +5 .5 V, 1 .2 5 Gb p s /2 .5 Gb p s
Lim it in g Am p lifie rs
V
CC
V
CC
ESD
STRUCTURES
ESD
STRUCTURES
100Ω
100Ω
OUT+
OUT-
OUT+
OUT-
GND
GND LEVEL
Figure 6. PECL Output Circuit
Figure 7. CML Output Circuit
The buffer’s output impedance is determined by the par-
allel combination of internal and external pullup resistors,
which are chosen to match the impedance of the trans-
mission line (Figure 1). The output buffer can be AC- or
DC-coupled to the load.
minimized when the input low-frequency cutoff (f ) is
IN
placed at a low frequency:
f
IN
= 1 / [2π(50)(C)]
For Fibre Channel, Gigabit Ethernet, or other applica-
tions using 8B/10B data coding, select (C
C
) ≥
IN, OUT
0.01µF, which provides f < 320kHz. For ATM/SONET
P ECL Ou t p u t Bu ffe r
The MAX3268/MAX3269/MAX3768 offer an industry-
standard PECL output. The PECL outputs should be
IN
or other applications using scrambled NRZ data, select
(C , C
) ≥ 0.1µF, which provides f < 32kHz.
IN OUT
IN
terminated to V
- 2V. Figure 6 shows the PECL out-
CC
S e le c t t h e Offs e t -Co rre c t io n Ca p a c it o r
(MAX3 2 6 4 /MAX3 2 6 5 TS S OP On ly)
To maintain stability, it is important to keep a one-
decade separation between fIN and the low-frequency
put circuit. The squelch function forces OUT+ to a high
level and OUT- to a low level when the input is below
the programmed LOS threshold. In the 10-pin µMAX,
SQUELCH is left unconnected.
cutoff (f ) associated with the DC-offset-correction cir-
OC
__________________De s ig n P ro c e d u re
cuit.
f
OC
= 75 / [2π 60k (C + 100pF)]
AZ
P ro g ra m t h e LOS As s e rt Th re s h o ld
The loss-of-signal threshold is programmed by external
-6
= 200 x 10 / (C + 100pF)
AZ
resistor R . See the LOS Threshold vs. R
the Typical Operating Characteristics.
graph in
TH
TH
For Fibre Channel, Gigabit Ethernet, or other applica-
tions using 8B/10B data coding, leave pins CAZ1, and
CAZ2 open (f
applications using scrambled NRZ data, select C
0.1µF, which typically provides f
= 2MHz). For ATM/SONET or other
OC
S e le c t t h e Co u p lin g Ca p a c it o rs
The coupling capacitors (C ) should be select-
ed to minimize the receiver’s deterministic jitter. Jitter is
≥
AZ
C
IN, OUT
= 2kHz.
OC
12 ______________________________________________________________________________________
+3 .0 V t o +5 .5 V, 1 .2 5 Gb p s /2 .5 Gb p s
Lim it in g Am p lifie rs
Ap p lic a t io n s In fo rm a t io n
V
MODULE
CC_
Op t ic a l Hys t e re s is
In an optical receiver, the electrical power change at
the limiting amplifier is 2x the optical power change.
HOST
V
HOST
CC_
GBIC MODULE
As an example, if a receiver’s optical input power (x)
increases by a factor of two, and the preamplifier is lin-
ear, then the voltage input to the limiting amplifier also
increases by a factor of two.
4.7kΩ
MAX3264
MAX3265
MAX3268
MAX3269
MAX3765
MAX3768
The optical power change is 10log(2x / x) = 10log(2) =
+3dB.
GENERAL-
PURPOSE
NPN
LOS
At the limiting amplifier, the electrical power change is:
2
2V
/ R
IN
(
)
IN
2
2
10log
= 10log(2 ) = 20log(2) = + 6dB
V
/ R
IN
IN
The MAX3264/MAX3265/MAX3268/MAX3269/MAX3765s’
typical voltage hysteresis is 4.4dB. This provides an opti-
cal hysteresis of 2.2dB.
Figure 8. Recommended GBIC LOS Circuit
GBIC Lo s s o f S ig n a l
In a GBIC application, the GBIC’s LOS output must be
high impedance when V
MODULE = GND. Figure 8
CC_
s hows the re c omme nd e d c irc uit to ma inta in hig h
impedance. ESD protection diodes on the MAX3264/
MAX3265/MAX3268/MAX3269/MAX3765/MAX3768
OUT+
470Ω
50Ω
MAX3268
MAX3269
MAX3768
LOS outp uts c a n b e turne d on whe n V
HOST >
CC_
V
CC_
MODULE.
P ECL Te rm in a t io n s
The standard PECL termination (50Ω to V - 2V) is
recommended for best performance and output char-
acteristics (see Figure 1). The data outputs operate at
high speed and should always drive transmission lines
with matched, balanced terminations.
OUT-
CC
470Ω
50Ω
DRIVING 50Ω TO GROUND
Figure 9 shows an alternate method for terminating the
data outputs. The technique provides approximately
8mA DC bias current, with a 45Ω AC load, for the out-
put termination. This technique is useful for viewing the
output on an oscilloscope or changing the PECL refer-
ence voltage.
Figure 9. Alternative PECL Termination
Wire Bo n d in g Dic e
For high current density and reliable operation, the
MAX3264/MAX3265/MAX3268/MAX3269 use gold met-
alization. Make connections to the dice with gold wire
only, and use ballbonding techniques (wedge bonding
is not recommended). Die-pad size is 4-mils square,
with a 6-mil pitch. Die thickness is 15 mils (0.375mm).
______________________________________________________________________________________ 13
+3 .0 V t o +5 .5 V, 1 .2 5 Gb p s /2 .5 Gb p s
Lim it in g Am p lifie rs
Typ ic a l Op e ra t in g Circ u it s (c o n t in u e d )
V
CC
V
CC
MAX3268CUB
MAX3269CUB
MAX3768CUB
C
IN
0.01µF
OUT+
OUT-
IN+
IN-
100Ω
MAX3266
MAX3267
C
IN
0.01µF
50Ω
50Ω
LOS
TH
R
TH
V
CC
- 2V
SIGNAL DETECT
Ord e rin g In fo rm a t io n (c o n t in u e d )
P in Co n fig u ra t io n s
PART
TEMP RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
10 µMAX-EP*
10 µMAX-EP*
Dice**
MAX3268CUB
MAX3268CUB+
MAX3268C/D
MAX3269CUB
MAX3269CUB+
MAX3269C/D
MAX3765CUB
MAX3765CUB+
MAX3768CUB
MAX3768CUB+
TOP VIEW
CAZ1
CAZ2
GND
IN+
1
2
3
4
5
6
7
8
16 N.C.
15 SQUELCH
10 µMAX-EP*
10 µMAX-EP*
Dice**
14
V
CC
MAX3264
MAX3265
13 OUT+
12 OUT-
IN-
10 µMAX-EP*
10 µMAX-EP*
10 µMAX-EP*
10 µMAX-EP*
GND
LEVEL
TH
11
V
CC
10 LOS
9
LOS
TSSOP
+Denotes lead-free package.
*EP = Exposed paddle.
NOTE: EXPOSED PADDLE IS GROUND.
**Dice are designed to operate from 0°C to +70°C, but are tested
and guaranteed only at T = +25°C.
A
GND
IN+
IN-
1
2
3
4
5
10
9
V
CC
OUT+
OUT-
MAX3265
MAX3268
MAX3269
MAX3765
MAX3768
8
GND
TH
7
V
CC
6
LOS
µMAX
14 ______________________________________________________________________________________
+3 .0 V t o +5 .5 V, 1 .2 5 Gb p s /2 .5 Gb p s
Lim it in g Am p lifie rs
S e le c t o r Gu id e
DATA RATE
(Gbps)
PIN-
PACKAGE
SQUELCH
FUNCTION
CML OUTPUT
LEVEL
PART
OUTPUT
CML
MAX3264
MAX3265
1.25
16 TSSOP-EP
16 TSSOP-EP
10 µMAX-EP
10 µMAX-EP
10 µMAX-EP
10 µMAX-EP
10 µMAX-EP
Selectable
Selectable
Disabled
Disabled
Disabled
Enabled
Selectable
Selectable
Maximum*
N/A
CML
2.5
MAX3268
MAX3269
MAX3765
MAX3768
PECL
PECL
CML
1.25
2.5
N/A
2.5
Maximum*
N/A
PECL
1.25
Enabled
*LEVEL pin grounded
Ch ip To p o g ra p h ie s
MAX3264/MAX3265/MAX3765
MAX3268/MAX3269/MAX3768
N.C.
CAZ1
N.C.
CAZ1
CAZ2
GND
SQUELCH
CAZ2
GND
SQUELCH
V
CC
V
CC
0.061"
IN+
IN-
OUT+
OUT-
0.061"
IN+
IN-
OUT+
OUT-
(1.55mm)
(1.55mm)
V
CC
GND
V
CC
GND
LEVEL
LOS
LOS
LOS
TH
N.C.
LOS
TH
N.C.
0.061"
(1.55mm)
0.061"
(1.55mm)
MAX3264/MAX3265/MAX3765
TRANSISTOR COUNT: 726
MAX3268/MAX3269/MAX3768
TRANSISTOR COUNT: 728
SUBSTRATE CONNECTED TO GND
______________________________________________________________________________________ 15
+3 .0 V t o +5 .5 V, 1 .2 5 Gb p s /2 .5 Gb p s
Lim it in g Am p lifie rs
P a c k a g e In fo rm a t io n
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
e
4X S
10
10
INCHES
MAX
MILLIMETERS
MAX
1.10
0.15
0.95
3.05
3.00
3.05
3.00
5.05
0.70
DIM MIN
MIN
-
A
-
0.043
0.006
0.037
0.120
0.118
0.120
0.118
0.199
A1
A2
D1
D2
E1
E2
H
0.002
0.030
0.116
0.114
0.116
0.114
0.187
0.05
0.75
2.95
2.89
2.95
2.89
4.75
0.40
H
0 0.50±0.1
0.6±0.1
L
0.0157 0.0275
0.037 REF
L1
b
0.940 REF
0.007
0.0106
0.177
0.270
0.200
1
1
e
0.0197 BSC
0.500 BSC
0.6±0.1
c
0.0035 0.0078
0.0196 REF
0.090
BOTTOM VIEW
0.498 REF
S
α
TOP VIEW
0°
6°
0°
6°
D2
E2
GAGE PLANE
A2
c
A
E1
b
L
α
A1
D1
L1
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0061
I
1
16 ______________________________________________________________________________________
+3 .0 V t o +5 .5 V, 1 .2 5 Gb p s /2 .5 Gb p s
Lim it in g Am p lifie rs
P a c k a g e In fo rm a t io n (c o n t in u e d )
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, TSSOP, 4.40 MM BODY
EXPOSED PAD
1
21-0108
D
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
17 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX3264CUE-T
Telecom Circuit, 1-Func, Bipolar, PDSO16, 4.40 MM, EXPOSED PAD, MO-153ABT, TSSOP-16
MAXIM
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