MAX32651GWE+ [MAXIM]
Microcontroller,;
| 型号： | MAX32651GWE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Microcontroller, 微控制器 |
| 文件： | 总59页 (文件大小：1181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Click here for production status of specific part numbers.
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with
3MB Flash and 1MB SRAM
General Description
Benefits and Features
DARWIN is a new breed of low-power microcontrollers
built to thrive in the rapidly evolving Internet of Things
(IoT). They are smart, with the biggest memories in their
class and a massively scalable memory architecture. They
run forever, thanks to wearable-grade power technology.
They are also tough enough to withstand the most ad-
vanced cyberattacks. DARWIN microcontrollers are de-
signed to run any application you can imagine—in places
where you wouldn’t dream of sending other microcon-
trollers.
● Ultra-Efficient Microcontroller for Battery-Powered
Applications
• 120MHz Arm Cortex-M4 Processor with FPU
• SmartDMA Provides Background Memory
Transfers with Programmable Data Processing
• 120MHz High-Speed and 50MHz Low-Power
Oscillators
• 7.3728MHz Low-Power Oscillators
• 32.768kHz and RTC Clock (Requires External
Crystal)
• 8kHz Always-On Ultra-Low Power Oscillator
• 3MB Internal Flash, 1MB Internal SRAM
• 104μW/MHz Executing from Cache at 1.1V
• Five Low Power Modes: Active, Sleep, Background,
Deep Sleep, and Backup
Generation UP microcontrollers are designed to handle
the increasingly complex applications demanded by to-
day’s advanced battery-powered devices and wireless
sensors. The MAX32650–MAX32652 are ultra-low-power
memory-scalable microcontrollers designed specifically
for high-performance, battery-powered applications. Thay
are based on an Arm® Cortex®-M4 with FPU CPU with
3MB flash and 1MB SRAM. Memory scalability is sup-
ported with multiple memory-expansion interfaces, includ-
ing a HyperBus™/XCCELA™ DDR interface and two SPI
execute in place (SPIX) interfaces. A secure digital inter-
face supports external high-speed memory cards, includ-
ing SD, SDIO, MMC, SDHC, and microSD®.
• 1.8V and 3.3V I/O with No Level Translators
● Scalable Cached External Memory Interfaces:
• 120MB/s HyperBus/XCCELA DDR Interface
• SPIXF/SPIXR for External Flash/RAM Expansion
• 240Mbps SDHC/eMMC/SDIO/microSD Interface
● Optimal Peripheral Mix Provides Platform Scalability
• 16-Channel DMA
• Three SPI Master (60MHz)/Slave (48MHz)
• One QuadSPI Master (60MHz)/Slave (48MHz)
• Up to Three 4Mbaud UARTs with Flow Control
Power management features provide five low power
modes for clock, peripheral, and voltage control. Individual
SRAM banks of 32KB, 96KB, or 1024KB (full retention)
can be retained with reduced power consumption. A
SmartDMA performs complex background processing
while the CPU is off to dramatically reduces overall power
consumption.
2
• Two 1MHz I C Master/Slave
2
• I S Slave
• Four-Channel 7.8ksps 10-Bit Delta-Sigma ADC
• USB 2.0 Hi-Speed Device Interface with PHY
• 16 Pulse Train Generators
• Six 32-Bit Timers with 8mA High Drive
• 1-Wire Master
The MAX32651 is a secure version with a trust protection
unit (TPU) providing a modular arithmetic accelerator
(MAA) for fast ECDSA, an AES Engine, TRNG, SHA-256
hash, and secure bootloader. A memory decryption in-
tegrity unit (MDIU) provides on-the-fly data decryption
(plain or executable) stored in external flash.
● Trust Protection Unit (TPU) for IP/Data Security
• Modular Arithmetic Accelerator (MAA), True
Random Number Generator (TRNG)
• Secure Nonvolatile Key Storage, SHA-256,
AES-128/192/256
The MAX32652 is
a high-density, 0.35mm pitch,
• Memory Decryption Integrity Unit, Secure Boot
ROM
140-bump WLP package targeted for tiny form factor prod-
ucts that require high I/O counts.
Ordering Information appears at end of data sheet.
Applications
● Sports Watches, Fitness Monitors
● Wearable Medical Patches, Portable Medical Devices
● Industrial Sensors, IoT
19-100220; Rev 6; 3/20
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Simplified Block Diagram
MAX32650/MAX32651/MAX32652
SECURE DIGITAL INTERFACE
120MHz
50MHz
HOST
ARM CORTEXTM. M4 WITH
FPU CPU
7.3728MHz
32.768kHz
8kHz
8 BYTE TX/
RX FIFOS
2 x I2C MASTER/
SLAVE
NVIC
32 BYTE
TX/RX
FIFOS
3 x 4-WIRE UART
TCK / SWCLK
JTAG SWD (SERIAL
WIRE DEBUG)
TMS / SWDIO
SHARED PAD
FUNCTIONS
TDO
TDI
MEMORY
32 BYTE
TX/RX
FIFOS
3 x SPI MASTER/
SLAVE (4 CS)
FLASH
3MB
TIMERS/PWM
CAPTURE/
COMPARE
SDHC
32 BYTE
TX/RX
FIFOS
QSPI MASTER/
SLAVE (4 CS)
POR,
BROWNOUT
MONITOR,
RSTN
SRAM
1MB
TM
HYPERBUS
SUPPLY VOLTAGE
MONITORS
TM
GPIO
XCCELA BUS
16KB
CACHE
QSPI FLASH XIP
MASTER
/SPECIAL
FUNCTION
UP TO 105
I2S
SPI
QSPI
QSPI XIP
I2C
16KB CACHE
32 BYTE
TX/RX
FIFOS
I2S SLAVE
V
DDIOH
V
DDIO
UART
V
CORE
VOLTAGE
REGULATION &
POWER CONTROL
STANDARD DMA
SMART DMA
1-WIRE
LCD CONTROLLER
1-WIRE MASTER
V
DDA
V
RTC
6 x 32-BIT TIMERS
16 × PULSE TRAIN ENGINES
24-BIT LCD CONTROLLER
EXTERNAL
INTERRUPTS
V
SS
V
SSA
32KOUT
32KIN
RTC
QSPI SRAM XIP
MASTER
16KB
2 × WATCHDOG TIMER
CRC 16/32
UNIQUE ID
CACHE
TM
HYPERBUS
DP
TM
HYP_CLKN
/XCCELA BUS
USB 2.0 Hi SPEED
CONTROLLER
DM
HYP_CLK
V
DDB
AIN0
AIN1
AIN2
AIN3
TRUST PROTECTION UNIT (TPU)
(MAX32651 ONLY)
÷5
÷5
MODULAR ARITHMETIC ACCELERATOR (MAA)
TRUE RANDOM NUMBER GENERATOR (TRNG)
10-BIT
ΣΔ ADC
V
V
V
V
V
V
DDB
÷4
÷2
DDA
SECURE NV KEY
SHA-256
CORE
RTC
÷4
DDIO
DDIOH
AES-128, -192, -256
÷4
SECURE BOOT ROM
MEMORY DECRYPTION INTEGRITY UNIT (MDIU)
19-100220
www.maximintegrated.com
Maxim Integrated | 2
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
140 WLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
96 WLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
144 TQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Characteristics—SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2
Electrical Characteristics—I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2
Electrical Characteristics—I S Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical Characteristics—SD/SDIO/SDHC/MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical Characteristics—HyperBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical Characteristics—1-Wire Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
140 WLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
96 WLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
144 TQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Arm Cortex-M4 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Internal Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Internal SRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Secure Digital Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Spansion HyperBus/XCCELA Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
General-Purpose I/O and Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Standard DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
SmartDMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Power Management Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Active Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Background Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
19-100220
www.maximintegrated.com
Maxim Integrated | 3
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
TABLE OF CONTENTS (CONTINUED)
Deep-Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Backup Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Real-Time Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
CRC Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Programmable Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
32-Bit Timer/Counter/PWM (TMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Pulse Train Engine (PT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Serial Peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Serial Peripheral Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2
I S Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
USB Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2
I C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
UART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Serial Peripheral Interface Execute in Place (SPIX) Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
1-Wire Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
24-Bit Color TFT Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Debug and Development Interface (SWD/JTAG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Trust Protection Unit (MAX32651 Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
True Random Number Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
MAA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
AES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SHA-256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Memory Decryption Integrity Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Secure Bootloader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Additional Documentation and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
GPIO and Alternate Function Matrix, 140 WLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
GPIO and Alternate Function Matrix, 96 WLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
GPIO and Alternate Function Matrix, 144 TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Pulse Oximeter and Heart Rate Monitor with BLE and GPS Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
19-100220
www.maximintegrated.com
Maxim Integrated | 4
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
LIST OF FIGURES
Figure 1. SPI Master Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 2. SPI Slave Mode Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2
Figure 3. I C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2
Figure 4. I S Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 5. SD/SDIO/SDHC/MMC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 6. HyperBus/XCCELA Bus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7. One-Wire Master Data Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8. Clocking Scheme Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 9. 32-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
19-100220
www.maximintegrated.com
Maxim Integrated | 5
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
LIST OF TABLES
Table 1. SPI Configuration Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 2. UART Configuration Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 3. GPIO and Alternate Function Matrix, 140 WLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 4. GPIO and Alternate Function Matrix, 96 WLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 5. GPIO and Alternate Function Matrix, 144 TQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
19-100220
www.maximintegrated.com
Maxim Integrated | 6
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Absolute Maximum Ratings
(All voltages with respect to V , unless otherwise noted.) ........
HYP_CLK, HYP_CLKN, P1.[21:18], P1.[16:11], P3.0 ..... -0.3V to
+0.3 not to exceed 1.98V
SS
V
V
V
V
V
................................................................... -0.3V to 1.21V
..................................................................... -0.3V to 1.98V
V
DDIO
CORE
V
V
V
V
pins (sink) ...............................................................100mA
DDA
DDIO
.................................................................... -0.3V to 1.98V
pins (sink).............................................................100mA
DDIO
DDIOH
DDIOH
.................................................................... -0.3V to 3.6V
..................................................................................100mA
....................................................................................100mA
SSA
...................................................................... -0.3V to 1.98V
RTC
SS
RSTN, GPIO (V
).................................-0.3V to V
+0.5V
+0.5V
+ 0.2V
Output Current (sink) by Any GPIO Pin ...............................25mA
Output Current (source) by Any GPIO Pin......................... -25mA
Continuous Package Power Dissipation TQFP (multilayer board)
DDIO
DDIO
GPIO (V
) ........................................-0.3V to V
DDIOH
DDIOH
32KIN, 32KOUT ......................................... -0.3V to V
RTC
AIN[1:0] ................................................................... -0.3V to 5.5V
T = +70°C (derate 45.5mW/°C above +70°C) .........2857.10mW
A
AIN[3:2] ...................................................... -0.3V to V + 0.2V
Operating Temperature Range...........................-40°C to +105°C
Storage Temperature Range ..............................-65°C to +150°C
Soldering Temperature .....................................................+260°C
DDA
V
DDB
....................................................................... -0.3V to 3.6V
DM, DP.................................................................... -0.3V to 3.6V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Package Information
140 WLP
Package Code
W1404A4+1
Outline Number
21-100219
Land Pattern Number
Thermal Resistance, Four-Layer Board:
Refer to Application Note 1891
Junction to Ambient (θ
)
35.13 °C/W
N/A
JA
Junction to Case (θ
)
JC
96 WLP
Package Code
Outline Number
W964A4+1
21-100240
Land Pattern Number
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ
Refer to Application Note 1891
)
33.61 °C/W
N/A
JA
Junction to Case (θ
)
JC
144 TQFP
Package Code
Outline Number
C144+1
21-0087
90-0144
Land Pattern Number
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ
)
28 °C/W
8 °C/W
JA
Junction to Case (θ
)
JC
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates
RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal
considerations, refer to www.maximintegrated.com/thermal-tutorial.
19-100220
www.maximintegrated.com
Maxim Integrated | 7
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Electrical Characteristics
(Limits are 100% tested at T = +25°C and T = +105°C. Limits over the operating temperature range and relevant supply voltage
A
A
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. General Purpose I/O
are only tested at T = +105°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER (Refer to the MAX32650 User Guide for sequencing requirements)
Supply Voltage, Core
Supply Voltage, Analog
Supply Voltage, RTC
Supply Voltage, GPIO
V
f
= 120MHz
0.99
1.71
1.71
1.71
1.1
1.8
1.8
1.8
1.21
1.89
1.89
1.89
V
V
V
V
CORE
SYS_CLK
V
DDA
V
RTC
V
DDIO
Supply Voltage, GPIO
(High)
V
1.71
1.8
3.6
V
DDIOH
Monitors V
Monitors V
Monitors V
Monitors V
0.835
1.67
1.67
1.67
CORE
DDA
Power-Fail Reset
Voltage
V
RST
V
RTC
DDIO
Power Fail Reset
Voltage
V
V
Monitors V
Monitors V
2.95
1.67
V
V
RST
DDB
Power-Fail Reset
Voltage
RST
DDIOH
Monitors V
Monitors V
Monitors V
0.594
1.52
1.17
CORE
DDA
Power-On Reset
Voltage
V
POR
V
DRV
V
V
RTC
RAM Data Retention
Voltage
0.81
Total current into V
pins, f
SYS_CLK
CORE
= 120MHz, V
mode, executing from cache, inputs tied
= 1.1V, CPU in Active
CORE
V
Dynamic
CORE
I
95
μA/MHz
CORE_DACT
Current, Active Mode
to V , V , or V , outputs
SS DDIO
DDIOH
source/sink 0mA
120MHz oscillator enabled, total current
into V pins, CPU in Active mode
CORE
0MHz execution, inputs tied to V
1500
790
SS,
V
DDIO
, or V
, outputs source/sink
DDIOH
0mA
7.3728MHz oscillator enabled, total
current into V pins, CPU in Active
V
Fixed Current,
CORE
I
μA
CORE_FACT
Active Mode
CORE
mode 0MHz execution, inputs tied to
V
, V , or V , outputs source/
SS DDIO
DDIOH
sink 0mA
19-100220
www.maximintegrated.com
Maxim Integrated | 8
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Electrical Characteristics (continued)
(Limits are 100% tested at T = +25°C and T = +105°C. Limits over the operating temperature range and relevant supply voltage
A
A
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. General Purpose I/O
are only tested at T = +105°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
120MHz oscillator enabled, total current
into V
pins, CPU in Active mode
DDA
0MHz execution, inputs tied to V
,
SS
348
V
DDIO
, or V
, outputs source/sink
DDIOH
0mA, V
and V
voltage monitors
DDA
CORE
enabled
7.3728MHz oscillator enabled, total
current into V pins, CPU in Active
V
Fixed Current,
DDA
I
μA
DDA_FACT
Active Mode
DDA
mode 0MHz execution, inputs tied to
39
V , V
SS DDIO
, or V
, outputs source/
DDIOH
sink 0mA, V
and V
voltage
DDA
CORE
monitors enabled
Total current into V
Sleep mode, standard DMA with two
channels active
pins, CPU in
CORE
V
Dynamic
CORE
I
114
1020
356
348
49
μA/MHz
CORE_DSLP
Current, Sleep Mode
f
V
= 120MHz, total current into
pins, CPU in Sleep mode,
SYS_CLK
CORE
standard DMA with two channels active
V
Fixed Current,
CORE
I
μA
CORE_FSLP
Sleep Mode
f
= 7.3728MHz, total current into
pins, CPU in Sleep mode,
SYS_CLK
V
CORE
standard DMA with two channels active
f
= 120MHz, total current into
pins, CPU in Sleep mode,
SYS_CLK
V
DDA
Standard DMA with two channels active
V
DDA
Fixed Current,
I
μA
DDA_FSLP
Sleep Mode
f
= 7.3728MHz, total current into
pins, CPU in Sleep mode, standard
SYS_CLK
V
DDA
DMA with two channels active
V
Dynamic
f
V
= 7.3728MHz, total current into
pins, CPU in Deep-sleep mode,
CORE
CORE
SYS_CLK
Current, Background
Mode
I
66
μA/MHz
CORE_DBKG
SmartDMA active
7.3728MHz oscillator enabled, total
V
Fixed Current,
CORE
I
current into V
pins, CPU in Deep-
330
70
μA
μA
nA
CORE_FBKG
CORE
Background Mode
sleep mode, SmartDMA active
V
Fixed Current,
CORE
I
Standby state with full data retention
Standby state with full data retention,
CORE_FDSL
Deep-Sleep Mode
V
DDA
Fixed Current,
I
V
CORE
and V voltage monitors
132
DDA_FDSL
DDA
Deep-Sleep Mode
enabled
Standby state with full data retention,
V = 1.8V, RTC enabled
RTC
V
RTC
Fixed Current,
I
540
30
nA
μA
nA
DDRTC_FDSL
Deep-Sleep Mode
V
CORE
Fixed Current,
I
No SRAM retention (0KB)
CORE_FBKU
Backup Mode
V
DDA
Fixed Current,
I
V
DDA
voltage monitor enabled
19-100220
132
DDA_FBKU
Backup Mode
www.maximintegrated.com
Maxim Integrated | 9
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Electrical Characteristics (continued)
(Limits are 100% tested at T = +25°C and T = +105°C. Limits over the operating temperature range and relevant supply voltage
A
A
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. General Purpose I/O
are only tested at T = +105°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RTC enabled, retention regulator off
540
V
Fixed Current,
RTC enabled, 32KB SRAM retained,
retention regulator on
RTC
I
720
156
575
nA
DDRTC_FBKU
Backup Mode
RTC disabled, retention regulator off
Sleep Mode Resume
Time
t
ns
μs
SLP_ON
DSL_ON
BKU_ON
Wake to f
Wake to f
9
DeepSleep Mode
Resume Time
LPCLK
HSCLK
t
18
Backup Mode Resume
Time
t
5
ms
USB
USB Supply Voltage
D+, D- Pin Capacitance
V
3.0
2.0
3.3
8
3.6
V
DDB
C
Pin to V
pF
IN_USB
SS
Driver Output
Resistance
45 ±
10%
R
Steady state drive
Ω
DRV
USB / FULL SPEED
Single-Ended Input High
Voltage (DP, DM)
V
V
V
IH_USB
Single-Ended Input Low
Voltage (DP, DM)
V
0.6
IL_USB
Output High Voltage
(DP, DM)
R = 1.5 kΩ from DP and DM to V , I
= -4mA
V
DDB
0.4
-
L
SS OH
V
V
DDB
V
OH_USB
Output Low Voltage
(DP, DM)
V
R = 1.5 kΩ from DP to V
L
, I = 4mA
DDB OL
V
SS
0.4
V
OL_USB
Differential Input
Sensitivity
V
|DP to DM|
0.2
0.8
4
V
DI
Common Mode Voltage
Range
V
Includes V range
2.5
20
V
CM
RF
DI
Transition Time (Rise/
Fall) D+, D- (Note 11)
t
C = 50pF
L
ns
kΩ
Pullup Resistor on
Upstream Ports
R
PU
1.05
1.5
1.95
USB / HI-SPEED
Hi-Speed Data Signaling
Common-Mode Voltage
Range
V
-50
+500
+10
mV
HSCM
Squelch detected
100
200
Hi-Speed Squelch
Detection Threshold
V
mV
mV
HSSQ
No squelch detected
Hi-Speed Idle Level
Output Voltage
V
-10
HSOI
19-100220
www.maximintegrated.com
Maxim Integrated | 10
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Electrical Characteristics (continued)
(Limits are 100% tested at T = +25°C and T = +105°C. Limits over the operating temperature range and relevant supply voltage
A
A
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. General Purpose I/O
are only tested at T = +105°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Hi-Speed Low Level
Output Voltage
V
HSOL
-10
+10
mV
Hi-Speed High Level
Output Voltage
V
400 ± 40
mV
mV
mV
HSOH
Chirp-J Output Voltage
(Differential)
900
±200
V
CHIRPJ
CHIRPK
Chirp-K Output Voltage
(Differential)
-700
±200
V
CLOCKS
System Clock
Frequency
f
t
0.256
120,000
kHz
ns
SYS_CLK
SYS_CLK
1/
System Clock Period
f
SYS_CL
K
High-Speed Oscillator
Frequency
f
f
Measured at +25ºC, 120MHz
120 ±1
50
MHz
MHz
MHz
KHz
kHz
HSCLK
Low-Power Oscillator
Frequency
f
LPCLK
7MHz Oscillator
Frequency
7.3728
8
7MCLK
Nano-Ring Oscillator
Frequency
f
NANO
32kHz watch crystal, C = 6pF, ESR <
L
70kΩ
RTC Input Frequency
f
32.768
32KIN
RTC Operating Current
RTC Power Up Time
I
Sleep or Active mode
0.39
250
μA
ms
RTC_ACTSLP
t
RTC_ ON
GENERAL-PURPOSE I/O
Input Low Voltage for All
GPIO
0.3 ×
V
V
V
selected as I/O supply
V
V
IL_VDDIO
DDIO
V
DDIO
Input Low Voltage for All
GPIO except P1.[21:18],
P1.[16:11], P3.0
0.3 ×
V
selected as I/O supply
IL_VDDIOH
DDIOH
V
DDIOH
Input Low Voltage for
RSTN
0.3 x
V
V
V
IL_RSTN
V
DDIO
Input High Voltage for
All GPIO
0.75 ×
V
V selected as I/O supply
DDIO
IH_VDDIO
V
DDIO
Input High Voltage for
All GPIO except
P1.[21:18], P1.[16:11],
P3.0
0.75 ×
V
V
selected as I/O supply
V
V
IH_VDDIOH
DDIOH
V
DDIOH
Input High Voltage for
RSTN
0.75 x
V
IH_RSTN
V
DDIO
19-100220
www.maximintegrated.com
Maxim Integrated | 11
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Electrical Characteristics (continued)
(Limits are 100% tested at T = +25°C and T = +105°C. Limits over the operating temperature range and relevant supply voltage
A
A
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. General Purpose I/O
are only tested at T = +105°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
selected as I/O supply, V
=
=
=
=
DDIO
DDIO
DDIO
DDIO
DDIO
0.2
0.4
1.71V, DS[1:0] = 00, I = 1mA
OL
V
DDIO
selected as I/O supply, V
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.4
0.4
0.4
0.4
0.4
0.4
1.71V, DS[1:0] = 01, I = 2mA
Output Low Voltage for
All GPIO
OL
V
V
OL_VDDIO
V
DDIO
selected as I/O supply, V
1.71V, DS[1:0] = 10, I = 4mA
OL
V
DDIO
selected as I/O supply, V
1.71V, DS[1:0] = 11, I = 8mA
OL
V
selected as I/O supply, V
DDIOH
DDIOH
DDIOH
DDIOH
DDIOH
= 1.71V, DS[1:0] = 00, I = 1mA
OL
V
selected as I/O supply, V
Output Low Voltage for
All GPIO except
P1.[21:18], P1.[16:11],
P3.0
DDIOH
= 1.71V, DS[1:0] = 01, I = 2mA
OL
V
V
mA
V
OL_VDDIOH
V
selected as I/O supply, V
DDIOH
= 1.71V, DS[1:0] = 10, I = 4mA
OL
V
selected as I/O supply, V
DDIOH
0.4
48
= 1.71V, DS[1:0] = 11, I = 8mA
OL
Combined I , All GPIO
OL
I
OL_TOTAL
V
selected as I/O supply, V
=
=
=
=
V
V
V
V
V
V
V
V
-
-
-
-
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
0.4
1.71V, DS[1:0] = 00, I = -1mA
OL
V
DDIO
selected as I/O supply, V
DDIO
0.4
1.71V, DS[1:0] = 01, I = -2mA
Output High Voltage for
All GPIO
OL
V
OH_VDDIO
V
DDIO
selected as I/O supply, V
DDIO
0.4
1.71V, DS[1:0] = 10, I = -4mA
OL
V
DDIO
selected as I/O supply, V
DDIO
0.4
1.71V, DS[1:0] = 00, I = -8mA
OL
V
selected as I/O supply, V
DDIOH
DDIOH
DDIOH
- 0.4
= 1.71V, DS[1:0] = 00, I = -1mA
OL
V
selected as I/O supply, V
DDIOH
Output High Voltage for
All GPIO except
P1.[21:18], P1.[16:11],
P3.0
DDIOH
DDIOH
- 0.4
= 1.71V, DS[1:0] = 01, I = -2mA
OL
V
V
OH_VDDIOH
V
selected as I/O supply, V
DDIOH
DDIOH
DDIOH
- 0.4
= 1.71V, DS[1:0] = 10, I = -8mA
OL
V
selected as I/O supply, V
DDIOH
DDIOH
DDIOH
- 0.4
= 1.71V, DS[1:0] = 11, I = -8mA
OL
Combined I , All GPIO
OH
I
-48
mA
mV
OH_TOTAL
Input Hysteresis
(Schmitt)
V
IHYS
300
V
= 1.89V, V
= 3.6V, V
DDIOH DDIOH
DDIO
Input Leakage Current
Low
I
selected as I/O supply, V = 0V, internal
pullup disabled
-1000
+1000
nA
IL
IN
19-100220
www.maximintegrated.com
Maxim Integrated | 12
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Electrical Characteristics (continued)
(Limits are 100% tested at T = +25°C and T = +105°C. Limits over the operating temperature range and relevant supply voltage
A
A
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. General Purpose I/O
are only tested at T = +105°C.)
A
PARAMETER
SYMBOL
CONDITIONS
= 1.89V, V = 3.6V, V
DDIOH
MIN
TYP
MAX
UNITS
V
DDIO
DDIOH
I
selected as I/O supply, V = 3.6V,
-1000
+1000
nA
IH
IN
internal pulldown disabled
Input Leakage Current
High
V
= 0V, V
= 0V, V
DDIOH DDIO
DDIO
I
-1
-2
+1
+2
OFF
selected as I/O supply, V < 1.89V
IN
μA
V
DDIO
= V
= 1.71V, V
DDIOH DDIO
I
IH3V
selected as I/O supply, V = 3.6V
IN
Input Pullup Resistor
TMS, TCK, TDI
R
25
25
kΩ
kΩ
PU_T
PU_R
Input Pullup Resistor
RSTN
R
R
Normal resistance
Highest resistance
25
1
kΩ
Input Pullup/Pulldown
Resistor for All GPIO
PU1
PU2
R
MΩ
FLASH MEMORY
t
Mass erase
Page erase
30
30
M_ERASE
Flash Erase Time
ms
μs
t
P_ERASE
Flash Programming
Time Per Word
t
60
PROG
Flash Endurance
Data Retention
10
10
kcycles
years
t
T = +85°C
A
RET
ADC (DELTA-SIGMA)
Resolution
10
Bits
MHz
μs
ADC Clock Rate
ADC Clock Period
f
0.1
8
ACLK
ACLK
t
1/f
ACLK
AIN[3:0], ADC_CHSEL = 0-3,
ADC_REFSEL = 1
V
0.05
+
SSA
V
BG
/2
AIN[3:0], ADC_CHSEL = 0-3,
ADC_REFSEL = 0
V
+
+
SSA
0.05
Input Voltage Range
Input Impedance
V
V
V
AIN
BG
AIN[1:0], ADC_CHSEL = 4-5,
ADC_REFSEL = 0
V
SSA
5.5
0.05
AIN[3:0], ADC_CHSEL=0-3, ADC active
AIN[1:0], ADC_CHSEL=4-5, ADC active
250
40
R
C
kΩ
AIN
AIN
Fixed capacitance to V
1
pF
fF
Analog Input
Capacitance
SSA
Dynamically switched capacitance
250
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
-2
-1
+2
+2
LSb
LSb
LSb
LSb
DNL
V
OS
±1
±2
Gain Error
GE
19-100220
www.maximintegrated.com
Maxim Integrated | 13
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Electrical Characteristics (continued)
(Limits are 100% tested at T = +25°C and T = +105°C. Limits over the operating temperature range and relevant supply voltage
A
A
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. General Purpose I/O
are only tested at T = +105°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ADC active, reference buffer enabled,
input buffer disabled
ADC Active Current
I
210
µA
ADC
Any powerup of: ADC clock or ADC bias
to CpuAdcStart
ADC Setup Time
t
10
µs
ADC_SU
tADC
ADC Output Latency
ADC Sample Rate
1025
t
ACLK
f
7.8
ksps
ADC
AIN0 or AIN1, ADC inactive or channel
not selected
0.01
0.01
ADC Input Leakage
I
ADC_LEAK
nA
AIN2 or AIN3, ADC inactive or channel
not selected
AIN0/AIN1 Resistor
Divider Error
ADC_CHSEL = 4 or 5, not including ADC
offset/gain error.
±2
1.2
15
LSb
V
Full Scale Voltage
V
ADC code = 0x3FF
FS
Bandgap Temperature
Coefficient
V
From +25ºC to +105ºC
ppm
TEMPCO
Electrical Characteristics—SPI
(Timing specifications are guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MASTER MODE
SPI Master Operating
Frequency
f
t
f
= f /2
SYS_CLK
60
MHz
ns
MCK
MCK(MAX)
SPI Master SCK Period
1/f
MCK
MCK
SCK Output Pulse-
Width High/Low
t
, t
t
t
t
/2
ns
MCH MCL
MCK
MCK
MCK
MOSI Output Hold Time
After SCK Sample Edge
t
/2
/2
ns
ns
MOH
MOSI Output Valid to
Sample Edge
t
MOV
MISO Input Valid to
SCK Sample Edge
Setup
t
5
ns
ns
MIS
MISO Input to SCK
Sample Edge Hold
t
t
/2
MIH
MCK
SLAVE MODE
SPI Slave Operating
Frequency
f
t
48
MHz
ns
SCK
SCK
SPI Slave SCK Period
1/f
SCK
SCK Input Pulse-Width
High/Low
t
, t
t
/2
SCK
SCH SCL
19-100220
www.maximintegrated.com
Maxim Integrated | 14
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Electrical Characteristics—SPI (continued)
(Timing specifications are guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SSx Active to First Shift
Edge
t
10
ns
SSE
MOSI Input to SCK
Sample Edge Rise/Fall
Setup
t
5
1
ns
ns
ns
SIS
MOSI Input from SCK
Sample Edge Transition
Hold
t
SIH
MISO Output Valid After
SCLK Shift Edge
Transition
t
5
SOV
SCK Inactive to SSx
Inactive
t
t
10
ns
μs
SSD
SSH
SSx Inactive Time
1/f
SCK
2
Electrical Characteristics—I C
(Timing specifications are guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STANDARD MODE
Standard mode, from V
to
IH(MIN)
Output Fall Time
t
150
ns
OF
V
IL(MAX)
SCL Clock Frequency
Low Period SCL Clock
High Time SCL Clock
f
0
100
kHz
μs
SCL
t
4.7
4.0
LOW
t
μs
HIGH
Setup Time for
Repeated Start
Condition
t
4.7
4.0
μs
μs
SU;STA
Hold Time for Repeated
Start Condition
t
t
HD;STA
Data Setup Time
Data Hold Time
300
10
ns
ns
SU;DAT
HD;DAT
t
Rise Time for SDA and
SCL
t
800
200
ns
ns
μs
R
Fall Time for SDA and
SCL
t
F
Setup Time for a Stop
Condition
t
t
4.0
4.7
SU;STO
Bus Free Time Between
a Stop and Start
Condition
t
μs
BUS
Data Valid Time
3.45
3.45
μs
μs
VD;DAT
VD;ACK
Data Valid Acknowledge
Time
t
19-100220
www.maximintegrated.com
Maxim Integrated | 15
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
2
Electrical Characteristics—I C (continued)
(Timing specifications are guaranteed by design and not production tested.)
PARAMETER
FAST MODE
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Fall Time
t
From V
to V
IL(MAX)
150
75
ns
ns
OF
IH(MIN)
Pulse Width Suppressed
by Input Filter
t
SP
SCL Clock Frequency
Low Period SCL Clock
High Time SCL Clock
f
0
400
kHz
μs
SCL
t
1.3
0.6
LOW
t
μs
HIGH
Setup Time for
Repeated Start
Condition
t
0.6
0.6
μs
μs
SU;STA
Hold Time for Repeated
Start Condition
t
t
HD;STA
Data Setup Time
Data Hold Time
125
10
ns
ns
SU;DAT
HD;DAT
t
Rise Time for SDA and
SCL
t
30
30
ns
ns
μs
R
Fall Time for SDA and
SCL
t
F
Setup Time for a Stop
Condition
t
t
0.6
1.3
SU;STO
Bus Free Time Between
a Stop and Start
Condition
t
μs
BUS
Data Valid Time
0.9
0.9
μs
μs
VD;DAT
VD;ACK
Data Valid Acknowledge
Time
t
FAST MODE PLUS
Output Fall Time
t
From V
to V
IL(MAX)
80
75
ns
ns
OF
IH(MIN)
Pulse Width Suppressed
by Input Filter
t
SP
SCL Clock Frequency
Low Period SCL Clock
High Time SCL clock
f
0
1000
kHz
μs
SCL
t
0.5
LOW
t
0.26
μs
HIGH
Setup Time for
Repeated Start
Condition
t
0.26
0.26
μs
μs
SU;STA
Hold Time for Repeated
Start Condition
t
t
HD;STA
Data Setup Time
Data Hold Time
50
10
ns
ns
SU;DAT
HD;DAT
t
Rise Time for SDA and
SCL
t
R
50
ns
19-100220
www.maximintegrated.com
Maxim Integrated | 16
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
2
Electrical Characteristics—I C (continued)
(Timing specifications are guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Fall Time for SDA and
SCL
t
30
ns
F
Setup Time for a Stop
Condition
t
0.26
0.5
μs
μs
SU;STO
Bus Free Time Between
a Stop and Start
Condition
t
BUS
Data Valid Time
t
0.45
0.45
μs
μs
VD;DAT
VD;ACK
Data Valid Acknowledge
Time
t
2
Electrical Characteristics—I S Slave
(Timing specifications are guaranteed by design and not production tested., T = -40°C to +105°C)
A
PARAMETER
Bit Clock Frequency
BCLK High Time
BCLK Low Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
96kHz LRCLK frequency
3.072
MHz
BCLK
t
0.5
0.5
25
1/f
1/f
WBCLKH
BCLK
BCLK
ns
LRCLK Setup Time
t
LRCLK_BLCK
Delay Time, BCLK to
SD (Output) Valid
t
12
ns
BCLK_SDO
Setup Time for SD
(Input)
t
6
3
ns
ns
SU_SDI
t
HD_SDI
Hold Time SD (Input)
Electrical Characteristics—SD/SDIO/SDHC/MMC
(T = -40°C to +105°C)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Clock Frequency in Data
Transfer Mode
f
0
f
/2
HSCLK
MHz
SDHC_CLK
1/
Clock Period
t
f
ns
ns
CLK
SDHC_C
LK
Clock Low Time
Clock High Time
Input Setup Time
Input Hold Time
Output Valid Time
Output Hold Time
t
7
7
5
1
5
6
WCL
t
WCH
t
ns
ns
ns
ns
ISU
t
IHLD
t
OVLD
t
OHLD
19-100220
www.maximintegrated.com
Maxim Integrated | 17
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Electrical Characteristics—HyperBus
(Timing specifications are guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
HYP_CLK, HYP_CLKN
Frequency
f
t
60
MHz
HYP_CLK
HYP_CLK
1/
HYP_CLK, HYP_CLKN
Period
f
ns
HYP_CL
K
HYP_CLK, HYP_CLKN
High Time
t
7
7
ns
ns
WHCKH
HYP_CLK, HYP_CLKN
Low Time
t
WHCKL
CS Setup to RWDS
RWDS Setup to CK
Dx Output Setup
Dx Output Hold
t
6
10
5
ns
ns
ns
ns
CSSU
t
RWDS_CK
t
t
OSU
t
3
OH
CS Hold After CK
Falling Edge
5
ns
ns
CSH
CS High Between
Transactions
t
15
CHSI
Dx Input Setup to
RWDS
t
4
2
ns
ns
ISU
Dx Input Hold
t
IHD
Electrical Characteristics—1-Wire Master
(Timing specifications are guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
60
8
MAX
UNITS
Standard
Overdrive
Standard
Write 0 Low Time
t
μs
W0L
6
Write 1 Low Time
t
Standard, long line mode
Overdrive
8
μs
μs
μs
W1L
1
Standard
70
85
9
Presence Detect
Sample
t
Standard, Long Line mode
Overdrive
MSP
Standard
15
24
3
Read Data Value
t
Standard, Long Line mode
Overdrive
MSR
Standard
10
20
4
Recovery Time
t
Standard, Long Line mode
Overdrive
μs
μs
REC0
Standard
480
58
Reset Time High
t
RSTH
Overdrive
19-100220
www.maximintegrated.com
Maxim Integrated | 18
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Electrical Characteristics—1-Wire Master (continued)
(Timing specifications are guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
600
70
MAX
UNITS
Standard
Overdrive
Standard
Overdrive
Reset Time Low
t
μs
RSTL
70
Time Slot
t
μs
SLOT
12
SHIFT SAMPLE SHIFT SAMPLE
SSx
(SHOWN ACTIVE LOW)
t
MCK
SCK
CKPOL/CKPHA
0/1 OR 1/0
t
MCH
t
MCL
SCK
CKPOL/CKPHA
0/0 OR 1/1
t
MOH
t
MOV
t
MLH
MOSI/SDIOx
(OUTPUT)
MSB
MSB-1
LSB
t
MIS
t
MIH
MISO/SDIOx
(INPUT)
MSB
MSB-1
LSB
Figure 1. SPI Master Mode Timing Diagram
19-100220
www.maximintegrated.com
Maxim Integrated | 19
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
SHIFT SAMPLE SHIFT SAMPLE
t
SSE
SSx
t
SSH
(SHOWN ACTIVE LOW)
t
SSD
t
SCK
SCK
CKPOL/CKPHA
0/1 OR 1/0
t
t
SCH
SCL
SCK
CKPOL/CKPHA
0/0 OR 1/1
t
SIS
t
SIH
MOSI/SDIOx
(INPUT)
MSB
MSB-1
LSB
t
SOV
t
SLH
MISO/SDIOx
(OUTPUT)
MSB
MSB-1
LSB
Figure 2. SPI Slave Mode Timing Diagram
STOP
START
START
REPEAT
START
t
BUS
SDA
t
OF
t
R
t
SU;STO
t
SP
t
t
HIGH
SU;STA
t
SU;DAT
SCL
t
HD;STA
t
t
HD;DAT
t
LOW
t
VD;ACK
VD;DAT
2
Figure 3. I C Timing Diagram
19-100220
www.maximintegrated.com
Maxim Integrated | 20
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
t
BLK
t
t
WBCLKH WBCLKL
BCLK
t
LRCLK_BCLK
LRCLK
t
BCLK_SDO
SD
(OUTPUT)
LSB
LSB
MSB
MSB
LSB
LSB
MSB
t
HD_SDI
t
SU_SDI
SD
(INPUT)
MSB
WORD N-1 RIGHT CHANNEL
WORD N LEFT CHANNEL
WORD N RIGHT CHANNEL
CONDITIONS: I2S_LJ = 0; I2S_MONO = 0;
CPOL = 0; CPHA = 0
2
Figure 4. I S Timing Diagram
t
CLK
t
t
WCL
WCH
SDHC_CLK
t
OVLD
t
OHLD
SDHC_DATx,
SDHC_CMD
(output)
NOT
VALID
NOT
VALID
tIHLD
t
ISU
SDHC_DATx,
SDHC_CMD
(input)
NOT
VALID
NOT
VALID
Figure 5. SD/SDIO/SDHC/MMC Timing Diagram
19-100220
www.maximintegrated.com
Maxim Integrated | 21
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
tCHSI
CSx
t
CSSU
t
CSH
t
t
WHCKL WHCKH
HYP_CLK,
HYP_CLKN
tRWDS_CK
t
CK
t
OH
Hi-Z
t
OSU
t
RWDS
OH
t
OSU
Dx
(output)
VALID VALID VALID VALID VALID VALID
VALID VALID VALID VALID
HOST DRIVES Dx AND RWDS
COMMAND-ADDRESS
t
IHD
HOST DRIVES Dx AND MEMORY DRIVES RWDS
Dx
(input)
VALID VALID VALID VALID
MEMORY DRIVES Dx AND RWDS
t
ISU
Figure 6. HyperBus/XCCELA Bus Timing Diagram
19-100220
www.maximintegrated.com
Maxim Integrated | 22
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
INITIALIZATION RESET AND PRESENCE-DETECT CYCLE
t
RSTH
t
MSP
OWM_IO
t
RSTL
WRITE TIME SLOTS
WRITE 1 SLOT
WRITE 0 SLOT
t
SLOT
t
SLOT
t
W0L
t
REC0
t
LOW1
OWM_IO
READ TIME SLOTS
READ 0 SLOT
READ 1 SLOT
t
SLOT
t
SLOT
t
W1L
t
REC0
t
W1L
OWM_IO
t
MSR
t
MSR
LEGEND
BOTH MASTER
ONE WIRE
MASTER ACTIVE
LOW
AND SLAVE
DEVICE ACTIVE
LOW
SLAVE DEVICE
ACTIVE LOW
RESISTOR
PULLUP
Figure 7. One-Wire Master Data Timing Diagram
19-100220
www.maximintegrated.com
Maxim Integrated | 23
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Pin Configurations
140 WLP
TOP VIEW (BUMP SIDE DOWN)
1
2
3
4
5
6
7
8
9
10
11
12
+
HYP_CLKN
P1.14
P0.24
P3.0
P1.5
HYP_CLK
A
B
VSS
VDDIOH
VDDIO
VSS
P1.18
P1.19
P2.22
P1.21
P1.20
P1.30
DP
DM
VDDB
P0.19
P0.21
P0.25
P0.20
P0.18
P1.4
P1.6
P1.11
P1.13
P1.16
VSS
P0.16
P0.17
P0.15
P1.1
P1.0
P1.3
P1.2
P1.10
P1.9
P1.12
P2.19
P1.15
P2.23
C
D
VSS
VSS
VCORE
P1.17
P1.23
P1.31
P0.30
P3.6
P3.5
P3.9
P3.8
P0.23
P0.13
P0.11
P0.14
P0.12
P1.7
P0.0
P1.8
P2.20
P2.18
P2.21
P0.31
E
F
VDDIO
P2.31
VDDIO
VSS
P1.25
P1.24
P0.29
P0.27
P3.4
P3.7
P0.10
P0.8
P0.9
P0.7
VDDIOH
VCORE
P2.16
P2.29
P2.15
P2.30
P2.27
P2.17
P2.24
P2.0
P2.1
G
H
VDDIOH
VDDA
VCORE
VSSA
P1.27
P1.28
P1.29
VSS
P0.26
P0.28
RSTN
P1.26
P0.22
P0.5
P0.1
P3.3
AIN2
AIN1
AIN0
VRTC
ANI3
P0.4
P0.2
P3.2
P3.1
P2.13
P2.28
P2.10
P2.11
P2.26
P2.25
P2.9
P2.8
P2.7
P2.6
VDDIO
P2.5
P2.4
P2.3
P2.2
J
K
L
VSS
P0.6
P0.3
32KOUT
32KIN
P2.14
P2.12
VSS
M
VDDIOH
140 WLP
19-100220
www.maximintegrated.com
Maxim Integrated | 24
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
96 WLP
TOP VIEW (BUMP SIDE DOWN)
1
2
3
4
5
6
7
8
9
10
+
D.N.C
D.N.C
P0.20
P1.8
P1.10
VDDIO
P2.23
P1.14
A
B
DP
VDDIOH
VDDB
VDDIO
VSS
P1.0
P0.21
P0.18
P1.6
P1.18
P1.21
P1.9
DM
VSS
P1.4
P1.5
P1.15
P1.16
P1.19
P1.25
P1.23
P1.30
VCORE
VSS
C
D
P1.2
P1.1
VSS
P3.6
P0.14
P3.9
P3.8
P3.7
P3.5
P3.4
P0.13
P0.11
P2.17
P0.17
P0.16
P1.3
P1.12
P1.11
P1.20
P0.29
P1.24
P0.26
P1.31
P0.27
E
F
VDDIOH
P0.19
VCORE
VDDA
P2.16
P2.12
VSS
P2.13
P2.5
P0.15
P2.4
P0.22
P2.18
P0.28
P1.29
P0.30
P1.27
AIN3
VSSA
G
H
P2.15
VRTC
AIN2
32KOUT
P2.14
J
AIN1
ANI0
32KIN
P2.9
P2.6
P2.3
P2.0
P2.2
P1.28
P1.26
RSTN
K
P1.13
P2.11
VDDIO
VSS
VDDIOH
96 WLP
19-100220
www.maximintegrated.com
Maxim Integrated | 25
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
144 TQFP
TOP VIEW
+
P2.16
1
2
3
4
5
6
7
8
9
108
107
106
N.C.
32KIN
P0.1
P0.2
32KOUT
105 N.C.
P0.3
VCORE
P0.4
104
AIN1
103 P0.26
AIN2
AIN3
P0.27
VDDA
VSSA
P3.4
102
101
100
99
P0.5
P0.6
VDDIOH
P0.22 10
VSS 11
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
P0.7 12
13
P3.7
P3.5
P3.8
P1.31
P1.24
P3.6
P3.9
P0.8
VCORE 14
15
P0.9
16
17
P2.30
P0.10
MAX32650/MAX32651
VDDIOH 18
19
20
P2.17
P2.18
VSS
VDDIO 21
VCORE
D.N.C
D.N.C
VSS
P0.11
P0.12
22
23
P0.23 24
N.C.
DM
25
26
27
P0.13
P0.14
VSS
N.C.
VSS
P0.15 28
VSS 29
VSS
P0.16 30
N.C.
DP
31
32
P0.17
P0.18
N.C.
VDDB
P1.22
N.C.
N.C.
VDDIO 33
P0.19 34
35
P0.20
P0.21 36
144 TQFP
Pin Description
PIN
NAME
FUNCTION
140 WLP
POWER
96 WLP
144 TQFP
Core Supply Voltage. This pin must be bypassed to V with a
SS
1.0μF capacitor as close as possible to the package.
H1, H4, D12
G1, C8
5, 14, 88
V
CORE
19-100220
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Maxim Integrated | 26
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Pin Description (continued)
PIN
NAME
FUNCTION
140 WLP
96 WLP
144 TQFP
1.8V Analog Supply Voltage. This pin must be bypassed to V
with 1.0μF and 0.01μF capacitors as close as possible to the
package.
SSA
H11
G10
99
V
V
DDA
USB Transceiver Supply Voltage. This pin must be bypassed to
with a 1.0μF capacitor as close as possible to the package.
B11
A7
B9
A5
76
21
DDB
V
SS
GPIO Supply Voltage. This pin must be bypassed to V with
SS
1.0μF and 0.01μF capacitors as close as possible to the package.
GPIO Supply Voltage. This pin must be bypassed to V with a
SS
E4, F1
M7
B1, K5
—
33, 55
126
V
DDIO
1.0μF and a 0.01μF capacitor as close as possible to the
package.
GPIO Supply Voltage. This pin must be bypassed to V with
SS
1.0μF and 0.01μF capacitors as close as possible to the package.
GPIO Supply Voltage, High. V
≥ V
. This pin must be
DDIO
DDIOH
A6
B5
9
bypassed to V with 1.0μF and 0.01μF capacitors as close as
SS
possible to the package.
GPIO Supply Voltage, High. V
≥ V
≥ V
. This pin must be
. This pin must be
DDIOH
DDIOH
DDIO
DDIO
G1
F1
18
V
DDIOH
bypassed to V
SS
GPIO Supply Voltage, High. V
G4, M6
M11
K4
54, 128
111
bypassed to V with 1.0μF and 0.01μF capacitors as close as
possible to the package.
SS
RTC Supply Voltage. This pin must be bypassed to V with a
SS
1.0μF capacitor as close as possible to the package.
H8
V
RTC
11, 27, 29,
47, 60, 80,
81, 85, 89,
119, 136
A4, A8, C11,
D1, D11, F4,
J1, M4, M9
B6, C1, C9,
D8, K7, J2
V
Digital Ground
SS
H12
G9
98
V
Analog Ground
SSA
RESET
Hardware Power Reset (Active-Low) Input. The device remains in
reset while this pin is in its active state. When the pin transitions to
its inactive state, the device performs a POR reset (resetting all
logic on all supplies except for real-time clock circuitry) and begins
L10
K8
114
RSTN
execution. This pin has an internal pullup to the V
supply.
DDIO
CLOCK
L12
32kHz Crystal Oscillator Input. Connect a 32kHz crystal between
32KIN and 32KOUT for RTC operation. Optionally, an external
clock source can be driven on 32KIN if the 32KOUT pin is left
unconnected.
J10
107
106
32KIN
K12
H10
32KOUT
32kHz Crystal Oscillator Output
GPIO AND ALTERNATE FUNCTIONS
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
F5
—
—
P0.0
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Maxim Integrated | 27
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Pin Description (continued)
PIN
NAME
FUNCTION
140 WLP
96 WLP
144 TQFP
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
L2
—
2
P0.1
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
K3
L1
—
—
—
—
—
—
—
—
—
E2
—
E1
D1
G4
3
P0.2
P0.3
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
4
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
J3
6
P0.4
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
K2
K1
H3
H2
G3
G2
F2
F3
E2
E3
D2
7
P0.5
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
8
P0.6
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
12
13
15
17
22
23
25
26
28
P0.7
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
P0.8
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
P0.9
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
P0.10
P0.11
P0.12
P0.13
P0.14
P0.15
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
19-100220
www.maximintegrated.com
Maxim Integrated | 28
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Pin Description (continued)
PIN
NAME
FUNCTION
140 WLP
96 WLP
144 TQFP
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
C1
F3
30
P0.16
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
C2
D3
E3
D2
F4
A2
C2
G5
—
31
32
P0.17
P0.18
P0.19
P0.20
P0.21
P0.22
P0.23
P0.24
P0.25
P0.26
P0.27
P0.28
P0.29
P0.30
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
B1
34
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
C3
35
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
B2
36
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
J2
10
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
E1
24
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
A2
—
40
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
B3
—
41
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
J10
H10
K10
G10
F10
F7
F8
G6
F6
G7
103
100
113
110
112
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
19-100220
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Maxim Integrated | 29
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Pin Description (continued)
PIN
NAME
FUNCTION
140 WLP
96 WLP
144 TQFP
General-Purpose I/O, Port 0. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
F8
—
61
P0.31
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
D4
C4
D5
C5
B4
A5
B5
E5
E6
D6
C6
B2
D3
C3
E4
C4
D4
B4
—
37
39
42
43
45
51
49
38
46
48
50
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P1.8
P1.9
P1.10
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
A3
B3
A4
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. This pin is connected to V
Table 4 and Table 5 GPIO and Alternate Function Matrix tables
for details.
only. See Table 3,
DDIO
B6
C7
F5
E5
52
53
P1.11
P1.12
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. This pin is connected to V
4 and Table 5 GPIO and Alternate Function Matrix tables for
only. See Table 3, Table
DDIO
details.
19-100220
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Maxim Integrated | 30
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Pin Description (continued)
PIN
NAME
FUNCTION
140 WLP
96 WLP
144 TQFP
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. This pin is connected to V
4 and Table 5 GPIO and Alternate Function Matrix tables for
only. See Table 3, Table
DDIO
B7
K2
56
P1.13
details.
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. This pin is connected to V
4 and Table 5 GPIO and Alternate Function Matrix tables for
details.
only. See Table 3, Table
DDIO
A11
C8
A9
C5
68
58
P1.14
P1.15
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. This pin is connected to V
4 and Table 5 GPIO and Alternate Function Matrix tables for
details.
only. See Table 3, Table
DDIO
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. This pin is connected to V
4 and Table 5 GPIO and Alternate Function Matrix tables for
details.
only. See Table 3, Table
DDIO
B8
E9
B9
D5
—
59
69
63
P1.16
P1.17
P1.18
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. This pin is connected to V
4 and Table 5 GPIO and Alternate Function Matrix tables for
details.
only. See Table 3, Table
DDIO
B7
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. This pin is connected to V
4 and Table 5 GPIO and Alternate Function Matrix tables for
details.
only. See Table 3, Table
DDIO
C9
C6
E6
B8
62
66
67
P1.19
P1.20
P1.21
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. This pin is connected to V
4 and Table 5 GPIO and Alternate Function Matrix tables for
details.
only. See Table 3, Table
DDIO
C10
B10
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. This pin is connected to V
4 and Table 5 GPIO and Alternate Function Matrix tables for
only. See Table 3, Table
DDIO
details.
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
—
F9
H9
G9
—
C7
E7
D6
75
70
92
72
P1.22
P1.23
P1.24
P1.25
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
19-100220
www.maximintegrated.com
Maxim Integrated | 31
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Pin Description (continued)
PIN
NAME
FUNCTION
140 WLP
96 WLP
144 TQFP
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
M10
J8
115
P1.26
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
J9
K9
L9
H7
J7
H6
D7
E8
J6
—
116
117
118
71
P1.27
P1.28
P1.29
P1.30
P1.31
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
D10
E10
G8
H8
M8
L8
General-Purpose I/O, Port 1. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
93
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
120
121
122
123
124
125
127
129
130
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
K6
J5
H4
H3
J4
—
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
K8
J8
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
L7
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
K7
J7
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
—
19-100220
www.maximintegrated.com
Maxim Integrated | 32
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Pin Description (continued)
PIN
NAME
FUNCTION
140 WLP
96 WLP
144 TQFP
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
L6
J3
131
P2.9
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
L5
M5
L4
—
K3
H2
G3
J1
134
132
137
140
143
144
1
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
P2.16
P2.17
P2.18
P2.19
P2.20
P2.21
P2.22
P2.23
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
J5
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
K4
H5
J4
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
H1
G2
F2
H5
—
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
G7
F7
D7
E7
E8
D9
D8
19
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
20
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
—
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
—
—
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
—
—
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
—
—
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
A6
57
19-100220
www.maximintegrated.com
Maxim Integrated | 33
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Pin Description (continued)
PIN
NAME
FUNCTION
140 WLP
96 WLP
144 TQFP
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
H7
—
—
P2.24
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
K6
J6
—
—
—
—
—
—
—
133
135
—
P2.25
P2.26
P2.27
P2.28
P2.29
P2.30
P2.31
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
H6
K5
G5
G6
F6
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
139
—
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
16
General-Purpose I/O, Port 2. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
—
General-Purpose I/O, Port 3. Most port pins have multiple special
functions. This pin is connected to V
4 and Table 5 GPIO and Alternate Function Matrix tables for
only. See Table 3, Table
DDIO
A3
—
44
P3.0
details.
General-Purpose I/O, Port 3. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
M3
L3
—
—
138
141
142
97
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
General-Purpose I/O, Port 3. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
General-Purpose I/O, Port 3. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
M2
—
General-Purpose I/O, Port 3. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
G11
F11
E11
F9
E9
D9
General-Purpose I/O, Port 3. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
95
General-Purpose I/O, Port 3. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
91
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Maxim Integrated | 34
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Pin Description (continued)
PIN
NAME
FUNCTION
140 WLP
96 WLP
144 TQFP
General-Purpose I/O, Port 3. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
G12
F10
96
P3.7
General-Purpose I/O, Port 3. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
F12
E12
E10
D10
94
90
P3.8
P3.9
General-Purpose I/O, Port 3. Most port pins have multiple special
functions. See Table 3, Table 4 and Table 5 GPIO and Alternate
Function Matrix tables for details.
ANALOG INPUT PINS
L11
K11
J11
J12
K9
109
104
102
101
AIN0
AIN1
AIN2
AIN3
ADC Input 0. 5V-tolerant input.
ADC Input 1. 5V-tolerant input.
ADC Input 2
J9
H9
G8
ADC Input 3
HYPERBUS CLOCKS
A10
A9
—
65
64
HYP_CLK
HyperBus Positive Clock
—
HYP_CLKN HyperBus Negative Clock
USB
USB DM Signal. This bidirectional pin carries the negative
C12
B12
C10
B10
83
78
DM
DP
differential data or single-ended data. This pin is weakly pulled
high internally when the USB is disabled.
USB DP Signal. This bidirectional pin carries the positive
differential data or single-ended data. This pin is weakly pulled
high internally when the USB is disabled.
NO CONNECT
Do Not Connect. Internally connected. Do not make any electrical
connection to this pin, including power supply grounds.
—
A7, A8
—
86, 87
D.N.C.
N.C.
73, 74, 77,
79, 82, 84,
105, 108
—
No Connection. Not internally connected.
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Maxim Integrated | 35
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Detailed Description
The MAX32650–MAX32652 are low-power, mixed signal microcontrollers based on the Arm Cortex-M4 with FPU CPU,
operating at a maximum frequency of 120MHz. The devices feature five powerful and flexible power modes. A SmartDMA
performs complex background processing on data being transferred, from simple arithmetic to multiply/accumulate, while
the CPU is off. This function dramatically reduces overall power consumption compared to conventional solutions. This
allows, for example, an external display to be refreshed while most of the chip is powered off. Built-in dynamic clock
gating and firmware-controlled power gating allows the user to optimize power for the specific application.
Application code executes from an onboard 3MB program flash memory, with 1MB SRAM available for general
application use. A 16KB cache improves execution throughput. Additionally, a SPI execute in place (XIP) external
memory interface allows application code and data (up to 128MB) to be accessed from an external SPI flash and/or
SRAM memory device.
A 10-bit delta-sigma ADC is provided with a multiplexer front end for four external input channels (two of which are
5V tolerant) and six internal power supply monitoring channels. Dedicated divided supply input channels allow direct
monitoring of internal power supply voltages by the ADC. Built-in limit monitors allow converted input samples to be
compared against user-configurable high and low limits, with an option to trigger an interrupt and wake the CPU from a
low power mode if attention is required.
A wide variety of communications and interface peripherals are provided, including a Hi-Speed USB 2.0 device interface,
three master/slave SPI interfaces, one QuadSPI master/slave interface, three UART interfaces with flow control support,
2
2
two master/slave I C interfaces, I S bidirectional slave interface. A Cypress Spansion HyperBus interface and a XCCELA
bus interface provides support for HyperFLASH, HyperRAM and XCCELA PSRAM operating up to 120MB/s throughput
with access up to 512MB. A SD/SDIO/MMC interface running up to 60MB/s supporting media file storage. A 24-bit TFT
LCD controller provides color and monochrome display support.
The MAX32651 is a secure version of the MAX32650. It provides a trust protection unit (TPU) with encryption and
advanced security features. These features include a modular arithmetic accelerator (MAA) for fast ECDSA and
RSA-4096 computation. A hardware AES engine uses 128/192/256-bit keys. A memory decryption integrity unit (MDIU)
provides on-the-fly code or data decryption stored in external flash. A hardware TRNG and a hardware SHA-256 HASH
function are also provided. A secure bootloader authenticates applications before they are allowed to execute and update
firmware with confidentiality.
The MAX32652 is a high-density, 0.35mm pitch, 140-bump WLP targeted for tiny form factor products that require high I/
O counts.
Arm Cortex-M4 with FPU
The Arm Cortex-M4 with FPU combines high-efficiency signal processing functionality with flexible low-power operating
modes. The features of this implementation of the familiar Arm Cortex-M4 architecture include:
● Floating point unit (FPU)
● Memory protection unit
● Multilayer, 32-bit AHB matrix
● Full debug support level
• Debug access port (DAP)
• Breakpoints
• Flash patch
• Halting debug
• Development and debug interface
● NVIC support
• Programmable IRQ generation for each interrupt source
• Unique vectors for each interrupt channel
• 8 programmable priority levels support nesting and preemption
• External GPIO interrupts grouped by GPIO port
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Maxim Integrated | 36
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
● DSP supports single instruction multiple data (SIMD) path DSP extensions, providing:
• 4 parallel 8-bit add/sub
• 2 parallel 16-bit add/sub
• 2 parallel MACs
• 32- or 64-bit accumulate
• Signed, unsigned, data with or without saturation
Memory
Internal Flash Memory
3MB of internal flash memory provides nonvolatile storage of program and data memory.
Flash can be expanded through the SPIXF flash serial interface backed by 16KB of cache. The SPIXF flash interface can
address an additional 128MB.
Internal SRAM
The internal 1MB SRAM provides low-power retention of application information in all power modes except shutdown.
The SRAM can be divided into granular banks that create a flexible SRAM retention architecture. This data retention
feature is optional and configurable. This granularity allows the application to minimize its power consumption by only
retaining the most essential data.
SRAM can be expanded through the SPIXR SRAM serial interface backed by 16KB of cache. The SPIXR SRAM interface
can address an additional 512MB.
Secure Digital Interface
The secure digital interface (SDI) provides high-speed, high-density data storage capability for media files and large long-
term data logs. This interface supports eMMC, SD, SDHC, and SDXC memory devices at transfer rates up to 60MB/s.
The 7-pin interface (4 data, 1 clock, 1 command, 1 write-protect) supports the following specifications:
• SD Host Controller Standard Specification Version 3.00
• SDIO Card Specification Version 3.0
• SD Memory Card Specification Version 3.01
• SD Memory Card Security Specification Version 1.01
• MMC Specification Version 4.51
Spansion HyperBus/XCCELA Bus
The Spansion HyperBus/Xccela bus interface provides access to external Cypress Spansion HyperBus and XCCELA bus
memory products both SRAM and/or flash. This interface provides a means of high-speed execution from external SRAM
or flash allowing system expansion when internal memory resources are insufficient. Up to 512MB SRAM or 512MB flash
at a speed of up to 60MHz or 120MB/s is supported. It is a high-speed low-pin count interface that is memory-mapped into
the CPU memory space making access to this external memory as easy as accessing on-chip RAM. Data is transferred
over a high-speed, 8-bit bus. Slave memory devices are selected with two chip selects. HyperBus transfers are clocked
using a differential clock while XCCELA bus transfers use a single-ended clock. This interface supports 1.8V operation
only.
Features of the HyperBus/XCCELA bus interface include:
● Master/slave system
● 120MB/s maximum data transfer rate
● Double data rate (DDR): two data transfers per clock cycle
● Transparent bus operation to the processor
● 16KB write-through cache
● Two chip selects for two memory ports
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Maxim Integrated | 37
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
• Each port supports memories up to 512MB
● Addresses two external memories, one at a time
● Interfaces to HyperFlash, HyperRAM, and XCCELA PSRAM
● Zero wait state burst mode operation
● Low-power half sleep mode
• Puts the external memory device into low power mode while retaining memory contents
● Configurable timing parameters
Clocking Scheme
The high-frequency oscillator operates at a maximum frequency of 120MHz.
Optionally, 4 other oscillators can be selected depending upon power needs:
● 50MHz low-power oscillator
● 8kHz nano-ring oscillator
● 32.768kHz oscillator (external crystal required)
● 7.3728MHz oscillator
This clock is the primary clock source for the digital logic and peripherals. Select the 7.3728MHz internal oscillator to
optimize active power consumption. Using the 7.3727MHz oscillator allows UART communications to meet a ±2% baud
rate tolerance.
Wakeup is possible from either the 7.3728MHz internal oscillator or the high-frequency oscillator. The device exits power-
on reset using the the 50MHz oscillator.
An external 32.768kHz timebase is required when using the RTC.
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Maxim Integrated | 38
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
RTC
CALIBRATION
OUTPUT
32KCAL
ALWAYS-ON DOMAIN
XTAL DRIVER OR
EXTERNAL CLOCK
32KIN
32KIN BYPASS
4kHz
DIGITAL
INTERFACE
32.768kHz
32kHz
CRYSTAL
32K
OSC
REAL-TIME CLOCK
NANO-RING
~8kHz
32KOUT
POWER SEQUENCER
120MHz
GCR_CLK_CTRL.sysosc_sel
GCR_CLK_CTRL.sysclk_prescale
HIGH-SPEED
OSCILLATOR
50MHz
120MHz
50MHz
PRESCALER
CPU
LOW-POWER
OSCILLATOR
TPU
7.3728MHz
TRUST PROTECTION
UNIT CIRCUITRY
OSCILLATOR BAUD
RATE CLOCK
÷2
APB CLK
AHB CLK
GCR_PCLK_DIV.sdhcfrq
ADC
CLOCK
SCALER
÷4
÷2, 4
< 8MHz
CTRL
PHY
SMART
DMA
SD/SDIO/
MMC
UART
ADC
HI-SPEED USB 2.0
Figure 8. Clocking Scheme Diagram
General-Purpose I/O and Special Function Pins
Most general-purpose I/O (GPIO) pins share both a firmware-controlled I/O function and one or more special function
signals associated with peripheral modules. Pins can be individually enabled for GPIO or peripheral special function use.
Configuring a pin as a special function usually supersedes its use as a firmware-controlled I/O. Though this multiplexing
between peripheral and GPIO functions is usually static, it can also be done dynamically. The electrical characteristics of
a GPIO pin are identical whether the pin is configured as an I/O or special function, except where explicitly noted in the
electrical characteristics tables.
In GPIO mode, pins are logically divided into ports of 32 pins. Each pin of a port has an interrupt function that can be
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Maxim Integrated | 39
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
independently enabled, and configured as a level- or edge-sensitive interrupt. All GPIOs of a given port share the same
interrupt vector. Some packages do not have all of the GPIOs available.
When configured as GPIO, the following features are provided. The features can be independently enabled or disabled
on a per-pin basis.
● Configurable as input, output, bidirectional, or high impedance
● Optional internal pullup resistor or internal pulldown resistor when configured as input
● Exit from low-power modes on rising or falling edge
● Selectable standard- or high-drive modes
The MAX32650–MAX32652 provides up to 105 GPIO (140 WLP), 97 GPIO (144 TQFP), and 67 GPIO (96 WLP).
GPIOs, which have any HyperBus alternate functionality (P1.[21:18], P1.[16:11], P3.0), can only be used with the V
supply, whether used as a GPIO or any alternate function.
DDIO
Standard DMA Controller
The Standard DMA (direct memory access) controller provides a means to off-load the CPU for memory/peripheral data
transfer leading to a more power-efficient system. It allows automatic one-way data transfer between two entities. These
entities can be either memories or peripherals. The transfers are done without using CPU resources.
The following transfer modes are supported:
● 16 channel
● Peripheral to data memory
● Data memory to peripheral
● Data memory to data memory
● Event support
All DMA transactions consist of an AHB burst read into the DMA FIFO followed immediately by an AHB burst write from
the FIFO.
SmartDMA Controller
The SmartDMA controller provides low-power memory/peripheral access control that can run data collection tasks
and perform complex background processing on data being transferred, from simple arithmetic to multiply/accumulate,
while the CPU is off, significantly reducing power consumption (Background mode). The SmartDMA controller allows
peripherals on the AHB to access main system memory (SRAM) independent of the CPU. It is configured through the
APB and can configure itself through the AHB-to-APB bridge. The SmartDMA engine runs code from system SRAM. If
desired, custom SmartDMA algorithms supporting data post-processing can be developed by the user.
Key features:
● Dedicated 32-bit controller with general-purpose timer
● APB read access to the SmartDMA registers
● Configurable start IP address
● Selects 32 interrupts from peripherals from a total of 80 available interrupts to initiate DMA operations
● Global enable (SDMA_EN) keeps SmartDMA in reset except APB interface
● Synchronous interrupt output to CPU
Analog-to-Digital Converter
The 10-bit delta-sigma ADC provides an integrated reference generator and a single-ended input multiplexer. The
multiplexer selects an input channel from either the external analog input signals (AIN0, AIN1, AIN2, and AIN3) or the
internal power supply inputs. AIN0 and AIN1 are 5V tolerant, making them suitable for monitoring batteries. An internal
1.22V bandgap or the V
analog supply can be chosen as the ADC reference.
DDA
An optional feature allows samples captured by the ADC to be automatically compared against user-programmable high
and low limits. Up to four channel limit pairs can be configured in this way. The comparison allows the ADC to trigger
an interrupt (and potentially wake the CPU from a low-power sleep mode) when a captured sample goes outside the
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Maxim Integrated | 40
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
preprogrammed limit range. Since this comparison is performed directly by the sample limit monitors, it can be performed
even while the main CPU is suspended in a low power mode.
The ADC measures:
● AIN[3:2] (up to 3.3V)
● AIN[1:0] (up to 5.5V)
● V
● V
● V
● V
● V
● V
CORE
DD18
DDB
RTC
DDIO
DDIOH
Power Management
Power Management Unit
The power management unit (PMU) provides high-performance operation while minimizing power consumption. It
exercises intelligent, precise control of power distribution to the CPU and peripheral circuitry.
The PMU provides the following features:
● User-configurable system clock
● Automatic enabling and disabling of crystal oscillators based on power mode
● Multiple clock domains
● Fast wakeup of powered-down peripherals when activity detected
Active Mode
In this mode, the CPU is executing application code and all digital and analog peripherals are available on demand.
Dynamic clocking disables peripherals not in use, providing the optimal mix of high performance and low power
consumption.
Sleep Mode
This mode allows for low-power consumption, but a faster wakeup because the clocks can optionally be enabled. The
CPU is asleep, peripherals are on, and the standard and SmartDMA blocks are available for optional use. The GPIO or
any active peripheral interrupt can be configured to interrupt and cause transition to the Active mode.
Background Mode
This mode is suitable for running the SmartDMA engine to collect and move data from enabled peripherals. The CPU
2
is in its Deep-sleep mode. Memory retention is configurable. The SmartDMA engine can access the SPI, UARTS, I C,
1-Wire, timers, pulse train engines, and the secure digital interface as well as SRAM. The transition from Background
to Active mode is faster than the transition from Backup mode because system initialization is not required. There are
four sources from which Background mode can be exited to return to Active mode: RTC interrupt, GPIO interrupt, USB
interrupt, or RSTN assertion.
Deep-Sleep Mode
This mode corresponds to the Arm Cortex-M4 with FPU Deep-sleep mode. In this mode, the register settings and all
volatile memory is preserved. The GPIO pins retain their state in this mode. The transition from Deep-sleep to Active
mode is faster than the transition from Backup mode because system initialization is not required.
The high-speed oscillator that generates the 120MHz system clock can be shut down to provide additional power savings
over Sleep or Background modes.
There are four sources from which Background mode can be exited to return to Active mode: RTC interrupt, GPIO
interrupt, USB interrupt, or RSTN assertion.
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MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Backup Mode
This mode places the CPU in a static, low-power state that supports a fast wake-up to Active mode feature. In Backup
mode, all of the SRAM can be retained with restrictions depending upon which supply is used to support this mode. Data
retention in this mode can be maintained using only the V
or V
supplies. Optionally, the V
voltage input
CORE
RTC
CORE
can be turned off at its source and an internal retention regulator can be enabled to power the state so that the V
voltage input is all that is required for mode operation including the RTC.
RTC
If the V
supply is used, then either 32KB or 96KB of SRAM can be retained and all GPIO can be retained. If the
RTC
V
CORE
supply is subsequently turned on then the power mode will wake to the Active state.
If the V
supply is used, then either 32KB, 96KB, or 1024KB of SRAM can be retained and all GPIO can be retained.
CORE
There are four sources from which Background mode can be exited to return to Active mode: RTC interrupt, GPIO
interrupt, USB interrupt, or RSTN assertion.
Real-Time Clock
A real-time clock (RTC) keeps the time of day in absolute seconds. The 32-bit seconds register can count up to
approximately 136 years and be translated to calendar format by application software.
The RTC provides a time-of-day alarm that can be programmed to any future value between 1 second and 12 days.
When configured for long intervals, the time-of-day alarm can be used as a power-saving timer, allowing the device to
remain in an extremely low-power mode but still awaken periodically to perform assigned tasks. A second independent
32-bit 1/4096 subsecond alarm can be programmed between 244μs and 1s. Both can be configured as recurring alarms.
When enabled, either alarm can cause an interrupt or wake the device from most low power modes.
The time base is generated by a 32.768kHz crystal or an external clock source that must meet the electrical/timing
requirements in the Electrical Characteristics table.
The RTC calibration feature provides the ability for user-software to compensate for minor variations in the RTC oscillator,
crystal, temperature, and board layout. Enabling the 32KCAL alternate function outputs a timing signal derived from the
RTC. External hardware can measure the frequency and adjust the RTC frequency in increments of ±127ppm with 1ppm
resolution. Under most circumstances, the oscillator does not require any calibration.
CRC Module
A cyclic redundancy check (CRC) hardware module provides fast calculations and data integrity checks by application
software. The CRC module supports the following polynomials:
● CRC-16-CCITT
32
26
23
22
16
12
11
10
8
7
5
4
2
● CRC-32 (X + X + X + X + X + X + X + X + X + X + X + X + X + X + 1)
Programmable Timers
32-Bit Timer/Counter/PWM (TMR)
General-purpose, 32-bit timers provide timing, capture/compare, or generation of pulse-width modulated (PWM) signals
with minimal software interaction. Each of the 32-bit timers can also be split into two 16-bit timers.
The timer provides the following features:
● 32-bit up/down autoreload
● Programmable prescaler
● PWM output generation
● Capture, compare, and capture/compare capability
● External pin multiplexed with GPIO for timer input, clock gating or capture
● Timer output pin
● Configurable as 2 × 16-bit general-purpose timers
● Timer interrupt
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MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
32-BIT TIMER BLOCK
APB
BUS
TIMER CONTROL
REGISTER
TIME INTERRUPT
REGISTER
32-BIT COMPARE
REGISTER
TIMER
INTERRUPT
COMPARE
APB
CLOCK
INTERRUPT
PWM AND TIMER
OUTPUT
32-BIT TIMER
(WITH PRESCALER)
CONTROL
TIMER
OUTPUT
COMPARE
32-BIT
PWM/COMPARE
TIMER
INPUT
Figure 9. 32-Bit Timer
The MAX32650–MAX32652 provides six instances of the general-purpose 32-bit timer (TMR0–TMR5).
Pulse Train Engine (PT)
Multiple, independent pulse train generators can provide either a square wave or a repeating pattern from 2 to 32 bits
in length. Any single pulse train generator or any desired group of pulse train generators can be synchronized at the bit
level allowing for multibit patterns. Each pulse train generator is independently configurable.
The pulse train generators provide the following features:
● Independently enabled
● Safe enable and disable for pulse trains without bit banding
● Multiple pin configurations allow for flexible layout
● Pulse trains can be started/synchronized independently or as a group
● Frequency of each enabled pulse train generator is also set separately, based on a divide down (divide by 2, divide
by 4, divide by 8, and so on) of the input pulse train module clock
● Multiple repetition options
• Single shot (nonrepeating pattern of 2 to 32 bits)
• Pattern repeats user-configurable number of times or indefinitely
• Termination of one pulse train loop count can restart one or more other pulse trains
The pulse train engine feature is an alternate function associated with a GPIO pin. In most cases, enabling the pulse train
engine function supersedes the GPIO function.
The MAX32650–MAX32652 provide up to 16 instances of the pulse train engine peripheral (PT[15:0]).
Serial Peripherals
Serial Peripheral Interface
The serial peripheral interface (SPI) is a highly configurable, flexible, and efficient synchronous interface between multiple
SPI devices on a single bus. The bus uses a single clock signal and multiple data signals, and one or more slave
select lines to address only the intended target device. The SPI operates independently and requires minimal processor
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MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
overhead.
The provided SPI peripherals can operate in either slave or master mode and provide the following features:
● SPI modes 0, 1, 2, 3 for single-bit communication
● 3- or 4-wire mode for single-bit slave device communication
● Full-duplex operation in single-bit, 4-wire mode
● Dual and quad data modes supported
● Multiple slave select lines on some instances
● Multimaster mode fault detection
● Programmable interface timing
● Programmable SCK frequency and duty cycle
● 32-byte transmit and receive FIFOs
● Slave select assertion and deassertion timing with respect to leading/trailing SCK edge
The MAX32650–MAX32652 provide four instances of the SPI peripheral (SPI0, SPI1 and SPI2, SPI3) in accordance with
the specifications shown in Table 1:
Table 1. SPI Configuration Options
SLAVE SELECT
LINES
MAXIMUM FREQUENCY
(MASTER MODE) (MHz)
MAXIMUM FREQUENCY
(SLAVE MODE) (MHz)
INSTANCE
DATA
144
140
96
TQFP WLP WLP
SPI0
SPI1
SPI2
3-wire, 4-wire
3-wire, 4-wire
3-wire, 4-wire
1
4
4
1
4
4
0
4
3
60
60
60
48
48
48
3-wire, 4-wire, dual, or
quad data support
SPI3
4
4
4
60
48
2
I S Interface
2
The I S interface is a bidirectional, three-wire serial bus that provides serial communications for codecs and audio
2
amplifiers compliant with the I S Bus Specification, June 5, 1996. It provides the following features:
● Slave mode operation
● Normal and left-justified data alignment
● 16-bit audio transfer
● Wakeup on FIFO status (full/empty/threshold)
● Interrupts generated for FIFO status
● Receiver FIFO depth of 32 bytes
● Transmitter FIFO depth of 32 bytes
2
The MAX32650–MAX32652 provide one instance of the I S peripheral that is multiplexed with the SPI2 peripheral.
USB Controller
The integrated USB device controller is compliant with the Hi-Speed (480Mbps) USB 2.0 specification. The integrated
USB physical interface (PHY) reduces board space and system cost. An integrated voltage regulator enables smart
switching between the main supply and V
when connected to a USB host controller.
DDB
● Supports DMA for the endpoint buffers. A total of 12 endpoint buffers are supported with configurable selection of IN
or OUT in addition to endpoint 0.
● Isochronous, bulk, interrupt, and control transfers
● Automatic packet splitting and combining
● FIFOs up to 4096 bytes deep
● Double packet buffering
● USB 2.0 test mode support
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MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
2
I C Interface
2
The I C interface is a bidirectional, two-wire serial bus that provides a medium-speed communications network. It can
2
operate as a one-to-one, one-to-many or many-to-many communications medium. Two I C master/slave interface to a
2
2
wide variety of I C-compatible peripherals. These engines support standard mode, fast mode, and fast mode plus I C
speeds. It provides the following features:
● Master or slave mode operation
● Supports standard 7-bit addressing or 10-bit addressing
● RESTART condition
● Interactive Receive mode
● Tx FIFO Preloading
● Support for clock stretching to allow slower slave devices to operate on higher speed busses
● Multiple transfer rates
• Standard mode: 100kbps
• Fast mode: 400kbps
• Fast mode plus: 1000kbps
● Internal filter to reject noise spikes
● Receiver FIFO depth of 8 bytes
● Transmitter FIFO depth of 8 bytes
2
The MAX32650–MAX32652 provide two instances of the I C peripheral (I2C0 and I2C1).
UART
The universal asynchronous receiver-transmitter (UART) interface supports full-duplex asynchronous communication
with optional hardware flow control (HFC) modes to prevent data overruns. If HFC mode is enabled on a given port,
the system uses two extra pins to implement the industry standard request to send (RTS) and clear to send (CTS) flow
control signaling. Each UART is individually programmable.
● 2-wire interface or 4-wire interface with flow control
● 32-byte send/receive FIFO
● Full-duplex operation for asynchronous data transfers
● Interrupts available for frame error, parity error, CTS, RX FIFO overrun and FIFO full/partially full conditions
● Automatic parity and frame error detection
● Independent baud-rate generator
● Programmable 9th bit parity support
● Multidrop support
● Start/stop bit support
● Hardware flow control using RTS/CTS
● Baud rate generation with ±2% optionally utilizing the 7.3727MHz oscillator baud rate clock
● Maximum baud rate 4000kB
● Two DMA channels can be connected (read and write FIFOs)
● Programmable word size (5 bits to 8 bits)
The MAX32650–MAX32652 provide three instances of the UART peripheral (UART0, UART1 and UART2) according to
the specifications in Table 2:
Table 2. UART Configuration Options
FLOW CONTROL
INSTANCE
MAXIMUM BAUD RATE (kb)
144 TQFP
Yes
140 WLP
Yes
96 WLP
No
UART0
UART1
UART2
4000
4000
4000
Yes
Yes
Yes
Yes
Yes
No
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MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Serial Peripheral Interface Execute in Place (SPIX) Master
There are two SPI execute-in-place master interfaces. One for SRAM (SPIXR) and one for flash (SPIXF) with dedicated
slave selects. This feature allows the CPU to transparently execute instructions stored in an external SPI memory device.
Instructions fetched through the SPI master are cached just like instructions fetched from internal program memory. The
SPI SRAM master provides write-back capability. These two SPI execute in place master interfaces can also be used to
access large amounts of external static data that would otherwise reside in internal data memory.
1-Wire Master
Maxim's 1-wire bus consists of a single line to provide both power and data communications and a ground return. The bus
supports a serial, multidrop communication protocol between a master and one or more slave devices with the minimum
amount of interconnection.
Maxim's 1-wire bus consists of one signal that carries data and also supplies power to the slave devices, and a ground
return. The bus master communicates serially with one or more slave devices through the bidirectional, multidrop 1-Wire
bus. The single contact serial interface is ideal for communication networks requiring minimal interconnection.
The provided 1-Wire master supports the following features:
● Single contact for control and operation
● Unique factory identifier for any 1-Wire device
● Multiple device capability on a single line
The MAX32650–MAX32652 1-Wire master supports both the standard (15.6 kbps) and overdrive (110 kbps) speeds.
24-Bit Color TFT Controller
The 24-bit color TFT controller is controlled by the CPU through the APB and fed graphic data through the AHB. The
controller supports the following display types:
● Active matrix TFT panels with up to 24-bit bus interface
● Single/dual-panel monochrome STN panels (4-bit and 8-bit bus interfaces)
● Single/dual-panel color STN panels, 8-bit bus interface
● TFT panels up to 24 bpp, direct 8:8:8 RG
● Color STN panels up to 16 bpp, direct 5:5:5 with one bit not being used
● Mono STN panels up to 4 bpp, pelletized, 16 gray scales selected from 16
The controller can be programmed to operate a wide range of panel resolutions (including but not limited to the following
settings):
● 320 x 200, 320 x 240
● 640 x 200, 640 x 240, 640 x 480
● 800 x 600
● 1024 x 768
● 2048 x 2048
● 4096 x 4096
Debug and Development Interface (SWD/JTAG)
Special versions of the device are available with a serial wire debug or JTAG interface that is used only during application
development and debugging. The interface is used for code loading, ICE debug activities, and control of boundary scan
activities.
Trust Protection Unit (MAX32651 Only)
True Random Number Generator
Random numbers are a vital part of a secure application, providing random numbers that can be used for cryptographic
seeds or strong encryption keys to ensure data privacy.
Software can use random numbers to trigger asynchronous events that result in nondeterministic behavior. This is helpful
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Maxim Integrated | 46
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
in thwarting replay attacks or key search approaches. An effective true random number generator (TRNG) must be
continuously updated by a high-entropy source.
The provided TRNG is continuously driven by a physically-unpredictable entropy source. It generates a 128-bit true
random number in 128 system clock cycles.
The TRNG can support the system-level validation of many security standards such as FIPS 140-2, PCI-PED, and
Common Criteria. Contact Maxim for details of compliance with specific standards.
MAA
The provided high-speed, hardware-based modulo arithmetic accelerator (MAA) performs mathematical computations
that support strong cryptographic algorithms. These include:
● 2048-bit DSA
● 4096-bit RSA
● Elliptic curve public key infrastructure
AES
The dedicated hardware-based AES engine supports the following algorithms:
● AES-128
● AES-192
● AES-256
The AES keys are automatically generated by the engine and stored in dedicated flash to protect against tampering. Key
generation and storage is transparent to the user.
SHA-256
SHA-256 is a cryptographic hash function part of the SHA-2 family of algorithms. It authenticates user data and verifies
its integrity. It is used for digital signatures.
The device provides a hardware SHA-256 engine for fast computation of 256-bit digests.
Memory Decryption Integrity Unit
The external SPI flash can optionally be encrypted for additional security. Data can be transparently encrypted when it is
loaded and decrypted on-the-fly. Encryption keys are stored in the always-on domain and preserved as as long as V
is present.
RTC
Secure Bootloader
The secure bootloader provides a secure, authenticated communication channel with a system host. The secure
communication protocol (SCP) allows the programming of internal and external memory.
The secure bootloader provides the following features:
● Life cycle management
● Authentications using ECDSA P-256, with 256-bit ECC key pairs and SHA-256 secure hash function
● Preprogrammed Maxim manufacturer root key (MRK)
● Programmable customer root key (CRK)
● Support for 2048- or 4096-bit RSA digital signature
Additional Documentation and Technical Support
Designers must have the following documents to use all the features of this device.
● This data sheet, which contains electrical/timing specifications, package information, and pin descriptions.
● The corresponding revision-specific errata sheet.
● The corresponding user guide, which contains detailed information and programming guidelines for core features and
peripherals.
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Maxim Integrated | 47
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Applications Information
GPIO and Alternate Function Matrix, 140 WLP
Table 3. GPIO and Alternate Function Matrix, 140 WLP
GPIO
ALTERNATE FUNCTION 1
ALTERNATE FUNCTION 2
P0.0
PT3
SPIXF_SDIO2**
―
P0.1
SPIXR_SDIO0**
SPIXR_SDIO2**
SPIXR_SCK**
SPIXR_SDIO3**
SPIXR_SDIO1**
SPIXR_SS0**
SPIXF_SS0**
SPIXF_SCK**
SPIXF_SDIO1**
SPIXF_SDIO0**
SPIXF_SDIO2**
SPIXF_SDIO3**
SPI3_SS1
P0.2
―
P0.3
―
P0.4
―
P0.5
―
P0.6
―
P0.7
―
P0.8
―
P0.9
―
P0.10
P0.11
P0.12
P0.13
P0.14
P0.15
P0.16
P0.17
P0.18
P0.19
P0.20
P0.21
P0.22
P0.23
P0.24
P0.25
P0.26
P0.27
P0.28
P0.29
P0.30
P0.31
P1.0
―
―
―
CLCD_G0
CLCD_G1
CLCD_G2
CLCD_G3
CLCD_G4
CLCD_G5
CLCD_G6
CLCD_G7
—
SPI3_SS2
SPI3_SDIO3
SPI3_SCK
SPI3_SDIO2
SPI3_SS3
SPI3_SS0
SPI3_SDIO1
SPI3_SDIO0
SPI0_SS0
CLCD_VDEN
CLCD_CLK
CLCD_HSYNC
CLCD_B0
TDI
PT15
RXEV
TXEV
TDI
TDO
TDO
TMS (SWDIO)††
TCK (SWDCLK)††
—
TMS (SWDIO)††
TCK (SWDCLK)††
CLCD_B0
SDHC_CDN
SPIXF_SDIO3**
SPIXF_SDIO1**
SPIXF_SS0**
CLCD_CLK
32KCAL
SDHC_CMD
SDHC_DAT2
SDHC_WP
SDHC_DAT3
P1.1
P1.2
P1.3
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Maxim Integrated | 48
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Table 3. GPIO and Alternate Function Matrix, 140 WLP (continued)
GPIO
ALTERNATE FUNCTION 1
SDHC_DAT0
SDHC_CLK
SDHC_DAT1
UART2_CTS
UART2_RTS
UART2_RX
UART2_TX
HYP_CS0N
HYP_D0
ALTERNATE FUNCTION 2
SPIXF_SDIO0**
SPIXF_SCK**
PT0
P1.4
P1.5
P1.6
P1.7
PT1
P1.8
PT2
P1.9
PT3
P1.10
P1.11
P1.12
P1.13
P1.14
P1.15
P1.16
P1.17
P1.18
P1.19
P1.20
P1.21
P1.22*
P1.23
P1.24
P1.25
P1.26
P1.27
P1.28
P1.29
P1.30
P1.31
P2.0
PT4
SPIXR_SDIO0**
SPIXR_SDIO1**
SPIXR_SS0**
PT5
HYP_D4
HYP_RWDS
HYP_D1
SPIXR_SDIO2**
SPIXR_SCK**
―
HYP_D5
PT9
HYP_D6
PT6
HYP_D2
PT7
HYP_D3
CLCD_HSYNC
PT8
HYP_D7
―
―
SPI1_SS0
CLCD_B1
CLCD_B2
CLCD_B3
CLCD_B4
CLCD_B5
CLCD_B6
CLCD_B7
CLCD_R0
CLCD_R1
PT9
SPI1_SS2
SPI1_SS1
SPI1_SCK
SPI1_SS3
SPI1_MISO
SPI1_MOSI
OWM_PUPEN
OWM_IO
SPI2_SS2
P2.1
SPI2_SS1
PT10
P2.2
SPI2_SCK (I2S_BCLK)†
SPI2_MISO (I2S_SDI)†
SPI2_MOSI (I2S_SDO)†
SPI2_SS0 (I2S_LRCLK)†
SPI2_SS3
CLCD_LEND
CLCD_PWREN
―
P2.3
P2.4
P2.5
PT11
P2.6
CLCD_VSYNC
―
P2.7
I2C0_SDA
P2.8
I2C0_SCL
―
P2.9
UART0_CTS
UART0_RTS
UART0_RX
PT12
P2.10
P2.11
PT14
PT13
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Maxim Integrated | 49
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Table 3. GPIO and Alternate Function Matrix, 140 WLP (continued)
GPIO
P2.12
P2.13
P2.14
P2.15
P2.16
P2.17
P2.18
P2.19
P2.20
P2.21
P2.22
P2.23
P2.24
P2.25
P2.26
P2.27
P2.28
P2.29
P2.30
P2.31
P3.0
ALTERNATE FUNCTION 1
UART0_TX
UART1_CTS
UART1_RX
UART1_RTS
UART1_TX
I2C1_SDA
I2C1_SCL
PT4
ALTERNATE FUNCTION 2
PT15
CLCD_R2
CLCD_R3
CLCD_R4
CLCD_R5
CLCD_R6
CLCD_R7
―
PT5
―
PT7
―
PT8
―
PT6
SPIXR_SDIO3**
PT10
―
PT11
―
PT12
―
PT13
―
PT14
―
PT0
―
PT1
―
PT2
―
PDOWN†††
SPI0_MISO
SPI0_MOSI
SPI0_SCK
TMR0
HYP_CS1N
P3.1
―
―
―
―
―
―
―
―
―
P3.2
P3.3
P3.4
P3.5
TMR2
P3.6
TMR4
P3.7
TMR1
P3.8
TMR3
P3.9
TMR5
*GPIO not pinned out.
**This signal can be mapped to more than one GPIO, but there is only one instance of this peripheral.
†I2S_BCLK, I2S_LRCLK, I2S_SDI, and I2S_SDO when enabled.
††Single-wire debug when enabled.
†††PDOWN is not operative during or immediately after reset since this function appears as an Alternate Function 1.
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Maxim Integrated | 50
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
GPIO and Alternate Function Matrix, 96 WLP
Table 4. GPIO and Alternate Function Matrix, 96 WLP
GPIO
P0.0*
P0.1*
P0.2*
P0.3*
P0.4*
P0.5*
P0.6*
P0.7*
P0.8*
P0.9*
P0.10*
P0.11
P0.12*
P0.13
P0.14
P0.15
P0.16
P0.17
P0.18
P0.19
P0.20
P0.21
P0.22
P0.23*
P0.24*
P0.25*
P0.26
P0.27
P0.28
P0.29
P0.30
P0.31*
P1.0
ALTERNATE FUNCTION 1
ALTERNATE FUNCTION 2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SPIXF_SDIO2**
—
P0.11
—
SPI3_SS1
SPI3_SS2
SPI3_SDIO3
SPI3_SCK
SPI3_SDIO2
SPI3_SS3
SPI3_SS0
SPI3_SDIO1
SPI3_SDIO0
—
CLCD_G0
CLCD_G1
CLCD_G2
CLCD_G3
CLCD_G4
CLCD_G5
CLCD_G6
CLCD_G7
—
CLCD_VDEN
—
—
—
—
—
—
TDI
—
TDO
—
TMS (SWDIO)††
TCK (SWDCLK)††
—
—
—
CLCD_B0
—
—
SDHC_CMD
SDHC_DAT2
SDHC_WP
SDHC_DAT3
SDHC_DAT0
SDHC_CLK
SDHC_DAT1
SPIXF_SDIO3**
SPIXF_SDIO1**
SPIXF_SS0**
CLCD_CLK
SPIXF_SDIO0**
SPIXF_SCK**
PT0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
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Maxim Integrated | 51
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Table 4. GPIO and Alternate Function Matrix, 96 WLP (continued)
GPIO
P1.7*
P1.8
ALTERNATE FUNCTION 1
ALTERNATE FUNCTION 2
—
—
PT2
UART2_RTS
P1.9
UART2_RX
PT3
P1.10
P1.11
P1.12
P1.13
P1.14
P1.15
P1.16
P1.17*
P1.18
P1.19
P1.20
P1.21
P1.22*
P1.23
P1.24
P1.25
P1.26
P1.27
P1.28
P1.29
P1.30
P1.31
P2.0
UART2_TX
PT4
—
SPIXR_SDIO0**
SPIXR_SDIO1**
SPIXR_SS0**
PT5
—
—
—
—
SPIXR_SDIO2**
SPIXR_SCK**
—
—
—
—
—
PT6
PT7
—
CLCD_HSYNC
PT8
—
—
—
SPI1_SS0
SPI1_SS2
SPI1_SS1
SPI1_SCK
SPI1_SS3
SPI1_MISO
SPI1_MOSI
OWM_PUPEN
OWM_IO
CLCD_B1
CLCD_B2
CLCD_B3
CLCD_B4
CLCD_B5
CLCD_B6
CLCD_B7
CLCD_R0
CLCD_R1
PT9
SPI2_SS2
—
P2.1*
P2.2
—
SPI2_SCK (I2S-BCLK)†
SPI2_MISO (I2S-SDI)†
SPI2_MOSI (I2S-SDO)†
SPI2_SS0 (I2S_LRCLK)†
SPI2_SS3
—
CLCD_LEND
CLCD_PWREN
—
P2.3
P2.4
P2.5
PT11
P2.6
CLCD_VSYNC
—
P2.7*
P2.8*
P2.9
—
—
UART0_CTS
—
PT12
P2.10*
P2.11
P2.12
P2.13
P2.14
—
UART0_RX
UART0_TX
UART1_CTS
UART1_RX
PT13
PT15
CLCD_R2
CLCD_R3
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Maxim Integrated | 52
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Table 4. GPIO and Alternate Function Matrix, 96 WLP (continued)
GPIO
P2.15
P2.16
P2.17
P2.18
P2.19*
P2.20*
P2.21*
P2.22*
P2.23
P2.24*
P2.25*
P2.26*
P2.27*
P2.28*
P2.29*
P2.30*
P2.31*
P3.0*
P3.1*
P3.2*
P3.3*
P3.4
ALTERNATE FUNCTION 1
ALTERNATE FUNCTION 2
UART1_RTS
CLCD_R4
UART1_TX
CLCD_R5
I2C1_SDA
I2C1_SCL
—
CLCD_R6
CLCD_R7
—
—
—
—
—
—
—
PT6
—
SPIXR_SDIO3**
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TMR0
TMR2
TMR4
TMR1
TMR3
TMR5
P3.5
P3.6
P3.7
P3.8
P3.9
*GPIO not pinned out.
**This signal can be mapped to more than one GPIO, but there is only one instance of this peripheral.
†I2S_BCLK, I2S_LRCLK, I2S_SDI, I2S_SDO when enabled.
††Single-wire debug when enabled.
GPIO and Alternate Function Matrix, 144 TQFP
Table 5. GPIO and Alternate Function Matrix, 144 TQFP
GPIO
P0.0*
P0.1
P0.2
P0.3
P0.4
ALTERNATE FUNCTION 1
ALTERNATE FUNCTION 2
—
—
—
—
—
—
SPIXR_SDIO0**
SPIXR_SDIO2**
SPIXR_SCK**
SPIXR_SDIO3**
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Maxim Integrated | 53
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Table 5. GPIO and Alternate Function Matrix, 144 TQFP (continued)
GPIO
ALTERNATE FUNCTION 1
SPIXR_SDIO1**
SPIXR_SS0**
SPIXF_SS0**
SPIXF_SCK**
SPIXF_SDIO1**
SPIXF_SDIO0**
SPIXF_SDIO2**
SPIXF_SDIO3**
SPI3_SS1
ALTERNATE FUNCTION 2
P0.5
—
—
P0.6
P0.7
—
P0.8
—
P0.9
—
P0.10
P0.11
P0.12
P0.13
P0.14
P0.15
P0.16
P0.17
P0.18
P0.19
P0.20
P0.21
P0.22
P0.23
P0.24
P0.25
P0.26
P0.27
P0.28
P0.29
P0.30
P0.31
P1.0
—
—
—
CLCD_G0
CLCD_G1
CLCD_G2
CLCD_G3
CLCD_G4
CLCD_G5
CLCD_G6
CLCD_G7
—
SPI3_SS2
SPI3_SDIO3
SPI3_SCK
SPI3_SDIO2
SPI3_SS3
SPI3_SS0
SPI3_SDIO1
SPI3_SDIO0
SPI0_SS0
CLCD_VDEN
CLCD_CLK
CLCD_HSYNC
CLCD_B0
—
PT15
RXEV
TXEV
TDI
TDO
—
TMS (SWDIO)†††
TCK (SWDCLK)†††
—
—
—
CLCD_B0
SDHC_CDN
SPIXF_SDIO3**
SPIXF_SDIO1**
SPIXF_SS0**
CLCD_CLK
SPIXF_SDIO0**
SPIXF_SCK**
PT0
32KCAL
SDHC_CMD
SDHC_DAT2
SDHC_WP
SDHC_DAT3
SDHC_DAT0
SDHC_CLK
SDHC_DAT1
UART2_CTS
UART2_RTS
UART2_RX
UART2_TX
HYP_CS0N
HYP_D0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
PT1
P1.8
PT2
P1.9
PT3
P1.10
P1.11
P1.12
PT4
SPIXR_SDIO0**
SPIXR_SDIO1**
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Maxim Integrated | 54
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Table 5. GPIO and Alternate Function Matrix, 144 TQFP (continued)
GPIO
P1.13
P1.14
P1.15
P1.16
P1.17
P1.18
P1.19
P1.20
P1.21
P1.22
P1.23
P1.24
P1.25
P1.26
P1.27
P1.28
P1.29
P1.30
P1.31
P2.0
ALTERNATE FUNCTION 1
ALTERNATE FUNCTION 2
SPIXR_SS0**
PT5
HYP_D4
HYP_RWDS
HYP_D1
SPIXR_SDIO2**
SPIXR_SCK**
-
HYP_D5
PT9
HYP_D6
PT6
HYP_D2
PT7
HYP_D3
CLCD_HSYNC
PT8
HYP_D7
—
—
SPI1_SS0
CLCD_B1
CLCD_B2
CLCD_B3
CLCD_B4
CLCD_B5
CLCD_B6
CLCD_B7
CLCD_R0
CLCD_R1
PT9
SPI1_SS2
SPI1_SS1
SPI1_SCK
SPI1_SS3
SPI1_MISO
SPI1_MOSI
OWM_PUPEN
OWM_IO
SPI2_SS2
P2.1
SPI2_SS1
PT10
P2.2
SPI2_SCK (I2S-BCLK)†
SPI2_MISO (I2S-SDI)†
SPI2_MOSI (I2S-SDO)†
SPI2_SS0 (I2S_LRCLK)†
SPI2_SS3
CLCD_LEND
CLCD_PWREN
—
P2.3
P2.4
P2.5
PT11
P2.6
CLCD_VSYNC
—
P2.7
I2C0_SDA
P2.8
I2C0_SCL
—
P2.9
UART0_CTS
UART0_RTS
UART0_RX
UART0_TX
UART1_CTS
UART1_RX
UART1_RTS
UART1_TX
I2C1_SDA
PT12
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
P2.16
P2.17
P2.18
P2.19*
P2.20*
PT14
PT13
PT15
CLCD_R2
CLCD_R3
CLCD_R4
CLCD_R5
CLCD_R6
CLCD_R7
—
I2C1_SCL
—
—
—
19-100220
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Maxim Integrated | 55
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Table 5. GPIO and Alternate Function Matrix, 144 TQFP (continued)
GPIO
P2.21*
P2.22*
P2.23
P2.24*
P2.25
P2.26
P2.27*
P2.28
P2.29*
P2.30
P2.31*
P3.0
ALTERNATE FUNCTION 1
ALTERNATE FUNCTION 2
—
—
—
—
PT6
SPIXR_SDIO3**
—
—
PT11
—
PT12
—
—
—
PT14
—
—
—
PT1
—
—
—
PDOWN††
SPI0_MISO
SPI0_MOSI
SPI0_SCK
TMR0
TMR2
TMR4
TMR1
TMR3
TMR5
HYP_CS1N
P3.1
—
—
—
—
—
—
—
—
—
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
*GPIO not pinned out.
**This signal can be mapped to more than one GPIO, but there is only one instance of this peripheral.
†I2S_BCLK, I2S_LRCLK, I2S_SDI, I2S_SDO when enabled.
††PDOWN does not operate during or immediately after reset since this function appears as an Alternate Function 1.
†††Single-wire debug when enabled.
19-100220
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Maxim Integrated | 56
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Typical Application Circuits
Pulse Oximeter and Heart Rate Monitor with BLE and GPS Location
V
V
DD
DD
V
V
V
V
DD
DD
DD
DD
V
V
DD
DD
ACCELEROMETER
SDA SCL
GPS
R
R
R
R
PU_SDA1
PU_SCL0
PU_SDA0
PU_SCL1
SDA SCL
SDA1 SCL1
GPIO1
POWER
MANAGEMENT
V
V
BAT
V
DD
BAT
SDA
SCL
SDA0 SCL0
RTC
SCL
SDA
V
V
DD
LED+
BAT
Li+
2.7 TO
5.5V
MAX30101
HIGH-SENSITIVITY PULSE
OXIMETER AND HEART RATE
SENSOR FOR WEARABLE
HEALTH
INT
GND
RSTN
RST
MAX32650
DRIVEP
MAX32651
MAX32652
VDD
V
DD
VIBRATION
MOTOR
M
1.8V
1.8V BUCK
1.1V BUCK
1.8V LDO
V
DDIO
DRIVEN
HV
1.1V
1.8V
V
V
CORE
SPI
BLUETOOTH™ LOW ENERGY
RTC
TFT
CONTROLLER
24-BIT COLOR TFT DISPLAY
V
DD
3.3V
3.3V LDO
V
DDB
LED0
LED1
DP
DM
SECURE DIGITAL HIGH
CAPACITY STORAGE
USB 2.0 HI-SPEED
SDHC
CONTROLLER
PIEZO
BUZZER
The Bluetooth word mark and logos are registered trademarks owned by Bluetooth SIG, Inc. and any use of such marks
by Maxim is under license.
Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
HyperBus is a trademark of Cypress Semiconductor Corporation.
XCCELA is a trademark of Micron Technology, Inc.
microSD is a registered trademark of SD-3C.
19-100220
www.maximintegrated.com
Maxim Integrated | 57
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Ordering Information
TRUST PROTECTION UNIT
PART
WITH SECURE
BOOTLOADER
PIN-PACKAGE
MAX32650GWQ+
MAX32650GWQ+T
MAX32650GCE+
MAX32651GWQ+
MAX32651GWQ+T
MAX32651GCE+
MAX32651GWE+
MAX32651GWE+T
MAX32652GWE+
MAX32652GWE+T
NO
NO
96 WLP (0.4mm pitch)
96 WLP (0.4mm pitch)
144 TQFP
NO
YES
YES
YES
YES
YES
NO
96 WLP (0.4mm pitch)
96 WLP (0.4mm pitch)
144 TQFP
140 WLP (0.35mm pitch)
140 WLP (0.35mm pitch)
140 WLP (0.35mm pitch)
140 WLP (0.35mm pitch)
NO
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
19-100220
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Maxim Integrated | 58
MAX32650–MAX32652
Ultra-Low-Power Arm Cortex-M4 Processor
with FPU-Based Microcontroller (MCU) with 3MB
Flash and 1MB SRAM
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
12/17
3/18
0
1
Initial release
—
Updated General Description and Benefits and Features sections
1
Updated title, Absolute Maximum Ratings, Debug and Development Interface (SWD/
JTAG), and Ordering Information sections
2
3
10/18
12/18
1, 2, 39, 46
Updated Debug and Development Interface (SWD/JTAG) section and Ordering
Information
39, 46
Updated General Description, Benefits and Features, Simplified Block Diagram,
Absolute Maximum Ratings, Package Information, Electrical Characteristics, Figure
1, Figure 2, Pin Description, Secure Digital Interface, Spansion HyperBus/XCCELA
Bus, Clocking Scheme, Figure 8, Standard DMA Controller, Background Mode,
Deep-Sleep Mode, Real-Time Clock, UART, 24-Bit Color TFT Controller, Additional
Documentation and Technical Support, Table 3, Table 4, Table 5, Pulse Oximeter
and Heart Rate Monitor with BLE and GPS Location, and Ordering Information
1, 2, 7–11, 13,
19, 25, 33,
35–41, 43, 44,
48, 49, 56
4
8/19
5
6
2/20
3/20
Updated Ordering Information
Updated Ordering Information
58
58
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max
limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2020 Maxim Integrated Products, Inc.
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