MAX1882_12 [MAXIM]
Quad-Output TFT LCD DC-DC Converters with Buffer; 四路输出TFT LCD DC-DC与缓冲转换器
| 型号： | MAX1882_12 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Quad-Output TFT LCD DC-DC Converters with Buffer |
| 文件： | 总39页 (文件大小：824K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAX1778/
MAX1880–MAX1885
Quad-Output TFT LCD DC-DC
Converters with Buffer
General Description
Features
The MAX1778/MAX1880–MAX1885 multiple-output
DC-DC converters provide the regulated voltages
required by active matrix thin-film transistor (TFT) liquid
crystal displays (LCD) in a low-profile TSSOP package.
One high-power step-up converter and two low-power
charge pumps convert the 2.7V to 5.5V input voltage
into three independent output voltages. A built-in linear
regulator and VCOM buffer complete the power-supply
requirements.
o 500kHz/1MHz Current-Mode PWM Step-Up
Regulator
Up to +13V Main High-Power Output
1ꢀ ꢁccurate
High Efficiency (91ꢀ)
o Dual Regulated Charge-Pump Outputs
(MꢁX1778/MꢁX1880–MꢁX1882 only)
Up to +40V Positive Charge-Pump Output
Up to -40V Negative Charge-Pump Output
The main step-up converter accurately generates an
externally set output voltage up to 13V that can supply
the display’s row/column drivers. The converter’s high
switching frequency and current-mode PWM architec-
ture provide fast transient response and allow the use
of small low-profile inductors and ceramic capacitors.
The low-power BiCMOS control circuitry and internal
14V switch (0.35Ω N-channel MOSFET) enable efficien-
cies up to 91%.
o Low-Dropout 40mꢁ Linear Regulator
(MꢁX1778/MꢁX1881/MꢁX1883/MꢁX1884 only)
Up to +15V LDO Input
o Optional Higher Current with External Transistor
o 2.7V to 5.5V Input Supply
o Internal Supply Sequencing and Soft-Start
o Power-Ready Output
The dual low-power charge pumps (MAX1778/
MAX1880/MAX1881/MAX1882 only) independently reg-
o ꢁdjustable Fault-Detection Latch
o Thermal Protection (+160°C)
ulate one positive output (V
) and one negative out-
POS
o 0.1µꢁ Shutdown Current
put (V
). These low-power outputs use external
NEG
diode and capacitor stages (as many stages as
required) to regulate output voltages up to +40V and
-40V. A unique control scheme minimizes output ripple
as well as capacitor sizes for both charge pumps.
o 0.7mꢁ IN Quiescent Current
o Ultra-Small External Components
o Thin TSSOP Package (1.1mm max height)
A resistor-programmable, 40mA, low-dropout linear
regulator (MAX1778/MAX1881/MAX1883/MAX1884
only) provides preregulation or postregulation for any of
the supplies. For higher current applications, an exter-
nal transistor can be added. Additionally, the VCOM
buffer provides a high current output that is ideal for
driving the capacitive backplane of TFT LCD panels.
The VCOM buffer’s output voltage is preset with an
internal 50% resistive-divider or can be externally
adjusted for other voltages.
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
24 TSSOP
24 TSSOP
24 TSSOP
24 TSSOP
24 TSSOP
24 TSSOP
20 TSSOP
20 TSSOP
20 TSSOP
MAX1778EUG
MAX1778EUG+
MAX1880EUG
MAX1880EUG/V+
MAX1881EUG
MAX1882EUG
MAX1883EUP
MAX1884EUP
MAX1885EUP
The MAX1778/MAX1880–MAX1885 are protected
against output undervoltage and thermal overload con-
ditions by a latched fault detection circuit that shuts
down the device. All devices are available in the ultra-
thin TSSOP package (1.1mm max height).
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
Applications
TFT LCD Notebook Displays
TFT LCD Desktop Monitor Panels
Typical Operating Circuit appears at end of data sheet.
Pin Configurations and Selector Guide appear at end of
data sheet.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-1979; Rev 2; 10/12
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
ꢁBSOLUTE MꢁXIMUM RꢁTINGS
IN, SHDN, TGND, FLTSET to GND...........................-0.3V to +6V
DRVN to GND.........................................-0.3V to (V
DRVP to GND..........................................-0.3V to (V
PGND to GND..................................................................... 0.3V
RDY, SUPB to GND................................................-0.3V to +14V
LX, SUPP, SUPN to PGND .....................................-0.3V to +14V
SUPL to GND..........................................................-0.3V to +18V
BUFOUT, BUF+, BUF- to GND...............-0.3V to (V
+ 0.3V)
SUPB
Continuous Power Dissipation (T = +70°C)
+ 0.3V)
+ 0.3V)
A
SUPN
SUPP
20-Pin TSSOP (derate 10.9mW/°C above +70°C) ......879mW
24-Pin TSSOP (derate 12.2mW/°C above +70°C) ......975mW
Operating Temperature Range
MAX1778EUG, MAX1883EUP........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
LDOOUT to GND ....................................-0.3V to (V
INTG, REF, FB, FBN, FBP to GND...............-0.3V to (V + 0.3V)
+ 0.3V)
SUPL
IN
FBL to GND .............-0.3V to the lower of (V
+ 0.3V) or +6V
SUP
L
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICꢁL CHꢁRꢁCTERISTICS
(V = +3.0V, SHDN = IN, V
= V
= V = V
= 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND =
SUPL
IN
SUPP
SUPN
SUPB
PGND = GND, C
= 0.22µF, C = 1µF, T = 0°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.)
BUF ꢁ A
REF
PARAMETER
Input Supply Range
SYMBOL
CONDITIONS
MIN
2.7
TYP
MAX
5.5
UNITS
V
V
V
IN
Input Undervoltage Threshold
V
V
V
rising, 40mV hysteresis (typ)
2.2
2.4
0.7
2.6
UVLO
IN
MAX1778/MAX1880/
MAX1883 (f = 1MHz)
1
1
OSC
= V
FB
FBP
IN Quiescent Supply Current
I
= 1.5V, V
= -0.2V
mA
IN
FBN
MAX1881/MAX1882/
MAX1884/MAX1885
0.6
(f
= 500kHz)
OSC
MAX1778/MAX1880
(f = 1MHz)
0.4
0.3
0.4
0.7
0.5
0.7
OSC
SUPP Quiescent Current
SUPN Quiescent Current
I
V
V
= 1.5V
mA
mA
SUPP
FBP
FBN
MAX1881/MAX1882
(f = 500kHz)
OSC
MAX1778/MAX1880
(f = 1MHz)
OSC
I
= -0.2V
SUPN
MAX1881/MAX1882
(f = 500kHz)
0.3
0.1
0.1
0.5
10
10
OSC
IN Shutdown Current
V
V
= 0, V = 5V
µA
µA
SHDN
SHDN
IN
= 0, V
= 13V,
SUPP
SUPP Shutdown Current
MAX1778/MAX1880/MAX1881/MAX1882
V
= 0, V = 13V,
SHDN
SUPN
SUPN Shutdown Current
0.1
10
µA
MAX1778/MAX1880/MAX1881/MAX1882
V
= 0, V = 13V
SHDN
SUPL
SUPL Shutdown Current
SUPB Shutdown Current
0.1
6
10
13
µA
µA
MAX1778/MAX1881/MAX1883/MAX1884
V
= 0, V = 13V
SHDN
SUPB
Maxim Integrated
2
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
ELECTRICꢁL CHꢁRꢁCTERISTICS (continued)
(V = +3.0V, SHDN = IN, V
= V
= V = V
= 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND =
IN
SUPP
SUPN
SUPB
SUPL
PGND = GND, C
= 0.22µF, C
= 1µF, T = 0°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.)
BUF ꢁ A
REF
PARAMETER
SYMBOL
UNITS
CONDITIONS
MIN
TYP
MAX
MAIN STEP-UP CONVERTER
Main Output Voltage Range
V
V
V
V
13
MAIN
IN
Integrator enabled, C
= 1000pF
1.234
1.220
-50
1.247
1.260
1.280
+50
INTG
FB Regulation Voltage
FB Input Bias Current
V
I
FB
Integrator disabled (INTG = REF)
nA
MHz
kHz
V
= 1.25V, INTG = GND
FB
FB
MAX1778/MAX1880/MAX1883
0.85
425
1
1.15
575
Operating Frequency
f
OSC
MAX1881/MAX1882/MAX1884/MAX1885
500
Oscillator Maximum Duty
Cycle
80
85
0.01
0.2
91
%
Integrator enabled,
C
= 1000pF
INTG
I
V
= 0 to 200mA,
LX
Load Regulation
%
= 10V
MAIN
Integrator disabled
(INTG = REF)
Line Regulation
0.1
317
0.35
0.01
0.38
0.75
1.12
1.5
%/V
µS
Ω
Integrator Transconductance
LX Switch On-Resistance
LX Leakage Current
R
I
= 100mA
0.7
20
LX(ON)
LX
I
V
= 13V
LX
µA
LX
Phase I = soft-start (1024/f
)
0.275
1.15
0.5
OSC
Phase II = soft-start (1024/f
)
OSC
LX Current Limit
I
A
LIM
Phase III = soft-start (1024/f
)
OSC
Phase IV = fully on (after 3072/f
)
1.85
OSC
Maximum RMS LX Current
Soft-Start Period
1
A
s
t
Power-up to the end of Phase III
Falling edge, FLTSET = GND
Falling edge, FLTSET = 1V
3072 / f
1.1
SS
OSC
1.07
1.14
FB Fault Trip Level
V
0.955
0.99
1.025
POSITIVE CHARGE PUMP (MAX1778/MAX1880/MAX1881/MAX1882 only)
V
2.7
13
V
Hz
V
SUPP Input Supply Range
SUPP
Operating Frequency
f
0.5 x f
OSC
CHP
FBP Regulation Voltage
FBP Input Bias Current
DRVP PCH On-Resistance
V
1.2
-50
1.25
1.3
+50
10
FBP
FBP
nA
Ω
I
V
= 1.5V
FBP
R
5
2
PCH(ON)
Ω
V
V
= 1.2V
= 1.3V
4
FBP
FBP
DRVP NCH On-Resistance
R
NCH(ON)
kΩ
A
20
Maximum RMS DRVP Current
FBP Power-Ready Trip Level
0.1
1.125
1.11
0.99
V
Rising edge
1.09
1.08
1.16
1.16
Falling edge, FLTSET = GND
Falling edge, FLTSET = 1V
FBP Fault Trip Level
Maxim Integrated
V
0.955
1.025
3
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
ELECTRICꢁL CHꢁRꢁCTERISTICS (continued)
(V = +3.0V, SHDN = IN, V
= V
= V = V
= 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND =
IN
SUPP
SUPN
SUPB
SUPL
PGND = GND, C
= 0.22µF, C
= 1µF, T = 0°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.)
BUF ꢁ A
REF
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
NEGATIVE CHARGE PUMP (MAX1778/MAX1880/MAX1881/MAX1882 only)
V
2.7
13
V
Hz
mV
nA
Ω
SUPN Input Supply Range
Operating Frequency
SUPN
f
0.5 x f
OSC
CHP
V
-50
-50
0
+50
+50
10
FBN Regulation Voltage
FBN Input Bias Current
DRVN PCH On-Resistance
FBN
I
V
= 0
FBN
FBN
R
5
2
PCH(ON)
R
NCH(ON)
4
Ω
V
V
= +50mV
= -50mV
FBN
FBN
DRVN NCH On-Resistance
20
kΩ
A
0.1
125
140
Maximum RMS DRVN Current
FBN Power-Ready Trip Level
FBN Fault Trip Level
Falling edge
Rising edge
80
80
165
190
mV
mV
LOW-DROPOUT LINEAR REGULATOR (MAX1778/MAX1881/MAX1883/MAX1884 only)
SUPL Input Supply Range
SUPL Undervoltage Lockout
SUPL Quiescent Current
V
4.5
3.8
15
4.3
V
V
SUPL
Rising edge, 50mV hysteresis (typ)
= 100µA
4
I
I
120
130
70
220
300
µA
SUPL
LDO
I
= 40mA
= 5mA
LDO
LDO
LDO is set to
regulate at 9V
Dropout Voltage (Note 1)
FBL Regulation Voltage
LDO Load Regulation
LDO Line Regulation
V
mV
V
DROP
I
V
= 10V, LDO regulating at 9V,
SUPL
V
1.235
1.25
1.265
1.2
FBL
I
= 15mA
LDO
V
= 10V, LDO regulating at 9V,
SUPL
%
I
= 100µA to 40mA
LDO
V
= 4.5V to 15V, FBL = LDOOUT,
SUPL
0.02
%/V
I
= 15mA
LDO
µA
FBL Input Bias Current
LDO Current Limit
I
V
V
= 1.25V
-0.8
40
+0.8
220
FBL
FBL
mA
I
= 10V, V
= 13V
= 9V, V = 1.2V
FBL
130
LDOLIM
SUPL
LDOOUT
VCOM BUFFER
V
SUPB Input Supply Range
SUPB Quiescent Current
BUFOUT Leakage Current
Power-Supply Rejection Ratio
V
4.5
13
SUPB
µA
µA
dB
V
I
V
V
420
98
850
+10
SUPB
SUPB
SUPB
-10
85
PSRR
= 4.5V to 13V, V
= 2.25V
CM
Input Common-Mode Voltage
Range
V
|V | < 10mV
1.2
8.8
CM
OS
dB
nA
Common-Mode Rejection Ratio
Input Bias Current
CMRR
V
V
V
= 1.2V to 8.8V
= 5V
75
CM
CM
CM
I
-100
-100
-10
13
+100
+100
BIAS
nA
Input Offset Current
I
= 5V
OS
kHz
Gain Bandwidth Product
GBW
C
= 1µF
BUF
Maxim Integrated
4
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
ELECTRICꢁL CHꢁRꢁCTERISTICS (continued)
(V = +3.0V, SHDN = IN, V
= V
= V = V
SUPB
ꢁ
= 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND =
IN
SUPP
SUPN
SUPL
PGND = GND, C
= 0.22µF, C
= 1µF, T = 0°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.)
REF
BUF
A
UNITS
PARAMETER
Output Voltage
SYMBOL
CONDITIONS
MIN
4.99
4.97
4.93
TYP
MAX
5.01
5.03
5.07
I
I
I
= 0
=
BUFOUT
BUFOUT
BUFOUT
V
V
BUF+ = GND
5mA
BUFOUT
=
45mA
V
V
(V
= 4.5V to 13V,
= 1.2V to
CM
I
=
=
5mA
-30
+30
+70
SUPB
BUFOUT
BUFOUT
Input Offset Voltage
V
mV
OS
- 1.2V)
I
45mA
-70
9
SUPB
Output Voltage Swing High
Output Voltage Swing Low
Peak Buffer Output Current
V
I
I
= -45mA, ∆V = 1V
9.6
0.4
150
V
V
OH
BUFOUT
OS
V
= +45mA, ∆V = 1V
1
OL
BUFOUT
OS
mA
BUF+ Dual Mode™ Threshold
Voltage
Falling edge, 20mV hysteresis (typ)
80
125
170
mV
REFERENCE
Reference Voltage
V
-2µA < I
< 50µA
1.231
0.9
1.25
1.05
1.269
1.2
V
V
REF
REF
Reference Undervoltage
Threshold
LOGIC SIGNALS
SHDN Input Low Voltage
SHDN Input High Voltage
SHDN Input Current
0.9
V
V
2.1
I
0.01
1
µA
SHDN
0.67 x
0.85 x
V
REF
FLTSET Input Voltage Range
V
V
REF
FLTSET Threshold Voltage
FLTSET Input Current
RDY Output Low Voltage
RDY Output High Leakage
Thermal Shutdown
Rising edge, 25mV hysteresis (typ)
= 1V
80
125
0.1
170
50
0.5
1
mV
nA
V
V
FLTSET
I
= 2mA
= 13V
0.25
0.01
160
SINK
V
µA
°C
RDY
Rising temperature
Dual Mode is a trademark of Maxim Integrated Products, Inc.
Maxim Integrated
5
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
ELECTRICꢁL CHꢁRꢁCTERISTICS
(V = +3.0V, SHDN = IN, V
= V
= V
= V
= 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND =
SUPL
IN
SUPP
SUPN
SUPB
PGND = GND, C
= 0.22µF, C = 1µF, T = -40°C to +85°C, unless otherwise noted.) (Note 2)
BUF ꢁ
REF
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Input Supply Range
V
2.7
5.5
V
IN
Input Undervoltage
Threshold
V
V
Rising, 40mV hysteresis (typ)
2.2
2.6
1
V
UVLO
IN
MAX1778/MAX1880/
MAX1883 (f = 1MHz)
V
V
V
=
FB
OSC
IN Quiescent Supply
Current
= 1.5V,
= -0.2V
I
mA
FBP
FBN
IN
MAX1881/MAX1882/MAX1884/
MAX1885 (f = 500kHz)
1
OSC
MAX1778/MAX1880
(f = 1MHz)
0.7
0.5
0.7
OSC
SUPP Quiescent Current
SUPN Quiescent Current
I
V
V
= 1.5V
mA
mA
SUPP
SUPN
FBP
FBN
MAX1881/MAX1882
(f = 500kHz)
OSC
MAX1778/MAX1880
(f = 1MHz)
OSC
I
= -0.2V
MAX1881/MAX1882
(f = 500kHz)
0.5
10
10
OSC
IN Shutdown Current
V
V
= 0, V = 5V
µA
µA
SHDN
SHDN
IN
= 0, V
= 13V,
SUPP
SUPP Shutdown Current
MAX1778/MAX1880/MAX1881/MAX1882
V
= 0, V = 13V,
SHDN
SUPN
SUPN Shutdown Current
SUPL Shutdown Current
10
µA
MAX1778/MAX1880/MAX1881/MAX1882
V
= 0, V = 13V,
SHDN
SUPL
10
13
µA
µA
MAX1778/MAX1881/MAX1883/MAX1884
V = 0, V = 13V
SHDN
SUPB Shutdown Current
SUPB
MAIN STEP-UP CONVERTER
Main Output Voltage Range
V
V
13
1.269
1.29
+50
1.25
625
V
V
MAIN
IN
Integrator enabled, C
= 1000pF
1.223
1.21
-50
INTG
FB Regulation Voltage
FB Input Bias Current
Operating Frequency
V
FB
Integrator disabled (INTG = REF)
= 1.25V, INTG = GND
I
V
nA
MHz
kHz
FB
FB
MAX1778/MAX1880/MAX1883
0.75
375
F
OSC
MAX1881/MAX1882/MAX1884/MAX1885
Oscillator Maximum Duty
Cycle
79
91
%
LX Switch On-Resistance
LX Leakage Current
R
I
= 100mA
0.7
20
Ω
LX(ON)
LX
I
LX
V
= 13V
LX
µA
Phase I = soft-start (1024/f
)
0.275
1.1
0.525
2.05
1.14
OSC
LX Current Limit
I
A
V
LIM
Phase IV = fully on (after 3072/f
)
OSC
FB Fault Trip Level
Falling edge, FLTSET = GND
1.07
Maxim Integrated
6
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
ELECTRICꢁL CHꢁRꢁCTERISTICS (continued)
(V = +3.0V, SHDN = IN, V
= V
= V
= V
= 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND =
IN
SUPP
SUPN
SUPB
SUPL
PGND = GND, C
= 0.22µF, C
= 1µF, T = -40°C to +85°C, unless otherwise noted.) (Note 2)
BUF ꢁ
REF
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
POSITIVE CHARGE PUMP (MAX1778/MAX1880/MAX1881/MAX1882 only)
SUPP Input Supply Range
FBP Regulation Voltage
FBP Input Bias Current
DRVP PCH On-Resistance
V
2.7
1.2
-50
13
1.3
+50
10
V
V
SUPP
V
FBP
I
V
= 1.5V
nA
Ω
FBP
FBP
R
R
PCH(ON)
V
V
= 1.2V
= 1.3V
4
Ω
FBP
FBP
DRVP NCH On-Resistance
NCH(ON)
20
kΩ
V
FBP Power-Ready Trip Level
Rising edge
1.09
1.16
NEGATIVE CHARGE PUMP (MAX1778/MAX1880/MAX1881/MAX1882 only)
SUPN Input Supply Range
FBN Regulation Voltage
FBN Input Bias Current
DRVN PCH On-Resistance
V
2.7
-50
-50
13
+50
+50
10
V
SUPN
V
mV
nA
Ω
FBN
FBN
I
V
= 0
FBN
R
R
PCH(ON)
V
V
= +50mV
= -50mV
4
Ω
FBN
FBN
DRVN NCH On-Resistance
NCH(ON)
20
80
kΩ
mV
FBN Power-Ready Trip Level
Falling edge
165
LOW DROPOUT LINEAR REGULATOR (MAX1778/MAX1881/MAX1883/MAX1884 only)
SUPL Input Supply Range
SUPL Undervoltage Lockout
SUPL Quiescent Current
Dropout Voltage (Note 1)
V
4.5
3.8
15
V
V
SUPL
Rising edge, 50mV hysteresis (typ)
= 100µA
4.3
240
330
I
I
µA
mV
SUPL
LDO
V
LDO regulating to 9V, I
= 40mA
DROP
LDO
V
= 10V, LDO regulating to 9V,
= 15mA
SUPL
FBL Regulation Voltage
LDO Load Regulation
LDO Line Regulation
V
1.222
1.265
1.2
V
%
FBL
I
LDO
V
= 10V, LDO regulating to 9V,
= 100µA to 40mA
SUPL
I
LDO
V
= 4.5V to 15V, FBL = LDOOUT,
= 15mA
SUPL
0.02
%/V
I
LDO
FBL Input Bias Current
LDO Current Limit
I
V
V
= 1.25V
-1.2
40
+1.2
260
µA
FBL
FBL
I
= 10V, V
= 13V
= 9V, V = 1.2V
FBL
mA
LDOLIM
SUPL
LDOOUT
VCOM BUFFER
SUPB Input Supply Range
SUPB Quiescent Current
BUFOUT Leakage Current
Input Common-Mode Voltage
V
4.5
13
850
+10
8.8
V
SUPB
I
V
µA
µA
V
SUPB
SUPB
-10
1.2
V
|V | < 10mV
OS
CM
Maxim Integrated
7
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
ELECTRICꢁL CHꢁRꢁCTERISTICS (continued)
(V = +3.0V, SHDN = IN, V
= V
= V
= V
= 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND =
IN
SUPP
SUPN
SUPB
SUPL
PGND = GND, C
= 0.22µF, C
= 1µF, T = -40°C to +85°C, unless otherwise noted.) (Note 2)
BUF ꢁ
REF
PARAMETER
Input Bias Current
Input Offset Current
SYMBOL
CONDITIONS
MIN
-500
-500
4.988
4.97
4.93
MAX
+500
+500
5.012
5.03
UNITS
nA
I
V
V
= 5V
= 5V
BIAS
CM
CM
I
nA
OS
I
I
I
= 0
=
BUFOUT
BUFOUT
BUFOUT
Output Voltage
V
BUF+ = GND
5mA
V
BUFOUT
=
45mA
5.07
V
V
(V
= 4.5V to 13V
= 1.2V to
I
=
=
5mA
-30
+30
+70
SUPB
BUFOUT
BUFOUT
Input Offset Voltage
V
mV
CM
OS
I
45mA
-70
9
- 1.2V)
SUPB
Output Voltage Swing High
Output Voltage Swing Low
V
I
I
= -45mA, ∆V = 1V
V
V
OH
BUFOUT
OS
V
= +45mA, ∆V = 1V
1
OL
BUFOUT
OS
BUF+ Dual-Mode
Threshold Voltage
Falling edge, 20mV hysteresis (typ)
80
170
mV
REFERENCE
Reference Voltage
V
-2µA < I
< 50µA
1.223
0.9
1.269
1.2
V
V
REF
REF
Reference Undervoltage
Threshold
LOGIC SIGNALS
SHDN Input Low Voltage
SHDN Input High Voltage
SHDN Input Current
0.9
1
V
V
2.1
I
µA
V
SHDN
FLTSET Input Voltage Range
FLTSET Threshold Voltage
FLTSET Input Current
0.74 x V
80
0.85 x V
REF
REF
Rising edge, 25mV hysteresis (typ)
= 1V
170
mV
nA
V
V
50
0.5
1
FLTSET
RDY Output Low Voltage
RDY Output High Leakage
I
= 2mA
= 13V
RDY
SINK
V
µA
Note 1: Dropout voltage is defined as the V
- V
, when V
is 100mV below the set value of V
.
SUPL
LDOOUT
SUPL
LDOOUT
Note 2: Specifications to -40°C are guaranteed by design, not production tested.
Maxim Integrated
8
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC-DC
Converters with Buffer
Typical Operating Characteristics
(Circuit of Figure 1, V = +3.3V, SHDN = IN, V
= V
= V
= V
= V
= 8V, BUF- = BUFOUT,
SUPL
IN
MAIN
SUPP
SUPN
SUPB
BUF+ = FLTSET = TGND = PGND = GND, T = +25°C.)
A
MAIN 8V OUTPUT VOLTAGE
vs. LOAD CURRENT
MAIN 8V OUTPUT EFFICIENCY
vs. LOAD CURRENT
MAIN 12V OUTPUT VOLTAGE
vs. LOAD CURRENT
8.12
8.08
8.04
8.00
7.96
7.92
7.88
100
90
80
70
60
50
40
12.24
V = 5V
IN
12.16
12.08
12.00
11.92
11.84
11.76
V = 3.3V
IN
V = 3.3V
IN
V
IN
3.3V
=
V = 5V
IN
V
5V
=
IN
V
R
C
C
= 8V
OUT
C
= 470pF
= 24kΩ
= 470pF
INTG
= 24kΩ
= 470pF
= 470pF
COMP
COMP
INTG
R
COMP
COMP
FIGURE 8
C = 470pF
INTG
C
0
100
200
300
(mA)
400
500
600
0
200
400
600
800
0
200
400
600
800
I
I
(mA)
I
(mA)
OUT
OUT
OUT
MAIN 12V OUTPUT EFFICIENCY
vs. LOAD CURRENT
STEP UP CONVERTERS
SWITCHING FREQUENCY vs. INPUT VOLTAGE
POSITIVE CHARGE-PUMP OUTPUT VOLTAGE
vs. LOAD CURRENT
1.20
100
90
80
70
60
50
40
20.2
20.0
19.8
19.6
19.4
19.2
MAX1778
V
5V
=
IN
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
V
SUPP
= 10V
V
IN
3.3V
=
V
SUPP
= 8V
V
SUPP
= 7.5V
FIGURE 8
= 12V
V
SUPP
= 7V
V
OUT
C
= 470pF
INTG
0
100
200
300
(mA)
400
500
600
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
0
5
10
(mA)
15
20
I
V
I
POS
OUT
IN
NEGATIVE CHARGE-PUMP OUTPUT VOLTAGE
vs. LOAD CURRENT
-4.90
POSITIVE CHARGE-PUMP EFFICIENCY
vs. LOAD CURRENT
MAXIMUM POSITIVE CHARGE-PUMP
OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
100
90
40
35
30
25
20
15
10
5
V
SUPP
= 7V
V
SUPP
= 7.5V
-4.92
-4.94
-4.96
-4.98
-5.00
-5.02
-5.04
V
= 7V
SUPN
80
70
60
50
40
30
V
SUPN
= 6V
V
SUPP
= 8V
I
= 1mA
I
POS
= 10mA
POS
V
SUPP
= 10V
V
= 8V
SUPN
V
POS
= 20V
0
5
10
(mA)
15
20
0
10
20
(mA)
30
40
2
4
6
8
10
12
14
I
I
NEG
NEG
V
(V)
SUPP
9
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V = +3.3V, SHDN = IN, V
= V
= V
= V
= V = 8V, BUF- = BUFOUT,
SUPL
IN
MAIN
SUPP
SUPN
SUPB
BUF+ = FLTSET = TGND = PGND = GND, T = +25°C.)
A
NEGATIVE CHARGE-PUMP EFFICIENCY
vs. LOAD CURRENT
MAXIMUM NEGATIVE CHARGE-PUMP
OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
REFERENCE VOLTAGE
vs. REFERENCE LOAD CURRENT
1.27
100
90
80
70
60
50
40
30
-2
-4
V
= -5V
NEG
V
SUPN
= 6V
1.26
1.25
1.24
1.23
-6
I
= 10mA
NEG
V
SUPN
= 7V
= 8V
-8
I
= 1mA
NEG
V
SUPN
-10
-12
-14
0
20
40
I
60
(µA)
80
100
2
4
6
8
10
12
14
0
10
20
(mA)
30
40
I
V
(V)
SUPN
REF
NEG
STEP-UP CONVERTER LOAD-TRANSIENT
STEP-UP CONVERTER LOAD-TRANSIENT
STEP-UP CONVERTER LOAD-TRANSIENT
RESPONSE (1µs PULSES)
RESPONSE
RESPONSE WITHOUT INTEGRATOR
MAX1778 toc15
MAX1778 toc13
MAX1778 toc14
0.5A
200mA
200mA
A
B
C
A
B
A
B
C
0
0
0
8.0V
8.1V
8.1V
7.9V
1A
8.0V
7.9V
1A
8.0V
7.9V
1A
0.5A
C
0
0
0
4µs/div
40µs/div
40µs/div
A. I
B. V
= 0 to 500mA, 500mA/div
= 8V, 100mV/div
A. I
B. V
= 20mA to 200mA, 200mA/div
= 8V, 100mV/div
A. I
B. V
= 20mA to 200mA, 200mA/div
= 8V, 100mV/div
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
C. INDUCTOR CURRENT, 500mA/div
C. INDUCTOR CURRENT, 1A/div
= 1000pF
C. INDUCTOR CURRENT, 1A/div
INTG = REF
C
INTG
Maxim Integrated
10
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V = +3.3V, SHDN = IN, V
= V
= V
= V
= V
= 8V, BUF- = BUFOUT,
SUPL
IN
MAIN
SUPP
SUPN
SUPB
BUF+ = FLTSET = TGND = PGND = GND, T = +25°C.)
A
STEP-UP CONVERTER
SOFT-START (LIGHT LOAD)
STEP-UP CONVERTER
SOFT-START (HEAVY LOAD)
RIPPLE VOLTAGE WAVEFORMS
MAX1778 toc17
MAX1778 toc16
MAX1778 toc18
2V
2V
A
A
A
0
8V
-5V
20V
0
8V
8V
B
6V
4V
B
B
6V
4V
0.5A
0
1.0A
0.5A
0
C
C
C
1ms/div
= O TO 2V, 2V/div
= 8V, 2V/div
1µs/div
= 200mA, 10mV/div
= 10mA, 20mV/div
= 5mA, 20mV/div
1ms/div
= O TO 2V, 2V/div
= 8V, 2V/div
A. V
B. V
A. V
B. V
C. V
= 8V, I
SHDN
MAIN
A. V
B. V
MAIN
NEG
POS
MAIN
SHDN
MAIN
= -5V, I
NEG
C. INDUCTOR CURRENT, 500mA/div
= 400Ω
= 20V, I
C. INDUCTOR CURRENT, 500mA/div
POS
R
LOAD
R
= 20Ω
LOAD
POWER-UP SEQUENCE
(CIRCUIT OF FIGURE 10)
POWER-UP INTO SHORT-CIRCUIT
(CIRCUIT OF FIGURE 10)
POWER-UP SEQUENCE
MAX1778 toc20
MAX1778 toc19
MAX1778 toc21
4V
2V
A
2V
4V
A
B
0
0
A
2V
0
20V
5V
B
10V
0
0
20V
10V
0
5V
0
C
C
D
B
0
10V
5V
0
D
-5V
C
E
-10V
1ms/div
2ms/div
100µs/div
A. RDY, 2V/div
B. POSITIVE CHARGE PUMP, V
C. STEP-UP CONVERTER: V
A. V
B. RDY, 5V/div
C. POSITIVE CHARGE PUMP = V
D. STEP-UP CONVERTER: V
= O TO 2V, 2V/div
SHDN
A. RDY, 2V/div
= 20V, 10V/div
= 8V, 10V/div
= -5V, -5V/div
POS(SYS)
MAIN(SYS)
B. GATE OF N-CH MOSFET, 5V/div
C. STEP-UP CONVERTER, V
= 20V, R
= 4kΩ, 10V/div
POS
LOAD
= 8V, 5V/div
MAIN(START)
D. NEGATIVE CHARGE PUMP, V
= 8V, R
= 40Ω, 10V/div
= -5V, R = 500Ω, 10V/div
LOAD
NEG
MAIN
LOAD
V
= GND
MAIN(SYS)
E. NEGATIVE CHARGE PUMP: V
NEG
Maxim Integrated
11
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V = +3.3V, SHDN = IN, V
= V
= V
= V
= V
= 8V, BUF- = BUFOUT,
SUPL
IN
MAIN
SUPP
SUPN
SUPB
BUF+ = FLTSET = TGND = PGND = GND, T = +25°C.)
A
LDO OUTPUT VOLTAGE
vs. LDO INPUT VOLTAGE
(INTERNAL LINEAR REGULATOR)
LDO OUTPUT VOLTAGE
vs. LDO OUTPUT CURRENT
(INTERNAL LINEAR REGULATOR)
LDO OUTPUT VOLTAGE vs. TEMPERATURE
(INTERNAL LINEAR REGULATOR)
5.10
5.04
5.05
5.00
4.95
4.90
4.85
4.80
4.75
I
= 0
5.08
5.06
LDOOUT
5.02
5.00
4.98
4.96
I
= 0
LDOOUT
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
I
= 40mA
LDOOUT
I
= 40mA
LDOOUT
4.94
4.92
4.90
4
6
8
10
12
0.01
0.1
1
10
100
-40
-15
10
35
60
85
V
(V)
I
(mA)
LDOOUT
TEMPERATURE (°C)
SUPL
DROPOUT VOLTAGE
vs. LDO LOAD CURRENT
(INTERNAL LINEAR REGULATOR)
LDO SUPPLY CURRENT
vs. LDO OUTPUT CURRENT
(INTERNAL LINEAR REGULATOR)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
200
160
120
80
V
= 5V
V
= 5V
LDOOUT
LDOOUT
40
0
0
10
20
30
40
0
10
20
30
40
I
(mA)
I
(mA)
LDOOUT
LDOOUT
Maxim Integrated
12
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V = +3.3V, SHDN = IN, V
= V
= V
= V
= V
= 8V, BUF- = BUFOUT,
SUPL
IN
MAIN
SUPP
SUPN
SUPB
BUF+ = FLTSET = TGND = PGND = GND, T = +25°C.)
A
LOAD-TRANSIENT RESPONSE
REGION OF STABLE C
ESR
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
LDOOUT
(INTERNAL LINEAR REGULATOR)
vs. LOAD CURRENT
MAX1778 toc29
100
80
100
10
C
= 1µF
LDOOUT
4OmA
A
B
0
60
1
40
5.00V
4.96V
STABLE REGION
0.1
0.01
20
C
I
= 4.7µF
LDOOUT
LDOOUT
= 40mA
0
0
40
100µs/div
10
20
30
1
10
100
1000
I
(mA)
LDOOUT
FREQUENCY (kHz)
A. I = 100µA TO 40mA, 40mA/div
LDO
B. V = 5V, 20mV/div
LDO
V
= V + 500mV
LDO
SUPL
LOAD-TRANSIENT RESPONSE NEAR
INTERNAL LINEAR-REGULATOR
RIPPLE REJECTION
INTERNAL LINEAR-REGULATOR
STARTUP
DROPOUT (INTERNAL LINEAR REGULATOR)
MAX1778 toc31
MAX1778 toc32
MAX1778 toc30
4OmA
0
2V
0
A
B
5.0V
8.0V
A
B
A
B
4V
2V
0
5.00V
4.94V
C
1.0A
0.5A
0
C
4V
2V
100µs/div
10µs/div
400µs/div
= 0 TO 2V, 2V/div
A. I = 100µA TO 40mA, 40mA/div
B. V = 5V, 20mV/div
A. V
= 5V, I
= 40mA, 10mV/div
A. V
B. V
C. V
LDO
LDO
= V + 100mV
LDOOUT
MAIN
LDOOUT
S
HDN
B. V
C. I
= V
= 8V, 200mV/div
= 5V, R
= 8V, R
= 125Ω, 2V/div
SUPL
LDOOUT
LDOOUT
= 40Ω, 2V/div
V
= 0 TO 750mA, 500mA/div
IN
LDO
MAIN
MAIN
MAIN
Maxim Integrated
13
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V = +3.3V, SHDN = IN, V
= V
= V
= V
= V
= 8V, BUF- = BUFOUT,
SUPL
IN
MAIN
SUPP
SUPN
SUPB
BUF+ = FLTSET = TGND = PGND = GND, T = +25°C.)
A
LINEAR-REGULATOR OUTPUT VOLTAGE
vs. INPUT VOLTAGE
(EXTERNAL LINEAR REGULATOR)
LINEAR-REGULATOR OUTPUT VOLTAGE
vs. LOAD CURRENT
(EXTERNAL LINEAR REGULATOR)
EXTERNAL LINEAR-REGULATOR
LOAD-TRANSIENT RESPONSE
MAX1778 toc35
2.55
2.53
2.51
2.49
2.47
2.45
2.55
FIGURE 7
250mA
2.53
2.51
2.49
2.47
50mA
A
B
I
= 0
LDO
2.55V
2.50V
2.45V
I
= 750mA
LDO
FIGURE 7
3.0
2.45
100µs/div
A. I = 50mA TO 250mA, 200mA/div
2.5
3.5
4.0
(V)
4.5
5.0
5.5
0.1
1
10
(mA)
100
1000
V
I
IN
LDO
LDO
B. V
= 2.5V, 50mV/div
LDO
FIGURE 7
EXTERNAL LINEAR-REGULATOR
RIPPLE REJECTION
INPUT OFFSET VOLTAGE DEVIATION
vs. COMMON-MODE VOLTAGE
INPUT OFFSET VOLTAGE DEVIATION
vs. BUFFER SUPPLY VOLTAGE
MAX1778 toc36
1.0
0.6
2.5
1.5
V
= V
/ 2
SUPB
CM
A
B
2.5V
V
= 4.5V
SUPB
V
= 13V
SUPB
8.0V
7.8V
1A
0.2
0.5
-0.5
-1.5
-2.5
-0.2
-0.6
-1.0
0.5A
C
0
10µs/div
0
2
4
6
8
10
12
14
4
6
8
10
(V)
12
14
V
(V)
V
SUPB
CM
A. V = 2.5V, I = 200mA, 10mV/div
LDO
MAIN
MAIN
LDO
SUPL
B. V
C. I
= V
= 8V, 200mV/div
= 0 TO 750mA, 500mA/div
FIGURE 7
Maxim Integrated
14
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V = +3.3V, SHDN = IN, V
= V
= V
= V
= V
= 8V, BUF- = BUFOUT,
SUPL
IN
MAIN
SUPP
SUPN
SUPB
BUF+ = FLTSET = TGND = PGND = GND, T = +25°C.)
A
INPUT OFFSET VOLTAGE DEVIATION
vs. TEMPERATURE
INPUT OFFSET VOLTAGE DEVIATION
vs. TEMPERATURE
BUFFER INPUT BIAS CURRENT
vs. COMMON-MODE VOLTAGE
1.0
0.6
0.2
-0.2
-0.6
0
1.0
0.6
0.2
-0.2
-0.6
0
10
V
V
= 13V
V
V
= 13V
SUPB
CM
SUPB
CM
V
= 13V
= V
SUPB
/2
= V
SUPB
/2
SUPB
8
6
4
2
0
V
= 4.5V
SUPB
-40
-15
10
35
60
85
-40
-15
10
35
60
85
0
2
4
6
8
(V)
10
12
14
TEMPERATURE (°C)
TEMPERATURE (°C)
V
CM
BUFFER INPUT BIAS CURRENT
vs. BUFFER SUPPLY VOLTAGE
BUFFER INPUT BIAS CURRENT
vs. TEMPERATURE
BUFFER SUPPLY CURRENT
vs. COMMON-MODE VOLTAGE
12
11
10
9
0.50
0.46
0.42
0.38
0.34
0.30
10
V
= V
/2
CM
SUPB
V
= 13V
SUPB
8
6
4
8
V
= 4.5V
SUPB
7
6
5
V
= V
/ 2
SUPB
CM
4
4
6
8
10
(V)
12
14
-40
-15
10
35
60
85
0
2
4
6
8
(V)
10
12
14
V
TEMPERATURE (°C)
V
SUPB
CM
BUFFER SUPPLY CURRENT
vs. BUFFER SUPPLY VOLTAGE
NO-LOAD BUFFER SUPPLY CURRENT
vs. TEMPERATURE
VCOM BUFFER
SMALL-SIGNAL RESPONSE
MAX1778 toc47
1.0
0.9
0.8
0.50
V
V
= 13V
SUPB
CM
= V
SUPB
/2
4.05V
0.46
0.42
0.38
0.34
0.30
4.00V
3.95V
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
A
B
4.05V
4.00V
3.95V
V
= V
/2
CM
SUPB
4
6
8
10
(V)
12
14
-40
-15
10
35
60
85
4µs/div
V
TEMPERATURE (°C)
SUPB
A. V
= 3.95V TO 4.05V, 50mV/div
BUF+
B. BUFOUT = BUF-, 50mV/div
= 1µF, V = 8V
C
BUF
SUPB
Maxim Integrated
15
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V = +3.3V, SHDN = IN, V
= V
= V
= V
= V = 8V, BUF- = BUFOUT,
SUPL
IN
MAIN
SUPP
SUPN
SUPB
BUF+ = FLTSET = TGND = PGND = GND, T = +25°C.)
A
VCOM BUFFER
LARGE-SIGNAL RESPONSE
VCOM BUFFER
LOAD-TRANSIENT RESPONSE
VCOM BUFFER
LOAD-TRANSIENT RESPONSE
MAX1778 toc48
MAX1778 toc49
MAX1778 toc50
4.50V
200mA
0
500mA
0
A
A
A
B
4.00V
3.50V
-200mA
4.2V
-500mA
4.5V
4.50V
4.0V
3.8V
8.0V
4.0V
3.5V
8.0V
B
B
4.00V
3.50V
C
C
10µs/div
4µs/div
4µs/div
A. V + = 3.50V TO 4.50V, 0.5V/div
BUF
A. I
= 200mA PULSES, 200mA/div
A. I
= 400mA PULSES, 500mA/div
BUFOUT
BUFOUT
B. BUFOUT = BUF-, 0.5V/div
B. BUFOUT = BUF-, 200mV/div
B. BUFOUT = BUF-, 0.5V/div
C
= 1µF, V
= 8V
C. V
V
= 8V, 50mV/div
C. V
V
= 8V, 100mV/div
BUF
SUPB
MAIN
SUPB
MAIN
SUPB
= V
, BUF+ = GND, C = 1µF
= V
, BUF+ = GND, C = 1µF
MAIN BUF
MAIN
BUF
VCOM BUFFER STARTUP
VCOM BUFFER STARTUP
MAX1778 toc51
MAX1778 toc51
4V
4V
2V
2V
A
A
0
4V
2V
0
4V
2V
B
B
0
8.1V
7.8V
0
8.1V
7.8V
C
C
100µs/div
100µs/div
A. RDY, 2V/div
B. BUFOUT = BUF-, C = 1µF, 2V/div
A. RDY, 2V/div
B. BUFOUT = BUF-, C = 1µF, 2V/div
BUF
C. V
BUF+ = GND
= V
= 8V, I
= 20mA, 200mV/div
SUPB
MAIN
MAIN
BUF
C. V
= V
MAIN
= 8V, I
= 20mA, 200mV/div
SUPB
MAIN
BUF+ = GND
Maxim Integrated
16
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC-DC
Converters with Buffer
Pin Description
PIN
MAX1778 MAX1880 MAX1883
MAX1885
NAME
FUNCTION
MAX1881 MAX1882 MAX1884
Main Step-Up Regulator Feedback Input. Regulates to 1.25V
1
2
1
2
1
2
1
FB
nominal. Connect a resistive divider from the output (V
to analog ground (GND).
) to FB
MAIN
Main Step-Up Integrator Output. When using the integrator,
connect 1000pF to analog ground (GND). To disable the
integrator, connect INTG to REF.
2
3
INTG
IN
Main Supply Voltage. The supply voltage powers the control
circuitry for all the regulators and can range from 2.7V to 5.5V.
Bypass with a 0.1µF capacitor between IN and GND, as close to
the pins as possible.
3
3
3
VCOM Buffer (Operational Transconductance Amplifier) Positive
Feedback Input. Connect to GND to select the internal resistive
divider that sets the positive input to half the amplifier’s supply
4
5
4
5
4
5
4
5
BUF+
voltage (V
= V
/2).
SUPB
BUF+
VCOM Buffer (Operational Transconductance Amplifier) Negative
Feedback Input
BUF-
VCOM Buffer (Operational Transconductance Amplifier) Supply
Voltage
6
7
8
6
7
8
6
7
8
6
7
8
SUPB
BUFOUT VCOM Buffer (Operational Transconductance Amplifier) Output
Analog Ground. Connect to power ground (PGND) underneath the
GND
IC.
Internal Reference Bypass Terminal. Connect a 0.22µF ceramic
9
9
9
9
REF
FBP
capacitor from REF to analog ground (GND). External load
capability up to 50µA.
Positive Charge-Pump Regulator Feedback Input. Regulates to
1.25V nominal. Connect a resistive divider from the positive
10
11
12
10
11
12
—
—
10
—
—
10
charge-pump output (V
) to FBP to analog ground (GND).
POS
Negative Charge-Pump Regulator Feedback Input. Regulates to
0V nominal. Connect a resistive divider from the negative charge-
FBN
pump output (V
) to FBN to the reference (REF).
NEG
Active-Low Shutdown Control Input. Pull SHDN low to force the
controller into shutdown. If unused, connect SHDN to IN for normal
operation. A rising edge on SHDN clears the fault latch.
SHDN
Low-Dropout Linear Regulator Input Voltage. Can range from 4.5V
to 15V. Bypass with a 1µF capacitor to GND (see Capacitor
Selection and Regulator Stability). Connect both input pins
together externally.
13
—
11
—
SUPL
Maxim Integrated
17
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
Pin Description (continued)
PIN
NAME
FUNCTION
MAX1778 MAX1880 MAX1883
MAX1885
MAX1881 MAX1882 MAX1884
Linear Regulator Output. Sources up to 40mA. Bypass to GND with
a ceramic capacitor determined by:
14
—
12
—
LDOOUT
I
⎛
⎞
LDOOUT(MAX)
C
≥ 0.5ms X
LDOOUT
⎜
⎟
V
⎝
⎠
LDOOUT
Voltage Setting Input. Connect a resistive divider from the linear
regulator output (V ) to FBL to analog ground (GND).
15
16
—
13
14
—
FBL
LDOOUT
Fault Trip-Level Set Input. Connect to a resistive divider between
REF and GND to set the main step-up converter’s and positive
16
14
FLTSET
charge pump’s fault thresholds between 0.67 x V
and 0.85 x
REF
V
. Connect to GND for the preset fault threshold (0.9 x V
).
REF
REF
Negative Charge-Pump Driver Supply Voltage. Bypass to power
ground (PGND) with a 0.1µF capacitor.
17
18
17
18
—
—
—
—
SUPN
DRVN
Negative Charge-Pump Driver Output. Output high level is V
and low level is PGND.
SUPN
Positive Charge-Pump Driver Supply Voltage. Bypass to power
ground (PGND) with a 0.1µF capacitor.
19
19
—
—
SUPP
Positive Charge-Pump Driver Output. Output high level is V
and low level is PGND
SUPP
20
21
20
21
—
—
DRVP
PGND
Power Ground. Connect to analog ground (GND) underneath the
IC.
17
17
Main Step-Up Regulator Power MOSFET N-Channel Drain. Place
output diode and output capacitor as close as possible to PGND.
22
23
24
22
23
24
18
19
20
18
19
20
LX
TGND
RDY
Must be connected to ground.
Active-Low, Open-Drain Output. Indicates all outputs are ready.
On-resistance is 125Ω (typ).
11–13,
15, 16
—
13–15
15, 16
N.C.
No Connection. Not internally connected.
Maxim Integrated
18
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
L1
6.8µH
MAIN
INPUT
= 3.3V
V
= 8V
V
MAIN
IN
C
C
4.7µF
OUT
IN
R2
274kΩ
R
RDY
(2) 4.7µF
IN
LX
FB
C1
0.22µF
100kΩ
SHDN
RDY
R2
49.9kΩ
TO LOGIC
MAIN
(8V)
SUPL
SUPB
SUPN
SUPP
LDOOUT
LDO
= 5V
V
LDOOUT
C
LDO
R7
150kΩ
C4
4.7µF
C5
MAX1778
0.1µF
R8
1.0µF
49.9kΩ
DRVP
FBL
C2
0.1µF
C4
0.1µF
C7
1.0µF
DRVN
FBN
POSITIVE
= 20V
R3
750kΩ
V
POS
FBP
NEGATIVE
= -5V
R5
200kΩ
R6
49.9kΩ
V
NEG
C3
1.0µF
R4
49.9kΩ
BUFFER OUTPUT
= V /2
BUFOUT
BUF-
REF
V
BUFOUT
SUPB
C
REF
C
BUF
1.0µF
INTG
0.22µF
BUF+
GND
FLTSET
PGND
TGND
Figure 1. Typical Application Circuit
A resistor-programmable 40mA linear regulator
(MAX1778/MAX1881/MAX1883/MAX1884 only) can
provide preregulation or postregulation for any of the
supplies. For higher current applications, an external
transistor can be added.
Detailed Description
The MAX1778/MAX1880–MAX1885 are highly efficient
multiple-output power supplies for thin-film transistor
(TFT) liquid crystal display (LCD) applications. The
devices contain one high-power step-up converter, two
low-power charge pumps, an operational transconduc-
tance amplifier (VCOM buffer), and a low-dropout linear
regulator. The primary step-up converter uses an internal
N-channel MOSFET to provide maximum efficiency and
to minimize the number of external components. The out-
Additionally, the VCOM buffer provides a high current
output that is ideal for driving capacitive loads, such as
the backplane of a TFT LCD panel. The positive feed-
back input features dual-mode operation, allowing this
input to be connected to an internal 50% resistive-
divider between the buffer’s supply voltage and
ground, or externally adjusted for other voltages.
put voltage of the main step-up converter (V
) can
MAIN
be set from V to 13V with external resistors.
IN
Also included in the MAX1778/MAX1880–MAX1885 is a
precision 1.25V reference that sources up to 50µA,
logic shutdown, soft-start, power-up sequencing,
adjustable fault detection, thermal shutdown, and an
active-low, open-drain ready output.
The dual charge pumps (MAX1778/MAX1880–MAX1882
only) independently regulate a positive output (V
)
POS
and a negative output (V
). These low-power outputs
NEG
use external diode and capacitor stages (as many
stages as required) to regulate output voltages from -
40V to +40V. A unique control scheme minimizes output
ripple as well as capacitor sizes for both charge pumps.
Maxim Integrated
19
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
Changes in the feedback voltage-error signal shift the
switch-current trip level, consequently modulating the
MOSFET duty cycle.
Main Step-up Controller
During normal pulse-width modulation (PWM) opera-
tion, the MAX1778/MAX1880–MAX1885 main step-up
controllers switch at a constant frequency of 500kHz or
1MHz (see the Selector Guide), allowing the use of low-
profile inductors and output capacitors. Depending on
the input-to-output voltage ratio, the controller regulates
the output voltage and controls the power transfer by
modulating the duty cycle (D) of each switching cycle:
Under very light loads, an inherent switchover to pulse-
skipping takes place (Figure 3). When this occurs, the
controller skips most of the oscillator pulses in order to
reduce the switching frequency and gate charge loss-
es. When pulse-skipping, the step-up controller initiates
a new switching cycle only when the output voltage
drops too low. The n-channel MOSFET turns on, allow-
ing the inductor current to ramp up until the multi-input
comparator trips. Then, the MOSFET turns off and the
diode turns on, forcing the inductor current to ramp
down. When the inductor current reaches zero, the
diode turns off, so the inductor stops conducting
current. This forces the threshold between pulse-skip-
ping and PWM operation to coincide with the boundary
between continuous and discontinuous inductor-
current operation:
V
- V
IN
MAIN
V
D ≈
MAIN
On the rising edge of the internal clock, the controller
sets a flip-flop when the output voltage is too low, which
turns on the n-channel MOSFET (Figure 2). The induc-
tor current ramps up linearly, storing energy in a mag-
netic field. Once the sum of the feedback voltage error
amplifier, slope-compensation, and current-feedback
signals trip the multi-input comparator, the MOSFET
turns off, the flip-flop resets, and the diode (D1) turns
on. This forces the current through the inductor to ramp
back down, transferring the energy stored in the mag-
netic field to the output capacitor and load. The
MOSFET remains off for the rest of the clock cycle.
2
⎛
⎞
⎛
⎞
1
2
V
V
- V
IN
MAIN IN
f
I
≈
LOAD(CROSSOVER)
⎜
⎟
⎜
⎟
V
L
⎝
⎠
⎝
⎠
MAIN
OSC
L1
V
IN
(2.7V TO 5.5V)
OSC
MAX1778
MAX1880
MAX1881
MAX1882
MAX1883
MAX1884
MAX1885
(80% DUTY)
C
IN
D1
V
MAIN
LX
(UP TO 13V)
S
C
OUT
R
Q
I
LIM
PWM
R1
COMPARATOR
PGND
FB
ILIM
COMPARATOR
R
COMP
(OPTIONAL)
C
COMP
g
m
(OPTIONAL)
ERROR
AMPLIFIER
REF
R2
V
REF
C
REF
1.25V
INTG
GND
R1
R2
V
V
=
1 +
V
REF
MAIN
( )
= 1.25V
REF
C
INTG
Figure 2. Main Step-Up Converter Block Diagram
20
Maxim Integrated
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
The switching waveforms appear noisy and asynchro-
Dual Charge-Pump Regulator (MAX1778/
MAX1880–MAX1882 Only)
nous when light loading causes pulse-skipping opera-
tion; this is a normal operating condition that improves
light-load efficiency.
The MAX1778/MAX1880–MAX1882 controllers contain
two independent low-power charge pumps (Figure 4).
One charge pump inverts the input voltage and pro-
vides a regulated negative output voltage. The second
charge pump doubles the input voltage and provides a
regulated positive output voltage. The controllers
contain internal p-channel and n-channel MOSFETs to
control the power transfer. The internal MOSFETs
switch at a constant frequency (fCHP = fOSC/2).
I
I
PEAK
Positive Charge Pump
During the first half-cycle, the n-channel MOSFET turns
on and charges flying capacitor C
(Figure 4).
X(POS)
LOAD
This initial charge is controlled by the variable
n-channel on-resistance. During the second half-cycle,
the n-channel MOSFET turns off and the p-channel
TIME
t
t
OFF
ON
MOSFET turns on, level shifting C
by V
volts.
SUPP
X(POS)
This connects C
in parallel with the reservoir
X(POS)
capacitor C
. If the voltage across C
POS
level-shifted flying capacitor voltage (V
OUT(POS)
plus a diode drop (V
OUT(POS)
+ V
) is smaller than the
DIODE
+
until
CX(POS)
Figure 3. Discontinuous-to-Continuous Conduction Crossover
Point
V
), charge flows from C
to C
SUPP
X(POS)
OUT(POS)
the diode (D3) turns off.
MAX1778
MAX1880
MAX1881
MAX1882
SUPP
DRVP
SUPN
DRVN
V
V
SUPP
2.7V TO 13V
SUPN
2.7V TO 13V
OSC
D4
D5
C
D2
D3
X(NEG)
C
X(POS)
V
SUPD
R5
R3
FBP
FBN
V
POS
V
NEG
C
C
OUT(NEG)
OUT(POS)
R6
V
REF
1.25V
R4
REF
C
REF
0.22µF
R3
R4
R5
V
REF
V
V
=
1 +
V
REF
V
V
=
-
GND
PGND
POS
REF
NEG
REF
( )
(R6)
= 1.25V
= 1.25V
Figure 4. Low-Power Charge Pump Block Diagram
Maxim Integrated
21
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
Negative Charge Pump
device increases the pass transistor base current,
During the first half-cycle, the p-channel MOSFET turns
which allows more current to pass to the output and
increases the output voltage. However, the linear regu-
lator also includes an output current limit to protect the
internal pass transistor against short circuits.
on, and flying capacitor C
charges to V
SUPN
X(NEG)
minus a diode drop (Figure 4). During the second
half-cycle, the p-channel MOSFET turns off, and the
n-channel MOSFET turns on, level shifting C
.
X(NEG)
The low-dropout linear regulator monitors and controls
the pass transistor’s base current, limiting the output
current to 130mA (typ). In conjunction with the thermal
overload protection, this current limit protects the
output, allowing it to be shorted to ground for an indefi-
nite period of time without damaging the part.
This connects C
in parallel with reservoir capaci-
X(NEG)
tor C
. If the voltage across C
minus
OUT(NEG)
OUT(NEG)
a diode drop is greater than the voltage across
, charge flows from C to C until
C
X(NEG)
OUT(NEG)
X(NEG)
the diode (D5) turns off. The amount of charge trans-
ferred to the output is controlled by the variable
n-channel on-resistance.
VCOM Buffer
The MAX1778/MAX1880–MAX1885 include a VCOM
buffer, which uses an operational transconductance
amplifier (OTA) to provide a current output that is ideal
for driving capacitive loads, such as the backplane of a
TFT LCD panel. The unity-gain bandwidth of this
current-output buffer is:
Low-Dropout Linear Regulator (MAX1778/
MAX1881/MAX1883/MAX1884 Only)
The MAX1778/MAX1881/MAX1883/MAX1884 contain a
low-dropout linear regulator (Figure 5) that uses an
internal PNP pass transistor (Q ) to supply loads up to
P
40mA. As illustrated in Figure 5, the 1.25V reference is
connected to the error amplifier, which compares this
reference with the feedback voltage and amplifies the
difference. If the feedback voltage is higher than the
reference voltage, the controller lowers the base
GBW = gm/C
OUT
where gm is the amplifier’s transconductance. The
bandwidth is inversely proportional to the output
capacitor, so large capacitive loads improve stability;
however, lower bandwidth decreases the buffer’s tran-
sient response time. To improve the transient response
current of Q , which reduces the amount of current to
P
the output. If the feedback voltage is too low, the
MAX1778
MAX1881
MAX1883
MAX1884
SUPL
V
SUPL
4.5V TO 15V
C
SUPL
THERMAL
SENSOR
Q
P
CURRENT
LIMIT
V
LDOOUT
1.25V TO (V
- 0.3V)
SUPL
LDOOUT
FBL
C
LDOOUT
R7
R8
ERROR
AMPLIFIER
V
REF
1.25V
R7
R8
V
=
1 +
V
REF
LDOOUT
( )
GND
V
= 1.25V
REF
Figure 5. Low-Dropout Linear Regulator Block Diagram
Maxim Integrated
22
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
SUPB
V
SUPB
MAX1778
MAX1880
MAX1881
MAX1882
MAX1883
MAX1884
MAX1885
4.5V TO 13V
BUFOUT
BUF-
V
BUFOUT
gm
1.2V TO (V
- 1.2V)
SUPB
C
BUF
R
R11
R12
BUF+
GND
R
125mV
R12
R11 + R12
V
=
V
SUPB
BUFOUT
(
)
Figure 6. VCOM Buffer Block Diagram
ready output signal are not affected by the regulation of
the linear regulator. While the main step-up converter
powers up, the output of the PWM comparator remains
low (Figure 2), and the step-up converter charges the
output capacitors, limited only by the maximum duty
cycle and current-limit comparator. When the step-up
converter approaches its nominal regulation value and
the PWM comparator’s output changes states for the
first time, the negative charge pump turns on. When the
negative output voltage reaches approximately 90% of
times, the amplifier’s transconductance increases as
the output current increases (see the Typical Operating
Characteristics).
The VCOM buffer’s positive feedback input features
dual mode operation. The buffer’s output voltage can
be internally set by a 50% resistive divider connected
to the buffer’s supply voltage (SUPB), or the output volt-
age can be externally adjusted for other voltages.
its nominal value (V
< 110mV), the positive charge
SHDN
FBN
Shutdown (
)
pump starts up. Finally, when the positive output volt-
age reaches 90% of its nominal value (V > 1.125V),
A logic-low level on SHDN shuts down all of the con-
verters and the reference. When shut down, the supply
current drops to 0.1µA to maximize battery life, and the
reference is pulled to ground. The output capacitance,
feedback resistors, and load current determine the rate
at which each output voltage decays. A logic-level high
on SHDN power activates the MAX1778/
MAX1880–MAX1885 (see the Power-Up Sequencing
section). Do not leave SHDN floating. If unused, con-
nect SHDN to IN. A logic-level transition on SHDN
clears the fault latch.
FBP
the active-low ready signal (RDY) goes low (see the
Power Ready section), and the VCOM buffer powers
up. The MAX1883–MAX1885 do not contain the charge
pumps, but the power-up sequence still contains the
charge pumps’ startup logic, which appears as a delay
ꢀ
(2 4096/fOSC) between the step-up converter reach-
ing regulation and when the ready signal and VCOM
buffer are activated.
Soft-Start
For the main step-up regulator, soft-start allows a grad-
ual increase of the current-limit level during startup to
reduce input surge currents. The MAX1778/MAX1880–
MAX1885 divide the soft-start period into four phases.
During the first phase, the controller limits the current
limit to only 0.38A (see the Electrical Characteristics),
approximately a quarter of the maximum current limit
Power-Up Sequencing
Upon power-up or exiting shutdown, the MAX1778/
MAX1880–MAX1885 start a power-up sequence. First,
the reference powers up. Then, the main DC-DC step-
up converter powers up with soft-start enabled. The lin-
ear regulator powers up at the same time as the main
step-up converter; however, the power sequence and
Maxim Integrated
23
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
(I
). If the output does not reach regulation within
set by FLTSET (see the Fault Trip Level (FLTSET) sec-
tion). For the negative charge pump, the fault threshold
measured at the charge-pump’s feedback input (FBN) is
140mV (typ).
LX(MAX)
1ms, soft-start enters phase II, and the current limit is
increased by another 25%. This process is repeated for
phase III. The maximum 1.5A (typ) current limit is
reached within 3072 clock cycles or when the output
reaches regulation, whichever occurs first (see the
startup waveforms in the Typical Operating
Characteristics).
RDY
Power Ready (
)
RDY is an open-drain output. When the power-up
sequence for the main step-up converter and low-
power charge pumps has properly completed, the 14V
MOSFET turns on and pulls RDY low with a 125Ω (typ)
on-resistance. If a fault is detected on any of these
three outputs, the internal open-drain MOSFET appears
as a high impedance. Connect a 100kΩ pullup resistor
between RDY and IN for a logic-level output.
For the charge pumps (MAX1778/MAX1880–MAX1882
only), soft-start is achieved by controlling the rate of
rise of the output voltage. Both charge-pump output
voltages are controlled to be in regulation within 4096
clock cycles, irregardless of output capacitance and
load, limited only by the charge pump’s output imped-
ance. Although the MAX1883–MAX1885 controllers do
not include the charge pumps, the soft-start logic still
contains the 4096 clock cycle startup periods for both
charge pumps.
Voltage Reference (REF)
The voltage at REF is nominally 1.25V. The reference can
source up to 50µA with good load regulation (see the
Typical Operating Characteristics). Connect a 0.22µF
ceramic bypass capacitor between REF and GND.
Fault Trip Level (FLTSET)
The MAX1778/MAX1880–MAX1885 feature dual-mode
operation to allow operation with either a preset fault
trip level or an adjustable trip level for the step-up con-
verter and positive charge-pump outputs. Connect
ꢀ
Thermal-Overload Protection
Thermal-overload protection limits total power dissipa-
tion in the MAX1778/MAX1880–MAX1885. When the
junction temperature exceeds T = +160°C, a thermal
J
FLTSET to GND to select the preset 0.9
V
fault
REF
sensor activates the fault protection, which shuts down
the controller, allowing the IC to cool. Once the device
cools down by 15°C, toggle shutdown (below 0.8V) or
cycle the input voltage (below 0.2V) to clear the fault
latch and reactivate the controller. Thermal-overload
protection protects the controller in the event of fault
conditions. For continuous operation, do not exceed
the absolute maximum junction-temperature rating of
threshold. The fault trip level can also be adjusted by
connecting a voltage-divider from REF to FLTSET
(Figure 8). For greatest accuracy, the total load on the
reference (including current through the negative
charge-pump feedback resistors) should not exceed
50µA so that V
is guaranteed to be in regulation
REF
(see the Electrical Characteristics). Therefore, select
R10 in the 100kΩ to 1MΩ range, and calculate R9 with
the following equation:
T = +150°C.
J
Operating Region and Power Dissipation
R9 = R10 [(V
/V
) - 1]
REF FLTSET
The MAX1778/MAX1880–MAX1885s’ maximum power
dissipation depends on the thermal resistance of the IC
package and circuit board, the temperature difference
between the die junction and ambient air, and the rate
of any airflow. The power dissipated in the device
depends on the operating conditions of each regulator
and the buffer.
where V
x V
= 1.25V, and V
can range from 0.67
REF
to 0.85 x V
FLTSET
. FLTSET’s input bias current has
REF
REF
a maximum value of 50nA. For 1% error, the current
through R10 should be at least 100 times the FLTSET
input bias current (I
).
FLTSET
Fault Condition
The step-up controller dissipates power across the
internal n-channel MOSFET as the controller ramps up
the inductor current. In continuous conduction, the
power dissipated internally can be approximated by:
Once RDY is low, if the output of the main regulator or
either low-power charge pump falls below its fault
detection threshold, or if the input drops below its
undervoltage threshold, then RDY goes high impedance
and all outputs shut down; however, the reference
remains active. After removing the fault condition, toggle
shutdown (below 0.8V) or cycle the input voltage (below
0.2V) to clear the fault latch and reactivate the device.
2
2
⎡
⎢
⎢
⎣
⎤
⎥
⎥
⎦
⎛
⎞
⎛
⎜
⎞
I
V
V D
IN
1
12 f
MAIN MAIN
P
≈
+
STEP−UP
⎜
⎟
⎟
V
L
⎝
⎠
⎝
⎠
IN
OSC
× R
D
The reference fault threshold is 1.05V. For the step-up
converter and positive charge-pump, the fault trip level is
DS(ON)
Maxim Integrated
24
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
where I
includes the primary load current and the
MAIN
input supply currents for the charge pumps (see the
Charge-Pump Input Power and Efficiency
Considerations section), linear regulator, and VCOM
buffer.
P
= (T
) - T )/(θ + θ
)
MAX
J(MAX
A
JB
BA
where T - T is the temperature difference between
J
A
the controller’s junction and the surrounding air, θ (or
JB
The linear regulator generates an output voltage by dis-
sipating power across an internal pass transistor, so
the power dissipation is simply the load current times
the input-to-output voltage differential:
θ
) is the thermal resistance of the package to the
JC
board, and θ
to the surrounding air.
is the thermal resistance from the PCB
BA
Design Procedure
P
= I
(V
- V
)
LDO(INT)
LDO SUPL
LDO
Main Step-Up Converter
Output-Voltage Selection
Adjust the output voltage by connecting a voltage-
When driving an external transistor, the internal linear
regulator provides the base drive current. Depending
on the external transistor’s current gain (β) and the
maximum load current, the power dissipated by the
internal linear regulator can still be significant:
divider from the output (V
) to FB to GND (see the
MAIN
Typical Operating Circuit). Select R2 in the 10kΩ to
50kΩ range. Calculate R1 with the following equations:
I
LDO
β
P
=
V
- V
+ 0.7V
(
)
]
[
LDO(INT)
SUPL
LDO
R1 = R2 [(V
/V
) - 1]
MAIN REF
= I
(V
- V
)
LDOOUT SUPL
LDOOUT
where V
= 1.25V. V
can range from V to 13V.
REF
MAIN IN
The charge pumps provide regulated output voltages
by dissipating power in the low-side n-channel
MOSFET, so they could be modeled as linear regula-
tors followed by unregulated charge pumps. Therefore,
their power dissipation is similar to a linear regulator:
Inductor Selection
Inductor selection depends upon the minimum required
inductance value, saturation rating, series resistance, and
size. These factors influence the converter’s efficiency,
maximum output load capability, transient response time,
and output-voltage ripple. For most applications, values
between 4.7µH and 22µH work best with the controller’s
switching frequency (Tables 1 and 2).
P
= I
V
- 2V
N - V
(
[
)
[
]
NEG
NEG SUPN
DIODE NEG
P
= I
V
- 2V
N + V
)
- V
POS
(
]
POS
POS
SUPP
DIODE
SUPD
The inductor value depends on the maximum output
load the application must support, input voltage, output
voltage, and switching frequency. With high inductor
values, the MAX1778/MAX1880–MAX1885 source high-
er output currents, have less output ripple, and enter
continuous conduction operation with lighter loads;
however, the circuit’s transient response time is slower.
On the other hand, low-value inductors respond faster
to transients, remain in discontinuous conduction oper-
ation, and typically offer smaller physical size for a
given series resistance and current rating. The equa-
tions provided here include a constant LIR, which is the
ratio of the peak-to-peak AC inductor current to the
average DC inductor current. For a good compromise
between the size of the inductor, power loss, and
output-voltage ripple, select an LIR of 0.3 to 0.5. The
inductance value is then given by:
where N is the number of charge-pump stages, V
DIODE
is the
is the diodes’ forward voltage, and V
SUPD
positive charge-pump diode supply (Figure 4).
The VCOM buffer’s power dissipation depends on the
capacitive load (C
) being driven, the peak-to-
P-P
LOAD
peak voltage change (V ) across the load, and the
load’s switching rate:
P
= V
C f V
BUF
P - P LOAD LOAD SUPB
To find the total power dissipated in the device, the
power dissipated by each regulator and the buffer must
be added together:
P
= P
+ P
TOTAL
STEP - UP LDO(INT)
+ P
+ P
+ P
NEG
POS BUF
2
⎛
⎞
⎟
V
V
- V
⎛
⎞
1
LIR
⎛
⎞
IN(MIN)
MAIN IN(MIN)
L
=
η
⎜
⎝
⎟
⎠
MIN
⎜
⎜
⎟
The maximum allowed power dissipation is 975mW (24-
pin TSSOP)/879mW (20-pin TSSOP) or:
V
I
f
⎝
⎠
MAIN
⎝
MAIN(MAX) OSC ⎠
Maxim Integrated
25
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
where η is the efficiency, f
is the oscillator frequen-
Output-voltage ripple has two components: variations
in the charge stored in the output capacitor with each
LX pulse, and the voltage drop across the capacitor’s
equivalent series resistance (ESR) caused by the
current into and out of the capacitor:
OSC
cy (see the Electrical Characteristics), and I
MAIN
includes the primary load current and the input supply
currents for the charge pumps (see the Charge-Pump
Input Power and Efficiency Considerations section), lin-
ear regulator, and VCOM buffer. Considering the typi-
cal application circuit, the maximum average DC load
V
= V
+ V
RIPPLE
RIPPLE(C) RIPPLE(ESR)
current (I
) is 300mA with an 8V output. Based
MAIN(MAX)
V
≈ I
R , AND
RIPPLE(ESR)
PEAK ESR(COUT)
on the above equations and assuming 85% efficiency,
⎛
⎞⎛
⎞
V
− V
I
the inductance value is then chosen to be 4.7µH.
MAIN
V
IN
MAIN
V
≈
RIPPLE(C)
⎜
⎟⎜
⎟
C
f
⎝
⎠⎝
⎠
The inductor’s saturation current rating should exceed
the peak inductor current throughout the normal operat-
ing range. The peak inductor current is then given by:
MAIN
OUT OSC
where I
is the peak inductor current (see the
PEAK
Inductor Selection section). For ceramic capacitors, the
output-voltage ripple is typically dominated by V
RIP-
⎛
⎞
I
V
⎛
⎞
LIR
2
1
η
MAIN(MAX) MAIN ⎛
⎞
. The voltage rating and temperature characteris-
I
=
1 +
⎜
PLE(C)
⎟
⎠
⎜
⎟
⎜
⎝
⎟
⎠
PEAK
⎝
V
IN(MIN)
tics of the output capacitor must also be considered.
⎝
⎠
Feedback Compensation
Under fault conditions, the inductor current can reach
up to 1.85A (I ), see the Electrical
Characteristics). However, the controller’s fast current-
limit circuitry allows the use of soft-saturation inductors
while still protecting the IC.
For stability, add a pole-zero pair from FB to GND in the
LIM(MAX)
form of a compensation resistor (R
) in series with
COMP
), as shown in Figure
a compensation capacitor (C
COMP
2. Select R
to be half the value of R2, the low-side
COMP
feedback resistor.
The inductor’s DC resistance can significantly affect
efficiency due to the power loss in the inductor. The
Integrator Capacitor
The MAX1778/MAX1880–MAX1885 contain an internal
current integrator that improves the DC load regulation
but increases the peak-to-peak transient voltage (see
the load-transient waveforms in the Typical Operating
Characteristics). For highly accurate DC load regula-
tion, enable the current integrator by connecting a
power loss due to the inductor’s series resistance (P
can be approximated by the following equation:
)
LR
2
⎛
⎞
I
X V
MAIN
MAIN
P
≅ R
L
LR
⎜
⎟
V
⎝
⎠
IN
470pF (ƒ
= 1MHz)/1000pF (ƒ
= 500kHz)
OSC
OSC
where R is the inductor’s series resistance. For best per-
L
capacitor to INTG. To minimize the peak-to-peak tran-
sient voltage at the expense of DC regulation, disable
the integrator by connecting INTG to REF. When using
the MAX1883–MAX1885, connect a 100kΩ resistor to
GND when disabling the integrator.
formance, select inductors with resistance less than the
internal n-channel MOSFET on-resistance (0.35Ω typ).
Use inductors with a ferrite core or equivalent. To mini-
mize radiated noise in sensitive applications, use a
shielded inductor.
Input Capacitor
Output Capacitor
Output capacitor selection depends on circuit stability
and output-voltage ripple. A 10µF ceramic capacitor
works well in most applications (Tables 1 and 2).
Additional feedback compensation is required (see the
Feedback Compensation section) to increase the mar-
gin for stability by reducing the bandwidth further. In
cases where the output capacitance is sufficiently large,
additional feedback compensation is not necessary.
The input capacitor (C ) in step-up designs reduces
IN
the current peaks drawn from the input supply and
reduces noise injection. The value of C is largely
IN
determined by the source impedance of the input sup-
ply. High source impedance requires high input capac-
itance, particularly as the input voltage falls. Since
step-up DC-DC converters act as “constant-power
”
loads to their input supply, input current rises as input
voltage falls. A good starting point is to use the same
capacitance value for C as for C
.
IN
OUT
Maxim Integrated
26
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
Rectifier Diode
Use a Schottky diode with an average current rating
equal to or greater than the peak inductor current, and
a voltage rating at least 1.5 times the main output volt-
charge pump’s output impedance can be approximat-
ed using the following equation:
⎛
⎞
1
R
= 2(R
+ R
)+
TX
PCH(ON)
NCH(ON)
⎜
⎟
age (V
).
MAIN
C f
⎝
⎠
X CHP
Charge Pumps (MAX1778/ MAX1880/
MAX1881/MAX1882 Only)
Selecting the Number of Charge-Pump Stages
⎛
⎞
⎟
1
+
⎜
C
f
⎝
⎠
OUT CHP
The number of charge-pump stages required to regu-
late the output voltage depends on the supply voltage,
output voltage, load current, switching frequency, the
diode’s forward voltage drop, and ceramic capacitor
values.
where the charge pump’s switching frequency (f
) is
CHP
equal to 0.5 x f
, the p-channel MOSFET’s on-resis-
OSC
tance (R
) is 10Ω, and the n-channel MOSFET’s
PCH(ON)
on-resistance (R
Characteristics).
)) is 4Ω (see the Electrical
NCH(ON
For positive charge-pump outputs, the number of
required stages can be determined by:
For negative charge-pump outputs, the number of
required stages can be determined by:
⎛
⎞
V
- V
SUPD
POS
N
≥
⎛
⎞
V
POS
⎜
⎟
NEG
V
- 1.1(2V
+ R
I
)
⎝
⎠
N
≥
SUPP
DIODE
TX LOAD
NEG
⎜
⎟
V
- 1.1(2V
+ R
I
)
⎝
⎠
SUPN
DROP
TX LOAD
where V
(Figure 4), V
is the positive charge-pump diode supply
DIODE
and R is the charge pump’s output impedance. The
SUPD
is the diode’s forward voltage drop,
where N
is rounded up to the nearest integer.
NEG
TX
Table 1. MꢁX1778/MꢁX1880/MꢁX1883 Component Values (f
= 1MHz)
OSC
CIRCUIT 1
3.3V
CIRCUIT 2
3.3V
CIRCUIT 3
3.3V
CIRCUIT 4
5V
CIRCUIT 5
5V
V
IN
V
9V
9V
9V
12V
12V
MAIN
MAIN(MAX)
I
100mA
-5V
200mA
-5V
200mA
-5V
220mA
-5V
220mA
-5V
V
NEG
NEG
I
2mA
5mA
5mA
5mA
5mA
V
24V
24V
24V
24V
24V
POS
I
2mA
5mA
5mA
5mA
5mA
POS
L
2.2µH
>1A
4.7µH
>1A
4.7µH
>1A
6.8µH
>1A
6.8µH
>1A
I
PEAK
C
4.7µF
309kΩ
49.9kΩ
None
None
10µF
309kΩ
49.9kΩ
None
None
20µF
10µF
429kΩ
49.9kΩ
None
None
20µF
OUT
R1
309kΩ
49.9kΩ
39kΩ*
100pF*
429kΩ
49.9kΩ
20kΩ*
200pF*
R2
R
C
COMP
COMP
*R
and C
are connected between the step-up converter’s output (V
) and FB.
COMP
COMP
MAIN
Maxim Integrated
27
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
Table 2. MꢁX1881/MꢁX1882/MꢁX1884/MꢁX1885 Component Values (f
= 500kHz)
OSC
CIRCUIT 6
3.3V
CIRCUIT 7
3.3V
CIRCUIT 8
3.3V
CIRCUIT 9
3.3V
V
IN
V
9V
9V
9V
9V
MAIN
MAIN(MAX)
I
100mA
-5V
100mA
-5V
200mA
-5V
200mA
-5V
V
NEG
NEG
I
2mA
2mA
5mA
5mA
V
24V
24V
24V
24V
POS
I
2mA
2mA
5mA
5mA
POS
L
4.7µH
>1A
10µH
>1A
10µH
>1A
10µH
>1A
I
PEAK
C
4.7µF
309kΩ
49.9kΩ
None
10µF
309kΩ
49.9kΩ
None
10µF
309kΩ
49.9kΩ
None
20µF
309kΩ
49.9kΩ
20kΩ*
OUT
R1
R2
R
C
COMP
None
None
None
200pF*
COMP
*R
COMP
and C
are connected between the step-up converter’s output (V
) and FB.
MAIN
COMP
Charge-Pump Input Power and
Efficiency Considerations
Table 3. Component Suppliers
The charge pumps in the MAX1778/MAX1880–MAX1882
provide regulated output voltages by controlling the
voltage drop across the low-side n-channel MOSFET, so
they can be modeled as linear regulators followed by an
unregulated charge pump when determining the input
power requirements and efficiency.
SUPPLIER
INDUCTORS
Coilcraft
PHONE
FAX
847-639-6400
561-241-7876
847-956-0666
847-297-0070
847-639-1469
561-241-9339
847-956-0702
847-699-1194
Coiltronics
Sumida USA
TOKO
The charge pump only provides charge to the output
capacitor during half the period (50% duty cycle), so
the input current is a function of the number of stages
and the load current:
CAPACITORS
AVX
803-946-0690
408-986-0424
619-661-6835
408-573-4150
803-626-3123
408-986-1442
619-661-1055
408-573-4159
KEMET
SANYO
I
= I
(N+1)
Taiyo Yuden
DIODES
Central
Semiconductor
SUPP
POS
for the positive charge pump, and:
= I (N+1)
516-435-1110
310-322-3331
516-435-1824
310-322-3332
I
SUPP
POS
International
Rectifier
for the negative charge pump, where N is the number
of charge-pump stages.
Motorola
Nihon
602-303-5454
847-843-7500
516-543-7100
602-994-6430
847-843-2798
516-864-7630
The efficiency characteristics of the MAX1778/
MAX1880–MAX1882 regulated charge pumps are simi-
lar to a linear regulator. It is dominated by quiescent
current at low output currents and by the input voltage
Zetex
Maxim Integrated
28
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
at higher output currents (see the Typical Operating
Characteristics). So the maximum efficiency can be
approximated by:
V
> 1.5(V
N)
CXN(NEG)
SUPN
for the negative charge pump, where N is the stage
number in which the flying capacitor appears, and
SUPD
VPOS
VSUPD + VSUPP
ηPOS
≅
N
V
is the positive charge pump’s diode supply
(Figure 4). For example, the two-stage positive charge
pump in the typical application circuit (Figure 1) where
for the positive charge pump, and:
VNEG
V
= V
= 8V contains two flying capacitors.
SUPD
SUPP
The flying capacitor in the first stage (C4) requires a
voltage rating over 12V. The flying capacitor in the
second stage (C6) requires a voltage rating over 24V.
ηNEG
≅
VSUPNN
Charge-Pump Output Capacitor
Increasing the output capacitance or decreasing the
ESR reduces the output ripple voltage and the peak-to-
peak transient voltage. With ceramic capacitors, the
output-voltage ripple is dominated by the capacitance
value. Use the following equation to approximate the
required capacitor value:
for the negative charge pump, where V
is the
SUPD
positive charge pump’s diode supply (Figure 4).
Output-Voltage Selection
Adjust the positive output voltage by connecting a volt-
age-divider from the output (V ) to FBP to GND (see
POS
the Typical Operating Circuit). Adjust the negative
output voltage by connecting a voltage-divider from the
I
output (V ) to FBN to REF. Select R4 and R6 in the
NEG
LOAD
V
C
≥
OUT
50kΩ to 100kΩ range. Higher resistor values improve
efficiency at low output current but increase output-
voltage error due to the feedback input bias current. For
the negative charge pump, higher resistor values also
reduce the load on the reference, which should not
exceed 50µA for greatest accuracy (including current
f
CHP RIPPLE
where f
is typically f
/2 (see the Electrical
OSC
CHP
Characteristics).
Charge-Pump Input Capacitor
Use a bypass capacitor with a value equal to or greater
than the flying capacitor. Place the capacitor as close
as possible to the IC. Connect directly to power ground
(PGND).
through the FLTSET resistors) to guarantee that V
REF
remains in regulation (see the Electrical Characteristics).
Calculate the remaining resistors with the following
equations:
Charge-Pump Rectifier Diodes
Use Schottky diodes with a current rating equal to or
greater than two times the average charge-pump input
R3 = R4 [(V
/V
) - 1]
POS REF
R5 = R6 |V
/V
|
NEG REF
current, and a voltage rating at least 1.5 times V
SUPP
for the positive charge pump and V
negative charge pump.
for the
SUPN
where V
= 1.25V. V
can range from V
to
SUPP
REF
POS
40V, and V
can range from 0V to -40V.
NEG
Low-Dropout Linear Regulator (MAX1778/
MAX1881/MAX1883/MAX1884 Only)
Flying Capacitor
Increasing the flying capacitor (CX) value increases the
output current capability. Above a certain point,
increasing the capacitance has a negligible effect
because the output current capability becomes domi-
nated by the internal switch resistance and the diode
impedance. The flying capacitor’s voltage rating must
exceed the following:
Output-Voltage Selection
Adjust the linear-regulator output voltage by connecting
a voltage-divider from LDOOUT to FBL to GND
(Figure 5). Select R8 in the 5kΩ to 50kΩ range. Calculate
R7 with the following equation:
R7 = R8 [(V
/V
) - 1]
LDOOUT FBL
where V
= 1.25V, and V
can range from
LDOOUT
FBL
V
> 1.5 V
+ V
(N -1)
1.25V to (V - 300mV). FBL’s input bias current is
SUPL
[
]
CXN(POS)
SUPD
SUPP
0.8µA (max). For less than 0.5% error due to FBL input
bias current (I ), R8 must be less than 8kΩ.
BL
F
for the positive charge pump, and:
Maxim Integrated
29
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
Capacitor Selection and Regulator Stability
Capacitors are required at the input and output of the
MAX1778/MAX1881/MAX1883/MAX1884 for stable
operation over the full temperature range and with load
currents up to 40mA. Connect a 1µF input bypass
For stable operation, place a capacitor (C
) and
LDOOUT
a minimum load resistor (R5) at the output of the inter-
nal linear regulator (the base of the external transistor)
to set the dominant pole:
⎛
⎞
1
capacitor (C
) between SUPL and ground to lower
SUPL
C
≥ 0.5ms
LDOOUT
⎜
⎟
the source impedance of the input supply. Connect a
ceramic capacitor between LDOOUT and ground,
using the following equation to determine the lowest
value required for stable operation:
V
⎝
⎠
LDO
I
⎛
⎞
V
+ 0.7V
R5
LOAD(MAX)
LDO
x
+
⎜
⎟
β
⎝
⎠
MIN
I
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
LDOOUT(MAX)
Since the LDO cannot sink current, a minimum pull-
down resistor (R5) is required at the base of the npn
transistor to sink leakage currents and improve the
high-to-low load-transient response. Under no-load
conditions, leakage currents from the internal pass
C
≥ 0.5ms X
LDOOUT
V
LDOOUT
For example, with a 5V linear regulator output voltage
and a maximum 40mA load, use at least 4µF of output
capacitance. Applications that experience high-current
load pulses may require more output capacitance.
transistor supply the output capacitor (C
), even
LDOOUT
when the transistor is off. As the leakage currents
increase over temperature, charge can build up on
The ESR of the linear regulator’s output capacitor
C
, making the linear regulator’s output rise
LDOOUT
(C
) affects stability and output noise. Use output
LDOOUT
above its set point. Therefore, R5 must sink at least
100µA to guarantee proper regulation. Additionally, the
minimum load current provided by R5 improves the
high-to-low load transients by lowering the impedance
capacitors with an ESR of 0.1Ω or less to ensure stability
and optimum transient response. Surface-mount ceram-
ic capacitors are good for this purpose. Place C
SUPL
and C
as close as possible to the linear regula-
LDOOUT
seen by C
after the transient occurs. Therefore,
LDOOUT
tor to minimize the impact of PCB trace inductance.
if large load transients are expected, select R5 so that
the minimum load current is 10% of the transistor’s
maximum base current:
External Pass Transistor
For applications where the linear regulator currents
exceed 40mA or where the power dissipation in the IC
needs to be reduced, an external npn transistor can be
used. In this case, the internal LDO only provides the
necessary base drive while the external npn transistor
supports the load, so most of the power dissipation occurs
across the external transistor’s collector and emitter.
⎡
⎢
V
+ 0.7V
(V
+ 0.7V)β
I
LOAD(MAX)
LDO
LDO MIN
R5 =
= 0.1
I
⎢
⎣
LDOOUT(MIN)
Alternatively, output capacitance placed on the external
linear regulator’s output (the emitter) adds a second pole
that could destabilize the regulator. A capacitive-divider
from the transistor’s base to the feedback input (C2 and
C3, Figure 7) circumvents this second pole by adding a
pole-zero pair. Furthermore, to minimize excessive over-
shoot, the capacitive-divider’s ratio must be the same as
the resistive-divider’s ratio. Once the output capacitor is
selected, using the following equations to determine the
required capacitive-divider values:
Selection of the external npn transistor is based on
three factors: the package’s power dissipation, the cur-
rent gain (β), and the collector-to-emitter saturation volt-
age (V
). First, the maximum power dissipation
CE(SAT)
should not exceed the transistor’s package rating:
P = (V − V ) x I
LOAD(MAX)
COLLECTOR
LDO
Once the appropriate package type is selected,
consider the npn transistor’s current gain. Since the
internal LDO cannot source more than 40mA (min), the
transistor’s current gain must be high enough at the
lowest collector-to-emitter voltage to support the
maximum output load:
C
100
R4
R3
⎛
⎝
⎞
⎠
LDO
C2 + C3 ≥
1 +
⎜
⎟
C2
R4
R3 + R4
V
REF
V
=
=
C2 + C3
LDO
I
- 40mA
LOAD(MAX)
β
≥
MIN
40mA
Maxim Integrated
30
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
Input-to-Output (Dropout) Voltage and Startup
voltage-divider from SUPB to BUF+ to GND (Figure 6).
Select R12 in the 10kΩ to 100kΩ range. Calculate R11
with the following equation:
A linear regulator’s minimum input-to-output voltage dif-
ferential (dropout voltage) determines the lowest use-
able supply voltage. Because the MAX1778/
MAX1881/MAX1883/MAX1884 use an internal pnp tran-
sistor (or external npn transistor), their dropout voltage
is a function of the transistor’s collector-to-emitter satu-
ration voltage (see the Typical Operating
Characteristics). The linear regulator’s quiescent cur-
rent increases when in dropout.
⎡
⎢
⎤
⎛
⎞
V
V
SUPB
R11 = R12
- 1
⎥
⎜
⎟
⎝
⎢
⎣
⎠
BUF+
⎥
⎦
where V
can range from 4.5V to 13V, and V
BUF+
SUPB
can range from 1.2V to (V
- 1.2V). Connect a mini-
SUPB
mum 1µF ceramic capacitor from BUFOUT to ground.
The internal linear regulator tries to start up once its
supply voltage (V
) exceeds 4V. When the linear
PCB Layout and Grounding
Careful PCB layout is extremely important for proper
operation. Follow the following guidelines for good PCB
layout:
SUPL
regulator powers up, the linear regulator may be in
dropout if the linear regulator’s output set voltage is
higher than its input supply voltage. Therefore, during
this brief period, the linear regulator draws additional
supply current until the input supply voltage exceeds
the output set voltage plus the pass transistor’s satura-
1) Place the main step-up converter output diode and
output capacitor less than 0.2in (5mm) from the LX
and PGND pins with wide traces and no vias.
tion voltage (V
) + V
).
LDO(SET
CE(SAT)
2) Separate analog ground and power ground. The
ground connections for the step-up converter’s and
charge pump’s input and output capacitors should
be connected to the power ground plane. The lin-
ear regulator’s and VCOM buffer’s input and output
capacitors should be connected to a separate
power-ground path, star-connected to the PGND
pin to minimize voltage drops. When using multi-
VCOM Buffer (Operational
Transconductance Amplifier)
Buffer Output Voltage and Capacitor Selection
The positive input (BUF+) features dual-mode opera-
tion. Connect BUF+ to GND for the preset V
/2 out-
SUPB
put voltage, set by an internal 50% resistive-divider.
Adjust the amplifier’s output voltage by connecting a
L1
6.8µH
INPUT
= 3.3V
MAIN
V
V
MAIN
= 8V
IN
C
IN
C
OUT
4.7µF
(2) 4.7µF
R1
274kΩ
LX
FB
IN
SHDN
C1
0.22µF
R2
C
1µF
49.9kΩ
LDOIN
MAX1778
MAX1883
(MAX1881)*
(MAX1884)*
SUPL
LDOOUT
Q1
INTG
REF
C
4.7µF
LDOOUT
R5
1.5kΩ
LDO
C
V
= 2.5V
REF
LDO
C2
C
1µF
LDO
0.22µF
0.01µF
R3
49.9kΩ
FBL
C3
R4
49.9kΩ
0.01µF
PGND
GND
Figure 7. External Linear Regulator
Maxim Integrated
31
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
layer boards, the top layer should contain the boost
regulator and charge-pump power ground plane,
and the inner layer should contain the analog
ground plane and power-ground plane/path for the
VCOM buffer and LDO. Connect all three ground
planes together at one place near the PGND pin.
between fast-charging nodes on the top layer and
high-impedance nodes on the bottom layer. The
fast-charging nodes, such as the LX and charge-
pump driver nodes, should not have any other
traces or ground planes near by.
5) Keep the charge-pump circuitry as close as possi-
ble to the IC, using wide traces and avoiding vias
when possible. Place 0.1µF ceramic bypass
capacitors near the charge-pump input pins (SUPP
and SUPN) to the PGND pin.
3) Locate all feedback resistive-dividers as close as
possible to their respective feedback pins. The volt-
age-divider’s center trace should be kept short.
Avoid running any feedback trace near the LX
switching node or the charge-pump drivers. The
resistive-dividers’ ground connections should be to
analog ground (GND).
6) To maximize output power and efficiency and mini-
mize output ripple voltage, use extra-wide, power-
ground traces, and solder the IC’s power-ground
pin directly to it.
4) When using multilayer boards, separate the top sig-
nal layer and bottom signal layer with a ground
plane between to eliminate capacitive coupling
Refer to the MAX1778/MAX1880–MAX1885 evaluation
kit for an example of proper board layout.
L1
10µH
MAIN
INPUT
V
= 12V
V
IN
= 5V
MAIN
C
C
IN
OUT
C1
0.22µF
R
RDY
R1
86.6kΩ
(2) 4.7µF
(2) 10µF
R
IN
LX
FB
COMP
100kΩ
4.7kΩ
SHDN
TO LOGIC
RDY
C
470pF
R2
10kΩ
COMP
SUPL
SUPB
SUPN
SUPP
Q1
LDOOUT
LDO
C
LDOOUT
4.7µF
V
= 3.3V
LDO
R8
1.5kΩ
C4
0.1µF
C6
1µF
MAX1778
R7
16.4kΩ
DRVP
FBP
C6
0.01µF
R8
10kΩ
FBL
POSITIVE
= 20V
V
POS
C5
1.0µF
R3
750kΩ
R4
49.9kΩ
DRVN
C7
C2
0.1µF
0.01µF
NEGATIVE
= -8V
FBN
BUFFER OUTPUT
= V /2
BUFOUT
BUF-
V
NEG
C3
1.0µF
V
R5
316kΩ
BUFOUT
SUPB
C
1.0µF
BUF
R9
R6
30kΩ
49.9kΩ
FLTSET
REF
REF
BUF+
GND
R10
100kΩ
INTG
C
REF
PGND
TGND
0.22µF
Figure 8. 5V Input Monitor Application
Maxim Integrated
32
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
Larger output capacitors with higher voltage ratings
Applications Information
allow configurations with output voltages above 10V.
Additionally, physically larger inductors with less series
resistance and higher saturation ratings provide more
output current and higher efficiency.
Low-Profile Components
Notebook applications generally require low-profile
components, potentially limiting the circuit’s perfor-
mance. For example, low-profile inductors typically
have lower saturation ratings and more series resis-
tance, limiting output current and efficiency. Low-profile
capacitors have lower voltage ratings for a given
capacitance value, so 3.3µF low-profile capacitors with
voltage ratings greater than 10V were not available at
the time of publication.
Input Voltage Above and
Below the Output Voltage
Combining the step-up converter and linear regulator
as shown in Figure 9 provides output-voltage regulation
above and below the input voltage. Supplied by the
step-up converter, the linear regulator output provides
a constant output voltage (V
). When the input volt-
LDO
age exceeds the main step-up converter’s nominal out-
put voltage, the controller stops switching but the linear
regulator maintains the output voltage. When the input
voltage drops below the output voltage, the step-up
Desktop Monitors
Monitor applications do not have the same component
height restrictions associated with laptops, allowing
more flexibility in component selection (Figure 8).
L1
6.8µH
POWER INPUT
V
BATT
= 10V TO 15V
C
IN
C
OUT
4.7µF
(3) 3.3µF
R1
511kΩ
INPUT
= 3.3V TO 5V
LX
FB
IN
V
IN
C1
0.1µF
R2
SHDN
49.9kΩ
R
RDY
100kΩ
TO LOGIC
BUFFER OUTPUT
RDY
SUPL
BUFOUT
BUF-
V
= V /2
BUFOUT
SUPB
Q1
LDOOUT
C
1.0µF
BUF
C
3.3µF
LDOOUT
C6
0.1µF
C2
0.1µF
MAX1778
LDO
SUPB
SUPN
SUPP
DRVN
FBN
V
= 13V
LDO
C7
0.1µF
C
R9
6.8kΩ
LDO
R7
470kΩ
(2) 3.3µF
NEGATIVE
= -12V
V
NEG
C3
1.0µF
R5
475kΩ
FBL
R8
R6
49.9kΩ
49.9kΩ
C4
0.1µF
REF
C
REF
DRVP
FBP
R9
30kΩ
0.22µF
R10
100kΩ
POSITIVE
V
POS
= 24V
C5
1.0µF
FLTSET
INTG
R3
909kΩ
BUF+
GND
R4
49.9kΩ
C
INTG
PGND
TGND
470pF
Figure 9. Input Voltage Above and Below the Output Voltage
Maxim Integrated
33
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
L1
6.8µH
STARTUP MAIN
= 8V
SYSTEM MAIN
V
V
= 8V
MAIN(START)
MAIN(SYS)
INPUT
V
= 3.3V
IN
C
IN
C
OUT
C8
4.7µF
(2) 3.3µF
3.3µF
R1
274kΩ
LX
FB
IN
SHDN
C1
0.22µF
R2
49.9kΩ
C10
0.1µF
SUPP
DRVP
C4
0.1µF
C5
1.0µF
R7
10kΩ
MAX1778
C6
0.1µF
C7
1.0µF
INTG
REF
C
REF
R3
750kΩ
0.22µF
R9
30kΩ
FBP
STARTUP
POSITIVE
SYSTEM
POSITIVE
V = 20V
POS(SYS)
FLTSET
R4
49.9kΩ
Q3
Q2
V
= 20V
POS(START)
R10
100kΩ
INPUT
= 3.3V
V
IN
RDY
TGND
GND
R
R8
100kΩ
RDY
5.1kΩ
PGND
Figure 10. Power-Up Sequencing and Fault Protection
converter steps up the input voltage so that the linear
regulator will not drop out. Therefore, to guarantee that
the external pass transistor does not saturate, the step-
up converter’s output voltage must be set above the lin-
ear regulator’s output voltage plus the transistor’s
the pnp transistor. Any fault on the positive charge-
pump output pulls down the charge pump’s output volt-
age and triggers the fault protection; otherwise, the
MOSFET’s gate slow charges. Once the MOSFET turns
on, any faults on the main step-up converter’s output
pull down the main output voltage and trigger the fault
protection.
saturation rating (V
≥ V
+ V
).
MAIN
LDO
SAT
Power-Up Sequencing and Fault Protection
The MAX1778/MAX1880–MAX1885’s fault protection
cannot be activated until the power-up sequence is
successfully completed and the power-ready output
goes low. Therefore, faults on the main output or posi-
tive charge-pump output could damage the controller
or external components. Additional fault protection can
be added as shown in Figure 10. The external MOSFET
and pnp transistor isolate the positive outputs during
startup. When the controller finishes the power-up
sequence, the power-ready output goes low, turning on
VCOM Buffer Startup
The VCOM buffer does not include soft-start. Therefore,
once the VCOM buffer turns on, it draws high surge
currents while charging the output capacitance. In
some applications, the buffer’s high startup surge
current could potentially trip the fault-detection circuit,
forcing the controller to shut down. In these cases,
adding a soft-start resistive-divider between SUPB and
BUFOUT reduces the startup surge current and voltage
drops associated with this load (Figure 11), as shown in
Maxim Integrated
34
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
L1
6.8µH
INPUT
= 3.3V
MAIN
V
V
= 8V
IN
MAIN
C
C
OUT
IN
4.7µF
(2) 4.7µF
R1
274kΩ
LX
FB
IN
SHDN
C1
0.22µF
R2
49.9kΩ
MAX1778
INTG
REF
SUPB
BUF-
C
1.0µF
SUPB
R3
10kΩ
C
REF
0.22µF
BUFFER OUTPUT
= V /2
BUFOUT
BUF+
V
BUFOUT
SUPB
C
BUF
R4
10kΩ
1.0µF
PGND
GND
V
SUPB
R3 = R4
-1
[( V ) ]
BUFOUT
Figure 11. VCOM Buffer Soft-Start
the Typical Operating Characteristics. Set the resistive-
divider to precharge BUFOUT, matching the buffer’s
output set voltage:
Selector Guide
STEP-UP
SWITCHING
FREQUENCY
(Hz)
DUAL
LINEAR
CHARGE
REGULATOR
PUMPS
PART
⎡
⎢
⎤
⎛
⎞
V
SUPB
R3 = R4
− 1
⎥
⎜
⎟
V
⎝
⎢
⎣
⎠
BUFOUT
⎥
⎦
Yes
Yes
Yes
Yes
No
MAX1778
MAX1880
MAX1881
MAX1882
MAX1883
MAX1884
MAX1885
1M
1M
Yes
No
These resistor values are selected to charge the output
capacitor close to the output set voltage before the
buffer starts up:
500k
500k
1M
Yes
No
Yes
Yes
No
5000
No
500k
500k
C
(R3||R4) ≈
BUFOUT
f
OSC
No
Maxim Integrated
35
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
Typical Operating Circuit
MAIN
INPUT
IN
LX
FB
SHDN
TO LOGIC
RDY
SUPL
LDOOUT
SUPB
SUPN
SUPP
LDO OUTPUT
MAX1778
FBL
DRVP
FBP
DRVN
FBN
POSITIVE
NEGATIVE
BUFOUT
BUF-
BUFFER OUTPUT
REF
BUF+
FLTSET
GND
INTG
PGND
TGND
Maxim Integrated
36
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
Pin Configurations
TOP VIEW
+
+
FB
INTG
IN
1
2
3
4
5
6
7
8
9
24 RDY
FB
INTG
IN
1
2
3
4
5
6
7
8
9
24 RDY
23 TGND
22 LX
23 TGND
22 LX
BUF+
BUF-
SUPB
BUFOUT
GND
21 PGND
20 DRVP
19 SUPP
18 DRVN
17 SUPN
16 FLTSET
15 FBL
BUF+
BUF-
SUPB
BUFOUT
GND
21 PGND
20 DRVP
19 SUPP
18 DRVN
17 SUPN
16 FLTSET
15 N.C.
14 N.C.
13 N.C.
MAX1778
MAX1881
MAX1880
MAX1882
REF
REF
FBP 10
FBN 11
FBP 10
FBN 11
14 LDOOUT
13 SUPL
SHDN 12
SHDN 12
TSSOP
TSSOP
TOP VIEW
+
+
FB
INTG
IN
1
2
3
4
5
6
7
8
9
20 RDY
19 TGND
18 LX
FB
INTG
IN
1
2
3
4
5
6
7
8
9
20 RDY
19 TGND
18 LX
BUF+
BUF-
SUPB
BUFOUT
GND
17 PGND
16 N.C.
15 N.C.
BUF+
BUF-
SUPB
BUFOUT
GND
17 PGND
16 N.C.
15 N.C.
MAX1883
MAX1884
MAX1885
14
14
FLTSET
FLTSET
13 FBL
13 N.C.
12 N.C.
11 N.C.
REF
12 LDOOUT
11 SUPL
REF
SHDN 10
SHDN 10
TSSOP
TSSOP
Maxim Integrated
37
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
Package Information
Chip Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
TRANSISTOR COUNT: 3739
LꢁND
PꢁTTERN NO.
PꢁCKꢁGE
TYPE
PꢁCKꢁGE
CODE
OUTLINE NO.
90-0116
90-0118
20 TSSOP
24 TSSOP
U20-2
U24-1
21-0066
21-0066
Maxim Integrated
38
MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC/DC
Converters with Buffer
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
2
10/12
Added MAX1880EUG/V+ to Ordering Information
1
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________ 39
© 2012 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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