MAX1761EEE+ [MAXIM]
Switching Controller, Current-mode, 428kHz Switching Freq-Max, PDSO16, 0.150 INCH, 0.025 INCH PITCH, QSOP-16;
| 型号： | MAX1761EEE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Switching Controller, Current-mode, 428kHz Switching Freq-Max, PDSO16, 0.150 INCH, 0.025 INCH PITCH, QSOP-16 开关 光电二极管 |
| 文件： | 总23页 (文件大小：472K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1835; Rev 0; 10/00
Small, Dual, High-Efficiency
Buck Controller for Notebooks
General Description
Features
The MAX1761 dual pulse-width-modulation (PWM),
step-down controller provides high efficiency, excellent
transient response, and high DC output accuracy in an
extremely compact circuit topology. These features are
essential for stepping down high-voltage batteries to
generate low-voltage CPU core, I/O, and chipset RAM
supplies in PC board area critical applications, such as
notebook computers and smart phones.
o Free-Running On-Demand PWM
o Selectable Light-Load Pulse-Skipping Operation
o ±±1 ꢀotal Dꢁ ꢂrror in Forced-PWM Mode
o 5V to 20V Input Range
o Flexible Output Voltages
OUꢀ±: Dual Mode™ Fixed 2.5V or ±V to 5.5V
Adjustable
Maxim’s proprietary Quick-PWM™ quick-response,
constant-on-time PWM control scheme handles wide
input/output voltage ratios with ease and provides
“instant-on” response to load transients while maintain-
ing a relatively constant switching frequency.
OUꢀ2: Dual Mode Fixed ±.8V or ±V to 5.5V
Adjustable
o Output Undervoltage Protection
o ꢁomplementary Synchronous Buck
o No ꢁurrent-Sense Resistor
The MAX1761 achieves high efficiency at reduced cost
by eliminating the current-sense resistor found in tradi-
tional current-mode PWMs. Efficiency is further
enhanced by its ability to drive large synchronous-recti-
fier MOSFETs. The MAX1761 employs a complemen-
tary MOSFET output stage, which reduces component
count by eliminating external bootstrap capacitors and
diodes.
o 4.65V at 25mA Linear Regulator Output
o 4µA V+ Shutdown Supply ꢁurrent
o 5µA VL Shutdown Supply ꢁurrent
o 950µA Quiescent Supply ꢁurrent
o ꢀiny ±6-Pin QSOP Package
Single-stage buck conversion allows this device to
directly step down high-voltage batteries for the highest
possible efficiency. Alternatively, two-stage conversion
(stepping down the +5V system supply instead of the
battery) at a higher switching frequency allows the mini-
mum possible physical size.
The MAX1761 is intended for CPU core, chipset,
DRAM, or other low-voltage supplies. The MAX1761 is
available in a 16-pin QSOP package. For applications
requiring greater output power, refer to the MAX1715
data sheet. For a single-output version, refer to the
MAX1762/MAX1791 data sheet.
Ordering Information
PART
TEMP. RANGE
PIN-PACKAGE
MAX1761EEE
-40°C to +85°C
16 QSOP
Pin Configuration
________________________Applications
Notebooks and PDAs
TOP VIEW
Digital Cameras
FB1
OUT1
REF
1
2
3
4
5
6
7
8
16 DH1
15 CS1
14 DL1
Handy-Terminals
Smart Phones
1.8V/2.5V Logic and I/O Supplies
ON2
V+
MAX1761
13 VL
12 GND
11 DL2
10 CS2
ON1
OUT2
FB2
9
DH2
Quick-PWM and Dual Mode are trademarks of
Maxim Integrated Products.
QSOP
________________________________________________________________ Maxim Integrated Products
±
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Small, Dual, High-Efficiency
Buck Controller for Notebooks
ABSOLUTE MAXIMUM RATINGS
V+ to GND..............................................................-0.3V to +22V
VL to GND ................................................................-0.3V to +6V
VL to V+ .............................................................................+0.3V
OUT_, ON2 to GND..................................................-0.3V to +6V
ON1, DH_ to GND ........................................-0.3V to (V+ + 0.3V)
FB_, REF, DL_ to GND.................................-0.3V to (VL + 0.3V)
CS_ to GND.....................................................-2V to (V+ + 0.3V)
REF Short Circuit to GND...........................................Continuous
Continuous Power Dissipation
16-Pin QSOP (derate 8.3mW/°C above +70°C)......….667mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature.........................................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = 15V, C = 4.7µF, C
= 0.1µF, VL not externally driven unless otherwise noted, T = 0°C to +85°C, unless
A
VL
REF
otherwise noted.) (Note 1)
PARAMETER
PWM CONTROLLERS
Input Voltage Range
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V+
(Note 2)
4.5
0.99
2.475
1.782
1
20
1.01
2.525
1.818
5.5
V
V
FB_ = OUT_
FB1 = GND
FB2 = GND
1
V+= 4.5V to 20V,
VL= 4.75V to 5.25V,
ON2 = VL
DC Output Voltage Accuracy
(Note 3)
V
2.5
1.8
OUT_
Output Voltage Adjust Range
OUT_ Input Resistance
FB_ Input Bias Current
CS_ Input Bias Current
Soft-Start Ramp Time
V
80
160
300
0.1
kΩ
µA
µA
µs
V
V
= 1V, VL = 5V
= 0, VL = 5V
-0.1
-1
FB_
CS_
1
Zero to full ILIM
1700
735
720
400
OUT1
OUT2
661
648
809
792
500
V+= 10V, V
= 2.5V,
OUT1
On-Time (Note 4)
t
ns
ns
ON
V
= 1.8V
OUT2
Minimum Off-Time (Note 4)
t
OFF
BIAS AND REFERENCE
FB1 = FB2 = GND, VL = 5V, V
and
OUT1
IL
0.60
1.20
mA
mA
V
forced above regulation point
OUT2
Quiescent Supply Current
FB1 = FB2 = GND, V
VL undriven
VL = 5V
0.95
0.38
1.70
0.65
OUT1
and V
forced
I+
OUT2
above regulation point
IL
I+
VL = 5V, ON1 = ON2 = GND
VL = 0, 5V
5
4
10
10
µA
µA
V
Shutdown Supply Current
VL Output Voltage
VL
I
= 0 to 25mA, V+ = 5V to 20V
4.5
4.65
2
4.75
2.02
8
LOAD
Reference Voltage
Reference Load Regulation
REF Sink Current
V
V+ = 5V to 20V, no load
= 0 to 50µA
1.98
V
REF
REF
I
I
mV
µA
REF
REF in regulation
Falling edge
10
1.6
REF Fault Lockout Voltage
V
Rising edge
1.94
2
_______________________________________________________________________________________
Small, Dual, High-Efficiency
Buck Controller for Notebooks
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, C = 4.7µF, C
= 0.1µF, VL not externally driven unless otherwise noted, T = 0°C to +85°C, unless
A
VL
REF
otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FAULT PROTECTION
Output Undervoltage Threshold
(Foldback)
V
With respect to the regulation point, no load
60
70
80
32
%
FB,UVFB
Output Undervoltage Blanking
Time
V
Measured from ON_ signal going high
GND - CS_, positive direction
10
92
ms
FB,UVLO(t)
100
-120
2.5
108
Current-Limit Threshold
mV
GND - CS_, negative direction, ON2 = floating -135
GND - CS_, zero crossing, ON2 = 5V
Hysteresis = 10oC
-105
Thermal Shutdown Threshold
160
oC
V
VL Undervoltage Lockout
Threshold
Rising edge, hysteresis = 20mV, PWM is
disabled below this voltage
V
4.1
4.4
VL,UVLO
GATE DRIVERS
DH_ Gate Driver On-Resistance
(Pullup)
V+ = 6V to 20V, DH_, high state
DH_, low state
3.7
6.2
3.4
2.0
0.6
8
10
8
Ω
Ω
Ω
Ω
A
DH_ Gate Driver On-Resistance
(Pulldown)
DL_ Gate Driver On-Resistance
(Pullup)
DL_ , high state
DL_ Gate Driver On-Resistance
(Pulldown)
DL_, low state
5
DH_ Gate Driver Source/Sink
Current
V
= 3V, V+ = 6V
DH_
DL_ Gate Drive Sink Current
DL_ Gate Drive Source Current
LOGIC CONTROLS
V
V
= 2.5V
= 2.5V
0.9
0.5
A
A
DL_
DL_
ON_ Logic Input High Voltage
2.05
1.3
V
V
ON2 Logic Input Float Voltage
(Forced-PWM Mode)
2.0V < V
< VL
1.7
1.95
ON1
ON_ Logic Input Low Voltage
ON1 Logic Input Current
0.5
1
V
-1
0
µA
µA
µA
mV
ON2 Logic High Input Current
ON2 Logic Low Input Current
FB_ Dual Mode Threshold
V
V
> 2.0V
1
3
ON2
ON2
< 0.5V, V
> 2.0V
-2
50
-1
0
ON1
100
150
_______________________________________________________________________________________
3
Small, Dual, High-Efficiency
Buck Controller for Notebooks
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = 15V, C = 4.7µF, C
= 0.1µF, VL not externally driven unless otherwise noted, T = -40°C to +85°C,
A
VL
REF
unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLERS
V+
VL
(Note 2)
4.5
4.75
0.99
2.475
1.782
1
20
5.25
1.01
2.525
1.818
5.5
V
Input Voltage Range
VL externally driven (Note 2)
FB_ = OUT_
FB1 = GND
FB2 = GND
V+= 4.5V to 20V,
VL= 4.75V to 5.25V,
ON2 = VL
DC Output Voltage Accuracy
(Note 3)
V
V
OUT_
Output Voltage Adjust Range
OUT_ Input Resistance
FB_ Input Bias Current
CS_ Input Bias Current
Soft-Start Ramp Time
V
80
300
0.1
kΩ
µA
µA
µs
V
V
= 1V, VL = 5V
= 0, VL = 5V
-0.1
-1
FB_
CS_
1
Zero to full ILIM
OUT1
OUT2
661
648
809
792
500
V+= 10V, V
= 2.5V,
OUT1
On-Time (Note 4)
t
ns
ns
ON
V
= 1.8V
OUT2
Minimum Off-Time (Note 4)
t
Above regulation point
OFF
BIAS AND REFERENCE
FB1 = FB2 = GND, VL = 5V, V
and
OUT1
IL
1.2
1.7
mA
mA
V
forced above regulation point
OUT2
Quiescent Supply Current
Shutdown Supply Current
FB1 = FB2 = GND, V
OUT1
VL undriven
VL = 5V
I+
and V
forced above
OUT2
regulation point
0.5
10
IL
I+
VL = 5V, ON1 = ON2 = GND
VL = 0, 5V
µA
µA
V
10
VL Output Voltage
VL
I
= 0 to 25mA, V+ = 5V to 20V
4.5
4.75
2.02
8
LOAD
Reference Voltage
V
V+ = 5V to 20V, no load
= 0 to 50µA
1.98
V
REF
REF
Reference Load Regulation
REF Sink Current
I
I
mV
µA
REF
REF in regulation
10
60
FAULT PROTECTION
Output Undervoltage Threshold
(Foldback)
V
With respect to the regulation point, no load
80
32
%
ms
mV
V
FB,UVFB
Output Undervoltage Lockout
Timer
V
Measured from ON_ signal going high
10
92
FB,UVLO(t)
GND – CS_, positive direction
108
Current-Limit Threshold
GND – CS_, negative direction, ON2 = floating -135
-105
VL Undervoltage Lockout
Threshold
Rising edge, hysteresis = 20mV, PWM is
disabled below this voltage
V
4.1
4.4
VL,UVLO
4
_______________________________________________________________________________________
Small, Dual, High-Efficiency
Buck Controller for Notebooks
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, C = 4.7µF, C
= 0.1µF, VL not externally driven unless otherwise noted, T = -40°C to +85°C,
A
VL
REF
unless otherwise noted.) (Note 1)
PARAMETER
GATE DRIVERS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DH_ Gate Driver On-Resistance
(Pullup)
V+ = 6V to 20V, DH_, high state
DH_, low state
8
10
8
Ω
Ω
Ω
Ω
A
DH_ Gate Driver On-Resistance
(Pulldown)
DL_ Gate Driver On-Resistance
(Pullup)
DL_, high state
DL_ Gate Driver On-Resistance
(Pulldown)
DL_, low state
5
DH_ Gate Driver Source/Sink
Current
V
= 3V, V+ = 6V
DH_
DL_ Gate Drive Sink Current
DL_ Gate Driver Source Current
LOGIC CONTROLS
V
V
= 2.5V
= 2.5V
A
A
DL_
DL_
ON_ Logic Input High Voltage
2.05
1.3
V
V
ON2 Logic Input Float Voltage
(Forced-PWM Mode)
V
> 2.0V
1.95
ON1
ON_ Logic Input Low Voltage
ON1 Logic Input Current
0.5
1
V
-1
0
µA
µA
µA
mV
ON2 Logic High Input Current
ON2 Logic Low Input Current
FB_ Dual Mode Threshold
V
V
> 2.0V
3
ON2
ON2
< 0.5V, V
> 2.0V
-2
50
0
ON1
150
Note 1: Specifications to -40°C are guaranteed by design, not production tested.
Note 2: If V+ is less than 5V, V+ must be connected to VL. If VL is connected to V+, V+ must be between 4.5V and 5.5V.
Note 3: DC output accuracy specifications refer to the trip-level error of the error amplifier. The output voltage will have a DC regula-
tion higher than the trip level by 50% of the ripple. In PFM mode, the output will rise by approximately 1.5% when transition-
ing from continuous conduction to no load.
Note 4: One-shot times are measured at the DH pin (V+ = 15V, C
= 400pF, 90% point to 90% point). Actual in-circuit times may
DH
be different due to MOSFET switching speeds.This effect can also cause the switching frequency to vary.
_______________________________________________________________________________________
5
Small, Dual, High-Efficiency
Buck Controller for Notebooks
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
EFFICIENCY vs. LOAD CURRENT
EFFICIENCY vs. LOAD CURRENT
(2.5V, PWM MODE)
EFFICIENCY vs. LOAD CURRENT
(1.8V, SKIP MODE)
(V
= 2.5V, SKIP MODE)
OUT
100
100
100
V+ = +5V = VL
90 V+ = +5V = VL
90
80
70
60
50
40
30
20
90
80
70
60
50
40
30
20
80
70
60
50
40
30
20
V+ = +5V = VL
V+ = +7V
V+ = +18V
V+ = +12V
V+ = +7V
V+ = +12V
V+ = +12V
V+ = +7V
V+ = +18V
V+ = +18V
10
0
10
0
10
0
1
10
100
1000
10,000
1
10
100
1000
10,000
1
10
100
1000
10,000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
EFFICIENCY vs. LOAD CURRENT
(1.8V, PWM MODE)
EFFICIENCY vs. LOAD CURRENT
(3.3V, SKIP MODE)
EFFICIENCY vs. LOAD CURRENT
(3.3V, PWM MODE)
100
100
100
V+ = +5V = VL
90
80
70
60
50
40
30
20
90
80
70
60
50
40
30
20
90
80
70
60
50
40
30
20
V+ = +5V = VL
V+ = +5V = VL
V+ = +7V
V+ = +18V
V+ = +12V
V+ = +18V
V+ = +7V
V+ = +18V
V+ = +7V
V+ = +12V
V+ = +12V
10
0
10
0
10
0
1
10
100
LOAD CURRENT (mA)
1000
10,000
1
10
100
1000
10,000
1
10
100
1000
10,000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
EFFICIENCY vs. LOAD CURRENT
(2.5V, SKIP MODE, 3.5A COMPONENTS)
FREQUENCY vs. LOAD CURRENT
VL VOLTAGE vs. OUTPUT CURRENT
100
350
300
250
200
150
100
50
0
90
80
70
60
50
40
30
20
V+ = +5V
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
-0.35
-0.40
-0.45
V
OUT
= + 2.5V
V
V
= + 1.8V
OUT
V+ = +18V
V+ = +12V
V
= + 2.5V
OUT
= + 1.8V
OUT
V+ = +7V
V
V
= 2.5V, I
= 1.8V, I
= 2A,
= 2A
10
0
OUT1
OUT1
SKIP MODE
PWN MODE
OUT2
OUT2
0
1
10
100
1000
10,000
0
400
800
1200
1600
2000
0
5
10
15
20
25
30
35
LOAD CURRENT (mA)
LOAD CURRENT (mA)
VL CURRENT (mA)
6
_______________________________________________________________________________________
Small, Dual, High-Efficiency
Buck Controller for Notebooks
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT vs. INPUT VOLTAGE
SUPPLY CURRENT vs. INPUT VOLTAGE
(PWM MODE)
NO-LOAD SUPPLY CURRENT vs.
INPUT VOLTAGE (SHUTDOWN)
(SKIP MODE)
8
7
6
5
4
3
2
1
0
0.7
30
25
20
15
10
5
0.6
0.5
0.4
0.3
0.2
ON1 = VL, ON2 = FLOAT
NO LOAD
ON1 = VL, ON2 = VL
0.1
NO LOAD
ON1 = GND, 0N2 = VL
0
0
4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5 20.5
4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5 20.5
INPUT VOLTAGE (V)
4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5 20.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
LOAD-TRANSIENT RESPONSE
LOAD-TRANSIENT RESPONSE
OUTPUT OVERLOAD WAVEFORMS
(2.5A COMPONENTS, V
= 2.5V)
(2.5A COMPONENTS, V
= 1.8V)
(I
= 4V, V
= 2.5V)
OUT
OUT
OUT
OUT
A
A
A
B
B
B
C
C
C
20 µs/div
20 µs/div
100 µs/div
A: V , AC-COUPLED, 10mV/div
OUT
B: INDUCTOR CURRENT, 1A/div
C: DL1, 5V/div
A: V , AC-COUPLED, 5mV/div
OUT
B: INDUCTOR CURRENT, 1A/div
C: DL1, 5V/div
A: V , 1V/div
OUT
B: INDUCTOR CURRENT, 2A/div
C: DL1, 2V/div
STARTUP AND SHUTDOWN WAVEFORMS
(V = 2.5V)
STARTUP AND SHUTDOWN WAVEFORMS
(V = 1.8V)
OUT
OUT
A
B
A
B
C
C
500 µs/div
500 µs/div
A: V , 2V/div
A: V , 2V/div
OUT
OUT
B: INDUCTOR CURRENT, 2A/div
B: INDUCTOR CURRENT, 2A/div
C: DL1, 5V/div
C: DL1, 5V/div
_______________________________________________________________________________________
7
Small, Dual, High-Efficiency
Buck Controller for Notebooks
Pin Description
PIN
NAME
FUNCTION
Feedback Input for the 2.5V PWM. Connect FB1 to GND for a fixed 2.5V output. Connect a resistive
voltage-divider to FB1 to adjust OUT1 from 1V to 5.5V. FB1 regulates to 1V (see Adjusting V section) .
1
FB1
OUT
Output Voltage Connection for PWM1. OUT1 senses the output voltage to set the regulator on-time
and is connected internally to a 160kΩ feedback input in fixed-output mode.
2
3
OUT1
REF
2V Reference Voltage Output. Bypass REF to GND with 0.1µF (min) capacitor. Can supply 50µA for
external loads.
When ON1 = High, Normal/Forced PWM Mode Selection and OUT2 On/Off Control Input
ON2 CONDITION
MODE SELECTED
4
ON2
LOW (ON2 < 0.5V)
OUT1 is enabled in normal mode; OUT2 is shut down.
HIGH (2V < ON2 < VL) Both outputs are enabled in normal mode.
Floating Both outputs are enabled in forced-PWM mode.
Battery Voltage. V+ is the input for the VL regulator and DH gate drivers and is also used for PWM
one-shot timing.
5
6
7
V+
On/Off Control Input. Drive ON1 high to enable the device. Drive ON1 low to enter micropower
shutdown mode. Both REF and VL are disabled in shutdown. ON1 may be pinstrapped to V+.
ON1
OUT2
Output Voltage Connection for PWM2. OUT2 senses the output voltage to set the regulator on-time
and is connected internally to a 160kΩ feedback input in fixed-output mode.
Feedback Input for the 1.8V PWM. Connect FB2 to GND for a fixed 1.8V output. Connect a resistive
8
9
FB2
DH2
CS2
voltage-divider to FB2 to adjust OUT2 from 1V to 5.5V. FB2 regulates to 1V (see Adjusting V
section) .
OUT
High-Side Gate Driver Output for PWM2. Swings between GND and V+.
Current-Sense Connection for PWM2. Connect CS2 to the drain of the low-side driver. Alternatively,
connect CS2 to the junction of the source of the low-side FET and a current-sense resistor to GND.
10
11
12
DL2
Low-Side Gate Driver Output for PWM2. DL2 swings between GND and VL.
Combined Power and Analog Ground
GND
Linear Regulator Output. VL is the output of the 4.65V internal linear regulator, capable of supplying
25mA for external loads. The VL pin also serves as the supply input for the DL gate driver and the
analog/logic blocks. VL can be overdriven by an external 5V supply to improve efficiency. Bypass
VL to GND with a 4.7µF ceramic capacitor.
13
VL
14
15
16
DL1
CS1
DH1
Low-Side Gate Driver Output for PWM1. DL1 swings between GND and VL.
Current-Sense Connection for PWM1. Connect CS1 to the drain of the low-side driver. Alternatively,
connect CS1 to the junction of the source of the low-side FET and a current-sense resistor to GND.
High-Side Gate Driver Output for PWM1. DH1 swings between GND and V+.
8
_______________________________________________________________________________________
Small, Dual, High-Efficiency
Buck Controller for Notebooks
5V < V
< 20V
BATT
10Ω
0.1µF
10µF
V+
ON1
DH1
DH2
V
V
OUT1
OUT2
LX1
7µH
LX2
7µH
2.5V
+1.8V
MAX1761
220µF
220µF
DL2
CS2
DL1
CS1
R1
R2
R3
R4
OUT1
VL
OUT2
REF
0.1µF
ON2
FB1
4.7µF
FB2
GND
Figure 1. Typical Application Circuit
nates external boost capacitors and diodes, reducing
PC board area and cost. The MAX1761 can step down
input voltages from 5V to 20V, to outputs ranging from
1V to 5.5V on either output. Dual Mode feedback inputs
allow fixed output voltages of 2.5V and 1.8V for OUT1
and OUT2, respectively; or, a resistive voltage-divider
can be used to adjust the output voltages from 1V to
5.5V. Other appropriate applications for this device are
digital cameras, large PDAs, and handy-terminals.
Typical Application Circuit
The typical application circuit in Figure 1 generates two
low-voltage rails for general-purpose use in notebook
and subnotebook computers (I/O supply, fixed CPU
core supply, DRAM supply). This DC-DC converter
steps down a battery or AC adapter voltage to voltages
from 1.0V to 5.5V with high efficiency and accuracy.
See Table 1 for a list of components for common appli-
cations. Table 2 lists component manufacturers.
V+ Input and VL +5V Logic Supplies
The MAX1761 has a 5V to 20V input voltage supply
range. A linear regulator powers the control logic and
other internal circuitry from the input supply pin (V+).
The linear regulator’s 4.65V output is available at VL
and can supply 25mA to external circuitry. When used
as an external supply, bypass VL to GND with a 4.7µF
capacitor. VL is turned off when the device is in shut-
down, and drops to approximately 4V when the device
experiences an output voltage fault.
Detailed Description
The MAX1761 dual buck controller is designed for low-
voltage power supplies in notebook and subnotebook
computers. Maxim’s proprietary Quick-PWM pulse-
width modulation circuit (Figure 2) is specifically
designed for handling fast load steps while maintaining
a relatively constant operating frequency over a wide
range of input voltages. The Quick-PWM architecture
circumvents the poor load-transient timing problems of
fixed-frequency current-mode PWMs while preventing
problems caused by widely varying switching frequen-
cies in conventional constant-on-time and constant-off-
time PWM schemes.
The MAX1761 includes an input undervoltage lockout
(UVLO) circuit that prevents the device from switching
until VL > 4.25V (max). UVLO ensures there is sufficient
drive for the external MOSFETs, prevents the high-side
MOSFET from being turned on for near 100% duty
cycle, and keeps the output in regulation. The UVLO
This MAX1761 controls two synchronously rectified out-
puts with complementary N- and P-channel MOSFETs.
Using the P-channel for the high-side MOSFET elimi-
_______________________________________________________________________________________
9
Small, Dual, High-Efficiency
Buck Controller for Notebooks
Table 1. Component Selection for Standard Applications
COMPONENT
Input Range
Frequency
2.5V AT 2.0A
5V to 18V
2.5V AT 3.5A
5V to 18V
1.8V AT 2.0A
5V to 18V
3.3V AT 2A
5V to 18V
350kHz
350kHz
250kHz
350kHz
Complementary
P- and N-Channel
MOSFETs
Fairchild FDS8958A
Siliconix IRF7319
Fairchild FDS8958A
Fairchild FDS8958A
7µH
3.5µH
Sumida CDRH127-
7µH
10µH
Sumida CDRH104-
Sumida CDRH104-
Sumida CDRH104-
Inductor
7R0NC
3R5NC
7R0NC
100NC
10µF, 25V
Taiyo Yuden
2 x 10µF, 25V
Taiyo Yuden
10µF, 25V
Taiyo Yuden
10µF, 25V
Taiyo Yuden
Input Capacitor
Output Capacitor
TMK432BJ106KM
TMK432BJ106KM
TMK432BJ106KM
TMK432BJ106KM
330µF, 10V
Kemet
2 x 330µF, 10V
Kemet
330µF, 10V
Kemet
330µF, 10V
Kemet
T510X337K101
T510X337K010
T510X337K010
T510X337K010
R = Short
1
R = 1k
1
R = Short
3
R = Short
1
Current-Sense
Feedback Resistors
R = Open
2
R = 1k
2
R = Open
4
R = Open
2
Table 2. Component Suppliers
Voltage Reference (REF)
The internal 2V reference is accurate to 1% (max)
over temperature and can supply a 50µA load current.
Bypass REF to GND with a 0.1µF capacitor when REF
is unloaded. Use a 0.22µF capacitor when applying an
external load.
SUPPLIER
PHONE
WEB
Fairchild
Semiconductor
408-822-2181
www.fairchildsemi.com
Kemet
408-986-0424
847-468-5624
www.kemet.com
Panasonic
www.panasonic. com
Free-Running Constant-On-Time PWM
Controller with Input Feed-Forward
www.rohmelectronics.
com
Rohm
760-929-2100
The Quick-PWM control architecture is a constant-on-
time, current-mode type with voltage feed-forward
(Figure 3). This architecture relies on the output ripple
voltage to provide the PWM ramp signal. Thus, the out-
put filter capacitor’s ESR acts as a feedback resistor.
The control algorithm is simple: the high-side switch on-
time is determined solely by a one-shot whose period is
inversely proportional to input voltage and directly pro-
portional to output voltage (see the On-Time One-Shot
section). Another one-shot sets a minimum off-time
(400ns typical). The on-time one-shot is triggered if the
error comparator is low, the low-side switch current is
below the current-limit threshold, and the minimum off-
time one-shot has timed out.
Sanyo
619-661-6835
408-988-8000
847-956-0666
408-573-4150
www.secc.co.jp
www.vishay.com
www.sumida.com
www.t-yuden.com
Siliconix
Sumida
Taiyo Yuden
comparator has 40mV hysteresis to prevent startup
oscillations on slowly rising input voltages.
If VL is not driven externally, then V+ should be at least
5V to ensure proper operation. If V+ is running from a
5V ( 10%) supply, V+ should be externally connected
to VL. Overdriving the VL regulator with an external 5V
supply also increases the MAX1761’s efficiency.
10 ______________________________________________________________________________________
Small, Dual, High-Efficiency
Buck Controller for Notebooks
V
IN
V
IN
VL
LINEAR
REG
2V
REF
REF
REF
VL
V
C
C
C
L
REF
MAX1761
V+
OUT1
V
IN
V
IN
C
IN2
IN1
ON1
DL1
DRIVER
DH2
DRIVER
DH1
DH2
DH
DH
Q3
Q1
PWM
CONTROL
BLOCK
ZERO
CROSSING
PWM
CONTROL
BLOCK
ZCC1
ZCC2
ZERO
CROSSING
CS2
CS1
ILIM
ILIM
ILIM2
ILIM1
VL
VOS
-0.1V
-0.1V
L1
L2
OUT1
OUT2
VL
DL1
DL2
C
OUT1
DL1
C
DL2
D1
OUT2
D2
Q2
DL
DL
Q4
DRIVER
DRIVER
OUT1
ON1
OUT2
OUT
OUT
ON1
ON2
SHDN
SHDN
ON2
GND
Figure 2. Functional Diagram
twofold: first, the switching noise occurs at a known fre-
quency and is easily filtered; second, the inductor rip-
ple current remains relatively constant, resulting in
predictable output voltage ripple and a relatively sim-
ple design procedure. The difference in frequencies
between OUT1 and OUT2 prevents audio-frequency
“beating” and minimizes crosstalk between the two
SMPS. The on-times can be calculated by using the
equation below that references the K values listed in
Table 3.
On-Time One-Shot
The heart of the PWM core is the one-shot that sets the
high-side switch on-time for both controllers. This fast,
low-jitter, adjustable one-shot includes circuitry that
varies the on-time in response to battery and output
voltage. The high-side switch on-time is inversely pro-
portional to the battery voltage as measured by the V+
input, and proportional to the output voltage. This algo-
rithm results in a nearly constant switching frequency
despite the absence of a fixed-frequency clock genera-
tor. The benefits of a constant switching frequency are
V
+ 0.1V
OUT_
On- Time = K
V
IN
Table 3. On-Time One-Shot
K
(µs)
2.857
4.000
MIN
(kHz)
318
227
TYP
(kHz)
350
250
MAX
(kHz)
428
278
The 0.1V offset term accounts for the expected drop
across the low-side MOSFET switch.
DEVICE
OUT1
OUT2
______________________________________________________________________________________ 11
Small, Dual, High-Efficiency
Buck Controller for Notebooks
TOFF
VIN
1-SHOT
Q
ON-TIME
COMPUTE
TRIG
TO DH DRIVER INPUT
TO DL DRIVER INPUT
OUT
Q
1-SHOT
TON
S
R
Q
Q
TRIG
S
R
Q
1-SHOT
FROM ZERO-CROSSING DETECTOR
FROM CURRENT-LIMIT COMPARATOR
ERROR
AMP
x2
GAIN
DRIVER
REF
REF
-30%
MAX1761
OUT
FB
UVP
FROM OUT
FEEDBACK
MUX
(SEE FIGURE 12)
SHDN
ON/OFF
CONTROL
UVP
LATCH
TIMER
SHDN
FROM FEEDBACK
Figure 3. PWM Controller (One Side Only)
The maximum on-time and minimum off-time, t
,
Resistive voltage drops in the inductor loop and the
dead-time effect cause switching-frequency variations.
Parasitic voltage losses decrease the effective voltage
applied to the inductor. The MAX1761 compensates by
shifting the duty cycle to maintain the regulated output
voltage. The resulting change in frequency is:
OFF(MIN)
one-shots restrict the continuous-conduction output
voltage. The worst-case dropout performance occurs
with the minimum on-time and the maximum off-time, so
the worst-case duty cycle for V = 6V, V
IN
given by:
= 5V is
OUT1
V
+V
DROP1
t
OUT
ON(MIN)
ƒ =
Duty Cycle=
=
t
(V +V
)
ON IN
DROP2
t
+ t
OFF(MAX)
ON(MIN)
2.054µs
2.054µs + 500ns
V
is the sum of the parasitic voltage drops in the
DROP1
= 80.4%
inductor discharge path, including synchronous rectifi-
er, inductor, and PC board resistances; V is the
DROP2
The duty cycle is ideally determined by the ratio of
input-to-output voltage (Duty Cycle = V /V ).
sum of the resistances in the charging path; and t
the on-time calculated by the MAX1761.
is
ON
OUT IN
Voltage losses in the loop cause the actual duty cycle
to deviate from this relationship. See the Dropout
Performance section for more information. Equate the
off-time duty cycle restriction to the nonideal input/out-
put voltage duty cycle ratio. Typical units will exhibit
better performance. Operation of any power supply in
dropout will greatly reduce the circuit’s transient
response, and some additional bulk capacitance may
be required to support fast load changes.
In forced PWM mode, the dead-time effect increases
the effective on-time, reducing the switching frequency
as one or both dead times. This occurs only at light or
negative loads when the inductor current reverses.
Under these conditions, the inductor’s EMF causes the
switching node of the inductor to go high during the
dead time, extending the effective on-time.
12 ______________________________________________________________________________________
Small, Dual, High-Efficiency
Buck Controller for Notebooks
Automatic Pulse-Skipping Switchover
Forced PWM Operation (ON2 floating)
The low-noise, forced-PWM mode (ON2 floating) dis-
ables the zero-crossing current comparator that con-
trols the low-side switch on-time. The resulting low-side
gate-drive waveform is forced to become the comple-
ment of the high-side gate-drive waveform. This, in turn,
causes the inductor current to reverse at light loads as
the PWM loop strives to maintain a constant duty ratio
In normal operation, the MAX1761’s PWM control algo-
rithm automatically skips pulses at light loads.
Comparators at each CS_ input in the MAX1761 trun-
cate the low-side switch’s on-time at the point where
the inductor current drops to zero. This occurs when
the inductor current is operating at the boundary
between continuous and discontinuous conduction
mode (Figure 4). This threshold is equal to 1/2 the
peak-to-peak ripple current, which is inversely propor-
tional to the inductor value:
of V
/V+. The benefit of forced-PWM mode is that it
OUT
keeps the switching frequency nearly constant, but it
results in a higher no-load battery current that can be
10mA to 40mA, depending on the gate capacitance of
the external MOSFETs.
V+ - V
K × V
OUT
OUT
I
≈
LOAD(SKIP)
2L
V+
Forced-PWM mode is most useful for reducing audio-
frequency noise, improving load-transient response,
and providing sink-current capability for dynamic out-
put voltage adjustment. Multiple-output applications
that use a flyback transformer or coupled inductor also
benefit from forced-PWM operation because the contin-
uous switching action improves cross-regulation.
where K is the on-time scale factor listed in Table 3. For
example, in the typical application circuit (Figure 1),
with V
= 2.5V, V+ = 15V, L = 9µH, and K =
OUT1
2.857µs (Table 3), switchover to pulse-skipping opera-
tion occurs at I = 0.33A or about 1/8 full load. The
LOAD
crossover point occurs at an even lower value if a
swinging (soft-saturation) inductor is used.
Low-Side Current-Limit Sensing
The current-limit circuit employs a unique “valley” cur-
rent-sensing algorithm that uses the on-state resistance
of the low-side MOSFET as a current-sensing element.
If the current-sense signal is above the current-limit
threshold, the PWM is not allowed to initiate a new
cycle (Figure 5). The actual peak current is greater than
the current-limit threshold by an amount equal to the
inductor ripple current. Therefore, the exact current-
limit characteristic and maximum load capability are a
function of the MOSFET on-resistance, inductor value,
and input voltage. The reward for this uncertainty is
robust, lossless overcurrent sensing. When combined
with the undervoltage protection circuit, this current-
limit method is effective in almost every circumstance.
The switching waveforms may appear noisy and asyn-
chronous when light loading causes pulse-skipping
operation; this is a normal operating condition that
improves light-load efficiency. Trade-offs in PFM noise
vs. light-load efficiency are made by varying the induc-
tor value. Generally, lower inductor values produce a
broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the
coil resistance remains fixed) and less output voltage
ripple. Penalties for using higher inductor values
include larger physical size and degraded load-tran-
sient response (especially at low input-voltage levels).
There is also a negative current limit that prevents
excessive reverse inductor currents when V
is sink-
OUT
∆i
∆t
V + -V
L
OUT
=
ing current (forced PWM mode only). The negative cur-
rent-limit threshold is set to approximately 120% of the
positive current limit.
-I
PEAK
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the cur-
rent-sense signals seen by CS_. Mount or place the IC
close to the low-side MOSFET with short, direct traces,
making a Kelvin-sense connection to the source and
drain terminals.
I
= I
/2
LOAD PEAK
If greater current-limit accuracy is desired, CS can be
connected to an external sense resistor inserted
between the source of the low-side switch and ground
(Figure 6). The resulting current limit will be ILIM = 0.1V
0
ON-TIME
TIME
Figure 4. Pulse-Skipping/Discontinuous Crossover Point
/ R
, and it will have 8% error.
SENSE
______________________________________________________________________________________ 13
Small, Dual, High-Efficiency
Buck Controller for Notebooks
DH output and prevents the low-side FET from turning
on until DH is fully off. The same considerations should
be used for routing the DH signal to the high-side FET.
I
PEAK
Since the transition time for a P-channel switch can be
much longer than an N-channel switch, the dead time
prior to the high-side PMOS turning on will be more
pronounced than in other synchronous step-down reg-
ulators, which use high-side N-channel switches. On
the high-to-low transition, the voltage on the inductor’s
"switched" terminal flies below ground until the low-side
switch turns on. A similar dead-time spike occurs on
the opposite low-to-high transition. Depending upon the
magnitude of the load current, these spikes usually
have a minor impact on efficiency.
I
LOAD
LIMIT
I
0
TIME
Figure 5. “Valley” Current-Limit Threshold Point
The high-side drivers (DH_) swing from V+ to GND and
will typically source/sink 0.6A from the gate of the P-
channel MOSFET. The low-side driver (DL_) swings
from VL to ground and will typically source 0.5A and
sink 0.9A from the gate of the N-channel FET.
V+
The internal pulldown transistors that drive DL low are
robust, with a 2.0Ω (typ) on-resistance. This helps pre-
vent DL from being pulled up when the high-side
switch turns on, due to capacitive coupling from the
drain to the gate of the low-side MOSFET. This places
some restrictions on the FETs that can be used. Using
a low-side FET with smaller gate-to-drain capacitance
can prevent these problems.
DH
V
OUT
MAX1761
DL
CS
Shutdown and Mode Control Inputs
The MAX1761 has two inputs (ON1, ON2) that control
the operating modes of the two regulators. Asserting
ON1 low places both regulators in micropower shut-
down mode, in which both VL and REF are disabled.
When ON1 is high, OUT1 is enabled, with VL and REF
active. ON2 serves a dual function: it is a shutdown
control for OUT2, and it determines the switching mode
for both regulators. When ON2 is low (ON2 < 0.5V),
OUT2 is disabled and OUT1 operates in normal mode.
Floating ON2 places both outputs in forced PWM
OUT
FB
Figure 6. Using a Low-Side Current-Sense Resistor
MOSFET Gate Drivers
The DH and DL outputs are optimized for driving mod-
erate-sized power MOSFETs. The MOSFET drive capa-
bility is stronger for the low-side switch. This is
consistent with the low duty factor seen in the notebook
mode. When ON2 is high (2V < ON2 < V ), both regula-
L
tors run in normal operating mode. Toggling ON1 from
low to high resets the fault latch (Table 4).
computer environment where a large V+ to V
differ-
OUT
ential exists. An adaptive dead-time circuit monitors the
DL output and prevents the high-side FET from turning
on until DL is fully off. There must be a low-resistance,
low-inductance path from the DL driver to the MOSFET
gate for the adaptive dead-time circuit to work properly.
Otherwise, the sense circuitry in the MAX1761 will inter-
pret the MOSFET gate as “off” while there is still charge
left on the gate. Use very short, wide traces measuring
10 to 20 squares or less (50mils to 100mils wide if the
MOSFET is 1 inch from the device). Similar to the DL
output, an adaptive dead-time circuit also monitors the
Output Undervoltage Protection
The output undervoltage protection function is similar to
foldback current limiting but employs a timer rather
than a variable current limit. If the MAX1761 output volt-
age is under 70% (typ) of the nominal output voltage
20ms after coming out of shutdown, then both PWMs
are latched off and will not restart until V+ is cycled or
ON1 is toggled low to high.
14 ______________________________________________________________________________________
Small, Dual, High-Efficiency
Buck Controller for Notebooks
Table 4. Operating Mode Control Summary
MODE
Shutdown
ON1
ON1 < 0.5V
ON2
DESCRIPTION
X
Both OUT1 and OUT2 off, VL and REF disabled
OUT1 on in normal mode, OUT2 off
ON1 Enabled
Forced PWM
2.0V < ON1 < V+
2.0V < ON1 < V+
2.0V < ON1 < V+
ON2 < 0.5V
Floating
Both OUT1 and OUT2 on in forced PWM mode
Both OUT1 and OUT2 on in normal mode
Normal Operation
2.0V < ON2 ≤ VL
erally exhibit I
= I
✕ 80%.
Thermal Fault Protection
LOAD
LOAD(MAX)
The MAX1761 features a thermal fault protection circuit.
When the temperature rises above +160°C, the DL low-
side gate-driver outputs latch high until ON1 is toggled
or V+ is cycled. The fault threshold has 10°C of thermal
hysteresis, which prevents the regulator from restarting
until the die cools off.
3) Inductor Operating Point. This choice provides
trade-offs between size and efficiency. Low induc-
tor values cause large ripple currents, resulting in
the smallest size, but poor efficiency and high out-
put noise. The minimum practical inductor value is
one that causes the circuit to operate at the edge of
critical conduction (where the inductor current just
touches zero with every cycle at maximum load).
Inductor values lower than this grant no further size-
reduction benefit.
POR and Soft-Start
Power-on reset (POR) occurs when V+ falls below
approximately 2V, resetting the fault latch and prepar-
ing the PWM for operation once the power is cycled. VL
undervoltage lockout (UVLO) circuitry inhibits switching
and forces the DL gate driver low until VL rises above
4.25V, whereupon an internal digital soft-start timer
begins to ramp up the maximum allowed current limit.
The ramp occurs in five steps: 20%, 40%, 60%, 80%,
and 100%; 100% current is available after 1.7ms.
The MAX1761’s pulse-skipping algorithm initiates skip
mode at the critical conduction point. So, the inductor
operating point also determines the load-current value
at which PWM/skip mode switchover occurs. The opti-
mum point is usually found between 20% and 50% rip-
ple current.
The inductor ripple current also impacts transient-
Design Procedure
response performance, especially at low V - V
dif-
IN
OUT
Firmly establish the input voltage range and the maxi-
mum load current before choosing the inductor operat-
ing point (ripple current ratio). The following three
factors determine the SMPS design using the
MAX1761:
ferentials. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load step.
The amount of output sag is also a function of the maxi-
mum duty factor, which can be calculated from the on-
time and minimum off-time:
1) Input Voltage Range. The maximum value
(V+(max)) must accommodate the worst-case high
AC adapter voltage. The minimum value (V+(min))
must account for the lowest battery voltage after
drops due to connectors, fuses, and battery selec-
tor switches. If there is a choice at all, lower input
voltages result in better efficiency.
(∆I
)2 × L
LOAD(MAX)
V
=
SAG
2C × DUTY(V +
- V
)
F
(MIN)
OUT
Inductor Selection
The switching frequency (on-time) and operating point
(% ripple or LIR) determine the inductor value as fol-
lows:
2) Maximum Load Current. There are two values to
consider, the peak load current (I
) and
LOAD(MAX)
). The peak load
the continuous load current (I
LOAD
current determines the instantaneous component
stresses and filtering requirements and thus drives
output capacitor selection, inductor saturation rat-
ing, and the design of the current-limit circuit. The
continuous load current determines the thermal
stresses and thus drives the selection of input
capacitors, MOSFETs, and other critical heat-con-
tributing components. Modern notebook CPUs gen-
V
(V + -V
)
OUT
OUT
L =
V+× ƒ × LIR ×I
LOAD(MAX)
Example: I
= 2.5A, V+(max) = 20V, V
2.5V, f = 350kHz, 35% ripple current or LIR = 0.35:
=
LOAD(MAX)
OUT1
______________________________________________________________________________________ 15
Small, Dual, High-Efficiency
Buck Controller for Notebooks
Output Capacitor Selection
The output filter capacitor must have low enough effec-
tive series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy the stability criterion.
2.5V(20V -2.5V)
20V × 350kHz× 0.35×2.5A
L =
= 7.1µH
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and works well at 250kHz. The core
must be large enough not to saturate at the peak induc-
In CPU V
converters and other applications where
CORE
the output is subject to violent load transients, the out-
put capacitor’s size depends on how much ESR is
needed to prevent the output from dipping too low
under a load transient. Ignoring the sag due to finite
capacitance:
tor current (I
):
PEAK
I
= I
- 1/2 LIR ✕ I =
LOAD(MAX)
PEAK
LOAD(MAX)
(1 - 0.5 LIR) I
LOAD(MAX)
V
DIP
LOAD(MAX)
R
≤
ESR
I
Setting Current Limit
The minimum current-limit threshold must be great
enough to support the maximum load current plus
some safety margin. For the circuit in Figure 1, with a
desired 2.5A maximum load current, the worst-case
current limit is set at 3.0A, providing a 20% safety mar-
gin. Under these conditions, the valley of the inductor
current waveform occurs at:
In non-CPU applications, the output capacitor’s size
depends on how much ESR is needed to maintain an
acceptable level of output voltage ripple:
Vp- p
R
≤
ESR
LIR ×I
LOAD(MAX)
I
= I
- 1/2 LIR ✕ I =
LOAD(MAX)
LOAD(MAX)
The actual required µF capacitance value relates to the
physical size needed to achieve low ESR as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tanta-
lums, SP, POS, and other electrolytics).
VALLEY
LOAD(MAX)
(1 - 0.5 LIR) I
The required valley current is I
= 3A - 1/2 (0.35)
VALLEY
✕ 2.5A = 2.56A. Next, the current-sense feedback volt-
age must be scaled taking into account the tolerance of
the CS_ current-limit threshold and the maximum MOS-
When using low-capacitance filter capacitors, such as
ceramic or polymer types, capacitor size is usually
determined by the capacitance needed to prevent
FET drain-source on-resistance (R
) variation
DS(ON)
over temperature. The minimum current-limit threshold
at the CS_ pins is 92mV. The worst-case maximum
V
and V
from causing problems during load
SOAR
SAG
value for (R
) over temperature is 50mΩ. At
DS(ON)
transients. Generally, once enough capacitance is
added to meet the V requirement, undershoot at
2.56A, the voltage developed across the low-side
switch is 128mV. A resistive voltage-divider with a
0.703 attenuation ratio is necessary to scale this volt-
age to the 92mV CS_ threshold.
SOAR
the rising load edge is no longer a problem (see the
equation in Design Procedure). The amount of
V
SAG
overshoot due to stored inductor energy can be calcu-
lated as:
A current-sense resistor can be used if a more accu-
rate current limit is needed than is available when using
the MOSFET (R
(Figure 6). Placing the sense
2
DS(ON)
(L ×I
)
PEAK
∆V ≈
resistor between the source of the low-side MOSFET
and ground provides a very accurate sense point for
the CS_ inputs. Alternatively, a small sense resistor can
be used in series with the low-side MOSFET to ballast
the device and reduce the temperature coefficient of
the current limit when sensing at the inductor’s
switched node. This provides a compromise between
sensing across the MOSFET device alone or using a
large sense resistor.
2CV
OUT
where I
is the peak inductor current.
PEAK
Stability Considerations
Stability is determined by the value of the ESR zero rel-
ative to the switching frequency. The point of instability
is given by the following equation:
ƒ
π
ƒ
=
ESR
16 ______________________________________________________________________________________
Small, Dual, High-Efficiency
Buck Controller for Notebooks
where:
CON) are preferred due to their resilience to power-up
surge currents.
1
ƒ
=
ESR
V
(V + - V )
OUT
OUT
2π × R
× C
F
ESR
I
= I
LOAD
RMS
V +
For a typical 350kHz application, the ESR zero frequen-
cy must be well below 100kHz, preferably below
50kHz. Tantalum and OS-CON capacitors have typical
ESR zero frequencies of 15kHz. Sanyo POS capacitors
have typical ESR zero frequencies of 20kHz. In the
design example used for inductor selection, the ESR
needed to support 50mVp-p ripple is 50mV / LIR(2.5A)
= 57.1mΩ. A single150µF/6.3V Sanyo POS capacitor
provides 55mΩ (max) ESR. This ESR results in a zero at
19.3kHz, well within the bounds of stability.
Power MOSFET Selection
DC bias and output power considerations dominate the
selection of the power MOSFETs used with the
MAX1761. Care should be taken not to exceed the
device’s maximum voltage ratings. In general, both
switches are exposed to the supply voltage, so select
MOSFETs with V
greater than V+(max). Gate
DS(MAX)
drive to the N-channel and P-channel MOSFETs is not
symmetrical. The N-channel device is driven from
ground to the logic supply VL. The P-channel device is
Don’t put high-value ceramic capacitors directly across
the fast feedback inputs (FB_/OUT_ to GND) without
taking precautions to ensure stability. Large ceramic
capacitors can have a high-ESR zero frequency and
may cause erratic, unstable operation. However, it’s
easy to add enough series resistance by placing the
capacitors a couple of inches downstream from the
junction of the inductor and FB_/OUT_ pin.
driven from V+ to ground. The maximum rating for V
GS
for the N-channel device is usually not an issue.
However, V for the P-channel must be at least
GS(MAX)
V+(max). Since V
is usually lower than
GS(MAX)
V
, gate-drive constraints often dictate the
DS(MAX)
required P-channel breakdown rating.
For moderate input-to-output differentials, the high-side
MOSFET (Q1) can be sized smaller than the low-side
MOSFET (Q2) without compromising efficiency. The
high-side switch operates at a very low duty cycle
under these conditions, so most conduction losses
occur in Q2. For maximum efficiency, choose a high-
side MOSFET (Q1) that has conduction losses (I2RD)
equal to the switching losses (fCV+2). Make sure that
the conduction losses at the minimum input voltage
don’t exceed the package thermal limits or violate the
overall thermal budget. Similarly check for rating viola-
tions for conduction and switching losses at the maxi-
mum input voltage (see MOSFET Power Dissipation).
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and fast-feed-
back loop instability.
Double-pulsing occurs due to noise on the output or
because the ESR is so low that there isn’t enough volt-
age ramp in the output voltage signal. This “fools” the
error comparator into triggering a new cycle immedi-
ately after the 500ns minimum off-time period has
expired. Double-pulsing is more annoying than harmful,
resulting in nothing worse than increased output ripple.
However, it can indicate the possible presence of loop
instability, which is caused by insufficient ESR. Loop
instability can result in oscillations at the output after
line or load perturbations that can cause the output
voltage to go outside the tolerance limit.
The MAX1761 has an adaptive dead-time circuitry that
prevents the high-side and low-side MOSFETs from
conducting at the same time (see MOSFET Gate
Drivers). Even with this protection, it is still possible for
delays internal to the MOSFET to prevent one MOSFET
from turning off when the other is turned on. The maxi-
mum mismatch time that can be tolerated is 60ns.
Select devices that have low turn-off times, and make
The easiest method for checking stability is to apply a
very fast zero-to-max load transient (refer to the
MAX1761 EV kit manual) and carefully observe the out-
put voltage ripple envelope for overshoot and ringing. It
can help to simultaneously monitor the inductor current
with an AC current probe. Don’t allow more than one
cycle of ringing after the initial step-response under- or
overshoot.
sure that NFET(t
) - PFET(t
) < 60ns,
DON(MIN)
DOFF(MAX)
and PFET(t
) - NFET(t
) < 60ns.
DON(MIN)
DOFF(MAX)
Failure to do so may result in efficiency-killing shoot-
through currents.
Input Capacitor Selection
The input capacitor must meet the ripple current
MOSFET selection also affects PC board layout. There
are four possible combinations of MOSFETs that can
be used with this switcher. The designs include:
requirement (I
) imposed by the switching currents.
RMS
Nontantalum chemistries (ceramic, aluminum, or OS-
•
Two dual complementary MOSFETs (Figure 7)
______________________________________________________________________________________ 17
Small, Dual, High-Efficiency
Buck Controller for Notebooks
•
•
•
A dual N-channel and a dual P-channel MOSFET
(Figure 8)
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
CV2F switching-loss equation. If the high-side MOSFET
Two single N-channels and a dual P-channel
(Figure 9)
you’ve chosen for adequate R
at low battery volt-
DS(ON)
Two single N-channels and two single P-channels
(Figure 10)
ages becomes extraordinarily hot when subjected to
V+ , reconsider your MOSFET choice.
(MAX)
There are trade-offs to each approach. Complementary
devices have appropriately scaled N- and P-channel
DS(ON)
Calculating the power dissipation in Q1 due to switch-
ing losses is difficult since it must allow for difficult
quantifying factors that influence the turn-on and turn-
off times. These factors include the internal gate resis-
tance, gate charge, threshold voltage, source
inductance, and PC board layout characteristics. The
following switching-loss calculation provides only a
very rough estimate and is no substitute for breadboard
evaluation, preferably including a verification using a
thermocouple mounted on Q1:
R
and matched turn-on/turn-off characteristics.
However, there are relatively few manufacturers of
these specialized devices. Selection may be limited.
Dual N- and P-channel MOSFETs are more widely
available. As such, more efficient designs that benefit
from the large low-side MOSFETs can be realized. This
approach is most useful when the output power
requirements for both regulators are about the same.
This limitation can be sidestepped by using a dual P-
channel and two single N-channels. Using four single
MOSFETs gives the greatest design flexibility but will
require the most board area.
2
C
× V+
׃ ×I
LOAD
RSS
(MAX)
P (Q1 switching) =
D
I
GATE
where C
and I
is the reverse transfer capacitance of Q1,
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET, the worst-case
RSS
is the peak gate-drive source/sink current
GATE
(1A typ).
power dissipation (P ) due to resistance occurs at the
D
For the low-side MOSFET (Q2) the worst-case power
dissipation always occurs at maximum battery voltage:
minimum battery voltage:
V
V+
2
OUT
V
V+
2
OUT
P (Q1 resistance) =
×I
×R
D
LOAD DS(ON)
P (Q2) = 1−
×I
×Rs
D
LOAD
(MIN)
(MAX)
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than
LOAD (MAX)
current limit and cause the fault latch to trip. To protect
against this possibility, the circuit must be overdesigned
to tolerate:
However, the R
required to stay within package
DS(ON)
I
but are not quite high enough to exceed the
power-dissipation limits often limits how small the MOS-
FET can be. The optimum occurs when the switching
(AC) losses equal the conduction (R
) losses.
DS(ON)
High-side switching losses don’t usually become an
issue until the input is greater than approximately 15V.
I
= I
+ 1/2 ✕ LIR ✕ I
LOAD (MAX)
LOAD
LIMIT (MAX)
V+
V+
D
D
D
D
G
S
G
S
DH1
DL1
D
D
D
D
G
DH2
P-CHANNEL
N-CHANNEL
P-CHANNEL
N-CHANNEL
S
G
S
LX1
LX2
DL2
1
1
Figure 7. Dual Complementary MOSFET Design
18 ______________________________________________________________________________________
Small, Dual, High-Efficiency
Buck Controller for Notebooks
V+
LX1
1
S
G
S
G
D
D
D
D
D
D
D
D
G
S
G
S
DL1
DL2
P-CHANNEL
P-CHANNEL
N-CHANNEL
N-CHANNEL
DH1
DH2
LX2
1
Figure 8. Dual N- and P-Channel MOSFET Design
where I
is the maximum valley current
LIMIT(MAX)
LX1
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. This means that
the MOSFETs must be very well heatsinked. If short-cir-
cuit protection without overload protection is enough, a
D
D
D
D
G
DL1
S
S
S
normal I
value can be used for calculating compo-
LOAD
nent stresses.
N-CHANNEL
V+
Choose a Schottky diode (D1, Figure 2) having a for-
ward voltage low enough to prevent the Q2 MOSFET
body diode from turning on during the dead time. As a
general rule, a diode having a DC current rating equal
to 1/3 of the load current is sufficient. This diode is
optional and can be removed if efficiency isn’t critical.
1
S
G
S
G
D
D
D
D
P-CHANNEL
P-CHANNEL
1
DH1
DH2
D
D
D
D
G
S
S
S
DL2
Applications Issues
N-CHANNEL
Dropout Performance
The output voltage adjust range for continuous-conduc-
tion operation is restricted by the nonadjustable 500ns
(max) minimum off-time one-shot. For best dropout per-
formance, use the side with the lower switching fre-
quency, FB2 (250kHz). When working with low input
voltages, the duty-factor limit must be calculated using
worst-case values for on- and off-times. Manufacturing
1
LX2
Figure 9. Two Single N-Channel MOSFETs and a Dual P-Channel
MOSFET Design
1
V+
V+
LX1
LX2
1
S
S
S
G
D
D
D
D
D
D
D
D
G
S
S
DL1
S
S
S
G
D
D
D
D
D
D
D
D
G
S
S
DL2
P-CHANNEL
N-CHANNEL
P-CHANNEL
N-CHANNEL
DH1
S
1
DH2
S
1
Figure 10. Two Single N-Channel MOSFETs and Two Single P-Channel MOSFETs Design
______________________________________________________________________________________ 19
Small, Dual, High-Efficiency
Buck Controller for Notebooks
tolerances and internal propagation delays introduce
an error to the t K-factor. Also, keep in mind that
transient response performance of buck regulators
operated close to dropout is poor, and bulk output
VL regulator will increase the drive on the low-side
MOSFETs, thereby lowering their R and reduc-
ing power consumption. Note that VL should not be
higher than 5.5V if connected to VL. Also note, V+
should not be brought below 5V unless VL is connect-
ed directly to V+.
ON
DS(ON)
capacitance must often be added (see the V
equa-
SAG
tion in Design Procedure).
Dropout design example: V = 6.5V (min), V
IN
=
OUT
PC Board Layout Guidelines
Careful PC board layout is critical to achieving low
switching losses and clean, stable operation. This is
especially true for dual converters, where one channel
can affect the other. The switching power stages
require particular attention (Figure 13). Refer to the
MAX1761 EV kit data sheet for a specific layout exam-
ple. If possible, mount all of the power components on
the top side of the board with their ground terminals
flush against one another. Follow these guidelines for
good PC board layout:
5V, f = 350kHz, 250kHz. The required duty is (V
+
OUT
V
) / (V+ - V ) = (5V + 0.1V) / (6.5V - 0.1V) = 79.7%.
SW
SW
The worst-case on-time for f = 350kHz is (V
+ 0.1V)
OUT
/ V+ ✕ K = 5.1V / 6.5V ✕ 2.857µs-V ✕ 90% = 2.017µs.
The IC duty-factor limitation is:
t
ON(MAX)
Duty =
=
t
+t
OFF(MIN)
ON(MAX)
2.017µs
2.017µs + 500ns
= 80.1%
•
Isolate the top-side power components from the
sensitive analog components on the bottom side
with a ground shield. Use a separate PGND plane
under the OUT1 and OUT2 sides (called PGND1
and PGND2). Avoid the introduction of AC currents
into the PGND1 and PGND2 ground planes. Run
the power plane ground currents on the top side
only, if possible.
Thus, operation at 350kHz meets the required duty
cycle. A similar analysis with f = 250kHz (K = 4µs-V)
shows that at f = 250kHz, the maximum duty cycle is
85.0%, also meeting the required duty cycle.,
Remember to include inductor resistance and MOSFET
on-state voltage drops (V ) when doing worst-case
SW
dropout duty-factor calculations.
•
•
Use a star ground connection on the power plane
to minimize the crosstalk between OUT1 and OUT2.
Fixed Output Voltages
The MAX1761’s dual-mode operation allows the selec-
tion of common voltages without requiring external
components (Figure 11). Connect FB1 to GND for a
fixed +2.5V output at OUT1; otherwise, connect FB1 to
a resistive voltage-divider for an adjustable output.
Connect FB2 to GND for a +1.8V output; otherwise,
connect FB2 to a resistive voltage-divider for an
adjustable output.
Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
•
•
Connect AGND and PGND together close to the IC.
Do not connect them together anywhere else.
Carefully follow the grounding instructions under
Step 4 of the Layout Procedure.
Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single mΩ of excess trace resistance caus-
es a measurable efficiency penalty.
Adjusting VOUT
The output voltage can be adjusted with a resistive volt-
age-divider if desired (Figure 12). The equation for
adjusting the output voltage is:
R
1
V
= V × 1+
FB
OUT
R
2
•
CS_ and PGND connections to the synchronous
rectifiers for current limiting must be made using
Kelvin sensed connections to guarantee the cur-
rent-limit accuracy. With SO-8 MOSFETs, this is
best done by routing power to the MOSFETs from
outside, using the top copper layer, while connect-
ing PGND and CS_ inside (underneath) the SO-8
package.
where V is 1.0V, and R2 is about 10kΩ.
FB
Low Input Voltage Operation (V+ = +5V)
The MAX1761 can be used in applications using a 5V
10% input supply by overdriving VL with the input
supply voltage, V+. This not only enables operation of
the MAX1761 down to V+ = 4.5V but has the added
benefit of increasing overall efficiency. Overdriving the
20 ______________________________________________________________________________________
Small, Dual, High-Efficiency
Buck Controller for Notebooks
switching noise away from the IC, feedback
dividers, and analog bypass capacitors.
OUT1
OUT2
•
Avoid coupling switching noise into control input
connections (ON1, ON2, etc.). These pins should
be referenced to a quiet analog ground plane.
TO ERROR TO ERROR
FIXED
2.5V
FIXED
1.8V
AMP1
AMP2
Layout Procedure
1) Place the power components first, with ground ter-
minals adjacent (Q2 source, CI , C
ble, make all these connections on the top layer
with wide, copper-filled areas.
). If possi-
N_
OUT_
FB1
FB2
0.1V
0.1V
2) Mount the controller IC adjacent to the synchronous
rectifier MOSFETs, preferably on the back side in
order to keep CS_, PGND_, and the DL_ gate-drive
line short and wide. The DL_ gate trace must be
short and wide, measuring 10 to 20 squares (50mils
to 100mils wide if the MOSFET is 1 inch from the
controller IC).
MAX1761
Figure 11. Feedback MUX
V+
3) Place the VL capacitor near the IC controller.
DH
4) Make the DC-DC controller ground connections as
follows: near the IC, create a small analog ground
plane. Use this plane for the ground connection for
the REF and VL bypass capacitor, and FB_
dividers. Create another small ground island for
PGND, and use it for the V+ bypass capacitor,
placed very close to the IC. Connect the AGND and
the PGND together under the IC (this is the only
connection between AGND and PGND).
1/2
V
OUT
CS
MAX1761
DL
GND
R1
OUT
FB
5) On the board’s top side (power planes), make a
star ground to minimize crosstalk between the two
sides. The top-side star ground is a star connection
of the input capacitors, side 1 low-side MOSFET,
and side 2 low-side MOSFET. Keep the resistance
low between the star ground and the sources of the
low-side MOSFETs for accurate current limit.
Connect the top-side star ground (used for MOS-
FET, input, and output capacitors) to the small
PGND island with a short, wide connection (prefer-
ably just a via). If multiple layers are available (high-
ly recommended), create PGND1 and PGND2
islands on the layer just below the top-side layer
(refer to the MAX1761 EV kit for an example) to act
as an EMI shield. Connect each of these individual-
ly to the star ground via, which connects the top
side to the PGND plane. Add one more solid
ground plane under the IC to act as an additional
shield, and also connect that to the star ground via.
R2
Figure 12. Setting V
with a Resistive Voltage-Divider
OUT
•
When trade-offs in trace lengths must be made, it’s
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it’s better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
•
•
Ensure that the OUT connection to C
is short
OUT
and direct. However, in some cases it may be
desirable to deliberately introduce some trace
length between the OUT inductor node and the out-
put filter capacitor (see Stability Considerations).
6) Connect the output power planes directly to the out-
put filter capacitor positive and negative terminals
with multiple vias.
Route high-speed switching nodes (CS_, DH_, and
DL_) away from sensitive analog areas (REF, FB_).
Use a PGND as an EMI shield to keep radiated
______________________________________________________________________________________ 21
Small, Dual, High-Efficiency
Buck Controller for Notebooks
USE AGND PLANE TO:
USE PGND PLANE TO:
- BYPASS V+
- BYPASS V AND REF
L
- TERMINATE EXTERNAL FB
DIVIDER (IF USED)
- PIN-STRAP CONTROL
INPUTS
- CONNECT PGND TO THE TOPSIDE
STAR GROUND
VOUT1
VOUT2
GND
AGND
C3
C4
C2
C1
L2
L1
VIA TO PGND
P1 N1
P2 N2
CONNECT PGND TO AGND
BENEATH THE MAX1761 AT
ONE POINT ONLY AS SHOWN.
VL
NOTE: EXAMPLE SHOWN IS FOR DUAL COMPLEMENTARY MOSFET.
VBATT
Figure 13. PC Board Layout Example
Chip Information
TRANSISTOR COUNT: 6045
22 ______________________________________________________________________________________
Small, Dual, High-Efficiency
Buck Controller for Notebooks
Package Information
Note: The MAX1761 does not have a heat slug.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23
© 2000 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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