MAX17598_13 [MAXIM]
Low IQ, Wide-Input Range, Active Clamp Current-Mode PWM Controllers; 低IQ ，宽输入范围，有源钳位电流模式PWM控制器
| 型号： | MAX17598_13 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Low IQ, Wide-Input Range, Active Clamp Current-Mode PWM Controllers |
| 文件： | 总24页 (文件大小：1206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
General Description
Benefits and Features
The MAX17598/MAX17599 low I , active clamp current-
Q
S Active Clamp, Peak Current-Mode Forward PWM
mode PWM controllers contain all the control circuitry
required for the design of wide-input isolated/non-iso-
lated forward-converter industrial power supplies. The
MAX17598 is well-suited for universal input (rectified 85V
AC to 265V AC) or telecom (36V DC to 72V DC) power
supplies. The MAX17599 is optimized for low-voltage
industrial supplies (4.5V DC to 36V DC).
Controller
S 20FA Startup Current in UVLO
S 4.5V to 36V Input-Supply Operating Range
(MAX17599)
S Programmable Input Undervoltage Lockout
S Programmable Input Overvoltage Protection
The devices include an AUX driver that drives an aux-
iliary MOSFET (clamp switch) that helps implement the
active-clamp transformer reset topology for forward con-
verters. Such a reset topology has several advantages
including reduced voltage stress on the switches, trans-
former size reduction due to larger allowable flux swing,
and improved efficiency due to elimination of dissipative
snubber circuitry. Programmable dead time between the
AUX and main driver allows for zero voltage switching (ZVS).
S Programmable 100kHz to 1MHz Switching
Frequency
S Switching Frequency Synchronization
S Programmable Frequency Dithering for Low EMI
Spread-Spectrum Operation
S Programmable Dead Time
S Adjustable Soft-Start
S Programmable Slope Compensation
S Fast Cycle-by-Cycle Peak-Current-Limit
The switching frequency is programmable from 100kHz
to 1MHz for the devices with an accuracy of Q8%
using an external resistor. This allows optimization of
the magnetic and filter components, resulting in com-
pact, cost-effective isolated/nonisolated power supplies.
For EMI-sensitive applications, the ICs incorporate a
programmable frequency-dithering scheme, enabling
low-EMI spread-spectrum operation.
S 70ns Internal Leading-Edge Current-Sense
Blanking
S Hiccup Mode Output Short-Circuit Protection
S Soft-Stop for Well-Controlled Clamp Capacitor
Discharge
S Negative Clamp-Switch Current Limit
S 3mm x 3mm, Lead-Free 16-Pin TQFN
S -40°C to +125°C Operating Temperature Range
An input undervoltage lockout (EN/UVLO) is provided for
programming input-supply start voltage, and to ensure
proper operation during brownout conditions. EN/UVLO
input is also used to turn on/off the ICs. Input overvoltage
(OVI) protection scheme is provided to make sure that
the regulator shuts down when input supply exceeds its
maximum allowed value.
Applications
Telecom and Datacom Power Supplies
Isolated Battery Chargers
To control inrush current, the devices incorporate an SS pin
to set the soft-start time for the regulators. Power dissipa-
tion under fault conditions is minimized by hiccup overcur-
rent protection (hiccup mode). Soft-stop feature provides
safe discharging of the clamp capacitor when the device
is turned off, and allows the controller to restart in a well-
controlled manner. Additionally, negative current limit is
provided in the current-sense circuitry, helping limit clamp
switch current under dynamic operating conditions.
Servers and Embedded Computing
Industrial Power Supplies
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to www.maximintegrated.com/MAX17598.related.
SYNC feature is provided to synchronize multiple convert-
ers to a common external clock in noise-sensitive applica-
tions. Overtemperature fault triggers thermal shutdown for
reliable protection of the device. The ICs are available in a
16-pin, TQFN package with 0.5 mm lead spacing.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-6179; Rev 1; 3/13
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
ABSOLUTE MAXIMUM RATINGS
V
V
(MAX17599 only) ............................................-0.3V to +40V
Maximum Input/Output Current (Continuous)
, V ......................................................................100mA
IN
DRV
to SGND
V
IN DRV
(MAX17598 Only) ..............................................-0.3V to +16V
(MAX17599 Only) ................................................-0.3V to +6V
NDRV (pulsed for less than 100ns) .........................+0.9A/-1.5A
AUXDRV (pulsed for less than 100ns).....................+0.3A/-0.7A
EN/UVLO to SGND.....................................-0.3V to (V + 0.3V)
Continuous Power Dissipation (T = +70NC)
IN
A
NDRV, AUXDRV to PGND.......................-0.3V to (V
OVI, RT, DITHER, COMP, SS, FB,
SLOPE, DT to SGND ..........................................-0.3V to +6V
CS to SGND ............................................................-0.8V to +6V
PGND to SGND....................................................-0.3V to +0.3V
+ 0.3V)
TQFN (derate 20.8mW/°C above 70°C)....................1666mW
Operating Temperature Range........................ -40°C to +125°C
Maximum Junction Temperature.....................................+150°C
Storage Temperature Range............................ -65°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
Soldering Temperature (reflow) ......................................+260°C
DRV
PACKAGE THERMAL CHARACTERISTICS
(Note 1)
TQFN
Junction-to-Case Thermal Resistance (q ).................7°C/W
JC
Junction-to-Ambient Thermal Resistance (q ) ..........48°C/W
JA
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = 12V (for MAX17598, bring V up to 21V for startup), V = V
= V = V
= V
= V
SGND
= 0V, V
= +2V,
EN/UVLO
OVI
IN
IN
CS
DITHER
FB
PGND
AUXDRV = NDRV = SS = COMP = SLOPE = unconnected, R = 25kI, R = 10kI, C
= 1FF, C
= 1FF, T = T = -40NC to
RT
DT
VIN
VDRV
A
J
+125NC, unless otherwise noted. Typical values are at T = T = +25NC.) (Note 2)
A
J
PARAMETER
INPUT SUPPLY (V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
)
IN
MAX17598
MAX17599
8
29
36
V
Voltage Range
V
V
V
IN
IN
4.5
18.5
3.8
6.5
3.6
MAX17598
20
4.1
7
21.5
4.4
7.5
4.2
V
V
Bootstrap UVLO Wakeup
Bootstrap UVLO
V
IN rising
IN falling
IN
IN-UVR
MAX17599
MAX17598
MAX17599
IN
V
V
IN-UVF
Shutdown Level
3.9
V
Supply Startup Current
I
IN
IN-
STARTUP
V
V
< UVLO
= 0V
20
32
32
FA
IN
(under UVLO)
V
Supply Shutdown
IN
I
20
2
FA
mA
V
IN-SH
EN
Current
V
Supply Current
Clamp Voltage
I
Switching, f
= 400kHz
IN
IN
IN-SW
SW
V
= 0V, I = 2mA sinking
IN
EN
V
V
30
33
36
INC
(MAX17598) (Note 3)
ENANBLE (EN)
V
V
V
V
rising
falling
1.16
1.1
1.21
1.15
1.26
1.20
+100
ENR
EN
EN
EN
EN Threshold
V
V
ENF
EN Input Leakage Current
I
= 1.5V, T = +25NC
-100
nA
EN
A
Maxim Integrated
2
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
ELECTRICAL CHARACTERISTICS (continued)
(V = 12V (for MAX17598, bring V up to 21V for startup), V = V
= V = V
= V
= V
SGND
= 0V, V
= +2V,
EN/UVLO
OVI
IN
IN
CS
DITHER
FB
PGND
AUXDRV = NDRV = SS = COMP = SLOPE = unconnected, R = 25kI, R = 10kI, C
= 1FF, C
= 1FF, T = T = -40NC to
RT
DT
VIN
VDRV
A
J
+125NC, unless otherwise noted. Typical values are at T = T = +25NC.) (Note 2)
A
J
PARAMETER
INTERNAL LDO (V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
)
DRV
8V < V < 15V and 0mA < I
IN
50mA (MAX17598)
<
<
VDRV
7.1
4.7
7.4
7.7
5.1
V
Output Voltage Range
V
V
DRV
VDRV
6V < V < 15V and 0mA < I
IN
50mA (MAX17599)
VDRV
4.9
V
V
Current Limit
Dropout
I
70
100
mA
V
DRV
VDRV-MAX
V
V
= 4.5V, I = 20mA (MAX17599)
VDRV
4.2
DRV
VDRV-DO
IN
OVERVOLTAGE PROTECTION (OVI)
V
V
V
rising
falling
1.16
1.1
1.21
1.15
2
1.26
1.2
OVIR
OVI
OVI Overvoltage Threshold
V
V
OVIF
OVI
OVI Masking Delay
t
Fs
OVI-MD
OVI Input Leakage Current
OSCILLATOR (RT)
I
V
= 1V, T = +25NC
-100
100
+100
1000
nA
OVI
OVI
A
NDRV Switching Frequency
Range
f
kHz
SW
NDRV Switching Frequency
Accuracy
-8
+8
74
%
%
Maximum Duty Cycle
D
f
= 400KHz, R = 10kI
71
72.5
50
MAX
SW
DT
SYNCHRONIZATION (DITHER/SYNC)
Synchronization Logic-High
Input
V
3
V
IH-SYNC
Synchronization Pulse Width
ns
Synchronization Frequency
Range
1.1 x
1.3 x
f
SYNC
f
f
SW
SW
DITHERING RAMP GENERATOR (DITHER/SYNC)
Charging Current
45
43
50
55
57
FA
FA
Discharging Current
Ramp-High Trip Point
Ramp-Low Trip Point
50
2
V
0.4
Maxim Integrated
3
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
ELECTRICAL CHARACTERISTICS (continued)
(V = 12V (for MAX17598, bring V up to 21V for startup), V = V
= V = V
= V
= V
SGND
= 0V, V
= +2V,
EN/UVLO
OVI
IN
IN
CS
DITHER
FB
PGND
AUXDRV = NDRV = SS = COMP = SLOPE = unconnected, R = 25kI, R = 10kI, C
= 1FF, C
= 1FF, T = T = -40NC to
RT
DT
VIN
VDRV
A
J
+125NC, unless otherwise noted. Typical values are at T = T = +25NC.) (Note 2)
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SOFT-START/SOFT-STOP (SS)
Soft-Start Charging Current
I
9
10
5
11
5.6
FA
FA
SSCH
Soft-Stop Discharging
Current
I
4.4
SSDISCH
SS Bias Voltage
V
1.19
1.21
0.15
1.23
V
V
SS
SS Discharge Threshold
NDRV DRIVER (NDRV)
Pulldown Impedance
V
Soft-stop completion
SSDISCH
I
I
R
I
I
(sinking) = 100mA
(sourcing) = 50mA
1.37
3
NDRV-N
NDRV
NDRV
Pullup Impedance
Peak Sink Current
Peak Source Current
Fall Time
R
4.26
1.5
0.9
10
8.5
NDRV-P
C
C
C
= 10nF
= 10nF
= 1nF
A
A
NDRV
NDRV
NDRV
t
ns
NDRV-F
Rise Time
t
C
= 1nF
20
ns
NDRV-R
NDRV
AUXDRV DRIVER (AUXDRV)
Pulldown Impedance
I
I
R
I
I
(sinking) = 100mA
3.35
7
AUXDRV-N
AUXDRV
AUXDRV
Pullup Impedance
Peak Sink Current
Peak Source Current
Fall Time
R
(sourcing) = 50mA
= 10nF
9.78
0.7
0.3
16
19
AUXDRV-P
C
C
C
A
A
AUXDRV
AUXDRV
AUXDRV
= 10nF
t
= 1nF
ns
AUXDRV-F
Rise Time
t
C
= 1nF
32
ns
AUXDRV-R
AUXDRV
DEAD TIME (DT)
R
R
R
R
= 10kI
= 100kI
= 10kI
= 100kI
25
250
25
DT
DT
DT
DT
NDRV$ to AUXDRV$
AUXDRV# to NDRV#
NDRV to AUXDRV Delay
(Dead Time)
t
ns
DT
250
CURRENT-LIMIT COMPARATOR (CS)
Cycle-by-Cycle Peak-
Current-Limit Threshold
V
290
340
-122
305
360
-102
320
380
-82
mV
mV
mV
CS-PEAK
Cycle-by-Cycle Runaway-
Current-Limit Threshold
V
CS-RUN
Cycle-by-Cycle Reverse-
Current-Limit Threshold
V
CS-REV
Maxim Integrated
4
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
ELECTRICAL CHARACTERISTICS (continued)
(V = 12V (for MAX17598, bring V up to 21V for startup), V = V
= V = V
= V
= V
SGND
= 0V, V
= +2V,
EN/UVLO
OVI
IN
IN
CS
DITHER
FB
PGND
AUXDRV = NDRV = SS = COMP = SLOPE = unconnected, R = 25kI, R = 10kI, C
= 1FF, C
= 1FF, T = T = -40NC to
RT
DT
VIN
VDRV
A
J
+125NC, unless otherwise noted. Typical values are at T = T = +25NC.) (Note 2)
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Current-Sense Leading-Edge
Blanking Time
t
From NDRV# edge
70
70
ns
CS-BLANK
Current-Sense-Blanking Time
for Reverse-Current Limit
t
CS-BLANK-
Rev
From AUXDRV$ edge
ns
ns
From CS rising (10mV overdrive) to
NDRV falling (excluding leading-edge
blanking)
Propagation Delay from
Comparator Input to NDRV
t
40
PDCS
Number of Consecutive
Peak-Current-Limit Events to
HICCUP
N
8
1
event
event
HICCUP-P
Number of Runaway Current-
Limit Events to HICCUP
N
-HICCUP-R
Overcurrent Hiccup Timeout
Minimum On-Time
32,768
130
cycle
ns
t
90
170
ON-MIN
SLOPE COMPENSATION (SLOPE)
Slope Bias Current
I
9
10
11
FA
kI
SLOPE
Slope Resistor Range
R
25
200
SLOPE
Slope Compensation Ramp
R
= 100kW
140
165
50
190
mV/Fs
mV/Fs
SLOPE
SLOPE
COMP,
Default Slope Compensation
Ramp
V
V
< 0.2V or 4V < V
SLOPE
PWM COMPARATOR
Comparator Offset Voltage
Current-Sense Gain
V
when V = 0V
1.65
1.75
1.81
1.97
2
V
PWM-OS
CS
A
DV
/DV
CS
2.15
V/V
CS-PWM
COMP
Comparator Propagation
Delay
Change in V = 10mV (including
CS
internal lead-edge blanking)
t
110
ns
PWM
ERROR AMPLIFIER
V
, when I
= 0V
= 1.8V
FB
COMP
FB Reference Voltage
V
1.19
-100
1.21
1.23
V
REF
and V
COMP
FB Input Bias Current
Open-Loop Voltage Gain
Transconductance
I
V
= 1.5V, T = +25NC
+100
nA
dB
mS
FB
FB
A
A
EAMP
Gm
90
1.5
1.8
2.1
Maxim Integrated
5
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
ELECTRICAL CHARACTERISTICS (continued)
(V = 12V (for MAX17598, bring V up to 21V for startup), V = V
= V = V
= V
= V
SGND
= 0V, V
= +2V,
EN/UVLO
OVI
IN
IN
CS
DITHER
FB
PGND
AUXDRV = NDRV = SS = COMP = SLOPE = unconnected, R = 25kI, R = 10kI, C
= 1FF, C
= 1FF, T = T = -40NC to
RT
DT
VIN
VDRV
A
J
+125NC, unless otherwise noted. Typical values are at T = T = +25NC.) (Note 2)
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Transconductance
Bandwidth
BW
Open-loop (gain = 1), -3dB frequency°
10
MHz
Source Current
V
V
= 1.8V, V = 1V
80
80
120
120
210
210
FA
FA
COMP
FB
Sink Current
= 1.8V, V = 1.75V
FB
COMP
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Temperature rising
160
20
°C
°C
Thermal Shutdown
Hysteresis
Note 2: All devices are 100% production tested at +25NC. Limits over temperature are guaranteed by design.
Note 3: The MAX17598 is intended for use in universal input power supplies. The internal clamp circuit at IN is used to prevent the
bootstrap capacitor from charging to a voltage beyond the absolute maximum rating of the device when EN is low (shut-
down mode). Externally limit the maximum current to IN (hence to clamp) to 2mA (max) when EN is low.
Typical Operating Characteristics
(V = 15V, V
= +2V, COMP = open, C
= 1FF, C
= 1FF, T = T = -40NC to +125NC, unless otherwise noted.)
A J
IN
EN/UVLO
VIN
VDRV
V
WAKEUP LEVEL
IN UVLO SHUTDOWN LEVEL
vs. TEMPERATURE (MAX17598)
BOOTSTRAP UVLO WAKE-UP LEVEL
vs. TEMPERATURE (MAX17598)
IN
vs. TEMPERATURE (MAX17599)
20.04
20.03
20.02
20.01
20.00
19.99
19.98
4.13
4.12
4.11
4.10
4.09
4.08
4.07
7.025
7.020
7.015
7.010
7.005
7.000
6.995
-40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
-40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
-40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
Maxim Integrated
6
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
Typical Operating Characteristics (continued)
(V = 15V, V
IN
= +2V, COMP = open, C
= 1FF, C
= 1FF, T = T = -40NC to +125NC, unless otherwise noted.)
EN/UVLO
VIN
VDRV A J
V
FALLING THRESHOLD vs.
IN SUPPLY CURRENT UNDER UVLO
vs. TEMPERATURE
NDRV SWITCHING FREQUENCY
vs. RESISTOR
IN
TEMPERATURE (MAX17599)
3.92
3.91
3.90
3.89
3.88
3.87
25.5
24.5
23.5
22.5
21.5
20.5
19.5
1000
900
800
700
600
500
400
300
200
100
0
-40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
-40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
5
15 25 35 45 55 65 75 85 95
FREQUENCY SELECTION RESISTOR (kI)
NDRV SWITCHING FREQUENCY
vs. TEMPERATURE
FREQUENCY DITHERING vs. R
DEAD TIME vs. R
DT
DITHER
14
12
10
8
950
850
750
650
550
450
350
250
150
50
R = 10kI
T
220
180
140
100
60
6
4
R = 100kI
T
2
20
200 300 400 500 600 700 800 900 1000
(kI)
10 20 30 40 50 60 70 80 90 100
(kI)
-40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
R
R
DT
DITHER
PEAK-CURRENT-LIMIT THRESHOLD
vs. TEMPERATURE
REVERSE CURRENT LIMIT THRESHOLD
vs. TEMPERATURE
DEAD TIME vs. TEMPERATURE
252
250
248
246
244
242
307
306
305
304
303
302
301
300
-95
-96
-97
-98
-99
-100
-101
-102
-103
-104
R
= 100kI
DT
-40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
-40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
-40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
Maxim Integrated
7
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
Typical Operating Characteristics (continued)
(V = 15V, V
IN
= +2V, COMP = open, C
= 1FF, C
= 1FF, T = T = -40NC to +125NC, unless otherwise noted.)
EN/UVLO
VIN
VDRV
A
J
FB REGULATION VOLTAGE
vs. TEMPERATURE
CURRENT-SENSE GAIN
vs. TEMPERATURE
1.217
1.215
1.213
1.211
1.209
1.207
1.205
1.99
1.98
1.97
1.96
1.95
1.94
1.93
1.92
-40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
-40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
NDRV PEAK SOURCE AND
SINK CURRENTS
AUXDRV PEAK SOURCE AND
SINK CURRENTS
MAX17598/9 toc15
MAX17598/9 toc16
PEAK SOURCE
CURRENT
PEAK SOURCE
CURRENT
I
AUXDRV
0.28A/div
I
NDRV
0.7A/div
PEAK SINK
CURRENT
PEAK SINK
CURRENT
200ns/div
200ns/div
Maxim Integrated
8
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
Typical Operating Characteristics (continued)
ENABLE SHUTDOWN WAVEFORM
(SOFT-STOP)
ENABLE STARTUP WAVEFORM
(DUTY-CYCLE SOFT-START)
MAX17598/9 toc18
MAX17598/9 toc17
V
EN/UVLO
2V/div
V
EN/UVLO
2V/div
V
OUT
2V/div
V
OUT
2V/div
4ms/div
4ms/div
SOFT-START FROM INPUT (FIGURE 9)
INPUT SHUTDOWN (FIGURE 9)
MAX17598/9 toc19
MAX17598/9 toc20
V
IN
20V/div
V
IN
20V/div
V
OUT
2V/div
V
OUT
2V/div
200ms/div
20ms/div
DEAD TIME BETWEEN NDRV
AND AUXDRV (FIGURE 9)
NDRV AND AUXDRV SIGNALS (FIGURE 9)
MAX17598/9 toc21
MAX17598/9 toc22
50ns
V
NDRV
5V/div
V
NDRV
5V/div
V
AUXDRV
5V/div
V
AUXDRV
5V/div
1µs/div
40ns/div
Maxim Integrated
9
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
Typical Operating Characteristics (continued)
MOMENTARY OVI
OPERATION (FIGURE 9)
SS, NDRV AND AUXDRV IN
HICCUP MODE (FIGURE 9)
MAX17598/9 toc24
MAX17598/9 toc23
V
OVI
5V/div
V
SS
500mV/div
V
SS
1V/div
V
NDRV
5V/div
V
OUT
5V/div
V
AUXDRV
5V/div
V
CLAMPCAP
50V/div
4ms/div
4ms/div
LOAD TRANSIENT RESPONSE (FIGURE 9)
EFFICIENCY CURVES
MAX17598/9 toc25
100
90
80
70
60
50
40
30
20
15
0
I
LOAD
2A/div
V
(AC)
OUT
100mV/div
V
V
V
= 36V
= 48V
= 72V
IN
IN
IN
0
2
4
6
8
10
200µs/div
OUTPUT CURRENT (A)
BODE PLOT (FIGURE 9)
ACTIVE CLAMP SWITCHING
WAVEFORM (FIGURE 9)
MAX17598/98 toc27
MAX17598/9 toc28
V
DS
50V/div
PHASE
36°/div
I
PRIMARY
1A/div
BANDWIDTH = 10.3kHz
PHASE MARGIN = 72°
GAIN
10dB/div
6 8 1
2
4
6 8 1
2
4 6 8 1
1µs/div
Maxim Integrated
10
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
Pin Configuration
TOP VIEW
12
11
10
9
SGND
SS
13
14
V
8
7
6
5
DRV
V
IN
MAX17598
MAX17599
FB
EN/UVLO 15
OVI 16
EP
COMP
+
1
2
3
4
TQFN
Pin Description
PIN
NAME
FUNCTION
Dead-Time Programming Resistor Connection. Connect resistor from DT to GND to set the desired
dead time between the NDRV and AUXDRV signals. See the Dead Time section to calculate the
resistor value for a particular dead time.
1
DT
Slope Compensation Programming Input. A resistor RSLOPE connected from SLOPE to SGND
programs the amount of internal slope compensation. Shorting this pin to SGND sets a default slope
compensation of 50mV/Fs.
2
3
SLOPE
RT
Switching Frequency Programming Resistor Connection. Connect resistor from RT to SGND to set the
PWM switching frequency.
Frequency Dithering Programming or Synchronization Connection. For spread-spectrum frequency
operation, connect a capacitor from DITHER to SGND and a resistor from DITHER to RT. To
synchronize the internal oscillator to the externally applied frequency, connect DITHER/SYNC to the
synchronization pulse.
4
DITHER/SYNC
Transconductance Amplifier Output. Connect the frequency compensation network between COMP
and SGND in nonisolated applications and between COMP and FB pins in isolated applications.
5
6
COMP
FB
Transconductance Error Amplifier Inverting Input
Soft-Start/Soft-Stop Capacitor Pin for Forward/Flyback Regulator. Connect a capacitor from SS to
SGND to set the soft-start/soft-stop time interval.
7
SS
8
SGND
CS
Signal Ground. Connect SGND to the signal ground plane.
Current-Sense Input. Current-sense connection for average current-sense and cycle-by-cycle
current limit. Peak current limit trip voltage is 350mV (typ).
9
10
PGND
Power Ground. Connect PGND to the power ground plane.
Maxim Integrated
11
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
Pin Description (continued)
PIN
NAME
FUNCTION
11
NDRV
External Switching NMOS Gate-Driver Output
PMOS Active-Clamp-Switch Gate-Driver Output. AUXDRV can also be used to drive a pulse
transformer for synchronous flyback application.
12
13
14
15
AUXDRV
Linear Regulator Output and Driver Input. Connect a 1FF bypass capacitor from V
to PGND as
DRV
V
DRV
close as possible to the IC.
Internal V
Regulator Input. Connect V to the input voltage source. Bypass V to PGND with a
IN IN
DRV
V
IN
0.1FF minimum ceramic capacitor.
Enable/Undervoltage Lockout Pin. To externally program the UVLO threshold of the input supply,
connect a resistive divider among input supply, EN/UVLO, and SGND.
EN/UVLO
Overvoltage Comparator Input. Connect a resistive divider among the input supply, OVI, and SGND
to set the input overvoltage threshold.
16
—
OVI
EP
Exposed Pad
Input Voltage Range
The MAX17598 has different rising and falling undervolt-
Detailed Description
The MAX17598/MAX17599 low I active-clamp current-
Q
age lockout (UVLO) thresholds on the V pin than those
IN
mode PWM controllers contain all the control circuitry
required for design of wide-input isolated/nonisolated for-
ward converter industrial power supplies. The MAX17598
has a rising UVLO threshold of 20V with a 13V hysteresis,
and is therefore well-suited for universal input (rectified
85V AC to 265V AC) or telecom (36V DC to 72V DC)
power supplies. The MAX17599 features a 4.1V rising
UVLO with a 200mV hysteresis and is optimized for low-
voltage industrial supplies (4.5V DC to 36V DC).
of the MAX17599. The thresholds for the MAX17598
are optimized for implementing power-supply startup
schemes typically used for off-line AC/DC and telecom
DC-DC power supplies that are typically encountered in
industrial applications. As such, the MAX17598 has no
limitation on the maximum input voltage, as long as the
external components are rated suitably, and the maxi-
mum operating voltages of the MAX17598 are respected.
The MAX17598 can be successfully used in universal
input (85V to 265V AC) rectified bus applications, recti-
fied 3-phase DC bus applications, and telecom (36V to
72V DC) applications.
The devices include an AUX driver that drives an auxiliary
MOSFET (clamp switch) that helps implement the active-
clamp transformer reset topology for forward converters.
Such a reset topology has several advantages, including
reduced voltage stress on the switches, transformer size
reduction due to larger allowable flux swing, and improved
efficiency due to elimination of dissipative snubber circuit-
ry. Programmable dead time between the AUX and main
driver allows for zero voltage switching (ZVS).
The V pin of the MAX17599 has a maximum operating
IN
voltage of 36V. The MAX17599 implements rising and
falling thresholds on the V pin that assume power-
IN
supply startup schemes, typical of lower voltage DC-DC
applications down to an input voltage of 4.5V DC. Thus
isolated/non-isolated active-clamp converters with sup-
ply-voltage range of 4.5V to 36V can be implemented
with the MAX17599. See Startup Operation section
for more details on power-supply startup schemes for
MAX17598/MAX17599.
Maxim Integrated
12
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
DT
V
DRV
AUXDRV
MAX17598
MAX17599
DRIVER
PGND
NDRV
V
DRV
AUXDRV
TSDN
THERMAL SENSOR
7.4V (MAX17598)
OR
4.9V (MAX17599)
NDRV
DRIVER
PGND
V
DRV
CONTROL AND
DRIVER LOGIC
LDO
DEAD TIME
HICCUP
REVERSE ILIM
COMP
POK
V
IN
-102mV
UVLO
1.21V
1.21V
SGND
PGND
EN/
UVLO
CHIPEN
CLK
SSDONE
8 PEAKEVENTS
OR 1 RUNAWAY
OSC
PEAKLIM
COMP
DITHER/SYNC
305mV
360mV
OVI
RT
RUNAWAY
COMP
BLANKING
70ns
0.9V
PWM
COMP
CS
CHIPEN
SS
10µA
5µA
SS
FIXED OR
VARIABLE
10µA
SSDONE
1.21V
SLOPE
DECODE
SLOPE
R
1x
CHIPEN/
HICCUP
CLK
COMP
FB
R
1.21V
DITHER/
SYNC
Q50µA
SS
CURRENT
SOFT-START
2V/0.4V
Figure 1. Block Diagram
Maxim Integrated
13
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
tion, only if the voltage at the OVI pin falls below 1.15V
(typ). The OVI feature is easily disabled by tying the pin
to ground. For given values of startup DC input voltage
Linear Regulator (V
)
DRV
The MAX17598/MAX17599 have an internal linear regu-
lator that is powered from the V pin. The output of
IN
(V
START
) and input overvoltage protection voltage (V ),
the linear regulator is connected to the V
pin, and
OVI
DRV
the resistor values for the divider can be calculated as
follows, assuming a 24.9kI resistor for R . R rep-
should be decoupled with a 1FF capacitor to ground
for stable operation. The V converter output sup-
OVI SUM
DRV
resents the series combination of several resistors that
might be needed in high-voltage DC bus applications
(MAX17598) or a single resistor in low-voltage DC-DC
applications (MAX17599).
plies the MOSFET drivers internal to the MAX17598/
MAX17599. The V voltage is regulated at 7.4V (typ)
in the MAX17598, and at 4.9V (typ) in the MAX17599. The
maximum operating voltage of the IN pin is 29V for the
MAX17598 and 36V for the MAX17599.
DRV
V
OVI
Maximum Duty Cycle (Dmax)
The MAX17598/MAX17599 operate at a maximum duty
cycle of 72.5% (typ). When the SLOPE pin is left OPEN,
the ICs have the necessary amount of slope compensa-
tion to provide stable, jitter-free current-mode control
operation in applications where the operating duty cycle
is less than 50%. Slope compensation is necessary for
stable operation of current-mode controlled converters
at duty cycles greater than 50%, in addition to the loop
compensation required for small signal stability. The
MAX17598/MAX17599 implement a SLOPE pin for this
purpose. See the Slope Compensation Programming
section for more details.
R
= 24.9×
−1 kW,
EN
V
START
where V
and V
are in volts.
START
OVI
V
START
1.21
R
= 24.9 + R
×
EN
−1 kW,
[
]
SUM
where R is in kI. R
might need to be implemented
as equal multiple resistors in series (R
so that voltage across each resistor is limited to its maxi-
mum operating voltage.
EN
SUM
, R
, R
)
DC1 DC2 DC3
R
SUM
3
R
= R
= R =
DC3
kW.
DC1
DC2
Applications Information
V
DC
Startup Voltage and Input Overvoltage
Protection Setting (EN/UVLO, OVI)
The EN/UVLO pin in the MAX17598/MAX17599 serves
as an enable/disable input, as well as an accurate
programmable undervoltage lockout (UVLO) pin. The
MAX17598/MAX17599 do not commence startup opera-
tions unless the EN/UVLO pin voltage exceeds 1.21V
(typ). The MAX17598/MAX17599 turn off if the EN/UVLO
pin voltage falls below 1.15V (typ). A resistor divider from
the input DC bus to ground maybe used to divide down
and apply a fraction of the input DC voltage to the EN/
UVLO pin as shown in Figure 2. The values of the resistor
divider can be selected so that the EN/UVLO pin voltage
exceeds the 1.21V (typ) turn on threshold at the desired
input DC bus voltage. The same resistor divider can be
R
R
R
DC1
DC2
DC3
R
SUM
EN/UVLO
MAX17598
MAX17599
R
EN
OVI
modified with an additional resistor, R , to implement
OVI
R
OVI
input overvoltage protection, in addition to the EN/UVLO
functionality as shown in Figure 2. When the voltage at the
OVI pin exceeds 1.21V (typ), the MAX17598/MAX17599
stop switching. Switching resumes with soft-start opera-
Figure 2. Programming EN/UVLO, OVI
Maxim Integrated
14
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
tor R
might need to be implemented as equal, mul-
Startup Operation
The MAX17598 is optimized for implementing active-
clamp converters operating either from a rectified AC
START
tiple resistors in series (R , R
applied high DC voltage in offline applications so that the
voltage across each resistor is limited to the maximum
continuous operating voltage rating. R
can be calculated as follows:
and R ) to share the
IN1
IN2
IN3
input or in a 36V DC to 72V
telecom application.
DC
and C
A cost-effective RC startup circuit can be used in such
applications. In this startup method (Figure 3), when
the input DC voltage is applied, the startup resistor
START
START
7.4× C
+ 0.04×I × C
VDRV
Q
IN
SS
R
charges the startup capacitor C
, causing
START
START
C
= 0.09
µF
the voltage at the V pin to increase towards the rising
× f
6
IN
START
GATE sw
+ I
+
t
IN
SS
V
UVLO threshold (20V typical). During this time, the
IN
10
MAX17598 draws a low startup current of 20FA (typ)
through the startup resistor R . When the voltage at
where I is the supply current drawn at the IN pin in
IN
mA, Q
nal MOSFETs Q1 and Q2 in nC, f
frequency of the converter in Hz, t
START
is the sum of the gate charges of the exter-
V
IN
reaches the rising IN UVLO threshold, the MAX17598
GATE
is the switching
is the soft-start
commences all internal operations and drives the exter-
nal MOSFETs connected to NDRV and AUXDRV. In this
condition, the MAX17598 draws 2mA (typ) current in
sw
SS
time programmed for the converter in ms. C
is
VDRV
cummulative capacitor used at DRV node in μF, and
is soft-start capacitor in nF. See the Soft-Start
from C , in addition to the current required to switch
START
C
the gates of the external MOSFETs Q1and Q2. Since
this current cannot be supported by the current through
SS
section.
R
, the voltage on C
starts to drop. When
START
START
V
−10 × 50
(
)
START
suitably configured as shown in Figure 3, the converter
operates to generate an output voltage (V ) that is
bootstrapped to the V pin. If the voltage V
R
=
kW,
START
1+ C
BIAS
START
exceeds
IN
BIAS
7V before the voltage on C
where C
is the startup capacitor in FF.
START
START
then the V voltage is sustained by V
IN
The IN UVLO rising threshold of the MAX17599 is set
to 4.1V with a hysteresis of 200mV, and is optimized for
low-voltage DC-DC applications in the range of 4.5V DC
to 36V DC. The IN pin is rated for a maximum operating
input voltage of 36V DC and can directly be connected
to the input DC supply.
ing the MAX17598 to continue to operate with energy
from V . The large hysteresis (13V typical) of the
BIAS
MAX17598 allows for a small startup capacitor (C
The low startup current (20FA typical) allows the use of
a large startup resistor (R ), thus reducing power
START
dissipation at higher DC bus voltages. The startup resis-
V
DC
R
R
R
IN1
IN2
IN3
V
DC
V
BIAS
L
BIAS
D1
R
START
C
D2
START
AUXDRV
NDRV
V
V
IN
LDO
Q1
C
CLAMP
MAX17598
DRV
C
VDRV
Q2
Figure 3. RC-Based Startup Circuit
Maxim Integrated
15
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
4.5V TO 36V DC
V
OUT
L
OUT
D1
MAX17599
C
D2
OUT
V
V
AUXDRV
NDRV
IN
LDO
Q1
C
CLAMP
DRV
C
VDRV
Q2
Figure 4. Typical Startup Circuit with IN Connected Directly to DC Input
A soft-stop feature ramps down the output voltage when
the device is turned off, and provides safe discharging
of the clamp capacitor, thus allowing the controller to
restart in a well-controlled manner. Additionally, a nega-
tive current limit is provided in the current-sense circuitry
that helps limit the clamp switch current under dynamic
operating conditions, such as momentary input overvolt-
age charging from a precharged output capacitor. The
soft-stop duration is twice that of the programmed soft-
start period.
Soft-Start and Soft-Stop
In a current-mode isolated active clamp forward con-
verter, the COMP voltage programs the peak current
in the primary, and thus the secondary-side inductor
current as well. The MAX17598/MAX17599 implement a
soft-start scheme that controls the COMP pin of the
device at turn on. A useful benefit of this feature is the
elimination of need for secondary-side soft-start circuitry
in such isolated applications. In the absence of sec-
ondary-side soft-start circuitry, the secondary-side error
amplifier can cause the output voltage to rapidly reach
the regulation value, thus causing inrush current and
output voltage overshoot. The MAX17598/MAX17599
avoid this issue by applying a soft-start to the COMP
pin. Thus the regulator’s primary and secondary currents
are ramped up in a well-controlled manner resulting in a
current-mode soft-start operation.
Programming Slope Compensation
Since the MAX17598/MAX17599 operate at a maximum
duty cycle of 72.5% (typ), slope compensation is required
to prevent subharmonic instability that occurs naturally
in continuous-conduction mode, peak current mode-
controlled converters operating at duty cycles greater
than 50%. A minimum amount of slope signal is added to
the sensed current signal, even for converters operating
below 50% duty to provide stable, jitter-free operation.
The SLOPE pin allows the user to program the necessary
slope compensation by setting the value of the resistor
Soft-start period of MAX17598/MAX17599 can be pro-
grammed by selecting the value of capacitor connected
from SS pin to GND. The capacitor C
lated as follows:
can be calcu-
SS
R
connected from SLOPE pin to ground.
SLOPE
10× t
SS
−1.81
C
=
nF
SS
S
− 8
E
V
COMP
R
=
kW
SLOPE
1.55
where t is in ms, V
is steady-state COMP voltage
SS
COMP,MAX
COMP
where S , the slope is expressed in mV per microseconds.
E
(V
= 2.6V).
For the default minimum slope compensation of 50mV/Fs
(typ), the SLOPE pin should be connected to SGND or
left unconnected.
Maxim Integrated
16
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
V
= I
x t/C
SS SSCH SS
V
COMP
* - 1.36V
SOFT-START BEGIN
0.4V
SOFT-START ENDS
0.0V
NDRV
AUXDRV
CS
Figure 5. Duty Cycle Soft-Start
V
* - 1.36V
SOFT-STOP ENDS
COMP
V
SS
= 1.21V - I x t/C
SSDISCH SS
0.4V
0.0V
SOFT-STOP BEGINS
NDRV
AUXDRV
CS
Figure 6. Duty Cycle or Current Soft-Stop
*V is steady-state COMP voltage.
COMP
Maxim Integrated
17
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
n-Channel MOSFET Gate Driver
The NDRV output drives an external n-channel MOSFET.
NDRV
NDRV can source/sink in excess of 900mA/1500mA
peak current. Therefore, select a MOSFET that yields
acceptable conduction and switching losses.
AUXDRV
DEAD TIME, t
p-Channel MOSFET Gate Driver
The AUXDRV output drives an external p-channel
MOSFET with the aid of a level shifter, as shown in the
Typical Application Circuits. AUXDRV can source/sink in
excess of 300mA/700mA peak current. Therefore, select
a MOSFET that yields acceptable conduction and switch-
ing losses. The external PMOSFET used must be able to
withstand the maximum clamp voltage.
DT
Figure 7. Dead Time Between AUXDRV and NDRV
compensation applied to stabilize the converter. The
following equation is used to calculate the value of R
Dead Time
Dead time between the main and AUX output edges
allow ZVS to occur, minimizing switching losses and
:
CS
305mV
R
=
CS
improving efficiency. The dead time (t ) is applied to
1.2×I
DT
PRI_PEAK
both leading and trailing edges of the main and AUX
outputs as shown in Figure 7. Connect a resistor between
where I
is the peak current in the primary side
PRI_PEAK
DT and GND to set t
250ns. RDT in kΩ, is calculated as:
to any value between 25ns and
of the transformer, which also flows through the main
n-channel MOSFET. When the voltage produced by this
current (through the current-sense resistor) exceeds the
current-limit comparator threshold, the MOSFET driver
(NDRV) terminates the current on-cycle within 40ns (typ).
DT
R
= 0.4× t kW,
DT
DT
where t is in ns.
DT
Oscillator/Switching Frequency
The devices implement 70ns of internal leading-edge
blanking to ignore leading-edge current spikes encoun-
tered in practice due to parasitics. Use a small RC
network for additional filtering of the leading-edge spike
on the sense waveform when needed. Set the corner
frequency of the RC filter network at 5 to 10 times the
switching frequency.
The ICs’ switching frequency is programmable between
100kHz and 1MHz with a resistor R connected between
RT
RT and GND. Use the following formula to determine the
appropriate value of R needed to generate the desired
RT
output switching frequency (f ):
SW
10
1×10
R
=
For a given peak-current-limit setting, the runaway cur-
rent limit is typically 20% higher. The peak current-limit-
triggered hiccup operation is disabled until the end of
soft-start, while the runaway current-limit-triggered hiccup
operation is always enabled.
RT
f
SW
where f
is the desired switching frequency.
SW
Peak-Current-Limit
The current-sense resistor (R ), connected between
CS
Negative Peak Current Limit
The MAX17598/MAX17599 protect against excessive
negative currents through the clamp switch, primary of
the transformer and the clamp capacitor under dynamic
operating conditions. The devices limit negative current
the source of the n-channel MOSFET and PGND, sets
the current limit. The source end of current-sense
resistor connects to CS pin of MAX17598/MAX17599.
The signal thus obtained is used by the devices,
both for current-mode control and peak-current limiting
purposes. The current-limit comparator has a voltage trip
by monitoring the voltage across R , while the AUXDRV
CS
output is low and the p-Channel FET is on. The typical
negative-current-limit threshold is set at -102mV (1/3 of
the positive-peak-current-limit threshold).
level (V
) of 305mV, and is independent of slope
CS-PEAK
Maxim Integrated
18
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
V
CS-PEAK
(305mV)
CURRENT-SENSE
VOLTAGE
HICCUP TIMEOUT
HICCUP SIGNAL
DISCHARGE WITH
ISSDISCH
V
SS-HI
SOFT-START
VOLTAGE, V
SS
t
t
RSTR
SS
Figure 8. Hiccup-Mode Timing Diagram
operation. Figure 8 shows the behavior of the device prior
and during hiccup mode.
Output Short-Circuit Protection
with Hiccup Mode
When the MAX17598/MAX17599 detect eight consecu-
tive peak-current-limit events, both NDRV and AUXDRV
driver outputs are turned off (hiccup is followed by soft-
Oscillator Synchronization
The internal oscillator can be synchronized to an external
clock by applying the clock to SYNC/DITHER directly.
The external clock frequency can be set anywhere
between 1.1x to 1.3x the internal clock frequency. Using
an external clock increases the maximum duty cycle by
stop) for a restart period, t
. After t , the device
RSTR
RSTR
turns on again with a soft-start. The duration of the restart
period is 32678 clock cycles, and therefore depends on
the switching frequency setting. The device also features
a runaway current limit setting at 120% (typ) of the peak
current limit. This feature is useful under short-circuit
faults in forward converters with synchronous rectifiers
that occur during minimum on-time conditions at high
input voltages. Under these conditions, the primary peak
current tends to build up and staircase beyond the peak
current limit setting due to insufficient discharging of the
output inductor. One single event of a runaway current
limit forces the MAX17598/MAX17599 into hiccup mode
a factor equal to f
/f
.
SYNC SW
Frequency Dithering for Spread-Spectrum
Applications (Low EMI)
The switching frequency of the converter can be dith-
ered in a range of Q10% by connecting a capacitor from
DITHER/SYNC to GND, and a resistor from DITHER to RT
as shown in the Typical Applications Circuit. This results
in lower EMI.
Maxim Integrated
19
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
A current source at SYNC/DITHER charges the capacitor
to 2V with 50FA. Upon reaching this trip point,
to the high di/dt of the currents in high-frequency switch-
ing power converters. This implies that the loop areas for
forward- and return-pulsed currents in various parts of the
circuit should be minimized. Additionally, small current
loop areas reduce radiated EMI. Similarly, the heatsink of
the MOSFET presents a dV/dt source. Therefore, the sur-
face area of the MOSFET heatsink should be minimized as
much as possible.
C
DITHER
it discharges C
to 0.4V with 50FA. The charging
DITHER
and discharging of the capacitor generates a triangular
waveform on SYNC/DITHER with peak levels at 0.4V and
2V. C
is calculated as:
DITHER
15.625
C
=
nF
DITHER
f
TRI
Ground planes must be kept as intact as possible. The
ground plane for the power section of the converter should
be kept separate from the analog ground plane, except for
a connection at the least-noisy section of the power ground
plane, typically the return of the input filter capacitor. The
negative terminal of the filter capacitor, the ground return
of the power switch, and current-sensing resistor must
be close together. PCB layout also affects the thermal
performance of the design. A number of thermal vias that
connect to a large ground plane should be provided under
the exposed pad of the part for efficient heat dissipation.
For a sample layout that ensures first pass success, please
refer to the MAX17598/MAX17599 Evaluation Kit layouts
available at www.maximintegrated.com. For universal
AC input designs, follow all applicable safety regulations.
Offline power supplies can require UL, VDE, and other
similar agency approvals.
where f
is in kHz.
TRI
Typically, f
should be set close to 1kHz. The resistor
connected from SYNC/DITHER to RT deter-
TRI
R
DITHER
mines the amount of dither as follows:
R
RT
DITHER
%DITHER =
R
where %DITHER is the amount of dither expressed as a
percentage of the switching frequency. Setting R
to 10 x R generates Q10% dither.
DITHER
RT
Layout Recommendations
All connections carrying pulsed currents must be very
short and as wide as possible. The inductance of these
connections must be kept to an absolute minimum due
Maxim Integrated
20
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
Typical Application Circuits
V
IN
L1
10mH
D1
V
OUT
T1
L2
1.5µH
C7
4.7µF
V
OUT
R1
D2
NB
NP
221kI
V
DC
R2
0R
R3
0R
3.3V, 8A
OUTPUT
C5
47µF
C4
330µF
C6
47µF
NS
INPUT
N1
36V TO
72V INPUT
C2
22µF
C3
2.2µF
PGND
PGND0
N2
PGND
PGND0
PGND
V
IN
C8
0.47µF
C10
22nF
PGND
IN
V
U1
C11
0.047µF
C16
100nF
R9
0R
SS
AUXDRV
P1
R20
OPEN
R12
0R
SLOPE
RT
NDRV
V
N3
OUT
R18
28.7kI
R14
10kI
V
DRV
R10
221
R11
49.9kI
D4
U2
R15
OPEN
PGND
CS
4
DITHER/
SYNC
SGND
1
2
R19
100
C18
0.47µF
C13
OPEN
DITHER/SYNC
R16
OPEN
V
C12
FB
SHORT
(PC TRACE)
C15
1000pF
SGND
3
SGND
R21
0.1
MAX17598
C14
2.2nF
R17
470
R13
10kI
R23
49.9kI
SGND
SGND
D3
PGND
V
OUT
C20
4.7µF
SGND
C19
R6
10kI
2
3
33nF
U3
COMP
1
PGND0
R22
C1
100pF
30kI
V
DRV
C9
1µF
V
FB
V
DRV
R24
22kI
FB
PGND0
PGND
R8
20kI
V
DC
DT
EP
R5
1.6MI
EN/UVLO
OVI
EN/UVLO
C17
OPEN
R7
35.7kI
SGND
OVI
R4
SGND
24.9kI
SGND
SGND
Figure 9. Typical Application Circuit (Telecom Power Supplies)
Maxim Integrated
21
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
Typical Application Circuits (continued)
V
IN
D2
T1
C16
47nF
NB
V
OUT
V
DC
L1
PGND
10µH
V
OUT
INPUT
R3
0R
17V TO
34V INPUT
C1
22µF
C2
0.1µF
R2
0R
R22
100kI
3.3V, 3A
OUTPUT
C4
100µF
C14
100µF
C15
100µF
C5
OPEN
NP
NS
N3
PGND
V
IN
Q1
D3
PGND
GND0
Z2
N2
6.2V
C6
0.47µF
GND0
C8
0.01µF
PGND
V
U1
IN
C18
2.2µF
C9
47nF
C13
47nF
R10
0R
SS
AUXDRV
P1
R11
OPEN
3
1
2
R12
0R
SLOPE
RT
NDRV
V
OUT
N1
R24
100kI
R25
R21
150kI
47I
R15
40kI
R6
10kI
D1
GND0
R7
120I
R8
332kI
R23
OPEN
PGND
CS
V
DRV
C17
SHORT
DITHER/
SYNC
U2
R16
100R
5
4
1
2
C19
0.1µF
C10
10nF
SGND
R13
C12
V
FB
22kI
R17
100m
4.7nF
MAX17599
SGND
SGND
SGND
C11
47pF
R19
49.9kI
R14
470R
PGND
COMP
C20
100pF
2
3
V
DRV
U3
C7
2.2µF
SGND
V
FB
1
V
DRV
R20
R18
200kI
33.2kI
FB
PGND
R9
20kI
V
DC
DT
EP
GND0
R1
3.3MI
EN/UVLO
OVI
EN/UVLO
SGND
R4
150kI
OVI
R5
121kI
SGND
SGND
Figure 10. Typical Application Circuit (Power Supply for Low-Voltage DC-DC Applications)
Maxim Integrated
22
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
Ordering Information
UVLO, IN
CLAMP
PART
TEMP RANGE
-40NC to +125NC
-40NC to +125NC
PIN PACKAGE
16 TQFN
FUNCTIONALITY
Dmax
70%
Active-clamp, peak-current-mode,
offline PWM controller
MAX17598ATE+
MAX17599ATE+
20V, Yes
Active-clamp, peak-current-mode,
PWM DC-DC controller
16 TQFN
4V, No
70%
+Denotes a lead(Pb)-free/RoHS-compliant package.
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
16 TQFN
T1633+4
21-0136
90-0032
Maxim Integrated
23
MAX17598/MAX17599
Low I , Wide-Input Range, Active Clamp
Q
Current-Mode PWM Controllers
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
1/12
Initial release
—
Updated General Description, Benefits and Features, Absolute Maximum Ratings,
Electrical Characteristics, Typical Operating Characteristics, Pin Description,
Detailed Description sections, and Figures 1, 3–6, 8–10
1
3/13
1–23
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
24
©
2013 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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