MAX1716_技术文档

19-1758; Rev 0; 8/00

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

General Description

Features

The MAX1716/MAX1854/MAX1855 step-down con-

trollers are intended for core CPU DC-DC converters in

notebook computers. They feature a dynamically

adjustable output (5-bit DAC), ultra-fast transient

response, high DC accuracy, and high efficiency need-

ed for leading-edge CPU core power supplies. Maxim's

proprietary Quick-PWM™ quick-response, constant-on-

time PWM control scheme handles wide input/output

voltage ratios with ease and provides 100ns “instant-on”

response to load transients while maintaining a relative-

ly constant switching frequency.

o High-Efficiency Voltage Positioning

o Quick-PWM Architecture

o ±±1 V

Line-Regulation Accuracy

OUT

o Adjustable Output Range (5-Bit DAC)

MAX±7±6: 0.925V to ±.6V

MAX±854: 0.925V to 2.0V

MAX±855: 0.600V to ±.75V

o 2V to 28V Input Range

o 200/300/400/550kHz Switching Frequency

o Output Undervoltage Protection

The MAX1716/MAX1854/MAX1855 are designed

specifically for CPU core applications requiring a volt-

age-positioned supply. The voltage-positioning input

(VPS), combined with a high DC accuracy control loop,

is used to implement a power supply that modifies its

output set point in response to the load current. This

arrangement decreases full-load power dissipation and

reduces the required number of output capacitors.

o Overvoltage Protection (MAX±7±6/MAX±855)

o Drive Large Synchronous-Rectifier MOSFETs

o ±.7ms Digital Soft-Start

o 700µA I

Supply Current

CC

The 28V input range of the MAX1716/MAX1854/MAX1855

enables single-stage buck conversion from high-volt-

age batteries for the maximum possible efficiency.

Alternatively, the devices’ high-frequency capability

combined with two-stage conversion (stepping down

the +5V system supply instead of the battery) allows

the smallest possible physical size. The output voltage

can be dynamically adjusted through the 5-bit digital-

to-analog converter (DAC) inputs.

o ±µA Shutdown Supply Current

o 2V ±±1 Reference Output

o V

Transition-Complete Indicator

GATE

o Small 24-Pin QSOP Package

Typical Operating Circuit

The MAX1716/MAX1854/MAX1855 are available in a

24-pin QSOP package. For applications requiring

SpeedStep™ power control (see the MAX1717).

BATTERY

2V TO 28V

+5V INPUT

________________________Applications

V

DD

V+

CC

SHDN

ILIM

REF

Notebook Computers

BST

DH

Docking Stations

OUTPUT

CPU Core Supply

MAX1716

MAX1854

MAX1855

CC

LX

DL

Single-Stage (BATT to V

) Converters

CORE

SKIP

Two-Stage (+5V to V

) Converters

CORE

GND

TON

CS

VPS

Ordering Information

D0

D1

D2

D3

D4

PART

TEMP. RANGE

-40°C to +85°C

PIN-PACKAGE

24 QSOP

PGND

DAC

INPUTS

MAX±7±6EEG

MAX±854EEG

MAX±855EEG

24 QSOP

FB

VGATE

24 QSOP

Quick-PWM is a trademark of Maxim Integrated Products.

SpeedStep is a trademark of Intel Corp.

Pin Configuration appears at end of data sheet.

________________________________________________________________ Maxim Integrated Products

±

For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.

For small orders, phone 1-800-835-8769.

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

ABSOLUTE MAXIMUM RATINGS

V+ to GND..............................................................-0.3V to +30V

LX to BST..................................................................-6V to +0.3V

CS to GND.................................................................-2V to +30V

REF Short Circuit to GND...........................................Continuous

V

, V

to GND .....................................................-0.3V to +6V

CC DD

PGND to GND..................................................................... 0.3V

SHDN, VGATE to GND.............................................-0.3V to +6V

ILIM, FB, CC, REF, D0–D4, VPS,

Continuous Power Dissipation (T = +70°C)

A

24-Pin QSOP (derate 9.5mW/°C above +70°C)...........762mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

TON to GND ...........................................-0.3V to (V

SKIP to GND (Note 1).................................-0.3V to (V

DL to PGND................................................-0.3V to (V

BST to GND............................................................-0.3V to +36V

DH to LX....................................................-0.3V to (V + 0.3V)

+ 0.3V)

CC

DD

BST

Note ±: SKIP may be forced below -0.3V, temporarily exceeding the absolute maximum rating, for the purpose of debugging proto-

type breadboards, using the no-fault test mode. Limit the current drawn to -2mA (max).

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(Circuit of Figure 1, V+ = +15V, V

= V

= 5V, SKIP = V , VPS = PGND, T = 0°C to +85°C, unless otherwise noted. Typical

CC

DD

CC

A

values are at T = +25°C.)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

PWM CONTROLLER

Battery voltage, V+

, V

2

28

Input Voltage Range

V

4.5

5.5

CC DD

DAC codes from

1.35V to 2.0V

-1

1

DC Output Voltage Accuracy

(Notes 2, 3)

V+ = 4.5V to 28V,

VPS = PGND

DAC codes from

0.925V to 1.3V

-1.2

-1.5

1.2

1.5

%

DAC codes from

0.6V to 0.9V

FB Input Bias Current

VPS Input Bias Current

VPS Gain

I

FB = 0.6V to 2.0V

-0.2

-1

0.2

1

µA

FB

I

V

=

40mV

VPS

A

VPS

I

CS

= 0 or -40mV, gain from VPS to FB

0.153

-1

0.175

0.197

1

%/mV

µA

CS Input Bias Current

ILIM Input Leakage Current

Soft-Start Ramp Time

0 to 28V

= 0 or 5.0V

I

V

0.01

1.7

100

nA

ILIM

0 to full ILIM

ms

TON = GND

TON = REF

TON = open

205

280

425

615

255

327

470

678

400

300

375

520

740

500

V+ = 11.0V,

On-Time (Note 4)

t

ns

ON

V

= 1.5V

FB

TON = V

CC

Minimum Off-Time (Note 4)

t

OFF(MIN)

2

_______________________________________________________________________________________

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V+ = +15V, V

= V = 5V, SKIP = V , VPS = PGND, T = 0°C to +85°C, unless otherwise noted. Typical

DD CC A

CC

values are at T = +25°C.)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

BIAS AND REFERENCE

Measured at V , FB forced above the

CC

regulation point

Quiescent Supply Current (V

)

I

700

<1

950

5

µA

CC

Measured at V , FB forced above the

DD

regulation point

Quiescent Supply Current (V

DD

I+

Quiescent Supply Current (V+)

25

<1

2

40

5

µA

V

Shutdown Supply Current (V

)

SHDN = GND

CC

DD

)

5

Shutdown Supply Current (V+)

Reference Voltage

SHDN = GND, V

= V

= 0 or 5V

DD

5

CC

V

= 4.5V to 5.5V, no external REF load

1.98

10

2.02

0.01

REF

CC

Reference Load Regulation

REF Sink Current

I

= 0 to 50µA

V

REF

I

REF in regulation

Falling edge

µA

V

REF

REF Fault Lockout Voltage

FAULT PROTECTION

1.6

MAX1716

MAX1855

1.8

1.9

2.0

Output Overvoltage Fault

Threshold (Note 5)

Measured at FB

V

1.97

2.03

Output Overvoltage Fault

Propagation Delay (Note 5)

FB forced to 2% above trip threshold

(MAX1716/MAX1855 only)

1.5

40

10

µs

Output Undervoltage Fault

Threshold (Foldback)

35

45

%

Output Undervoltage Fault

Propagation Delay

FB forced to 2% below trip threshold

µs

Output Undervoltage Fault

Blanking Time (Foldback)

From SHDN signal going high

10

30

ms

mV

Current-Limit Threshold

(Positive, Default)

V

- V , ILIM = V

CC

110

120

130

ITH

PGND

CS

V

= 0.5V

40

50

60

ILIM

Current-Limit Threshold

(Positive, Adjustable)

- V

CS

- V

CS

- V

CS

= 2V (REF)

170

200

230

Negative Current-Limit

Threshold

-1.2 ×

V

ITH

Zero-Crossing Current-Limit

Threshold

3

mV

°C

V

Thermal Shutdown Threshold

Hysteresis = 10°C

150

V

Undervoltage Lockout

Rising edge, hysteresis = 20mV, switching

disabled below this level

CC

4.0

4.45

Threshold

_______________________________________________________________________________________

3

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V+ = +15V, V

= V = 5V, SKIP = V , VPS = PGND, T = 0°C to +85°C, unless otherwise noted. Typical

DD CC A

CC

values are at T = +25°C.)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Measured at FB with respect to unloaded

output voltage, falling edge

VGATE Lower Trip Threshold

-12.5

-10

-7.5

%

Measured at FB with respect to unloaded

output voltage, rising edge

VGATE Upper Trip Threshold

VGATE Propagation Delay

7.5

10

12.5

%

Falling edge, FB forced 2% below or above

VGATE trip threshold

1.5

µs

VGATE Output Low Voltage

VGATE Leakage Current

GATE DRIVERS

I

= 1mA

0.4

1

V

SINK

High state, forced to 5.5V

µA

DH Gate Driver On-Resistance

R

V

- V forced to 5V

1.3

1.5

0.5

5

Ω

ON(DH)

BST

LX

High state (pullup)

DL Gate Driver On-Resistance

ON(DL)

Low state (pulldown)

1.7

DH Gate Driver Source/Sink

Current

I

DH forced to 2.5V, V

- V forced to 5V

LX

1

A

DH

BST

DL Gate Drive Sink Current

I

DL forced to 5V

DL forced to 2.5V

DL rising

3

1

A

DL

DL Gate Driver Source Current

35

26

Dead-Time

ns

DH rising

LOGIC AND I/O

Logic Input High Voltage

Logic Input Low Voltage

V

D0−D4, SHDN, SKIP

2.4

V

IH

V

0.8

IL

TON = V

(200kHz operation)

V

- 0.4

CC

TON = open (300kHz operation)

TON = REF (400kHz operation)

TON = GND (550kHz operation)

3.15

3.85

2.35

0.5

3

TON Input Levels

V

1.65

TON = GND or V

-3

-1

CC

Logic Input Current

µA

SHDN, SKIP = GND or V

D0−D4 = GND

1

CC

D0−D4 Pullup Current

3

5

10

µA

SKIP No-Fault Mode Current

T

= +25°C

-1.5

-0.1

mA

A

4

_______________________________________________________________________________________

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

ELECTRICAL CHARACTERISTICS

(Circuit of Figure 1, V+ = +15V, V

= V

= 5V, SKIP = V , VPS = PGND, T = -40°C to +85°C, unless otherwise noted.) (Note 6)

CC

DD

CC

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

PWM CONTROLLER

Battery voltage, V+

, V

2

28

Input Voltage Range

V

4.5

5.5

CC DD

DAC codes from

1.35V to 2.0V

-1.6

-2

1.6

2

DC Output Voltage Accuracy

(Notes 2, 3)

V+ = 4.5V to 28V,

VPS = PGND

%

DAC codes from

0.6V to 1.3V

FB Input Bias Current

VPS Input Bias Current

VPS Gain

I

FB = 0.6V to 2.0V

-0.2

-1

0.2

1

µA

FB

I

V

=

40mV

VPS

A

VPS

I

CS

= 0 or -40mV, gain from VPS to FB

0.153

-1

0.197

1

%/mV

µA

CS Input Bias Current

ILIM Input Leakage Current

0 to 28V

= 0 or 5.0V

I

V

100

300

375

520

740

500

nA

ILIM

TON = GND

TON = REF

TON = open

205

280

425

615

V+ = 11.0V,

= 1.5V

On-Time (Note 4)

t

ns

ON

V

FB

TON = V

CC

Minimum Off-Time (Note 4)

t

OFF(MIN)

BIAS AND REFERENCE

Measured at V , FB forced above the

CC

regulation point

Quiescent Supply Current (V

)

I

950

5

µA

CC

Measured at V , FB forced above the

DD

regulation point

Quiescent Supply Current (V

)

DD

I+

Quiescent Supply Current (V+)

40

5

µA

V

Shutdown Supply Current (V

)

SHDN = GND

CC

DD

)

5

Shutdown Supply Current (V+)

Reference Voltage

SH DN = GND, V+ = 28V, V = V = 0 or 5V

5

CC

DD

V

= 4.5V to 5.5V, no external REF load

1.98

10

2.02

0.01

REF

CC

Reference Load Regulation

REF Sink Current

I

= 0 to 50µA

V

REF

I

REF in regulation

µA

REF

FAULT PROTECTION

MAX1716

MAX1855

1.8

2.0

V

Output Overvoltage Fault

Threshold (Note 5)

Measured at FB

1.97

2.03

Output Undervoltage Fault

Threshold (Foldback)

35

10

45

30

%

Output Undervoltage Fault

Blanking Time (Foldback)

From SHDN signal going high

ms

_______________________________________________________________________________________

5

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V+ = +15V, V

= V

= 5V, SKIP = V , VPS = PGND, T = -40°C to +85°C, unless otherwise noted.) (Note 6)

CC

DD

CC

A

PARAMETER

SYMBOL

CONDITIONS

- V , ILIM = V

MIN

TYP

MAX

UNITS

Current-Limit Threshold

(Positive, Default)

V

100

140

mV

ITH

PGND

CS

CC

V

= 0.5V

35

65

ILIM

Current-Limit Threshold

(Positive, Adjustable)

- V

CS

mV

V

= 2V (REF)

160

240

V

Undervoltage Lockout

Threshold

Rising edge, hysteresis = 20mV, switching

disabled below this level

CC

4.0

-12.5

7.5

4.45

-7.5

12.5

Measured at FB with respect to unloaded

output voltage, falling edge

VGATE Lower Trip Threshold

%

Measured at FB with respect to unloaded

output voltage, rising edge

VGATE Upper Trip Threshold

VGATE Output Low Voltage

VGATE Leakage Current

GATE DRIVERS

I

= 1mA

0.4

1

V

SINK

High state, forced to 5.5V

µA

DH Gate Driver On-Resistance

R

V

- V forced to 5V

5

Ω

ON(DH)

BST

LX

High state (pullup)

DL Gate Driver On-Resistance

ON(DL)

Low state (pulldown)

1.7

LOGIC AND I/O

Logic Input High Voltage

Logic Input Low Voltage

V

D0−D4, SHDN, SKIP

2.4

V

IH

V

0.8

IL

TON = V

(200kHz operation)

V

- 0.4

CC

TON = open (300kHz operation)

TON = REF (400kHz operation)

TON = GND (550kHz operation)

3.15

3.85

2.35

0.5

3

TON Input Levels

V

1.65

TON = GND or V

-3

-1

3

CC

Logic Input Current

µA

SHDN, SKIP = GND or V

1

CC

D0−D4 Pullup Current

D0−D4 = GND

10

Note 2: Output voltage accuracy specifications apply to DAC voltages from 0.6V to 2.0V. Includes load-regulation error.

Note 3: When the inductor is in continuous conduction, the output voltage will have a DC regulation level higher than the error-com-

parator threshold by 50% of the ripple. In discontinuous conduction (SKIP = GND, light load), the output voltage will have a

DC regulation level higher than the trip level by approximately 1.5% due to slope compensation.

Note 4: On-time and off-time specifications are measured from 50% to 50% at the DH pin, with LX forced to 0, BST forced to 5V, and

a 500pF capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times may be different

due to MOSFET switching speeds.

Note 5: The MAX1854 does not have overvoltage protection.

Note 6: Specifications to -40°C are guaranteed by design, not production tested.

6

_______________________________________________________________________________________

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

Typical Operating Characteristics

(Circuit from Figure 1, components from Table 2, T = +25°C, unless otherwise noted.)

A

EFFICIENCY vs. LOAD CURRENT

(1.6V AT 300kHz)

(2.0V AT 300kHz)

100

SKIP MODE (SKIP = GND)

B1

C1

95

90

85

80

75

70

65

60

95

90

85

80

75

70

65

60

C1

A1

A1:

B1:

C1:

D1:

V

= 4.5V

= 7V

= 15V

= 24V

BATT

V

BATT

V

D1

A2

B2

D1

A2

PWM MODE (SKIP = V

)

CC

A2:

B2:

C2:

D2:

V

= 4.5V

= 7V

= 15V

= 24V

BATT

C2

D2

C2

B2

D2

55

50

55

50

MAX1854 ONLY

10 100

0.01

10.1

1

0.01

10.1

1

10

100

LOAD CURRENT (A)

EFFICIENCY vs.

LOAD CURRENT (1.3V AT 200kHz)

EFFICIENCY vs.

LOAD CURRENT (1.3V AT 300kHz)

EFFICIENCY vs.

LOAD CURRENT (1.3V AT 550kHz)

100

C1

B1

95

90

85

80

75

70

65

60

95

90

85

80

75

70

65

60

95

90

85

80

75

70

65

60

C1

B1

C1

B1

A1

D1

A2

B2

A2

B2

A2

B2

C2

D2

C2

D2

D1

CIRCUIT #2

55

50

55

50

55

50

L = 1.5µH

L = 1.0µH

L = 0.68µH

0.01

0.1

1

10

100

0.01

0.1

1

10

100

0.01

0.1

1

10

100

LOAD CURRENT (A)

EFFECTIVE EFFICIENCY vs.

LOAD CURRENT (1.3V AT 200kHz)

EFFECTIVE EFFICIENCY vs.

LOAD CURRENT (1.3V AT 300kHz)

EFFECTIVE EFFICIENCY vs.

LOAD CURRENT (1.3V AT 550kHz)

100

C1

B1

C1

B1

95

90

85

80

75

70

65

60

95

90

85

80

75

70

65

60

95

90

85

80

75

70

65

60

B1

C1

A1

D1

A2

B2

A2

B2

A2

B2

C2

D2

C2

D2

C2

D1

D2

CIRCUIT #2

L = 1.0µH

CIRCUIT #2

L = 1.5µH

CIRCUIT #2

L = 0.68µH

55

50

55

50

55

50

0.01

0.1

1

10

100

0.01

0.1

1

10

100

0.01

0.1

1

10

100

LOAD CURRENT (A)

_______________________________________________________________________________________

7

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

Typical Operating Characteristics (continued)

(Circuit from Figure 1, components from Table 2, T = +25°C, unless otherwise noted.)

A

OUTPUT VOLTAGE vs. LOAD CURRENT

(1.6V AT 300kHz)

OUTPUT VOLTAGE vs.

LOAD CURRENT (1.3V AT 300kHz)

EFFICIENCY vs.

LOAD CURRENT (1.0V AT 400kHz)

1.64

1.62

1.60

1.58

1.56

1.54

1.52

1.50

1.34

1.32

1.30

1.28

1.26

1.24

1.22

1.20

100

PWM MODE

SKIP MODE

PWM MODE

SKIP MODE

95

90

85

80

75

70

65

60

C1

B1

A1

V

BATT

= 24V

V

= 24V

BATT

V

BATT

= 7V

V

= 7V

BATT

B2

A2

C2

D2

D1

CIRCUIT #2

L = 1.0µH

55

50

CIRCUIT #3

10 100

0

5

10

15

20

25

0

2

4

6

8

10

12

14

0.01

0.1

1

LOAD CURRENT (A)

OUTPUT VOLTAGE vs.

LOAD CURRENT (1.0V AT 400kHz)

SWITCHING FREQUENCY

vs. LOAD CURRENT

SWITCHING FREQUENCY

vs. BATTERY VOLTAGE

1.02

1.00

350

300

250

200

150

100

50

320

310

300

290

280

270

260

PWM MODE

SKIP MODE

V

= 1.6V

OUT(PROG)

V

= 24V

BATT

PWM MODE

SKIP MODE

0.98

0.96

0.94

V

= 7V

BATT

V

= 0.925V

OUT(PROG)

V

= 7V

BATT

= 1.6V

V

OUT(PROG)

I

= 12A

4

CIRCUIT #3

2

OUT

0.92

0

4

6

8

10

12

14

0

4

8

12

16

20

0

8

12

16

20

24

LOAD CURRENT (A)

V

BATT

(V)

SWITCHING FREQUENCY

vs. TEMPERATURE

NORMALIZED CURRENT-LIMIT ERROR

vs. TEMPERATURE

ON-TIME vs. TEMPERATURE

0.88

0.86

0.84

0.82

0.80

0.78

0.76

0.74

330

320

310

300

290

280

270

6

I

= 12A

OUT

4

2

I

= 1A

OUT

I

= 5A

OUT

0

I

= 5A

OUT

-2

-4

-6

I

= 1A

OUT

I

= 12A

OUT

-40

-15

10

35

60

85

-40

-15

10

35

60

85

-40

-15

10

35

60

85

TEMPERATURE (°C)

8

_______________________________________________________________________________________

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

Typical Operating Characteristics (continued)

(Circuit from Figure 1, components from Table 2, T = +25°C, unless otherwise noted.)

A

INDUCTOR CURRENT PEAKS AND

VALLEYS vs. BATTERY VOLTAGE

CONTINUOUS-TO-DISCONTINUOUS

CURRENT-LIMIT ERROR vs. V

ILIM

INDUCTOR CURRENT POINT

3

2

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

25

20

15

10

5

CIRCUIT#1

I

PEAK

V

OUT

= 1.6V

1

0

CIRCUIT#2

V

OUT

= 1.3V

I

VALLEY

CIRCUIT#3

= 1.0V

-1

-2

-3

V

OUT

V

OUT

= 1.3V

CIRCUIT#2 (L = 1µH)

0

0.5

1.0

1.5

2.0

2.5

3.0

0

4

8

12

16

20

24

0

4

8

12

16 20 24

V

BATT

(V)

V

BATT

(V)

V

ILIM

(V)

NO-LOAD SUPPLY CURRENT

vs. BATTERY VOLTAGE

NO-LOAD SUPPLY CURRENT

vs. BATTERY VOLTAGE

NO-LOAD SUPPLY CURRENT

vs. BATTERY VOLTAGE

0.8

30

25

20

15

10

5

14

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

12

10

8

I + I

CC DD

I + I

CC DD

I + I

CC DD

SKIP MODE

550kHz (TON = GND)

CURCUIT#2 (L = 0.68µH)

I

BATT

6

I

BATT

4

PWM MODE

550kHz (TON = GND)

CURCUIT#2 (L = 0.68µH)

PWM MODE

200kHz (TON = V

CURCUIT#2 (L = 1.5µH)

2

)

CC

I

BATT

0

4

8

12

16

20

24

0

4

8

12

16

20

24

0

4

8

12

16

20

24

V

BATT

(V)

V

BATT

(V)

V

BATT

(V)

LOAD-TRANSIENT RESPONSE

WITH DISABLED VOLTAGE POSITIONING

(V

BATT

= 15V, PWM MODE)

1.60V

A

B

1.55V

1.50V

A

B

1.55V

1.50V

20A

10A

0

20A

10A

0

40µs/div

A. V

= 1.6V, 50mV/div; B. I

= 0.3A TO 18A, 10A/div;

OUT

A. V

= 1.6V, 50mV/div; B. I

= 1.3A TO 18A, 10A/div;

OUT

CIRCUIT #1, V

= 15V, PWM MODE; VPS = PGND

BATT

CIRCUIT #1, V

= 15V, PWM MODE

BATT

_______________________________________________________________________________________

9

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

Typical Operating Characteristics (continued)

(Circuit from Figure 1, components from Table 2, T = +25°C, unless otherwise noted.)

A

LOAD-TRANSIENT RESPONSE

(V = 4.5V)

(V

= 15V, SKIP MODE)

BATT

1.60V

1.55V

1.50V

1.60V

1.55V

1.50V

A

B

A

B

20A

10A

0

20A

10A

0

40µs/div

A. V

OUT

= 1.6V, 50mV/div; B. I

= 0.3A TO 18A, 10A/div

A. V

OUT

= 1.6V, 50mV/div

OUT

CIRCUIT #1, V

= 15V, SKIP MODE

B. I

OUT

= 0.3A TO 18A, 10A/div

BATT

CIRCUIT #1, V

= 4.5V, PWM MODE

BATT

LOAD-TRANSIENT RESPONSE

(V = 1.0V)

LOAD-TRANSIENT RESPONSE

WITH CERAMIC OUTPUT CAPACITORS

OUT(PROG)

1.00V

0.98V

0.96V

0.94V

20A

1.65V

1.60V

1.55V

1.50V

A

B

20A

10A

0

B

10A

0

40µs/div

A. V

OUT

= 1.0V, 20mV/div

A. V

= 1.6V, 50mV/div

OUT

B. I

OUT

= 0.3A TO 12A, 10A/div

B. I

OUT

= 0.3A TO 18A, 10A/div

CIRCUIT #3, V

= 4.5V, PWM MODE

CIRCUIT #4, V

= 15V, PWM MODE

BATT

10 ______________________________________________________________________________________

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

Typical Operating Characteristics (continued)

(Circuit from Figure 1, components from Table 2, T = +25°C, unless otherwise noted.)

A

STARTUP WAVEFORM

(18A LOAD)

SHORT-CIRCUIT WAVEFORM

MAX1716-30

MAX1716-31

2V

1V

2V

1V

A

0

20A

10A

20A

10A

B

0

5V

0

5V

0

C

200µs/div

= 1.6V, 1V/div

20µs/div

= 1.6V, 1V/div

A. V

OUT

A. V

OUT

B. I , L = 0.68µH, 10A/div

L

B. I , L = 0.68µH, 10A/div

L

C. V

= 0 TO V , 5V/div

CC

SHDN

C. SHORT-CIRCUIT CONTROL, 5V/div

R

OUT

= 88mΩ

STARTUP WAVEFORM

(NO-LOAD)

SHUTDOWN WAVEFORM

MAX1716-33

MAX1716-32

2V

1V

0

2V

0

A

B

A

20A

0

10A

0

B

C

D

-20A

5V

0

5V

0

C

D

5V

0

5V

0

100µs/div

= 1.6V, NO LOAD, 1V/div

100µs/div

= 1.6V, R = 88mΩ, 2V/div

A. V

OUT

A. V

OUT

B. I , L = 0.68µH, 10A/div

L

B. I , L = 0.68µH, 20A/div

L

C. V , 5V/div

DL

C. V , 5V/div

DL

D. V

= 0 TO V , 5V/div

CC

D. V

= V TO 0, 5V/div

CC

SHDN

______________________________________________________________________________________ 11

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

Pin Description

NAME

FUNCTION

1

DH

High-Side Gate Driver Output. DH swings from LX to BST.

Battery Voltage Sense Connection. Connect V+ to input power source. V+ is used only for PWM

one-shot timing. DH on-time is inversely proportional to input voltage over a 2V to 28V range.

2

3

V+

Shutdown Control Input. Drive SHDN to GND to force the MAX1716/MAX1854/MAX1855 into

SHDN

shutdown. Drive or connect to V

latch.

for normal operation. A rising edge on SHDN clears the fault

CC

Feedback Input. Normally connected to V

locally at the power supply. An external resistive divider can optionally set the output voltage.

. FB is connected to the bulk output filter capacitors

OUT

4

5

FB

Voltage-Positioning Compensation Capacitor. Connect a 47pF to 1000pF (47pF typ) capacitor from

CC to GND to adjust the loop’s response time.

CC

Current-Limit Adjustment. The GND-CS current-limit threshold defaults to 120mV, if ILIM is tied to

V

. In adjustable mode, the current-limit threshold voltage is 1/10th the voltage seen at ILIM over a

CC

6

ILIM

0.5V to 2.0V range. The logic threshold for switchover to the 120mV default value is approximately

- 1V. Connect ILIM to REF for a fixed 200mV threshold.

V

CC

Analog Supply Input for PWM Core. Connect to the system supply voltage (+4.5V to +5.5V) with a

series 20Ω resistor. Bypass to GND with a 0.22µF (min) ceramic capacitor.

7

8

V

CC

On-Time Selection-Control Input. This is a four-level input used to determine DH on-time. Connect to

GND, REF, or V , or leave TON unconnected to set the following switching frequencies: GND =

CC

TON

550kHz, REF = 400kHz, floating = 300kHz, and V

= 200kHz.

CC

+2.0V Reference Voltage Output. Bypass to GND with 0.22µF (min) capacitor. Can supply 50µA for

external loads.

9

REF

10

GND

Analog Gound

Voltage-Positioning Sense Input. Connect to CS through a 1kΩ resistor to maximize the load-

dependent output voltage drop, or adjust the voltage positioning level by connecting a resistive

divider from CS to PGND. Refer to Setting Voltage Positioning on how to select resistor values.

11

12

VPS

Open-Drain Power-Good Output. VGATE is normally high when the output is in regulation. VGATE is

low in shutdown, undervoltage lockout, and during soft-start. Any fault condition forces VGATE low,

and it remains low until the fault is cleared.

VGATE

13

14

DL

Low-Side Gate-Driver Output. DL swings from PGND to V

.

DD

PGND

Power Ground

Supply Input for the DL Gate Drive. Connect to the system supply voltage, +4.5V to +5.5V. Bypass

to PGND with a 1µF (min) ceramic capacitor.

15

V

DD

16

17

18

19

20

D4

MSB DAC Code Input. 5µA internal pullup to V

(Table 5).

CC

D3

D2

D1

D0

DAC Code Input. 5µA internal pullup to V

(Table 5).

CC

LSB DAC Code Input. 5µA internal pullup to V

(Table 5).

CC

12 ______________________________________________________________________________________

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

Pin Description (continued)

NAME

FUNCTION

Pulse-Skipping or Low-Noise Mode Control Input. Connect to V for low-noise forced-PWM mode.

CC

Connect to GND to enable pulse-skipping operation. Low-noise forced-PWM mode causes inductor

current recirculation at light loads and suppresses pulse-skipping operation. Normal operation

prevents current recirculation. SKIP can also be used to disable both overvoltage and undervoltage

protection circuits and clear the fault latch (see No-Fault Test Mode). Do not leave SKIP floating.

21

SKIP

Boost Flying-Capacitor Connection. Connect to an external capacitor and diode according to the

standard application circuit (Figure 1).

22

23

BST

LX

External Inductor Connection. Connect LX to the switched side of the inductor. LX serves as the

lower supply rail for the DH high-side gate driver. LX does not connect to the current-limit

comparator.

Current-Sense Input. Connect a resistor (R

) between CS and PGND. The current-limit

SENSE

threshold is set by ILIM. If the current-sense signal (Inductor Current ✕ R ) exceeds the

SENSE

24

CS

current-limit threshold, the MAX1716/MAX1854/MAX1855 will not initiate a new cycle.

Table 1. Component Selection for Standard Applications

CIRCUIT 1

(FIGURE 1)

CIRCUIT 2

(FIGURE 11)

CIRCUIT 3

(FIGURE 12)

CIRCUIT 4

(FIGURE 13)

COMPONENT

Output Voltage

1.6V

7V to 24V

18A

1.3V

7V to 24V

12A

1.0V

7V to 24V

12A

1.6V

7V to 24V

18A

Input Voltage Range

Maximum Load Current

0.68µH

Sumida

CDEP134H-0R6

or Panasonic

ETQP6F0R6BFA

1µH

Sumida

CEP125-1R0MC

or Panasonic

ETQP6FIRIBFA

0.68µH

Sumida

CDEP134H-0R6

or Panasonic

ETQP6F0R6BFA

0.47µH

Sumitomo

CXE-R47

Inductor

TON Level

Frequency

Float

REF

GND

300kHz

400kHz

550kHz

International Rectifier

(2) IRF7811

International Rectifier

IRF7811

International Rectifier

IRF7811

International Rectifier

(2) IRF7811

High-Side MOSFET

Fairchild (2) FDS7764A

Or International

Fairchild (2) FDS7764A

Or International

Fairchild (2) FDS7764A

Or International

Fairchild (2) FDS7764A

Or International

Low-Side MOSFET

Rectifier (2) IRF7811

(5) 10µF

(4) 10µF

(5) 10µF

Input Capacitor

Taiyo Yuden

TMK432BJ106

(8) 47µF

Taiyo Yuden

JMK432BJ476MM

or TDK

(5) 220µF

Panasonic

EEFUE0E221R

(4) 220µF

Panasonic

EEFUE0E221R

(4) 220µF

Panasonic

EEFUE0E221R

Output Capacitor

C4532X5ROJ476M

Current-Sense Resistor

ILIM Level

3mΩ

3.5mΩ

3mΩ

V

/3

V

/4

V

/4

V

/3

REF

Voltage-Positioning

Resistor Ratio

1:1 (0.5x)

1:2 (0.66x)

1:1 (0.5x)

______________________________________________________________________________________ 13

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

Table 2. Component Suppliers

MANUFACTURER

MOSFETs

PHONE (COUNTRY CODE)

WEBSITE

Fairchild Semiconductor

International Rectifier

Siliconix

(1) 888-522-5372

(1) 310-322-3331

(1) 203-268-6261

www.fairchildsemi.com

www.irf.com

www.vishay.com

CAPACITORS

Kemet

(1) 408-986-0424

(1) 847-468-5624

www.kemet.com

Panasonic

www.panasonic.com

(65) 281-3226 (Singapore)

(1) 408-749-9714

Sanyo

www.secc.co.jp

(03) 3667-3408 (Japan)

(1) 408-573-4150

Taiyo Yuden

www.t-yuden.com

www.tdk.com

TDK

(1) 847-390-4373

INDUCTORS

Coilcraft

Coiltronics

Sumida

(1) 800-322-2645

(1) 561-752-5000

(1) 408-982-9660

www.coilcraft.com

www.coiltronics.com

www.sumida.com

(1) 408-451-8441 (USA)

81 75 961-3141 (Japan)

Sumitomo

www.ssmc.co.jp

The +5V bias supply powers V

DD

(PWM controller) and

CC

_______________Detailed Description

V

(gate-drive power). The maximum current is:

The MAX1716/MAX1854/MAX1855 buck controllers are

targeted for low-voltage, high-current CPU core power

supplies for notebook computers that typically require

18A (or greater) load steps. The proprietary Quick-

PWM pulse-width modulator in the converter is specifi-

cally designed for handling fast load steps while

maintaining a relatively constant operating frequency

and inductor operating point over a wide range of input

voltages. The Quick-PWM architecture circumvents the

poor load-transient timing problems of fixed-frequency

current-mode PWMs while also avoiding the problems

caused by widely varying switching frequencies in con-

ventional constant on-time and constant off-time PFM

schemes.

I

= I

+ ƒ × (Q + Q ) = 10mA to 40mA (typ)

BIAS

CC G1 G2

where I

and Q

is 700µA (typ), ƒ is the switching frequency,

CC

G1

and Q

are the MOSFET data sheet total

G2

gate-charge specification limits at V = 5V.

GS

The battery input (V+) and +5V bias inputs (V

DD

fixed 4.5V to 5.5V supply. If the +5V bias supply is

powered up prior to the battery supply, the enable sig-

nal (SHDN) must be delayed until the battery voltage is

present to ensure startup.

and

CC

V

) can be connected together if the input source is a

Free-Running, Constant-On-Time PWM

Controller with Input Feed-Forward

The Quick-PWM control architecture is a constant-on-

time, current-mode type with voltage feed-forward

(Figure 2). This architecture relies on the output ripple

voltage to provide the PWM ramp signal. Thus, the out-

put filter capacitor’s ESR acts as a feedback resistor.

The control algorithm is simple: the high-side switch on-

time is determined solely by a one-shot whose period is

inversely proportional to input voltage and directly pro-

portional to output voltage (see On-Time One-Shot).

Another one-shot sets a minimum off-time (400ns typ).

The on-time one-shot is triggered if the error compara-

+5V Bias Supply (V

CC

and V )

DD

The MAX1716/MAX1854/MAX1855 require an external

+5V bias supply in addition to the battery. Typically this

+5V bias supply is the notebook’s 95% efficient +5V

system supply. Keeping the bias supply external to the

IC improves efficiency and eliminates the cost associat-

ed with the +5V linear regulator that would otherwise be

needed to supply the PWM circuit and gate drivers. If

stand-alone capability is needed, the +5V supply can

be generated with an external linear regulator.

14 ______________________________________________________________________________________

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

+5V INPUT

BIAS SUPPLY

BATTERY (V

7V TO 24V

)

BATT

C4

1µF

R3

10Ω

C5

1µF

C

IN

Q1: (2) IRF7811

INTERNATIONAL RECTIFIER

Q2: (2) IRF7811

INTERNATIONAL RECTIFIER

D1: CMPSH-3

CENTRAL SEMICONDUCTOR

D2: CMSH2-60

CENTRAL SEMICONDUCTOR

(5) 10µF

R4

100kΩ

D1

V

DD

CC

POWER-GOOD

INDICATOR

VGATE

V+

BST

DH

SHDN

ILIM

ON OFF

L1

1.6V OUTPUT

UP TO 18A

Q1

0.68µH

C3

0.1µF

R5

C1

0.22µF

200kΩ

R6

100kΩ

C

OUT

REF

CC

MAX1716

MAX1854

MAX1855

(5) 220µF

LX

PANASONIC

D2

C2

47pF

Q2

R

DL

CS

SKIP

D0

R1

1kΩ

SENSE

3mΩ

D1

PGND

D2

R2

1kΩ

D3

TO V

CC

VPS

D4

FB

GND

TON

MAX1716 DAC CODE SHOWN

FLOAT (300kHz)

Figure 1. Standard High-Power Application (Circuit #1)

tor is low, the low-side switch current is below the cur-

rent-limit threshold, and the minimum off-time one-shot

has timed out.

easy design methodology and predictable output volt-

age ripple.

On-Time = K × (V

+ 75mV) / V+

OUT

where K is set by the TON pin-strap connection, and

75mV is an approximation to accommodate for the

expected drop across the low-side MOSFET switch and

current-sense resistor (Table 3).

On-Time One-Shot (TON)

The heart of the PWM core is the one-shot that sets the

high-side switch on-time. This fast, low-jitter, adjustable

one-shot includes circuitry that varies the on-time in

response to the input and output voltages. The high-

side switch on-time is inversely proportional to V+, and

directly proportional to the output voltage as set by the

DAC code. This algorithm results in a nearly constant

switching frequency despite the lack of a fixed-frequen-

cy clock generator. The benefits of a constant switch-

ing frequency are twofold: first, the frequency can be

selected to avoid noise-sensitive regions, such as the

455kHz IF band; second, the inductor ripple-current

operating point remains relatively constant, resulting in

The on-time one-shot has good accuracy at the operat-

ing points specified in the Electrical Characteristics

table. On-times at operating points far removed from

the conditions specified in the Electrical Characteristics

table can vary over a wide range. For example, the

550kHz setting will typically run about 10% slower with

inputs much greater than the +5V due to the very short

on-times required.

While the on-time is set by TON, V+, and the output

voltage, other factors also contribute to the overall

______________________________________________________________________________________ 15

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

IN

2V TO 28V

REF

V+

I

LIM

MAX1716

MAX1854

MAX1855

TOFF

+5V

1-SHOT

TON

FROM

OUT

ON-TIME

TRIG

Q

9R

COMPUTE

BST

DH

R

TON

S

R

Q

TRIG

CURRENT

LIMIT

1-SHOT

LX

Σ

SKIP

ERROR

AMP

CS

OUTPUT

SHDN

ZERO CROSSING

REF

7R

V

DD

+5V

R

DL

PGND

FB

CC

S

R

Q

200k

gm

x2

VPS

V

CHIP

SUPPLY

CC

REF

+10%

REF

-10%

+5V

*

CS

OVP/UVP

DETECT

R-2R

DAC

VGATE

2V REF

REF

D0 D1 D2 D3 D4

NO OVERVOLTAGE PROTECTION ON THE MAX1854

*

Figure 2. Functional Diagram

Table 3. Approximate K-Factor Errors

TON SETTING

(kHz)

K-FACTOR

APPROXIMATE

K-FACTOR ERROR (%)

MIN RECOMMENDED V

AT

BATT

(µs)

V

OUT

= 1.6V (V)

200

300

400

550

5

9

2.04

2.28

2.84

3.55

3.3

2.2

1.8

11

15

20

16 ______________________________________________________________________________________

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

-I

PEAK

∆i

∆t

V

- V

BATT OUT

=

L

-I

PEAK

I

LOAD

I

= I

/2

LOAD PEAK

I

LIMIT

0

ON-TIME

TIME

0

TIME

Figure 4. “Valley” Current-Limit Threshold Point

Figure 3. Pulse-Skipping/Discontinuous Crossover Point

switching frequency. The on-time guaranteed in the

Electrical Characteristics table is influenced by switch-

ing delays in the external high-side MOSFET. Resistive

losses—including the inductor, both MOSFETs, output

capacitor ESR, and PC board copper losses in the out-

put and ground—tend to raise the switching frequency

at higher output currents. Switch dead-time can

increase the effective on-time, reducing the switching

frequency. This effect occurs only in PWM mode (SKIP

= high) when the inductor current reverses at light or

negative load currents. With reversed inductor current,

the inductor’s EMF causes LX to go high earlier than

normal, extending the on-time by a period equal to the

DH-rising dead-time.

between continuous and discontinuous inductor-cur-

rent operation. For an input voltage (V+) range of 7V to

24V, this threshold is relatively constant, with only a

minor dependence on the input voltage:

K × V

V + − V

OUT







OUT

I

≈













LOAD(SKIP)

2L

V +

where K is the on-time scale factor (Table 3). The load-

current level at which PFM/PWM crossover occurs,

I , is equal to 1/2 the peak-to-peak ripple cur-

LOAD(SKIP)

rent, which is a function of the inductor value (Figure 3).

For example, in the standard application circuit with

K = 3.3µs (300kHz), V

= 12V, V

= 1.6V, and

OUT

BATT

When the controller operates in continuous mode, the

dead-time is no longer a factor and the actual switching

frequency is:

L = 0.68µH, switchover to pulse-skipping operation

occurs at I = 2.3A or about 1/4 full load. The

crossover point occurs at an even lower value if a

swinging (soft-saturation) inductor is used.

LOAD

ƒ = (V

+ V

) / [t

× (V+ + V

– V

)]

OUT

DROP1

ON

DROP1

DROP2

The switching waveforms may appear noisy and asyn-

chronous when light loading causes pulse-skipping

operation; this is a normal operating condition that

improves light-load efficiency. Trade-offs in PFM noise

vs. light-load efficiency are made by varying the induc-

tor value. Generally, low inductor values produce a

broader efficiency vs. load curve, while higher values

result in higher full-load efficiency (assuming that the

coil resistance remains fixed) and less output voltage

ripple. Penalties for using higher inductor values

include larger physical size and degraded load-tran-

sient response (especially at low input voltage levels).

where V

is the sum of the parasitic voltage drops

DROP1

in the inductor discharge path, including synchronous

rectifier, inductor, and PC board resistances; V is

DROP2

the sum of the resistances in the charging path, includ-

ing high-side switch, inductor, and PC board resis-

tances; and t

MAX1716/MAX1854/MAX1855.

is the on-time calculated by the

ON

Automatic Pulse-Skipping Switchover

In skip mode (SKIP = low), an inherent automatic

switchover to PFM takes place at light loads (Figure 3).

This switchover is controlled by a comparator that trun-

cates the low-side switch on-time at the inductor cur-

rent’s zero crossing. This mechanism causes the

threshold between pulse-skipping PFM and nonskip-

ping PWM operation to coincide with the boundary

SKIP

Forced-PWM Mode (

= High)

The low-noise, forced-PWM mode (SKIP driven high)

disables the zero-crossing comparator that controls the

______________________________________________________________________________________ 17

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

Table 4. Operating Mode Truth Table

SHDN

SKIP

DL

MODE

COMMENTS

Micropower shutdown state.

0

X

High

Shutdown

Automatic switchover from PWM mode to pulse-skipping

PFM mode at light loads. Prevents inductor current from

recirculating into the input.

Normal

Operation

1

GND

Switching

Low-noise forced-PWM mode causes inductor current to

reverse at light loads and suppresses pulse-skipping

operation.

V

Forced PWM

CC

Test mode with overvoltage, undervoltage, and thermal

shutdown faults disabled. Otherwise, the converter

operates as if SKIP = GND.

No-Fault Test

Mode

1

Below GND

X = Don’t care

low-side switch on-time. The resulting low-side gate-

drive waveform is forced to be the complement of the

high-side gate-drive waveform. This, in turn causes the

inductor current to reverse at light loads, as the PWM

therefore tracks the positive current limit when ILIM is

adjusted.

The MAX1716/MAX1854/MAX1855 measure the current

by sensing the voltage between CS and PGND.

Connect an external sense resistor between the source

of the low-side N-channel MOSFET and PGND. This

same resistor is also used to generate the input voltage

for the VPS input (see Setting Voltage Positioning).

Reducing the sense voltage increases the relative mea-

surement error. However, the configuration eliminates

the uncertainty of using the low-side MOSFET on-resis-

tance to measure the current, so the resulting current-

limit tolerance is tighter when sensing with a 1% sense

resistor.

loop strives to maintain a duty ratio of V

/V+. The

OUT

benefit of forced-PWM mode is to keep the switching

frequency nearly constant, but it results in higher no-

load supply current that can be 10mA to 40mA,

depending on the external MOSFETs and switching fre-

quency.

Forced-PWM mode is most useful for minimizing audio-

frequency noise and improving the cross-regulation of

multiple-output applications that use a flyback trans-

former or coupled inductor.

In some applications, the signal required for voltage

positioning is much smaller than the minimum current-

limit voltage (50mV). There are two options for address-

ing this issue. One method is to use a larger

current-sense resistor to develop the appropriate cur-

rent-limit voltage and divide down this signal to obtain

the desired VPS input. This solution provides the maxi-

mum current-limit accuracy. Alternatively, select a

sense resistance to generate the desired VPS voltage

and connect CS to LX. This results in minimum power-

dissipation with reduced current-limit accuracy. The

Current-Limit Circuit (ILIM)

The current-limit circuit employs a unique “valley” cur-

rent-sensing algorithm. If the current-sense signal is

above the current-limit threshold, the MAX1716/

MAX1854/MAX1855 will not initiate a new cycle (Figure

4). The actual peak current is greater than the current-

limit threshold by an amount equal to the inductor rip-

ple current. Therefore, the exact current-limit

characteristic and maximum load capability are a func-

tion of the current-limit threshold, inductor value, and

input voltage. The reward for this uncertainty is robust,

loss-less overcurrent sensing. When combined with the

UVP protection circuit, this current-limit method is effec-

tive in almost every circumstance.

default 120mV current limit (ILIM = V ) accommo-

CC

dates current-limit detection using the low-side power

MOSFET and low-value sense resistor.

The voltage at ILIM sets the current-limit threshold. For

voltages from 500mV to 2V, the current-limit threshold

There is also a negative current limit that prevents

excessive reverse inductor currents when V

is sink-

OUT

voltage is precisely 0.1 × V

. Set this voltage with a

ILIM

ing current. The negative current-limit threshold is set to

approximately 120% of the positive current limit and

resistive divider between REF and GND. The current-

limit threshold defaults to 120mV when ILIM is tied to

18 ______________________________________________________________________________________

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

drain to the gate of the low-side synchronous-rectifier

MOSFET. However, for high-current applications, some

+5V

combinations of high- and low-side FETs may cause

excessive gate-drain coupling, leading to poor efficien-

cy, EMI, and shoot-through currents. This is often reme-

died by adding a resistor in series with BST, which

increases the turn-on time of the high-side FET without

degrading the turn-off time (Figure 5).

V

BATT

5Ω TYP

BST

DH

LX

DAC Converter (D0–D4)

The digital-to-analog converter (DAC) programs the

output voltage. It receives a preset digital code from

the VID inputs (D0–D4), which contain weak internal

pullups to eliminate external resistors. They can also be

driven by digital logic, general-purpose I/O, or an exter-

nal multiplexer. The available DAC codes and resulting

output voltages (Table 5) are compatible with Intel’s

mobile Pentium III™ specifications.

MAX1716

MAX1854

MAX1855

Figure 5. Reducing the Switching-Node Rise Time

D0-D4 can be changed while the regulator is active, ini-

tiating a transition to a new output voltage level.

Change D0–D4 synchronously to avoid errors during a

V

. The logic threshold for switchover to the 120mV

CC

default value is approximately V

- 1V.

CC

Carefully observe the PC board layout guidelines to

ensure that noise and DC errors don’t corrupt the cur-

rent-sense signals seen by CS and PGND. The IC must

be mounted close to the current-sense resistor with

short, direct traces making a Kelvin sense connection.

V

transition. If the skew between bits exceeds 1µs,

OUT

incorrect DAC outputs may cause a partial transition to

the wrong voltage level, followed by the intended tran-

sition to the correct voltage level, lengthening the over-

all transition time.

When changing the MAX1855 DAC code while pow-

ered up, the undervoltage protection feature can be

activated if the code change increases the output volt-

age by more than 120%. For example, a transition from

any DAC code below 0.8V to 1.75V will activate the

undervoltage protection. In the preceding example,

transitioning from 0.8V to 1.35V and then from 1.35V to

1.75V avoids activating the undervoltage protection

feature.

MOSFET Gate Drivers (DH and DL)

The DH and DL drivers are optimized for driving mod-

erate-sized, high-side and larger, low-side power

MOSFETs. This is consistent with the low duty factor

seen in the notebook CPU environment, where a large

V

- V

differential exists. An adaptive dead-time

OUT

IN

circuit monitors the DL output and prevents the high-

side FET from turning on until DL is fully off. There must

be a low-resistance, low-inductance path from the DL

driver to the MOSFET gate in order for the adaptive

dead-time circuit to work properly. Otherwise, the

sense circuitry in the MAX1716/MAX1854/MAX1855 will

interpret the MOSFET gate as “off” while there is actual-

ly still charge left on the gate. Use very short, wide

traces measuring 10 to 20 squares (50 to 100 mils wide

if the MOSFET is 1 inch from the device). The dead

time at the other edge (DH turning off) is determined by

a fixed 35ns internal delay.

SHDN

Shutdown (

)

Drive SHDN low to force the MAX1716/MAX1854/

MAX1855 into a low-current shutdown state. Shutdown

turns on the low-side MOSFET by forcing the DL gate

driver high, which discharges the output capacitor and

forces the output to ground. Drive or connect SHDN to

V

for normal operation. A rising edge on SHDN

CC

clears the fault latch.

Power-on Reset

Power-on reset (POR) occurs when V rises above

approximately 2V. This resets the fault latch and soft-

start counter, preparing the regulator for operation.

The internal pulldown transistor that drives DL low is

robust, with a 0.5Ω (typ) on-resistance. This helps pre-

vent DL from being pulled up during the fast rise time

of the LX node, due to capacitive coupling from the

CC

Pentium III is a trademark of Intel Corp.

______________________________________________________________________________________ 19

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

Table 5. Output Voltage vs. DAC Codes

OUTPUT VOLTAGE

D4

D3

D2

D1

D0

MAX1716

No CPU*

1.600V

1.550V

1.500V

1.450V

1.400V

1.350V

1.300V

No CPU*

1.275V

1.250V

1.225V

1.200V

1.175V

1.150V

1.125V

1.100V

1.075V

1.050V

1.025V

1.000V

0.975V

0.950V

0.925V

No CPU*

MAX1854

2.000V

1.950V

1.900V

1.850V

1.800V

1.750V

1.700V

1.650V

1.600V

1.550V

1.500V

1.450V

1.400V

1.350V

1.300V

No CPU*

1.275V

1.250V

1.225V

1.200V

1.175V

1.150V

1.125V

1.100V

1.075V

1.050V

1.025V

1.000V

0.975V

0.950V

0.925V

No CPU*

MAX1855

1.750V

1.700V

1.650V

1.600V

1.550V

1.500V

1.450V

1.400V

1.350V

1.300V

1.250V

1.200V

1.150V

1.100V

1.050V

1.000V

0.975V

0.950V

0.925V

0.900V

0.875V

0.850V

0.825V

0.800V

0.775V

0.750V

0.725V

0.700V

0.675V

0.650V

0.625V

0.600V

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

*Note: In the no-CPU state, DH and DL are held low.

make valid decisions. To protect the output from over-

voltage faults, DL is forced high in this mode. This will

force the output to GND and results in large negative

Undervoltage Lockout and Soft-Start

V

undervoltage lockout (UVLO) circuitry inhibits

CC

switching, forces VGATE low, and drives the DL output

high. If the V voltage drops below 4.2V, it is

inductor current that pulls the output below GND. If V

CC

is likely to drop in this fashion, the output can be

assumed that there is not enough supply voltage to

20 ______________________________________________________________________________________

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

clamped with a Schottky diode to GND to reduce the

negative excursion.

UVP can be defeated through the no-fault test mode

(see No-Fault Test Mode).

To ensure correct startup, V+ should be present before

CC

regulation without V+ present, the fault latch will trip.

Thermal Fault Protection

The MAX1716/MAX1854/MAX1855 feature a thermal

fault protection circuit. When the temperature rises

above +150°C, the DL low-side gate-driver output

V

. If the converter attempts to bring the output into

After V rises above 4.2V, an internal digital soft-start

CC

timer begins to ramp up the maximum allowed current

limit. The ramp occurs in five steps: 20%, 40%, 60%,

80%, and 100%, with 100% load current available after

1.7ms 50%.

latches high until SHDN toggles or V

pulses below

CC

1V. The threshold has +10°C of thermal hysteresis,

which prevents the regulator from restarting until the

die cools off.

Power-Good Output (VGATE)

VGATE is the open-drain output of a window compara-

tor. This power-good output remains high impedance

as long as the output voltage is within 10% of the reg-

ulation voltage. When the output voltage is greater than

or less than the 10% window limits, the internal MOS-

FET is activated and pulls the output low. Any fault con-

dition forces VGATE low until the fault is cleared.

VGATE is also low in shutdown, undervoltage lockout,

and during soft-start. For logic-level output voltages,

connect an external pullup resistor between VGATE

No-Fault Test Mode

The over/undervoltage protection features can compli-

cate the process of debugging prototype breadboards

since there are at most a few milliseconds in which to

determine what went wrong. Therefore, a test mode is

provided to disable the OVP, UVP, and thermal shut-

down features, and clear the fault latch if it has been

set. The PWM operates as if SKIP were low (SKIP

mode).

The no-fault test mode is entered by sinking 1.5mA

from SKIP through an external negative voltage source

in series with a resistor. SKIP is clamped to GND with a

silicon diode, so choose the resistor value equal to

and V

(or V ). A 100kΩ resistor works well in most

DD

CC

applications.

(V

- 0.65V) / 1.5mA.

FORCE

Output Overvoltage Protection

(MAX1716/MAX1855 only)

Design Procedure

The overvoltage protection (OVP) circuit is designed to

protect against a shorted high-side MOSFET by draw-

ing high current and activating the battery’s protection

circuit. The output voltage is continuously monitored for

overvoltage. If the output exceeds the OVP threshold

(1.9V with the MAX1716, 2.0V with the MAX1855), OVP

is triggered and the circuit shuts down. The DL low-

side gate-driver output latches high until SHDN toggles

Firmly establish the input voltage range and maximum

load current before choosing a switching frequency

and inductor operating point (ripple-current ratio). The

primary design trade-off lies in choosing a good switch-

ing frequency and inductor operating point. The follow-

ing four factors dictate the design:

Input voltage range: The maximum value (V+

)

(MAX)

must accommodate the worst-case high AC-adapter

voltage. The minimum value (V+ ) must account for

or V

pulses below 1V. This action turns on the syn-

CC

(MIN)

chronous-rectifier MOSFET with 100% duty cycle and,

in turn, rapidly discharges the output filter capacitor,

forcing the output to ground. If the condition that

caused the overvoltage (such as a shorted high-side

MOSFET) persists, the battery’s internal protection cir-

cuit will engage.

the lowest input voltage after drops due to connectors,

fuses, and battery selector switches. If there is a choice

at all, lower input voltages result in better efficiency.

Maximum load current: There are two values to con-

sider. The peak load current (I

) determines

LOAD(MAX)

the instantaneous component stresses and filtering

requirements, and thus drives output capacitor selec-

tion, inductor saturation rating, and the design of the

current-limit circuit. The continuous load current

OVP can be defeated through the no-fault test mode

(see No-Fault Test Mode).

Output Undervoltage Protection

The output undervoltage protection (UVP) function is

similar to foldback current limiting, but employs a timer

rather than a variable current limit. If the regulator’s out-

put voltage is under 40% of the nominal value, anytime

after the 20ms undervoltage fault-blanking time, the

PWM is latched off and won’t restart until SHDN toggles

(I

) determines the thermal stresses and thus dri-

LOAD

ves the selection of input capacitors, MOSFETs, and

other critical heat-contributing components. Modern

notebook CPUs generally exhibit I

80%.

= I

×

LOAD(MAX)

LOAD

Switching frequency: This choice determines the

basic trade-off between size and efficiency. The opti-

or V

pulses below 1V.

CC

______________________________________________________________________________________ 21

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

mal frequency is largely a function of maximum input

voltage, due to MOSFET switching losses that are pro-

portional to frequency and V+². The optimum frequency

is also a moving target, due to rapid improvements in

MOSFET technology that are making higher frequen-

cies more practical.

Find a low-loss inductor having the lowest possible DC

resistance that fits in the allotted dimensions. Ferrite

cores are often the best choice, although powdered

iron is inexpensive and can work well at 200kHz. The

core must be large enough not to saturate at the peak

inductor current (IPEAK).

Inductor operating point: This choice provides trade-

offs between size vs. efficiency. Low inductor values

cause large ripple currents, resulting in the smallest

size, but poor efficiency and high output noise. The

minimum practical inductor value is one that causes the

circuit to operate at the edge of critical conduction

(where the inductor current just touches zero with every

cycle at maximum load). Inductor values lower than this

grant no further size-reduction benefit.

I

= I

+ (I

× LIR / 2)

PEAK

LOAD(MAX)

Setting the Current Limit

The minimum current-limit threshold must be great

enough to support the maximum load current when the

current limit is at the minimum tolerance value. The val-

ley of the inductor current occurs at I

half of the ripple current; therefore:

minus

LOAD(MAX)

I

> I

- (I

× LIR / 2)

LOAD(MAX)

LIMIT(LOW)

LOAD(MAX)

The MAX1716/MAX1854/MAX1855’s pulse-skipping

algorithm initiates skip mode at the critical-conduction

point. Thus, the inductor operating point also deter-

mines the load-current value at which PFM/PWM

switchover occurs. The optimum point is usually found

between 20% and 50% ripple current.

where I

equals the minimum current-limit

LIMIT(LOW)

threshold voltage divided by R

. For the 120mV

SENSE

default setting, the minimum current-limit threshold is

110mV.

Connect ILIM to V

for a default 120mV current-limit

CC

threshold. In the adjustable mode, the current-limit

threshold is precisely 1/10th the voltage seen at ILIM.

For an adjustable threshold, connect a resistive divider

from REF to GND, with ILIM connected to the center

tap. The external 0.5V to 2.0V adjustment range corre-

sponds to a current-limit threshold of 50mV to 200mV.

When adjusting the current limit, use 1% tolerance

resistors and a 10µA divider current to prevent a signifi-

cant increase of errors in the current-limit value.

The inductor ripple current impacts transient-response

performance, especially at low V - V

differentials.

OUT

IN

Low inductor values allow the inductor current to slew

faster, replenishing charge removed from the output fil-

ter capacitors by a sudden load step. The amount of

output sag is also a function of the maximum duty fac-

tor, which can be calculated from the on-time and mini-

mum off-time:

Output Capacitor Selection

The output filter capacitor must have low enough effec-

tive series resistance (ESR) to meet output ripple and

load-transient requirements, yet have high enough ESR

to satisfy stability requirements. Also, the capacitance

value must be high enough to absorb the inductor

energy going from a full-load to no-load condition with-

out tripping the overvoltage protection circuit.









V

V +







2

OUT

(I

− I

)

× L × K ×

− t

OFF(MIN)









LOAD1 LOAD2



V

=

SAG





V + − V







OUT

2 × C

× V

× K ×

− t



OFF(MIN)











OUT

V +



where t

is the minimum off-time (see Electrical

Characteristics), and K is from Table 3.

OFF(MIN)

In CPU V

converters and other applications where

CORE

Inductor Selection

the output is subject to violent load transients, the out-

put capacitor’s size typically depends on how much

ESR is needed to prevent the output from dipping too

low under a load transient. Ignoring the sag due to

finite capacitance:

The switching frequency and operating point (% ripple

or LIR) determine the inductor value as follows:

V

× V + −V

OUT

(

OUT

)

L =

R

= V

/ I

V + × ƒ_SW× LIR × I

ESR

STEP(MAX) LOAD(MAX)

LOAD(MAX)

The actual µF capacitance value required relates to the

physical size needed to achieve low ESR, as well as to

the chemistry of the capacitor technology. Thus, the

capacitor is usually selected by ESR and voltage rating

rather than by capacitance value (this is true of tanta-

lums, OS-CONs, and other electrolytics).

Example: I

SW

= 18A, V = 7V, V

= 1.6V,

OUT

LOAD(MAX)

= 300kHz, 30% ripple current or LIR = 0.3.

IN

f

1.6V× (7V − 1.6V)

L =

= 0.76µH

7V × 300kHz × 0.30 × 18A

22 ______________________________________________________________________________________

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

When using low-capacity filter capacitors, such as

ceramic or polymer types, capacitor size is usually

put voltage to rise above or fall below the tolerance

limit.

determined by the capacity needed to prevent V

SAG,

The easiest method for checking stability is to apply a

very fast zero-to-max load transient and carefully

observe the output voltage ripple envelope for over-

shoot and ringing. It can help to simultaneously monitor

the inductor current with an AC current probe. Don’t

allow more than one cycle of ringing after the initial

step-response under/overshoot.

and V

from causing problems during load tran-

SOAR

sients. Generally, once enough capacitance is added

to meet the overshoot requirement, undershoot at the

rising load edge is no longer a problem (see the V

SAG

equation in the Design Procedure). The amount of over-

shoot due to stored inductor energy can be calculated

as:

Input Capacitor Selection

V

≈ (L × I

²) / (2 × C

× V

)

SOAR

PEAK

OUT

The input capacitor must meet the ripple-current

where I

is the peak inductor current.

PEAK

requirement (I

) imposed by the switching currents

defined by the following equation:

RMS

Output Capacitor Stability Considerations

Stability is determined by the value of the ESR zero rel-

ative to the switching frequency. The boundary of insta-

bility is given by the following equation:

V

V + − V

OUT

(

)

OUT

I

= I

LOAD

RMS

V +

ƒ

= ƒ

/ π

SW

ESR

For most applications, nontantalum chemistries (ceram-

ic, aluminum, or OS-CON) are preferred due to their

resistance to inrush surge currents typical of systems

with a mechanical switch or connector in series with the

input. If the MAX1716/MAX1854/MAX1855 are operated

as the second stage of a two-stage power-conversion

system, tantalum input capacitors are acceptable. In

either configuration, choose an input capacitor that

exhibits <+10°C temperature rise at the RMS input cur-

rent for optimal circuit longevity.

where: ƒ

= 1 / (2 × π × R

× C

)

ESR

OUT

For a standard 300kHz application, the ESR zero fre-

quency must be well below 95kHz, preferably below

50kHz. Tantalum, Sanyo POSCAP, and Panasonic SP

capacitors in widespread use at the time of this publi-

cation have typical ESR zero frequencies below 30kHz.

In the standard application used for inductor selection,

the ESR needed to support a 50mVp-p ripple is

50mV/(18A × 0.3) = 9.3mΩ. Five 220µF/2.5V Panasonic

SP capacitors in parallel provide 3mΩ (max) ESR. Their

typical combined ESR results in a zero at 48kHz.

Power MOSFET Selection

Most of the following MOSFET guidelines focus on the

challenge of obtaining high load-current capability

(>18A) when using high-voltage (>20V) AC adapters.

Low-current applications usually require less attention.

Don’t put high-value ceramic capacitors directly across

the output without taking precautions to ensure stability.

Ceramic capacitors have a high ESR zero frequency

and may cause erratic, unstable operation. However,

it’s easy to add enough series resistance by placing

the capacitors a couple of inches downstream from the

junction of the inductor and FB pin.

For maximum efficiency, choose a high-side MOSFET

that has conduction losses equal to the switching loss-

es at the average input voltage (3 Li+ cells = 11V, 4 Li+

cells = 14V). Check to ensure that conduction losses

plus switching losses don’t exceed the package ratings

or violate the overall thermal budget at the maximum

and minimum input voltages.

Unstable operation manifests itself in two related but

distinctly different ways: double-pulsing and fast-feed-

back loop instability.

Double-pulsing occurs due to noise on the output or

because the ESR is so low that there isn’t enough volt-

age ramp in the output voltage signal. This “fools” the

error comparator into triggering a new cycle immedi-

ately after the minimum off-time period has expired.

Double-pulsing is more annoying than harmful, result-

ing in nothing worse than increased output ripple.

However, it can indicate the possible presence of loop

instability, which is caused by insufficient ESR.

Choose a low-side MOSFET that has the lowest possi-

ble on-resistance (R

), comes in a moderate-

DS(ON)

sized package (i.e., one or two SO-8s, DPAK or

D²PAK), and is reasonably priced. Make sure that the

DL gate driver can supply sufficient current to support

the gate charge and the current injected into the para-

sitic gate-to-drain capacitor caused by the high-side

MOSFET turning on; otherwise, cross-conduction prob-

lems may occur.

Loop instability can result in oscillations at the output

after line or load perturbations that can cause the out-

______________________________________________________________________________________ 23

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

tect against this possibility, “overdesign” the circuit to

MOSFET Power Dissipation

Worst-case conduction losses occur at the duty factor

extremes. For the high-side MOSFET (Q1), the worst-

case power dissipation due to resistance occurs at the

minimum input voltage:

tolerate:

I

= I

+ (I

× LIR/2)

LOAD

LIMIT(HIGH)

LOAD(MAX)

where I

is the maximum valley current

LIMIT(HIGH)

allowed by the current-limit circuit, including threshold

tolerance and on-resistance variation. The MOSFETs

must be very well heatsinked to handle the overload

power dissipation.

PD (Q1 Resistive) = (V

/V+) × I

²× R

OUT

LOAD DS(ON)

Generally, a small high-side MOSFET is desired to

reduce switching losses at high input voltages.

However, the R

required to stay within package

DS(ON)

Choose a Schottky diode (D1) with a forward voltage

low enough to prevent the low-side MOSFET body

diode from turning on during the dead-time. As a gen-

eral rule, select a diode with a DC current rating equal

to 1/3 of the load current. This diode is optional and

can be removed if efficiency isn’t critical.

power-dissipation often limits how small the MOSFET

can be. Again, the optimum occurs when the switching

losses equal the conduction (R

) losses. High-

DS(ON)

side switching losses don’t usually become an issue

until the input is greater than approximately 15V.

Calculating the power dissipation in the high-side MOS-

FET (Q1) due to switching losses is difficult since it

must allow for difficult quantifying factors that influence

the turn-on and turn-off times. These factors include the

internal gate resistance, gate charge, threshold volt-

age, source inductance, and PC board layout charac-

teristics. The following switching-loss calculation

provides only a very rough estimate and is no substi-

tute for breadboard evaluation, preferably including

verification using a thermocouple mounted on Q1:

Setting Voltage Positioning (VPS)

Voltage positioning dynamically changes the output

voltage set point in response to the load current. When

the output is loaded, the signal fed back from the VPS

input adjusts the output voltage set point, thereby

decreasing power dissipation. The load transient

response of this control loop is extremely fast yet well

controlled, so the amount of voltage change can be

accurately confined within the limits stipulated in the

microprocessor power-supply guidelines. To under-

stand the benefits of dynamically adjusting the output

voltage, see Voltage Positioning and Effective Efficiency.

2

C

V +

f

I

RSS (MAX) SW LOAD

PD

(Q1SWITCHING)

=

I

GATE

The amount of voltage change is set by a small-value

where C

GATE

(1A typ).

is the reverse transfer capacitance of Q1,

sense resistor (R

). Place this resistor between the

RSS

SENSE

and I

is the peak gate-drive source/sink current

source of the low-side MOSFET and PGND. The volt-

age developed across this resistor (V

output voltage as follows:

) relates to the

VPS

Switching losses in the high-side MOSFET can become

an insidious heat problem when maximum AC adapter

voltages are applied, due to the squared term in the

V

OUT

= V

(1 + A

V

)

OUT(PROG)

VPS VPS

where V

set by the DAC code (Table 5), and the voltage-posi-

tioning gain factor (A ) is 0.175%/mV (see Electrical

is the programmed output voltage

OUT(PROG)

C × V²× ƒ

switching-loss equation. If the high-side

SW

MOSFET chosen for adequate R

at low battery

DS(ON)

VPS

voltages becomes extraordinarily hot when biased from

Characteristics). The MAX1716/MAX1854/MAX1855

contain internal clamps to limit the voltage positioning

between 10% below and 2% above the programmed

output voltage.

V+

, consider choosing another MOSFET with

(MAX)

lower parasitic capacitance.

For the low-side MOSFET (Q2), the worst-case power

dissipation always occurs at maximum input voltage:

The voltage present at VPS can be set in several differ-

ent ways. Connect VPS directly to CS through a 1kΩ

resistor, or through a resistive divider. When connected

directly to CS, the output voltage position is:









2

V

OUT

V +

PD

(Q2 RESISTIVE)

=

I −

I

R

DS(ON)

LOAD









(MAX)

V

= V = -I

R

(1 - D)

VPS

CS

LOAD SENSE

The worst case for MOSFET power dissipation occurs

under heavy overloads that are greater than

LOAD(MAX)

where D = V

/ V+ is the regulator’s duty cycle.

OUT

I

but are not quite high enough to exceed

However, since the ratio of the output to input voltage is

usually relatively large, the effect of the duty cycle on

the circuit’s performance is not significant. Therefore,

the current limit and cause the fault latch to trip. To pro-

24 ______________________________________________________________________________________

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

N

DL

CS

REF

VPS

C

REF

0.22µF

R3

MAX1716

MAX1854

MAX1855

MAX1716

MAX1854

MAX1855

Q2

R1

R2

R

SENSE

DL

CS

VPS

R

SENSE

PGND

a) SCALED VOLTAGE POSITION SIGNAL

b) POSITIVE NO-LOAD VOLTAGE POSITIONING

Figure 6. Voltage-Positioning Configurations

the complete expression for the voltage-positioned out-

put depends only upon the value of the current-sense

resistor and the load current:

to VPS to PGND (Figure 6b). Set R1 to 1kΩ, and use the

following equation to calculate R2:







ESR

COUT

R2 = R1



V

OUT

≈ V

(1 - A

I

R

)

OUT(PROG)

VPS LOAD SENSE

A

V

R

− ESR









VPS OUT(PROG) SENSE COUT

Some applications require the addition of a positive off-

set to the output voltage to ensure that it remains within

the load specifications. The positive offset may be gen-

erated by connecting a resistive divider from REF to

VPS to CS (Figure 6a). Set R1 to 1kΩ, and use the fol-

lowing equation to calculate R3:

The MAX1716/MAX1854/MAX1855 voltage-positioning

circuit has several advantages over older circuits,

which added a fixed voltage offset on the sense point

and used a low-value resistor in series with the output.

The new circuit can use the same current-sense resis-

tor for both voltage positioning and current-limit detec-

tion. This simultaneously provides accurate current

limiting and voltage positioning. Since the new circuit

adjusts the output voltage within the control loop, the

voltage-positioning signal may be internally amplified.

The additional gain allows the use of low-value current-

sense resistors, so the power dissipated in this sense

resistor is significantly lower than a single resistor con-

nected directly in series with the output.

V

A

V





REF VPS OUT(PROG)

R3 = R1

− 1









V

OFFSET

where V

is typically 2.0V, and V

is the

OFFSET

REF

required positive offset voltage. When attenuating the

voltage-positioning signal, replace R1 with the parallel

combination of R1 and R2 (R1//R2), where R2 is the

attenuation resistor (Figure 6b).

After a load transient, the output instantly changes by

Voltage-Positioning Compensation (CC)

The voltage-positioning compensation capacitor filters

the amplified VPS signal, allowing the user to adjust the

dynamics of the voltage-positioning loop. The imped-

ance at this node is approximately 200kΩ, so the pole

provided by this node can be approximated by 1 / (2 ×

π × RC). The response time is set with a 47pF to

1000pF capacitor from CC to GND.

ESR

× ∆I

. Setting the load-dependent volt-

LOAD

COUT

age position to match this initial load step allows the

output voltage to change by ESR and

× ∆I

COUT

LOAD

stay there as long as the load remains unchanged (see

Voltage Positioning and Effective Efficiency). To set the

voltage position equal to the initial voltage drop gener-

ated by the output capacitor’s ESR, select R

=

SENSE

ESR

/ (V

× A ).

VPS

COUT

OUT(PROG)

For applications using a larger current-sense resistor,

adjust V by connecting a resistive divider from CS

VPS

______________________________________________________________________________________ 25

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

VOLTAGE POSITIONING THE OUTPUT

CAPACITOR SOAR

(ENERGY IN L

MAX1716-Figure 07

TRANSFERRED TO C

)

OUT

ESR STEP-DOWN

AND STEP-UP

STEP

A

B

1.6V

(I

X ESR)

V

OUT

RECOVERY

CAPACITIVE SAG

(dV/dt = I /C

)

OUT OUT

I

A. CONVENTIONAL CONVERTER (50mV/div)

B. VOLTAGE POSITIONED OUTPUT (50mV/div)

LOAD

Figure 7. Voltage Positioning the Output

Figure 8. Transient-Response Regions

requires only twice the ESR. Since the ESR specifica-

tion is achieved by paralleling several capacitors, fewer

units are needed for the voltage-positioned circuit.

________________Applications Issues

Voltage Positioning and

Effective Efficiency

An additional benefit of voltage positioning is reduced

power consumption at high load currents. Because the

output voltage is lower under load, the CPU draws less

current. The result is lower power dissipation in the

CPU, although some extra power is dissipated in

Powering new mobile processors requires careful

attention to detail to reduce cost, size, and power dissi-

pation. As CPUs became more power hungry, it was

recognized that even the fastest DC-DC converters

were inadequate to handle the transient power require-

ments. After a load transient, the output instantly

R

. For a nominal 1.6V, 18A output (R

=

LOAD

SENSE

89mΩ), reducing the output voltage 2.9% gives an out-

put voltage of 1.55V and an output current of 17.44A.

Given these values, CPU power consumption is

reduced from 28.8W to 27.03W. The additional power

changes by ESR

× ∆I

. Conventional DC-DC

COUT

LOAD

converters respond by regulating the output voltage

back to its nominal state after the load transient occurs

(Figure 7). However, the CPU only requires that the out-

put voltage remain above a specified minimum value.

Dynamically positioning the output voltage to this lower

limit allows the use of fewer output capacitors and

reduces power consumption under load.

consumption of R

is:

SENSE

2.5mΩ × (17.44A)²= 0.76W

and the overall power savings is as follows:

28.8W - (27.03W + 0.76W) = 1.01W

For a conventional (nonvoltage-positioned) circuit, the

total voltage change is:

In effect, 1.8W of CPU dissipation is saved and the

power supply dissipates much of the savings, but both

the net savings and the transfer of heat away from the

CPU are beneficial. Effective efficiency is defined as

the efficiency required of a nonvoltage-positioned cir-

cuit to equal the total dissipation of a voltage-posi-

tioned circuit for a given CPU operating condition.

V

P-P1

= 2 × (ESR

× ∆I ) + V + V

LOAD SAG SOAR

COUT

where V

and V

are defined in Figure 8. Setting

SOAR

SAG

the converter to regulate at a lower voltage when under

load allows a larger voltage step when the output cur-

rent suddenly decreases (Figure 7). So the total voltage

change for a voltage positioned circuit is:

Calculate effective efficiency as follows:

V

= (ESR

× ∆I

) + V

+ V

1) Start with the efficiency data for the positioned

P-P2

COUT

LOAD

SAG SOAR

circuit (V , I , V

, I

).

IN IN OUT OUT

where V

and V

are defined in the Design

SOAR

SAG

Procedure. Since the amplitudes are the same for both

circuits (V = V ), the voltage-positioned circuit

2) Model the load resistance for each data point:

P-P1

P-P2

26 ______________________________________________________________________________________

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

R

= V

/ I

where V

and V

are the parasitic voltage

DROP2

LOAD

OUT OUT

DROP1

drops in the discharge and charge paths (see On-Time

3) Calculate the output current that would exist for

each R data point in a nonpositioned

One-Shot),

t

is from the Electrical

OFF(MIN)

LOAD

Characteristics table, and K is taken from Table 3. The

application:

absolute minimum input voltage is calculated with h = 1.

I

= V / R

NP LOAD

NP

If the calculated V

is greater than the required

IN(MIN)

where V = 1.6V (in this example).

NP

minimum input voltage, then reduce the operating fre-

quency or add output capacitance to obtain an accept-

4) Calculate effective efficiency as:

able V

. If operation near dropout is anticipated,

SAG

Effective efficiency = (V

calculated nonpositioned power output divided by

the measured voltage-positioned power input.

× I ) / (V × I ) =

NP IN IN

NP

calculate V

sponse.

to be sure of adequate transient re-

SAG

Dropout Design Example:

5) Plot the efficiency data point at the nonpositioned

V

OUT

= 1.6V

current, I

.

NP

ƒ

= 550kHz

The effective efficiency of voltage-positioned circuits is

SW

shown in the Typical Operating Characteristics.

K = 1.8µs, worst-case K = 1.58µs

= 500ns

t

Dropout Performance

The output-voltage adjustable range for continuous-

conduction operation is restricted by the nonadjustable

500ns (max) minimum off-time one-shot. For best

dropout performance, use the slower (200kHz) on-time

settings. When working with low input voltages, the

duty-factor limit must be calculated using worst-case

values for on- and off-times. Manufacturing tolerances

and internal propagation delays introduce an error to

the TON K-factor. This error is greater at higher fre-

quencies (Table 3). Also, keep in mind that transient

response performance of buck regulators operated

close to dropout is poor, and bulk output capacitance

OFF(MIN)

V

= V

= 100mV

DROP1

DROP2

h = 1.5

V

= [(1.6V + 0.1V) / (1 - (0.5µs × 1.5 / 1.58µs))] +

IN(MIN)

0.1V - 0.1V = 3.2V

Calculating again with h = 1 gives the absolute limit of

dropout:

V

= [(1.6V + 0.1V) / (1 - (0.5µs × 1.0 / 1.58µs))] +

IN(MIN)

0.1V - 0.1V = 2.5V

Therefore, V must be greater than 2.5V, even with

IN

very large output capacitance, and a practical input

voltage with reasonable output capacitance would be

3.2V.

must often be added (see the V

Design Procedure section).

equation in the

SAG

The absolute point of dropout is when the inductor cur-

rent ramps down during the minimum off-time (∆I

Adjusting V

OUT

with a Resistive Divider

)

DOWN

UP

The output voltage can be adjusted with a resistive-

divider rather than the DAC if desired (Figure 9). The

drawback is that the on-time doesn’t automatically

receive correct compensation for changing output volt-

age levels. This can result in variable switching fre-

quency as the resistor ratio is changed, and/or

excessive switching frequency. The equation for adjust-

ing the output voltage is:

as much as it ramps up during the on-time (∆I ). The

ratio h = ∆I / ∆I

is an indicator of ability to slew

UP

DOWN

the inductor current higher in response to increased

load and must always be >1. As h approaches 1, the

absolute minimum dropout point, the inductor current

cannot increase as much during each switching cycle,

and V

greatly increases unless additional output

SAG

capacitance is used.

V

OUT

= V (1 + R1 / (R2 || R ))

FB INT

A reasonable minimum value for h is 1.5, but adjusting

where V

INT

is the currently selected DAC value, and

FB

this up or down allows trade-offs between V , output

SAG

R

is the FB input resistance. In resistor-adjusted cir-

capacitance, and minimum operating voltage. For a

given value of h, the minimum operating voltage can be

calculated as:

cuits, the DAC code should be set as close as possible

to the actual output voltage in order to minimize the

shift in switching frequency.

Adjusting V

OUT

Above 2V

V

+ V

OUT

DROP1

The feed-forward circuit that makes the on-time depen-

dent on the input voltage maintains a nearly constant

V

=

+ V

– V

DROP1

IN(MIN)

DROP2

t

h

OFF(MIN)

K

switching frequency as V+, I , and the DAC code

LOAD

1 –

are changed. This works extremely well as long as FB

is connected directly to the output. When the output is

______________________________________________________________________________________ 27

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

er transient response than the single stage, this can be

offset by the use of a voltage-positioned converter.

Q1

DH

LX

Ceramic Output Capacitor Applications

Ceramic capacitors have advantages and disadvan-

tages. They have ultra-low ESR and are noncom-

bustible, relatively small, and nonpolarized. However,

they are also expensive and brittle, and their ultra-low

ESR characteristic can result in excessively high ESR

zero frequencies. In addition, their relatively low capac-

itance value can cause output overshoot when step-

ping from full-load to no-load conditions, unless a small

inductor value is used (high switching frequency), or

there are some bulk tantalum or electrolytic capacitors

in parallel to absorb the stored inductor energy. In

some cases, there may be no room for electrolytics,

creating a need for a DC-DC design that uses nothing

but ceramics.

L1

V

OUT

R4

R5

MAX1716

MAX1854

MAX1855

Q2

DL

CS

VPS

R

SENSE

PGND

FB

The MAX1716 can take full advantage of the small size

and low ESR of ceramic output capacitors in a voltage-

positioned circuit. The addition of the positioning resis-

tor increases the ripple at FB, lowering the effective

ESR zero frequency of the ceramic output capacitor.

V

= V (1 + R4/R5)

FB

OUT

Figure 9. Adjusting V

with a Resistor-Divider

OUT

Output overshoot (V

determines the minimum out-

SOAR)

adjusted with a resistor-divider, the switching frequen-

cy is increased by the inverse of the divider ratio.

put capacitance requirement (see Output Capacitor

Selection). Often the switching frequency is increased

to 400kHz or 550kHz, and the inductor value is

reduced to minimize the energy transferred from induc-

tor to capacitor during load-step recovery. The efficien-

cy penalty for operating at 400kHz is about 2% to 3%

and about 5% at 550kHz when compared to the

300kHz voltage-positioned circuit, primarily due to the

high-side MOSFET switching losses.

This change in frequency can be compensated with the

addition of a resistor-divider to the battery-sense input

(V+). Attach a resistor-divider from the battery voltage

to V+ on the MAX1716/MAX1854/MAX1855, with the

same attenuation factor as the output divider. The V+

input has a nominal input impedance of 600kΩ, which

should be considered when selecting resistor values.

One-Stage (Battery Input) vs. Two-Stage

(5V Input) Applications

The MAX1716/MAX1854/MAX1855 can be used with a

direct battery connection (one stage) or can obtain

power from a regulated 5V supply (two stage). Each

approach has advantages, and careful consideration

should go into the selection of the final design.

Table 1 and the Typical Operating Characteristics

include a circuit using ceramic capacitors with a

550kHz switching frequency (Figure 13).

PC Board Layout Guidelines

Careful PC board layout is critical to achieve low

switching losses and clean, stable operation. The

switching power stage requires particular attention

(Figure 10). If possible, mount all of the power compo-

nents on the top side of the board with their ground ter-

minals flush against one another. Follow these

guidelines for good PC board layout:

The one-stage approach offers smaller total inductor

size and fewer capacitors overall due to the reduced

demands on the 5V supply. The transient response of

the single stage is better due to the ability to ramp the

inductor current faster. The total efficiency of a single

stage is better than the two-stage approach.

1) Keep the high-current paths short, especially at the

ground terminals. This is essential for stable, jitter-

free operation.

The two-stage approach allows flexible placement due

to smaller circuit size and reduced local power dissipa-

tion. The power supply can be placed closer to the

CPU for better regulation and lower I²R losses from PC

board traces. Although the two-stage design has slow-

2) Connect all analog grounds to a separate solid cop-

per plane, which connects to the GND pin of the

MAX1716/MAX1854/MAX1855. This includes the

28 ______________________________________________________________________________________

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

VIA TO V+

VIA TO GND

BATTERY

INPUT

GND

INPUT

VIA TO CS

AND VPS

NEAR R

ALL ANALOG GROUNDS

CONNECT TO LOCAL PLANE ONLY

SENSE

C

IN

MAX1717

V

CC

GND

OUTPUT

R

SENSE

CC

Q1

REF

V

DD

D1

C

OUT

Q2

V

OUT

GND

VIA TO

SOURCE

OF Q2

L1

CONNECT LOCAL ANALOG GROUND PLANE DIRECTLY TO GND FROM

THE SIDE OPPOSITE THE V CAPACITOR GND TO AVOID V GROUND

DD

CURRENTS FROM FLOWING IN THE ANALOG GROUND PLANE.

VIA TO FB

VIA TO LX

INDUCTOR DISCHARGE PATH HAS LOW DC RESISTANCE.

NOTES: "STAR" GROUND IS USED.

D1 IS DIRECTLY ACROSS Q2.

Figure 10. Power-Stage PC Board Layout Example

V

, REF, and CC capacitors, as well as the resis-

MOSFET or between the inductor and the output filter

capacitor.

CC

tive-dividers connected to FB and ILIM.

3) Keep the power traces and load connections short.

This is essential for high efficiency. The use of thick

copper PC boards (2oz vs. 1oz) can enhance full-

load efficiency by 1% or more. Correctly routing PC

board traces is a difficult task that must be

approached in terms of fractions of centimeters,

where a single mΩ of excess trace resistance caus-

es a measurable efficiency penalty.

6) Ensure the FB connection to the output is short and

direct.

7) Route high-speed switching nodes away from sensi-

tive analog areas (CC, REF, ILIM). Make all pin-strap

control input connections (SKIP, SHDN, ILIM, etc.) to

analog ground or V

rather than PGND or V

.

DD

CC

Layout Procedure

1) Place the power components first, with ground termi-

nals adjacent (low-side MOSFET source, C , C

4) CS and PGND connections for current limiting must

be made using Kelvin sense connections to guaran-

tee the current-limit accuracy.

,

OUT

IN

and D1 anode). If possible, make all these connec-

tions on the top layer with wide, copper-filled areas.

5) When trade-offs in trace lengths must be made, it’s

preferable to allow the inductor charging path to be

made longer than the discharge path. For example,

it’s better to allow some extra distance between the

input capacitors and the high-side MOSFET than to

allow distance between the inductor and the low-side

2)Mount the controller IC adjacent to the low-side

MOSFET. The DL gate trace must be short and wide,

measuring 10 to 20 squares (50mils to 100mils wide

if the MOSFET is 1 inch from the controller IC).

______________________________________________________________________________________ 29

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

+5V INPUT

BIAS SUPPLY

BATTERY (V

7V TO 24V

)

BATT

C4

1µF

R3

10Ω

C5

1µF

C

IN

Q1: IRF7811

INTERNATIONAL RECTIFIER

Q2: (2) IRF7811

INTERNATIONAL RECTIFIER

D1: CMPSH-3

CENTRAL SEMICONDUCTOR

D2: CMSH2-60

CENTRAL SEMICONDUCTOR

(4) 10µF

R4

100kΩ

D1

V

DD

CC

POWER-GOOD

INDICATOR

VGATE

V+

BST

DH

SHDN

ILIM

ON OFF

L1

1.3V OUTPUT

UP TO 12A

Q1

1.0µH

C3

0.1µF

R5

C1

0.22µF

300kΩ

R6

100kΩ

C

OUT

(4) 220µF

REF

CC

MAX1716

MAX1854

MAX1855

LX

DL

CS

D2

C2

47pF

Q2

R

SKIP

D0

R1

1kΩ

SENSE

3.5mΩ

D1

PGND

D2

R2

2kΩ

D3

TO V

CC

VPS

D4

FB

GND

TON

MAX1716 DAC CODE SHOWN

FLOAT (300kHz)

Figure 11. Low-Current Application (Circuit #2)

3) Group the gate-drive components (BST diode and

capacitor, V bypass capacitor) together near the

point must also be very close to the output capacitor

ground terminal.

DD

controller IC.

5)Connect the output power planes (V

and sys-

CORE

4)Make the DC-DC controller ground connections as

shown in Figure 1. This diagram can be viewed as

having three separate ground planes: output ground,

where all the high-power components go; the GND

tem ground planes) directly to the output filter

capacitor positive and negative terminals with multi-

ple vias. Place the entire DC-DC converter circuit as

close to the CPU as is practical.

plane, where the GND pin and V

bypass capaci-

DD

___________________Chip Information

TRANSISTOR COUNT: 3729

tors go; and an analog ground plane where sensitive

analog components go. The analog ground plane

and GND plane must meet only at a single point

directly beneath the IC. These two planes are then

connected to the high-power output ground with a

short connection from GND to the source of the low-

side MOSFET (the middle of the star ground). This

30 ______________________________________________________________________________________

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

+5V INPUT

BIAS SUPPLY

BATTERY (V

7V TO 24V

)

BATT

C4

1µF

R3

10Ω

C5

1µF

C

IN

Q1: IRF7811

INTERNATIONAL RECTIFIER

Q2: (2) IRF7811

INTERNATIONAL RECTIFIER

D1: CMPSH-3

CENTRAL SEMICONDUCTOR

D2: CMSH2-60

CENTRAL SEMICONDUCTOR

(4) 10µF

R4

100kΩ

D1

V

DD

CC

POWER-GOOD

INDICATOR

VGATE

V+

BST

DH

SHDN

ILIM

ON OFF

L1

1.0V OUTPUT

UP TO 12A

Q1

0.68µH

C3

0.1µF

R5

C1

0.22µF

300kΩ

R6

100kΩ

C

OUT

REF

CC

MAX1716

MAX1854

MAX1855

(4) 220µF

LX

DL

CS

D2

C2

47pF

Q2

R

SKIP

D0

R1

1kΩ

SENSE

3.5mΩ

D1

PGND

D2

R2

2kΩ

D3

TO V

CC

VPS

D4

FB

GND

TON

MAX1716 DAC CODE SHOWN

REF (400kHz)

Figure 12. Low-Voltage Application (Circuit #3)

______________________________________________________________________________________ 31

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

+5V INPUT

BIAS SUPPLY

BATTERY (V

7V TO 24V

)

BATT

C4

1µF

R3

10Ω

C5

1µF

C

IN

Q1: (2) IRF7811

INTERNATIONAL RECTIFIER

Q2: (2) IRF7811

INTERNATIONAL RECTIFIER

D1: CMPSH-3

CENTRAL SEMICONDUCTOR

D2: CMSH2-60

CENTRAL SEMICONDUCTOR

(5) 10µF

R4

100kΩ

D1

V

DD

CC

POWER-GOOD

INDICATOR

VGATE

V+

BST

DH

SHDN

ILIM

ON OFF

L1

1.6V OUTPUT

UP TO 18A

Q1

0.47µH

C3

0.1µF

R5

C1

0.22µF

200kΩ

R6

100kΩ

C

OUT

REF

CC

MAX1716

MAX1854

MAX1855

(8) 47µF

LX

DL

CS

D2

C2

47pF

Q2

R

SKIP

D0

R1

1kΩ

SENSE

3mΩ

D1

PGND

D2

R2

1kΩ

D3

TO V

CC

VPS

D4

FB

GND

TON

MAX1716 DAC CODE SHOWN

GND (550kHz)

Figure 13. All-Ceramic-Capacitor Application (Circuit #4)

Pin Configuration

TOP VIEW

DH

V+

1

2

3

4

5

6

7

8

9

24 CS

23 LX

SHDN

FB

22 BST

21 SKIP

MAX1716

MAX1854

MAX1855

CC

20 D0

19 D1

18 D2

17 D3

16 D4

ILIM

V

CC

TON

REF

GND 10

VPS 11

15 V

DD

14 PGND

13 DL

VGATE 12

QSOP

32 ______________________________________________________________________________________

High-Speed, Adjustable, Synchronous Step-Down

Controllers with Integrated Voltage Positioning

Package Information

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

33 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Printed USA

is a registered trademark of Maxim Integrated Products.


型号：	MAX1716
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	High-Speed, Adjustable, Synchronous Step-Down Controllers with Integrated Voltage Positioning 高速，可调，同步降压型控制器，集成电压定位控制器
文件：	总33页 (文件大小：838K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX1716 [MAXIM]

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