MAX1717BEEG [MAXIM]
Switching Controller, Current-mode, 1000kHz Switching Freq-Max, PDSO24, 0.150 INCH, 0.025 INCH PITCH, MO-137AC, QSOP-24;
| 型号： | MAX1717BEEG |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Switching Controller, Current-mode, 1000kHz Switching Freq-Max, PDSO24, 0.150 INCH, 0.025 INCH PITCH, MO-137AC, QSOP-24 开关 光电二极管 |
| 文件： | 总33页 (文件大小：444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1636; Rev 3; 8/05
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
General Description
Features
The MAX1717 step-down controller is intended for core
CPU DC-DC converters in notebook computers. It fea-
tures a dynamically adjustable output, ultra-fast tran-
sient response, high DC accuracy, and high efficiency
needed for leading-edge CPU core power supplies.
Maxim’s proprietary Quick-PWM™ quick-response,
constant-on-time PWM control scheme handles wide
input/output voltage ratios with ease and provides
100ns “instant-on” response to load transients while
maintaining a relatively constant switching frequency.
♦ Quick-PWM Architecture
♦ ±±1 ꢀ Accuracy Over Line and Load
OUT
♦ 5-Bit On-Board DAC with Input Mux
♦ Precision-Adjustable ꢀ Slew Control
OUT
♦ 0.925ꢀ to 2ꢀ Output Adjust Range
♦ Supports ꢀoltage-Positioned Applications
♦ 2ꢀ to 28ꢀ Battery Input Range
♦ Requires a Separate +5ꢀ Bias Supply
♦ 200/300/550/±000kHz Switching Frequency
♦ Over/Undervoltage Protection
The output voltage can be dynamically adjusted
through the 5-bit digital-to-analog converter (DAC)
inputs over a 0.925V to 2V range. A unique feature of
the MAX1717 is an internal multiplexer (mux) that
accepts two 5-bit DAC settings with only five digital
input pins. Output voltage transitions are accomplished
with a proprietary precision slew-rate control† that mini-
mizes surge currents to and from the battery while
guaranteeing “just-in-time” arrival at the new DAC setting.
♦ Drives Large Synchronous-Rectifier FETs
♦ 700µA (typ) I
Supply Current
CC
♦ 2µA (typ) Shutdown Supply Current
♦ 2ꢀ ±±1 Reference Output
♦ ꢀGATE Transition-Complete Indicator
♦ Small 24-Pin QSOP Package
High DC precision is enhanced by a two-wire remote-
sensing scheme that compensates for voltage drops in
the ground bus and output voltage rail. Alternatively,
the remote-sensing inputs can be used together with
the MAX1717’s high DC accuracy to implement a volt-
age-positioned circuit that modifies the load-transient
response to reduce output capacitor requirements and
full-load power dissipation.
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
24 QSOP
MAX1717EEG
MAX1717EEG+
24 QSOP
+ Denotes lead-free package.
Single-stage buck conversion allows these devices to
directly step down high-voltage batteries for the highest
possible efficiency. Alternatively, two-stage conversion
(stepping down the +5V system supply instead of the
battery) at a higher switching frequency allows the mini-
mum possible physical size.
Minimal Operating Circuit
BATTERY
2.5V TO 28V
+5V INPUT
MAX1717
The MAX1717 is available in a 24-pin QSOP package.
V
CC
V
DD
V+
SKP/SDN
FBS
Applications
Notebook Computers with SpeedStep™ or
Other Dynamically Adjustable Processors
BST
DH
ILIM
GNDS
OUTPUT
0.925V TO 2V
2-Cell to 4-Cell Li+ Battery to CPU Core Supply
Converters
A/B
REF
5V to CPU Core Supply Converters
LX
DL
TON
CC
D0
D1
D2
D3
D4
Pin Configuration appears at end of data sheet.
GND
†
Patent pending.
DAC
INPUTS
FB
TIME
Quick-PWM is a trademark of Maxim Integrated Products.
SpeedStep is a trademark of Intel Corp.
VGATE
________________________________________________________________ Maxim Integrated Products
±
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
ABSOLUTE MAXIMUM RATINGS
V+ to GND..............................................................-0.3V to +30V
LX to BST..................................................................-6V to +0.3V
REF Short Circuit to GND...........................................Continuous
Continuous Power Dissipation
24-Pin QSOP (derate 9.5mW/°C above +70°C)..........762mW
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature.........................................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
V
, V
CC DD
to GND .....................................................-0.3V to +6V
D0–D4, A/B, VGATE, to GND ..................................-0.3V to +6V
SKP/SDN to GND ...................................................-0.3V to +16V
ILIM, FB, FBS, CC, REF, GNDS, TON,
TIME to GND ..........................................-0.3V to (V
DL to GND..................................................-0.3V to (V
BST to GND............................................................-0.3V to +36V
DH to LX .....................................................-0.3V to (BST + 0.3V)
+ 0.3V)
+ 0.3V)
CC
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = +15V, V
= V
= SKP/SDN = +5V, V
= 1.6V, T = 0°C to +85°C, unless otherwise noted.)
OUT A
CC
DD
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
PWM CONTROLLER
Battery voltage, V+
, V
2
28
V
Input Voltage Range
V
4.5
5.5
CC DD
V+ = 4.5V to 28V,
includes load
regulation error
DAC codes from 1.3V to 2V
-1
1
%
%
DC Output Voltage Accuracy
(Note 1)
DAC codes from 0.925V to 1.275V
-1.2
1.2
Remote Sense Voltage Error
Line Regulation Error
FB to FBS or GNDS to GND = 0 to 25mV
= 4.5V to 5.5V, V = 4.5V to 28V
3
5
mV
mV
kΩ
µA
µA
V
CC
BATT
FB Input Resistance
115
-0.2
-1
180
265
0.2
FBS Input Bias Current
GNDS Input Bias Current
1
150kHz nominal, R
380kHz nominal, R
= 120kΩ
-8
+8
TIME
TIME
TIME Frequency Accuracy
= 47kΩ
-12
-12
375
135
260
375
+12
+12
475
173
318
461
500
375
%
38kHz nominal, R
= 470kΩ
TIME
V+ = 5V, FB = 2V, TON = GND (1000kHz)
TON = REF (550kHz)
TON = open (300kHz)
TON = V (200kHz)
425
155
289
418
400
300
On-Time (Note 2)
ns
V+ = 24V, FB = 2V
CC
Minimum Off-Time (Note 2)
Minimum Off-Time (Note 2)
BIAS AND REFERENCE
TON = V , open, or REF (200kHz, 300kHz, or 550kHz)
CC
ns
ns
TON = GND (1000kHz)
Quiescent Supply Current (V
Quiescent Supply Current (V
)
Measured at V , FB forced above the regulation point
700
<1
1200
5
µA
µA
CC
CC
)
Measured at V , FB forced above the regulation point
DD
DD
Quiescent Battery Supply
Current (V+)
25
40
µA
Shutdown Supply Current (V
)
2
5
5
µA
µA
SKP/SDN = 0
SKP/SDN = 0
CC
Shutdown Supply Current (V
)
<1
DD
Shutdown Battery Supply
Current (V+)
<1
2
5
µA
V
SKP/SDN = 0, V
= V
= 0 or 5V
DD
CC
Reference Voltage
V
= 4.5V to 5.5V, no REF load
1.98
2.02
CC
2
_______________________________________________________________________________________
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = +15V, V
= V
= SKP/SDN = +5V, V
= 1.6V, T = 0°C to +85°C, unless otherwise noted.)
OUT A
CC
DD
PARAMETER
Reference Load Regulation
REF Sink Current
CONDITIONS
MIN
TYP
MAX UNITS
I
= 0 to 50µA
0.01
2.30
V
REF
REF in regulation
10
µA
FAULT PROTECTION
Overvoltage Trip Threshold
Measured at FB
2.20
2.25
10
V
Overvoltage Fault Propagation
Delay
FB forced 2% above trip threshold
µs
Output Undervoltage Fault
Protection Threshold
With respect to unloaded output voltage
FB forced 2% below trip threshold
65
70
10
75
%
µs
Output Undervoltage Fault
Propagation Delay
Output Undervoltage Fault
Blanking Time
256
100
clks
mV
mV
mV
mV
From SKP/SDN signal going high, clock speed set by R
TIME
T
T
= +25°C to +85°C
= 0°C to +85°C
90
85
110
115
65
A
Current-Limit Threshold
(Positive, Default)
GND - LX, ILIM = V
GND - LX
CC
CC
A
ILIM = 0.5V
35
50
Current-Limit Threshold
(Positive, Adjustable)
ILIM = REF (2V)
165
200
230
Current-Limit Threshold
(Negative)
LX - GND, ILIM = V
GND - LX
-140
3
-110
4
-80
Current-Limit Threshold
(Zero Crossing)
Current-Limit Default
Switchover Threshold
V
- 1 V - 0.4
V
°C
V
CC
CC
Thermal Shutdown Threshold
Hysteresis = 10°C
150
V
Undervoltage Lockout
Rising edge, hysteresis = 20mV, PWM disabled below
this level
CC
4.1
-8
4.4
-5
Threshold
Measured at FB with respect to unloaded output voltage,
rising edge, hysteresis = 1%
VGATE Lower Trip Threshold
-6.5
%
%
Measured at FB with respect to unloaded output voltage,
rising edge, hysteresis = 1%
VGATE Upper Trip Threshold
+10
+12
+14
VGATE Propagation Delay
VGATE Transition Delay
VGATE Output Low Voltage
VGATE Leakage Current
GATE DRIꢀERS
FB forced 2% outside VGATE trip threshold
10
1
µs
clk
V
After X = Y, clock speed set by R
TIME
I
= 1mA
0.4
1
SINK
High state, forced to 5.5V
µA
DH Gate Driver On-Resistance
BST - LX forced to 5V
DL, high state (pullup)
DL, low state (pulldown)
1.0
1.0
0.4
3.5
3.5
1.0
Ω
Ω
DL Gate Driver On-Resistance
DH Gate-Driver Source/Sink
Current
DH forced to 2.5V, BST - LX forced to 5V
DL forced to 2.5V
1.3
4
A
A
DL Gate-Driver Sink Current
_______________________________________________________________________________________
3
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = +15V, V
= V
= SKP/SDN = +5V, V
= 1.6V, T = 0°C to +85°C, unless otherwise noted.)
OUT A
CC
DD
PARAMETER
CONDITIONS
MIN
TYP
1.3
35
MAX UNITS
DL Gate-Driver Source Current
DL forced to 2.5V
DL rising
A
Dead Time
ns
DH rising
26
LOGIC AND I/O
Logic Input High Voltage
Logic Input Low Voltage
2.4
95
D0–D4, A/B
D0–D4, A/B
0.8
D0–D4, 0 to 0.4V or 2.6V to 5.5V applied through resistor,
A/B = GND
DAC B-Mode Programming
Resistor, Low
1.05
D0–D4, 0 to 0.4V or 2.6V to 5.5V applied through resistor,
A/B = GND
DAC B-Mode Programming
Resistor, High
kΩ
kΩ
Pull up
Entering B mode
40
8
D0–D4 Pullup/Pulldown
Logic Input Current
Pull down
-1
-1
1
D0–D4, A/B = 5V
A/B
µA
1
For TON = V
(200kHz operation)
V
- 0.4
CC
CC
For TON = open (300kHz operation)
For TON = REF (550kHz operation)
For TON = GND (1000kHz operation)
3.15
1.65
3.85
V
TON Input Levels
2.35
0.5
-3
3
µA
V
SKP/SDN and TON Input Current SKP/SDN, TON forced to GND or V
CC
2.8
1.8
6
SKP/SDN = logic high (SKIP mode)
SKP/SDN = open (PWM mode)
SKP/SDN = logic low (shutdown mode)
To enable no-fault mode
2.2
0.5
15
SKP/SDN Input Levels
12
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = +15V, V = V = SKP/SDN = +5V, V
= 1.6V, T = -40°C to +85°C, unless otherwise noted.) (Note 3)
A
CC
DD
OUT
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
-1.5
1.5
%
1.7
V+ = 4.5V to 28V,
includes load
regulation error
DAC codes from 1.3V to 2V
DC Output Voltage Accuracy
(Note 1)
DAC codes from 0.925V to 1.275V
-1.7
150kHz nominal, R
380kHz nominal, R
= 120kΩ
= 47kΩ
-8
+8
TIME
-12
-12
375
136
260
365
+12
+12
475
173
318
471
500
375
%
ns
ns
TIME Frequency Accuracy
On-Time (Note 2)
TIME
38kHz nominal, R
= 470kΩ
TIME
V+ = 5V, FB = 2V, TON = GND (1000kHz)
TON = REF (550kHz)
TON = open (300kHz)
TON = V (200kHz)
On-Time (Note 2)
V+ = 24V, FB = 2V
CC
Minimum Off-Time (Note 2)
Minimum Off-Time (Note 2)
TON = V , open, or REF (200kHz, 300kHz, or 550kHz)
CC
ns
ns
TON = GND (1000kHz)
4
_______________________________________________________________________________________
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = +15V, V = V = SKP/SDN = +5V, V
=1.6V, T = -40°C to +85°C, unless otherwise noted.) (Note 3)
A
CC
DD
OUT
PARAMETER
CONDITIONS
Measured at V , FB forced above the regulation point
MIN
TYP
MAX UNITS
Quiescent Supply Current (V
Quiescent Supply Current (V
)
)
1200
5
µA
µA
CC
CC
Measured at V , FB forced above the regulation point
DD
DD
Quiescent Battery Supply
Current (V+)
40
µA
Shutdown Supply Current (V
)
5
5
µA
µA
SKP/SDN = 0
SKP/SDN = 0
CC
Shutdown Supply Current (V
)
DD
Shutdown Battery Supply
Current (V+)
5
µA
SKP/SDN = 0, V
= V
= 0 or 5V
DD
CC
Reference Voltage
V
= 4.5V to 5.5V, no REF load
1.98
2.20
2.02
2.30
V
V
CC
Overvoltage Trip Threshold
Measured at FB
Output Undervoltage Protection
Threshold
With respect to unloaded output voltage
65
80
75
%
mV
mV
mV
V
Current-Limit Threshold
(Positive, Default)
GND - LX, ILIM = V
GND - LX
115
CC
ILIM = 0.5V
33
65
Current-Limit Threshold
(Positive, Adjustable)
ILIM = REF (2V)
160
240
Current-Limit Threshold
(Negative)
LX - GND, ILIM = V
-140
4.1
-80
4.4
CC
V
CC
Undervoltage Lockout
Rising edge, hysteresis = 20mV, PWM disabled below this
level
Threshold
DH Gate Driver On-Resistance
BST - LX forced to 5V
DL, high state (pullup)
DL, low state (pulldown)
D0–D4, A/B
3.5
3.5
1.0
Ω
Ω
Ω
V
DL Gate Driver On-Resistance
Logic Input High Voltage
Logic Input Low Voltage
2.4
0.8
1
V
D0–D4, A/B
D0–D4, 0 to 0.4V or 2.6V to 5.5V applied through resistor,
A/B = GND
DAC B-Mode Programming
Resistor, Low
kΩ
kΩ
%
D0–D4, 0 to 0.4V or 2.6V to 5.5V applied through resistor,
A/B = GND
DAC B-Mode Programming
Resistor, High
100
-8.4
+10
Measured at FB with respect to unloaded output voltage,
falling edge, hysteresis = 1%
VGATE Lower Trip Threshold
VGATE Upper Trip Threshold
-4.6
+15
Measured at FB with respect to unloaded output voltage,
rising edge, hysteresis = 1%
%
Note ±: Output voltage accuracy specifications apply to DAC voltages from 0.925V to 2V. Includes load-regulation error.
Note 2: On-Time specifications are measured from 50% to 50% at the DH pin, with LX forced to 0, BST forced to 5V, and a 500pF
capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times may be different due to
MOSFET switching speeds.
Note 3: Specifications to -40°C are guaranteed by design and not production tested.
_______________________________________________________________________________________
5
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
Typical Operating Characteristics
(Circuit of Figure 1, components of Table 1, V+ = +12V, V = V = SKP/SDN = +5V, V = 1.6V, T = +25°C, unless otherwise noted.)
OUT A
DD
CC
EFFICIENCY vs. LOAD CURRENT
300kHz STANDARD APPLICATION,
CIRCUIT 1
EFFICIENCY vs. LOAD CURRENT
300kHz VOLTAGE POSITIONED, CIRCUIT 2
EFFECTIVE EFFICIENCY vs. LOAD CURRENT
300kHz VOLTAGE POSITIONED, CIRCUIT 2
100
90
100
90
100
SKIP MODE, V+ = 7V
SKIP MODE, V+ = 12V
SKIP MODE, V+ = 7V
SKIP MODE, V+ = 12V
SKIP MODE, V+ = 7V
SKIP MODE, V+ = 12V
90
SKIP MODE,
V+ = 20V
SKIP MODE,
V+ = 20V
SKIP MODE,
V+ = 20V
80
70
60
80
70
60
80
PWM MODE,
V+ = 7V
PWM
MODE,
V+ = 7V
PWM MODE,
V+ = 7V
70
PWM MODE,
V+ = 12V
PWM MODE, V+ = 12V
PWM MODE, V+ = 20V
PWM MODE, V+ = 12V
60
PWM MODE,
V+ = 20V
PWM MODE, V+ = 20V
50
0.01
50
50
0.01
0.1
1
10
0.01
0.1
1
10
0.1
1
10
LOAD CURRENT (A)
LOAD CURRENT (A)
NONPOSITIONED LOAD CURRENT (A)
EFFICIENCY vs. LOAD CURRENT
550kHz VOLTAGE POSITIONED, CIRCUIT 3
EFFECTIVE EFFICIENCY vs. LOAD CURRENT
550kHz VOLTAGE POSITIONED, CIRCUIT 3
EFFICIENCY vs. LOAD CURRENT
1000kHz, +5V, CIRCUIT 4
100
90
100
90
100
90
SKIP MODE, V+ = 7V
SKIP MODE, V+ = 12V
SKIP MODE, V+ = 7V
SKIP MODE, V+ = 12V
SKIP MODE
PWM MODE,
V+ = 7V
PWM MODE,
V+ = 7V
80
70
60
80
70
60
80
70
60
SKIP MODE,
V+ = 20V
SKIP MODE,
V+ = 20V
PWM MODE
PWM MODE,
V+ = 12V
PWM MODE,
V+ = 12V
PWM MODE, V+ = 20V
PWM MODE, V+ = 20V
50
50
50
0.01
0.1
1
10
0.01
0.1
1
10
0.01
0.1
1
10
LOAD CURRENT (A)
NONPOSITIONED LOAD CURRENT (A)
LOAD CURRENT (A)
EFFICIENCY vs. LOAD CURRENT
1000kHz VOLTAGE POSITIONED,
CIRCUIT 5
EFFECTIVE EFFICIENCY vs. LOAD CURRENT
1000kHz VOLTAGE POSITIONED,
CIRCUIT 5
EFFECTIVE EFFICIENCY vs. LOAD CURRENT
1000kHz, +5V, CIRCUIT 4
100
90
100
90
100
SKIP MODE, V+ = 7V
SKIP MODE, V+ = 7V
SKIP MODE, V+ = 12V
SKIP MODE
90
SKIP MODE, V+ = 12V
PWM MODE,
V+ = 7V
PWM MODE,
V+ = 7V
80
70
60
80
70
60
80
70
60
SKIP MODE,
V+ = 20V
SKIP MODE,
V+ = 20V
PWM MODE
PWM MODE,
V+ = 12V
PWM MODE,
V+ = 12V
PWM MODE,
V+ = 20V
PWM MODE,
V+ = 20V
50
50
50
0.01
0.1
1
10
0.01
0.1
1
10
0.01
0.1
1
10
LOAD CURRENT (A)
NONPOSITIONED LOAD CURRENT (A)
NONPOSITIONED LOAD CURRENT (A)
6
_______________________________________________________________________________________
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
Typical Operating Characteristics (continued)
(Circuit of Figure 1, components of Table 1, V+ = +12V, V = V = SKP/SDN = +5V, V
= 1.6V, T = +25°C, unless otherwise noted.)
A
DD
CC
OUT
FREQUENCY vs. LOAD CURRENT
FREQUENCY vs. LOAD CURRENT
FREQUENCY vs. INPUT VOLTAGE
1250
1000
400
300
400
300kHz VOLTAGE POSITIONED, CIRCUIT 2
1000kHz VOLTAGE POSITIONED, CIRCUIT 5
300kHz VOLTAGE POSITIONED, CIRCUIT 2
PWM MODE
PWM MODE
350
750
500
250
0
I
I
= 12A
OUT
OUT
200
100
0
300
250
200
SKIP MODE
SKIP MODE
= 0.3A
0
3
6
9
12
0
3
6
9
12
5
10
15
INPUT VOLTAGE (V)
20
25
LOAD CURRENT (A)
LOAD CURRENT (A)
OUTPUT CURRENT AT CURRENT LIMIT
vs. TEMPERATURE
FREQUENCY vs. TEMPERATURE
FREQUENCY vs. INPUT VOLTAGE
350
340
330
320
310
300
30
25
20
15
10
5
1200
1000
300kHz VOLTAGE POSITIONED, CIRCUIT 2
300kHz VOLTAGE POSITIONED, CIRCUIT 2
1000kHz VOLTAGE POSITIONED, CIRCUIT 5
I
I
= 12A
OUT
800
600
400
= 0.3A
OUT
20
0
-40
-20
0
20
40
60
80 85
-40
-20
0
20
40
60
80 85
5
10
15
INPUT VOLTAGE (V)
25
TEMPERATURE (°C)
TEMPERATURE (°C)
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE
INDUCTOR CURRENT PEAKS AND
VALLEYS vs. INPUT VOLTAGE
CONTINUOUS-TO-DISCONTINUOUS
INDUCTOR CURRENT POINT
1000
800
30
25
20
15
10
5
3.0
2.5
2.0
1.5
1.0
0.5
0
300kHz VOLTAGE POSITIONED, CIRCUIT 2,
SKIP MODE
300kHz VOLTAGE POSITIONED, CIRCUIT 2
I
I
PEAK
I
+ I
CC DD
VALLEY
600
400
200
0
AT CURRENT-LIMIT POINT
300kHz VOLTAGE POSITIONED, CIRCUIT 2
I+
0
5
7
9
11 13 15 17 19 21 23 25
INPUT VOLTAGE (V)
5
10
15
20
25
0
5
10
15
20
25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
_______________________________________________________________________________________
7
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
Typical Operating Characteristics (continued)
(Circuit of Figure 1, components of Table 1, V+ = +12V, V = V = SKP/SDN = +5V, V
= 1.6V, T = +25°C, unless otherwise noted.)
A
DD
CC
OUT
NO-LOAD SUPPLY CURRENT
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE
vs. INPUT VOLTAGE
40
1000
800
40
30
20
10
0
1000kHz VOLTAGE POSITIONED, CIRCUIT 5,
SKIP MODE
I
+ I
CC DD
30
600
400
200
0
I
+ I
CC DD
20
10
0
I
+ I
CC DD
I+
I+
I+
550kHz VOLTAGE POSITIONED,
CIRCUIT 3, PWM MODE
300kHz VOLTAGE POSITIONED,
CIRCUIT 2, PWM MODE
5
10
15
20
25
5
10
15
20
25
5
10
15
20
25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE
LOAD-TRANSIENT RESPONSE
LOAD-TRANSIENT RESPONSE
40
30
20
10
0
300kHz STANDARD APPLICATION, CIRCUIT 1,
PWM MODE
300kHz VOLTAGE POSITIONED,
CIRCUIT 2, PWM MODE
I
+ I
CC DD
A
B
A
B
I+
1000kHz VOLTAGE POSITIONED,
CIRCUIT 5, PWM MODE
10μs/div
5
10
15
20
25
10μs/div
INPUT VOLTAGE (V)
A = V , 50mV/div, AC-COUPLED
OUT
B = INDUCTOR CURRENT, 10A/div
A = V , 50mV/div, AC-COUPLED
OUT
B = INDUCTOR CURRENT, 10A/div
LOAD-TRANSIENT RESPONSE
LOAD-TRANSIENT RESPONSE
LOAD-TRANSIENT RESPONSE
550kHz VOLTAGE POSITIONED, CIRCUIT 3,
PWM MODE
1000kHz +5V, CIRCUIT 4, PWM MODE
1000kHz VOLTAGE POSITIONED, CIRCUIT 5,
PWM MODE
A
B
A
B
A
B
5μs/div
4μs/div
4μs/div
A = V , 50mV/div, AC-COUPLED
OUT
B = INDUCTOR CURRENT, 10A/div
A = V , 50mV/div, AC-COUPLED
OUT
B = INDUCTOR CURRENT, 10A/div
A = V , 50mV/div, AC-COUPLED
OUT
B = INDUCTOR CURRENT, 10A/div
8
_______________________________________________________________________________________
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
Typical Operating Characteristics (continued)
(Circuit of Figure 1, components of Table 1, V+ = +12V, V = V = SKP/SDN = +5V, V = 1.6V, T = +25°C, unless otherwise noted.)
OUT A
DD
CC
STARTUP WAVEFORM
STARTUP WAVEFORM
DYNAMIC OUTPUT VOLTAGE TRANSITION
300kHz VOLTAGE POSITIONED,
CIRCUIT 2, PWM MODE,
NO LOAD
300kHz VOLTAGE POSITIONED,
CIRCUIT 2, I =12A
A
OUT
A
B
A
B
B
C
C
C
D
100μs/div
100μs/div
50μs/div
A = V , 1V/div
OUT
A = V , 1V/div
OUT
300kHz STANDARD APPLICATION, CIRCUIT 1,
B = INDUCTOR CURRENT, 10A/div
B = INDUCTOR CURRENT, 10A/div
PWM MODE, V
= 1.35V TO 1.6V, I
= 0.3A,
OUT
OUT
R
= 120kΩ
C = SKP/SDN, 5V/div
C = SKP/SDN, 5V/div
TIME
A = V , 200mV/div, AC-COUPLED
OUT
B = INDUCTOR CURRENT, 10A/div
C = VGATE, 5V/div
D = A/B, 5V/div
DYNAMIC OUTPUT VOLTAGE TRANSITION
OUTPUT OVERLOAD WAVEFORM
DYNAMIC OUTPUT VOLTAGE TRANSITION
300kHz VOLTAGE POSITIONED, CIRCUIT 2,
PWM MODE
A
B
A
B
A
B
C
D
C
D
20μs/div
40μs/div
50μs/div
A = V , 200mV/div, AC-COUPLED
OUT
A = V , 500mV/div
OUT
300kHz STANDARD APPLICATION, CIRCUIT 1,
B = INDUCTOR CURRENT, 10A/div
C = VGATE, 5V/div
D = A/B, 5V/div
B = INDUCTOR CURRENT, 10A/div
PWM MODE, V
= 1.35V TO 1.6V,
= 120kΩ
OUT
I
= 12A, R
OUT
TIME
A = V , 200mV/div, AC-COUPLED
OUT
1000kHz +5V, CIRCUIT 4,
B = INDUCTOR CURRENT, 10A/div
C = VGATE, 5V/div
PWM MODE, V
= 1.35V TO 1.6V,
OUT
I
= 0.3A, R
= 51kΩ
D = A/B, 5V/div
OUT
TIME
_______________________________________________________________________________________
9
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
Typical Operating Characteristics (continued)
(Circuit of Figure 1, components of Table 1, V+ = +12V, V = V = SKP/SDN = +5V, V = 1.6V, T = +25°C, unless otherwise noted.)
OUT A
DD
CC
SHUTDOWN WAVEFORM
SHUTDOWN WAVEFORM
A
B
A
B
C
C
100μs/div
100μs/div
300kHz VOLTAGE POSITIONED, CIRCUIT 2,
PWM MODE, I = 12A
300kHz VOLTAGE POSITIONED, CIRCUIT 2,
PWM MODE, NO LOAD
OUT
A = V , 1V/div
A = V , 1V/div
OUT
OUT
B = INDUCTOR CURRENT, 10A/div
C = SKP/SDN, 5V/div
B = INDUCTOR CURRENT, 10A/div
C = SKP/SDN, 5V/div
Pin Description
PIN
NAME
FUNCTION
Battery Voltage Sense Connection. Connect V+ to input power source. V+ is used only for PWM one-shot
timing. DH on-time is inversely proportional to input voltage over a range of 2V to 28V.
1
V+
Combined Shutdown and Skip-Mode Control. Drive SKP/SDN to GND for shutdown. Leave SKP/SDN open for
low-noise forced-PWM mode, or drive to V for normal pulse-skipping operation. Low-noise forced-PWM mode
CC
2
causes inductor current recirculation at light loads and suppresses pulse-skipping operation. SKP/SDN can also
be used to disable over/undervoltage protection circuits and clear the fault latch by forcing it to 12V < SKP/SDN
< 15V (with otherwise normal PFM/PWM operation). Do not connect SKP/SDN to > 15V.
SKP/SDN
Slew-Rate Adjustment Pin. Connect a resistor from TIME to GND to set the internal slew-rate clock. A 470kΩ
3
4
TIME
FB
to 47kΩ resistor sets the clock from 38kHz to 380kHz, f
= 150kHz x 120kΩ / R
.
TIME
SLEW
Fast Feedback Input. Connect FB to the junction of the external inductor and output capacitor for nonvolt-
age-positioned circuits (Figure 1). For voltage-positioned circuits, connect FB to the junction of the external
inductor and the positioning resistor (Figure 3).
Feedback Remote-Sense Input. For nonvoltage-positioned circuits, connect FBS to V
directly at the
OUT
load. FBS internally connects to the integrator that fine tunes the DC output voltage. For voltage-positioned
circuits, connect FBS directly to FB near the IC to disable the FBS remote-sense integrator amplifier. To dis-
5
FBS
CC
able all three integrator amplifiers, connect FBS to V
.
CC
Integrator Capacitor Connection. Connect a 100pF to 1000pF (470pF typ) capacitor from CC to GND to set
the integration time constant. CC can be left open if FBS is tied to V
6
7
.
CC
Analog Supply Voltage Input for PWM Core. Connect V
to the system supply voltage (4.5V to 5.5V) with a
CC
V
CC
series 20Ω resistor. Bypass to GND with a 0.22µF (min) capacitor.
±0 ______________________________________________________________________________________
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
Pin Description (continued)
PIN
NAME
FUNCTION
On-Time Selection Control Input. This is a four-level input that sets the K factor (Table 3) to determine
DH on-time. Connect TON to the following pins for the indicated operation:
GND = 1000kHz
REF = 550kHz
Open = 300kHz
8
TON
V
= 200kHz
CC
2V Reference Output. Bypass to GND with 0.22µF (min) capacitor. Can source 50µA for external loads.
Loading REF degrades FB accuracy according to the REF load-regulation error.
9
REF
ILIM
Current-Limit Adjustment. The GND - LX current-limit threshold defaults to 100mV if ILIM is tied to V . In
CC
adjustable mode, the current-limit threshold voltage is 1/10th the voltage seen at ILIM over a 0.5V to 3.0V
10
range. The logic threshold for switchover to the 100mV default value is approximately V
REF for a fixed 200mV threshold.
- 1V. Tie ILIM to
CC
Ground Remote-Sense Input. For nonvoltage-positioned circuits, connect GNDS to ground directly at the
load. GNDS internally connects to the integrator that fine tunes the output voltage. The output voltage rises
by an amount of GNDS - GND. For voltage-positioned circuits, increase the output voltage (24mV (typ)) by
biasing GNDS with a resistor-divider from REF to GND.
11
12
GNDS
Open-Drain Power-Good Output. VGATE is normally high when the output is in regulation. VGATE goes low
whenever the DAC code changes, and returns high one clock period after the slew-rate controller finishes
and the output is in regulation. VGATE is low in shutdown.
VGATE
13
14
15
GND
DL
Analog and Power Ground. Also connects to the current-limit comparator.
Low-Side Gate Driver Output. DL swings GND to V
.
DD
V
Supply Voltage Input for the DL Gate Driver, 4.5V to 5.5V. Bypass to GND with a 1µF capacitor.
DD
Internal MUX Select Input. When A/B is high, the DAC code is determined by logic-level voltages on D0–D4.
On the falling edge of A/B (or during power-up with A/B low), the DAC code is determined by the resistor
values at D0–D4.
16
17–21
22
A/B
D4–D0
BST
DAC Code Inputs. D0 is the LSB and D4 is the MSB for the internal 5-bit DAC (see Table 4). When A/B is
high, D0–D4 function as high-input-impedance logic inputs. On the falling edge of A/B (or during power-up
with A/B low), the series resistance on each input sets its logic state as follows:
(series resistance ≤ 1kΩ 5%) = logic low
(series resistance ≥ 100kΩ 5%) = logic high
Boost Flying Capacitor Connection. Connect BST to the external boost diode and capacitor as shown in the
Standard Application Circuit. An optional resistor in series with BST allows the DH pullup current to be
adjusted (Figure 5).
Inductor Connection. LX is the internal lower supply rail for the DH high-side gate driver. It also connects to
the current-limit comparator and the skip-mode zero-crossing comparator.
23
24
LX
DH
High-Side Gate-Driver Output. DH swings LX to BST.
______________________________________________________________________________________ ±±
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
V
BATT
7V TO 24V
+5V
BIAS SUPPLY
C5
1μF
C6
1μF
R1
20Ω
C1
4 x10μF, 25V
15
7
D2
CMPSH-3
V
V
DD
CC
1
2
22
24
V+
BST
DH
ON/OFF
CONTROL
SKP/SDN
Q1
L1
R7
V
OUT
1μH
120kΩ
3
C7
0.1μF
A/B = LOW = 1.60V
A/B = HIGH = 1.35V
TIME
C2
21
20
19
TO V
CC
23
14
13
6 x 470μF
KEMET T510
D0
D1
D2
D3
MAX1717
LX
DL
D1
Q2
100kΩ
18
17
8
GND
D4
C4
1μF
TON
REF
9
4
FB
FBS
5
6
11
CC
GNDS
+5V
C3
470pF
R2
100kΩ
16
A/B
HIGH/LOW
Q1 = IRF7811
Q2 = 2 x IRF7805
D1 = INTL RECT 10MQ040N
C1 = TAIYO YUDEN TMK432BJ106KM
C2 = KEMET T510X477M006
L1 = SUMIDA CEP125
12
POWER-GOOD
INDICATOR
ILIM VGATE
10
TO V
CC
Figure 1. Standard Application Circuit
±2 ______________________________________________________________________________________
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
Table ±. Component Selection for Standard Applications
300kHz, STANDARD 300kHz, ꢀOLTAGE 550kHz, ꢀOLTAGE
±000kHz, ꢀOLTAGE
POSITIONED,
CIRCUIT 5
±000kHz, +5ꢀ,
CIRCUIT 4
COMPONENT
APPLICATION,
CIRCUIT ±
POSITIONED,
CIRCUIT 2
POSITIONED,
CIRCUIT 3
Figure Number
Input Range
1
3
3
3
3
7V to 24V
7V to 24V
7V to 24V
4.5V to 5.5V
7V to 24V
(V
)
BATT
Output Current
Frequency
14A
14A
14A
14A
14A
300kHz
300kHz
550kHz
1000kHz
1000kHz
High-Side MOSFET
Q1
International
Rectifier IRF7811
International
Rectifier IRF7811
International
Rectifier IRF7811
International
Rectifier IRF7811
International
Rectifier IRF7811
(2) International
Rectifier IRF7805,
IRF7811, or
(2) International
Rectifier IRF7805,
IRF7811, or
(2) International
Rectifier IRF7805,
IRF7811, or
(2) International
Rectifier IRF7805,
IRF7811, or
(2) International
Rectifier IRF7805,
IRF7811, or
Low-Side MOSFET
Q2
IRF7811A
IRF7811A
IRF7811A
IRF7811A
IRF7811A
(4) 10µF, 25V
ceramic
Taiyo Yuden
TMK432BJ106KM
(4) 10µF, 25V
ceramic
Taiyo Yuden
TMK432BJ106KM
(4) 10µF, 25V
ceramic
Taiyo Yuden
TMK432BJ106KM
(5) 22µF, 10V
ceramic
Taiyo Yuden
LMK432BJ226KM
(4) 10µF, 25V
ceramic
Taiyo Yuden
TMK432BJ106KM
Input Capacitor
C1
(5) 220µF, 2.5V,
25mΩ specialty
polymer
Panasonic
EEFUE0E221R
(4) 220µF, 2.5V,
25mΩ specialty
polymer
Panasonic
EEFUE0E221R
(6) 470µF, 6.3V
tantalum
Kemet
(5) 47µF, 6.3V
ceramic
Taiyo Yuden
JMK432BJ476MM
(5) 47µF, 6.3V
ceramic
Taiyo Yuden
JMK432BJ476MM
Output Capacitor
C2
T510X477M006AS
1µH
Sumida
1µH
Sumida
0.3µH
Sumida
CEP12D38 4713-
T001
0.47µH
Sumida
CEP125-4712-T006
0.19µH
Coilcraft
X8357-A
Inductor
L1
CEP125-1R0MC or CEP125-1R0MC or
Panasonic
ETQP6F1R1BFA
Panasonic
ETQP6F1R1BFA
Voltage-
Positioning
Resistor R6
5mΩ 1%, 1W
Dale
WSL-2512-R005F
5mΩ 1%, 1W
Dale
WSL-2512-R005F
5mΩ 1%, 1W
Dale
WSL-2512-R005F
5mΩ 1%, 1W
Dale
WSL-2512-R005F
—
Voltage-
Positioning Offset
—
24mV
Float
24mV
REF
24mV
GND
24mV
GND
TON Level
Float
______________________________________________________________________________________ ±3
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
the low-side switch current is below the current-limit
threshold, and the minimum off-time one-shot has timed
out.
Table 2. Component Suppliers
FACTORY FAX
[Country Code]
MANUFACTURER
USA PHONE
Coilcraft
847-639-6400 [1] 847-639-1469
402-564-3131 [1] 402-563-6418
310-322-3331 [1] 310-322-3332
408-986-0424 [1] 408-986-1442
714-373-7939 [1] 714-373-7183
847-956-0666 [81] 3-3607-5144
408-573-4150 [1] 408-573-4159
On-Time One-Shot (TON)
The heart of the PWM core is the one-shot that sets the
high-side switch on-time. This fast, low-jitter, adjustable
one-shot includes circuitry that varies the on-time in
response to battery and output voltage. The high-side
switch on-time is inversely proportional to the battery
voltage as measured by the V+ input, and proportional
to the output voltage. This algorithm results in a nearly
constant switching frequency despite the lack of a
fixed-frequency clock generator. The benefits of a con-
stant switching frequency are twofold: first, the frequency
can be selected to avoid noise-sensitive regions such
as the 455kHz IF band; second, the inductor ripple-cur-
rent operating point remains relatively constant, resulting
in easy design methodology and predictable output
voltage ripple.
Dale-Vishay
International Rectifier
Kemet
Panasonic
Sumida
Taiyo Yuden
Detailed Description
+5V Bias Supply (V
CC
and V
)
DD
The MAX1717 requires an external +5V bias supply in
addition to the battery. Typically, this +5V bias supply
is the notebook’s 95% efficient +5V system supply.
Keeping the bias supply external to the IC improves
efficiency and eliminates the cost associated with the
+5V linear regulator that would otherwise be needed to
supply the PWM circuit and gate drivers. If stand-alone
capability is needed, the +5V supply can be generated
with an external linear regulator.
On-Time = K (V
+ 0.075V) / V
IN
OUT
where K is set by the TON pin-strap connection and
0.075V is an approximation to accommodate the expect-
ed drop across the low-side MOSFET switch (Table 3).
The +5V bias supply must provide V
troller) and V
current drawn is:
(PWM con-
CC
The on-time one-shot has good accuracy at the operating
points specified in the Electrical Characteristics ( 10% at
200kHz and 300kHz, 12% at 550kHz and 1000kHz).
On-times at operating points far removed from the condi-
tions specified in the Electrical Characteristics can vary
over a wide range. For example, the 1000kHz setting will
typically run about 10% slower with inputs much greater
than +5V due to the very short on-times required.
(gate-drive power), so the maximum
DD
I
= I
+ f (Q + Q ) = 10mA to 40mA (typ)
CC G1 G2
BIAS
where I
and Q
is 700µA (typ), f is the switching frequency,
are the MOSFET data sheet total
CC
G1
and Q
G2
gate-charge specification limits at V = 5V.
GS
V+ and V
can be tied together if the input power
DD
On-times translate only roughly to switching frequencies.
The on-times guaranteed in the Electrical Character-
istics are influenced by switching delays in the external
high-side MOSFET. Resistive losses, including the
inductor, both MOSFETs, output capacitor ESR, and PC
board copper losses in the output and ground tend to
raise the switching frequency at higher output currents.
source is a fixed +4.5V to +5.5V supply. If the +5V bias
supply is powered up prior to the battery supply, the
enable signal (SKP/SDN going from low to high or
open) must be delayed until the battery voltage is pre-
sent to ensure startup.
Free-Running, Constant On-Time PWM
Controller with Input Feed-Forward
Table 3. Approximate K-Factors Errors
The Quick-PWM control architecture is a pseudofixed-
frequency, constant-on-time current-mode type with volt-
age feed-forward (Figure 2). This architecture relies on
the output filter capacitor’s ESR to act as the current-
sense resistor, so the output ripple voltage provides the
PWM ramp signal. The control algorithm is simple: the
high-side switch on-time is determined solely by a one-
shot whose period is inversely proportional to input volt-
age and directly proportional to output voltage. Another
one-shot sets a minimum off-time (400ns typ). The on-
time one-shot is triggered if the error comparator is low,
TON
K
APPROXIMATE MIN RECOMMENDED
SETTING FACTOR K-FACTOR
V
AT V
= 1.6V
OUT
BATT
(kHz)
200
(μs)
5
ERROR (%)
(V)
10
10
2.1
2.3
3.2
4.5
300
3.3
1.8
1.0
550
12.5
12.5
1000
14 ______________________________________________________________________________________
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
V
BATT
2V TO 28V
REF
V+
I
LIM
MAX1717
TOFF
+5V
1-SHOT
TON
FROM
D/A
ON-TIME
COMPUTE
TRIG
Q
9
BST
1
TON
S
R
Q
Q
TRIG
DH
LX
CURRENT
LIMIT
1-SHOT
Σ
ERROR
AMP
OUTPUT
SKP/SDN
CC
ZERO CROSSING
REF
10k
V
+5V
DD
70k
DL
REF
S
R
Q
GND
g
g
g
m
m
m
FB
GNDS
FBS
FB
REF
+12%
REF
-7%
CHIP SUPPLY
V
CC
+5V
OVP/UVP
DETECT
VGATE
R-2R
2V
REF
REF
D/A CONVERTER
MUX AND SLEW CONTROL
D0 D1 D2 D3
A/B
D4
TIME
120k
Figure 2. Functional Diagram
______________________________________________________________________________________ 15
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
The dead-time effect increases the effective on-time,
reducing the switching frequency. It occurs only in
PWM mode (SKP/SDN = open) and dynamic output
voltage transitions when the inductor current reverses
at light or negative load currents. With reversed inductor
current, the inductor’s EMF causes LX to go high earlier
than normal, extending the on-time by a period equal to
the DH-rising dead time.
load-transient response. The fastest transient response
is achieved when all three integrators are disabled.
This can work very well if the MAX1717 circuit is placed
very close to the CPU.
All three integrators can be disabled by connecting
FBS to V . When the integrators are disabled, CC can
CC
be left unconnected, which eliminates a component,
but leaves GNDS connected to any convenient ground.
When the inductor is in continuous conduction, the output
voltage will have a DC regulation higher than the trip
level by 50% of the ripple. In discontinuous conduction
(SKP/SDN open, light-loaded), the output voltage will
have a DC regulation higher than the trip level by
approximately 1.5% due to slope compensation.
For loads above the critical conduction point, where the
dead-time effect is no longer a factor, the actual switching
frequency is:
f = (V
+ V
) / t
(V + V
- V
)
DROP2
OUT
DROP1
ON IN
DROP1
where V
is the sum of the parasitic voltage drops
DROP1
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; V is
the sum of the parasitic voltage drops in the inductor
charge path, including high-side switch, inductor, and
There is often a connector, or at least many milliohms of
PC board trace resistance, between the DC-DC con-
verter and the CPU. In these cases, the best strategy is
to place most of the bulk bypass capacitors close to
the CPU, with just one capacitor on the other side of the
connector near the MAX1717 to control ripple if the
CPU card is unplugged. In this situation, the remote-
sense lines (GNDS and FBS) and integrators provide a
real benefit.
DROP2
PC board resistances; t
the MAX1717.
is the on-time calculated by
ON
Integrator Amplifiers
Three integrator amplifiers provide a fine adjustment to
the output regulation point. One amplifier integrates the
difference between GNDS and GND, a second inte-
grates the difference between FBS and FB. The third
amplifier integrates the difference between REF and the
DAC output. These three transconductance amplifiers’
outputs are directly summed inside the chip, so the
integration time constant can be set easily with one
When operating the MAX1717 in a voltage-positioned
circuit (Figure 3), GNDS can be offset with a resistor
divider from REF to GND, which causes the GNDS inte-
grator to increase the output voltage by 90% of the
applied offset (27mV typ). A low-value (5mΩ typ) voltage-
positioning resistor is added in series between the
external inductor and the output capacitor. FBS is con-
nected to FB directly at the junction of the external
inductor and the voltage-positioning resistor. The net
effect of these two changes is an output voltage that is
slightly higher than the programmed DAC voltage at
light loads, and slightly less than the DAC voltage at
full-load current. For further information on voltage-posi-
tioning, see the Applications section.
capacitor. The g of each amplifier is 160µS (typ).
m
The integrator block has the ability to lower the output
voltage by 2% and raise it by 6%. For each amplifier, the
differential input voltage range is at least 70mV total,
including DC offset and AC ripple. The integrator corrects
for approximately 90% of the total error, due to finite gain.
The FBS amplifier corrects for DC voltage drops in PC
board traces and connectors in the output bus path
between the DC-DC converter and the load. The GNDS
amplifier performs a similar DC correction task for the
output ground bus. The third integrator amplifier cor-
rects the small offset of the error amplifier and provides
Automatic Pulse-Skipping Switchover
In skip mode (SKP/SDN high), an inherent automatic
switchover to PFM takes place at light loads (Figure 4).
This switchover is effected by a comparator that trun-
cates the low-side switch on-time at the inductor current’s
zero crossing. This mechanism causes the threshold
between pulse-skipping PFM and nonskipping PWM
operation to coincide with the boundary between con-
tinuous and discontinuous inductor-current operation
(see the Continuous-to-Discontinuous Inductor Current
Point graph in the Typical Operating Characteristics).
an averaging function that forces V
to be regulated
OUT
at the average value of the output ripple waveform.
Integrators have both beneficial and detrimental char-
acteristics. Although they correct for drops due to DC
bus resistance and tighten the DC output voltage toler-
ance limits by averaging the peak-to-peak output ripple,
they can interfere with achieving the fastest possible
16 ______________________________________________________________________________________
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
V
BATT
+5V
BIAS SUPPLY
C5
1μF
C6
1μF
R1
20Ω
C1
15
7
D2
CMPSH-3
V
DD
V
CC
1
2
22
24
V+
BST
DH
ON/OFF
CONTROL
SKP/SDN
Q1
Q2
L1
1μH
R6
0.005Ω
R7
120kΩ
V
OUT
A/B = LOW = 1.60V
A/B = HIGH = 1.35V
3
C7
0.1μF
TIME
C2
21
20
19
23
14
13
TO V
D0
D1
D2
D3
MAX1717
CC
LX
DL
D1
100kΩ
18
17
8
GND
D4
C4
1μF
TON
REF
9
4
FB
FBS
R4
2kΩ
5
6
11
CC
GNDS
+5V
C3
470pF
R5
150kΩ
R2
100kΩ
16
HIGH/LOW
A/B
TO V
REF
12
POWER-GOOD
INDICATOR
ILIM VGATE
10
D1 = INTL RECT 10MQ040N.
FOR OTHER COMPONENTS,
SEE TABLE 1 VALUES.
TO V
CC
Figure 3. Voltage-Positioned Circuit
For a battery range of 7V to 24V, this threshold is rela-
tively constant, with only a minor dependence on bat-
tery voltage:
The crossover point occurs at an even lower value if a
swinging (soft-saturation) inductor is used.
The switching waveforms may appear noisy and asyn-
chronous when light loading causes pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs in PFM
noise vs. light-load efficiency are made by varying the
inductor value. Generally, low inductor values produce
a broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the
coil resistance remains fixed) and less output voltage
ripple. Penalties for using higher inductor values
include larger physical size and degraded load-tran-
sient response (especially at low input voltage levels).
K × V
V
− V
OUT
BATT OUT
I
≈
×
LOAD(SKIP)
2
×
L
V
BATT
where K is the on-time scale factor (Table 3). The load-
current level at which PFM/PWM crossover occurs,
I
, is equal to 1/2 the peak-to-peak ripple cur-
LOAD(SKIP)
rent, which is a function of the inductor value (Figure 4).
For example, in the standard application circuit this
becomes:
3.3μs × 1.6V
× 1μH
12V − 1.6V
×
= 2.3A
2
12V
______________________________________________________________________________________ 17
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
-I
PEAK
Δi
Δt
V
- V
BATT OUT
=
L
-I
PEAK
I
LOAD
I
= I
/2
LOAD PEAK
I
LIMIT
0
ON-TIME
TIME
0
TIME
Figure 4. Pulse-Skipping/Discontinuous Crossover Point
Figure 5. “Valley” Current-Limit Threshold Point
rent. The negative current-limit threshold is set to approxi-
mately 120% of the positive current limit, and therefore
tracks the positive current limit when ILIM is adjusted.
Forced-PWM Mode (SKP/SDN Open)
The low-noise forced-PWM mode (SKP/SDN open) dis-
ables the zero-crossing comparator that controls the
low-side switch on-time. This causes the low-side gate-
drive waveform to become the complement of the high-
side gate-drive waveform. This in turn causes the
inductor current to reverse at light loads as the PWM
The current-limit threshold is adjusted with an external
resistor-divider at ILIM. The current-limit threshold
adjustment range is from 50mV to 300mV. In the
adjustable mode, the current-limit threshold voltage is
precisely 1/10th the voltage seen at ILIM. The threshold
loop strives to maintain a duty ratio of V
/V
. The
OUT BATT
benefit of forced-PWM mode is to keep the switching
frequency fairly constant, but it comes at a cost: the no-
load battery current can be 10mA to 40mA, depending
on the external MOSFETs and switching frequency.
defaults to 100mV when ILIM is connected to V . The
CC
logic threshold for switchover to the 100mV default
value is approximately V
- 1V.
CC
The adjustable current limit accommodates MOSFETs
with a wide range of on-resistance characteristics (see
the Design Procedure section).
Forced-PWM mode is most useful for reducing audio-
frequency noise and improving the cross-regulation of
multiple-output applications that use a flyback trans-
former or coupled inductor.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors don’t corrupt the cur-
rent-sense signals seen by LX and GND. Place the IC
close to the low-side MOSFET with short, direct traces,
making a Kelvin sense connection to the source and
drain terminals.
Current-Limit Circuit
The current-limit circuit employs a unique “valley” current-
sensing algorithm that uses the on-resistance of the
low-side MOSFET as a current-sensing element. If the
current-sense signal is above the current-limit thresh-
old, the PWM is not allowed to initiate a new cycle
(Figure 5). The actual peak current is greater than the
current-limit threshold by an amount equal to the induc-
tor ripple current. Therefore, the exact current-limit
characteristic and maximum load capability are a func-
tion of the MOSFET on-resistance, inductor value, and
battery voltage. The reward for this uncertainty is
robust, lossless overcurrent sensing. When combined
with the undervoltage protection circuit, this current-
limit method is effective in almost every circumstance.
MOSFET Gate Drivers (DH, DL)
The DH and DL drivers are optimized for driving mod-
erate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in the notebook CPU environment, where a large
V
- V
differential exists. An adaptive dead-time
OUT
BATT
circuit monitors the DL output and prevents the high-
side FET from turning on until DL is fully off. There must
be a low-resistance, low-inductance path from the DL
driver to the MOSFET gate for the adaptive dead-time cir-
cuit to work properly. Otherwise, the sense circuitry in the
MAX1717 will interpret the MOSFET gate as “off” while
there is actually still charge left on the gate. Use very
There is also a negative current limit that prevents exces-
sive reverse inductor currents when V
is sinking cur-
OUT
18 ______________________________________________________________________________________
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
short, wide traces measuring 10 to 20 squares (50 to 100
Shutdown
When SKP/SDN goes low, the MAX1717 goes into low-
power shutdown mode. VGATE goes low immediately.
The output voltage ramps down to 0 in 25mV steps at
mils wide if the MOSFET is 1 inch from the MAX1717).
The dead time at the other edge (DH turning off) is
determined by a fixed 35ns (typ) internal delay.
the clock rate set by R
. When the DAC reaches the
TIME
The internal pull-down transistor that drives DL low is
robust, with a 0.5Ω typical on-resistance. This helps
prevent DL from being pulled up during the fast rise-
time of the inductor node, due to capacitive coupling
from the drain to the gate of the low-side synchronous-
rectifier MOSFET. However, for high-current applications,
you might still encounter some combinations of high-
and low-side FETs that will cause excessive gate-drain
coupling, which can lead to efficiency-killing, EMI-
producing shoot-through currents. This is often remedied
by adding a resistor in series with BST, which increases
the turn-on time of the high-side FET without degrading
the turn-off time (Figure 6).
0V setting, DL goes high, DH goes low, the reference is
turned off, and the supply current drops to about 2µA.
When SKP/SDN goes high or floats, the reference pow-
ers up, and after the reference UVLO is passed, the
DAC target is evaluated and switching begins. The
slew-rate controller ramps up from zero in 25mV steps
to the currently selected code value (based on A/B).
There is no traditional soft-start (variable current limit)
circuitry, so full output current is available immediately.
VGATE goes high after the slew-rate controller has ter-
minated and the output voltage is in regulation. As soon
as VGATE goes high, full power is available.
UVLO
POR
If the V
voltage drops low enough to trip the UVLO
CC
Power-on reset (POR) occurs when V
rises above
CC
comparator, it is assumed that there is not enough supply
voltage to make valid decisions. To protect the output
from overvoltage faults, DL is forced high in this mode.
This will force the output to GND, but it will not use the
slew-rate controller. This results in large negative
inductor current and possibly small negative output
is likely to drop in this fashion, the output
can be clamped with a Schottky diode to GND to
reduce the negative excursion.
approximately 2V, resetting the fault latch and preparing
the PWM for operation. V undervoltage lockout
(UVLO) circuitry inhibits switching, forces VGATE low,
and forces the DL gate driver high (to enforce output
rises above 4.2V, the
DAC inputs are sampled and the output voltage begins
to slew to the DAC setting.
CC
overvoltage protection). When V
CC
voltages. If V
CC
For automatic startup, the battery voltage should be
present before V . If the MAX1717 attempts to bring
CC
the output into regulation without the battery voltage
present, the fault latch will trip. The SKP/SDN pin can
be toggled to reset the fault latch.
DAC Inputs D0–D4
The digital-to-analog converter (DAC) programs the
output voltage. It typically receives a preset digital
code from the CPU pins, which are either hard-wired to
GND or left open-circuit. They can also be driven by
digital logic, general-purpose I/O, or an external mux.
Do not leave D0–D4 floating—use 1MΩ or less pull-ups
if the inputs may float. D0–D4 can be changed while
the SMPS is active, initiating a transition to a new output
voltage level. If this mode of DAC control is used, connect
A/B high. Change D0–D4 together, avoiding greater
than 1µs skew between bits. Otherwise, incorrect DAC
readings may cause a partial transition to the wrong
voltage level, followed by the intended transition to the
correct voltage level, lengthening the overall transition
time. The available DAC codes and resulting output
voltages (Table 4) are compatible with Intel’s mobile
Pentium® IIIspecification.
+5V
V
BATT
5Ω TYP
BST
DH
LX
MAX1717
Figure 6. Reducing the Switching-Node Rise Time
Pentium is a registered trademark of Intel Corp.
______________________________________________________________________________________ 19
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
A/B Internal Mux
Table 4. Output Voltage vs. DAC Codes
The MAX1717 contains an internal mux that can be used
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V
(V)
OUT
to select one of two programmed DAC codes and output
voltages. The internal mux is controlled with the A/B pin,
which selects between the A mode and the B mode. In
the A mode, the voltage levels on D0–D4 select the out-
put voltage according to Table 4. Do not leave D0–D4
floating; there are no internal pull-up resistors.
2.00
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.30
The B mode is programmed by external resistors in
series with D0–D4, using a unique scheme that allows
two sets of data bits using only one set of pins (Figure
7). When A/B goes low (or during power-up with A/B
low), D0–D4 are tested to see if there is a large resis-
tance in series with the pin. If the voltage level on the
pin is a logic low, an internal switch connects the pin to
an internal 40kΩ pull-up for about 4µs to see if the pin
voltage can be forced high (Figure 8). If the pin voltage
cannot be pulled to a logic high, the pin is considered
low impedance and its B-mode logic state is low. If the
pin can be pulled to a logic high, the impedance is
considered high and so is the B-mode logic state.
Similarly, if the voltage level on the pin is a logic high,
an internal switch connects the pin to an internal 8kΩ
pull-down to see if the pin voltage can be forced low. If
so, the pin is high-impedance and its B-mode logic
state is high. Otherwise, its logic state is low.
No CPU
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
No CPU
A high pin impedance (and logic high) is 100kΩ or
greater, and a low impedance (and logic low) is 1kΩ or
less. The Electrical Characteristics guaranteed levels for
these impedances are 95kΩ and 1.05kΩ to allow the use
of standard 100kΩ and 1kΩ resistors with 5% tolerance.
If the output voltage codes are fixed at PC board
design time, program both codes with a simple combi-
nation of pin-strap connections and series resistors
(Figure 7). If the output voltage codes are chosen dur-
ing PC board assembly, both codes can be indepen-
dently programmed with resistors (Figure 9). This
matrix of 10 resistor-footprints can be programmed to all
possible A-mode and B-mode code combinations with
only five resistors.
Often, one or more output-voltage codes are provided
directly by the CPU’s VID pins. If the CPU actively dri-
ves these pins, connect A/B high (A mode) and let the
CPU determine the output voltages. If the B mode is
needed for startup or other reasons, insert resistors in
series with D0–D4 to program the B-mode voltage. Be
sure that the VID pins are actively driven at all times.
Note: In the no-CPU state, DH and DL are held low and the
slew-rate controller is set for 0.9V.
processor’s VID pins can be used for the A-mode set-
ting, together with suitable pull-up resistors. However,
the B-mode VID code is set with resistors in series with
D0–D4, and in order for the B-mode to work, any pins
intended to be B-mode logic low must appear to be low
impedance, at least for the 4µs sampling interval.
If the CPU’s VID pins float, the open-circuit pins can
present a problem for the MAX1717’s internal mux. The
20 ______________________________________________________________________________________
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
This can be achieved in several ways, including the fol-
lowing two (Figure 10). By using low-impedance pull-up
resistors with the CPU’s VID pins, each pin provides the
low impedance needed for the mux to correctly inter-
pret the B-mode setting. Unfortunately, the low resis-
tances cause several mA additional quiescent current
for each of the CPU’s grounded VID pins. This quies-
cent current can be avoided by taking advantage of the
fact that D0–D4 need only appear low impedance
briefly, not necessarily on a continuous DC basis. High-
impedance pull-ups can also be used if they are
bypassed with a large enough capacitance to make
them appear low impedance for the 4µs sampling inter-
val. As noted in Figure 10, 4.7nF capacitors allow the
inputs to appear low impedance even though they are
pulled up with 1MΩ resistors.
3V TO 5.5V
MAX1717
D4
D3
D2
D1
D0
100kΩ
A-MODE VID =
01101 → 1.35V
A/B
B-MODE VID =
01000 → 1.60V
A/B = LOW = 1.60V
A/B = HIGH = 1.35V
Figure 7. Using the Internal Mux with Hard-Wired A-Mode and
B-Mode DAC Codes
+5V
V
CC
MAX1717
3V TO 5.5V
40kΩ
40kΩ
40kΩ 40kΩ
40kΩ
D4
100kΩ
D3
D2
D1
D0
B-DATA
LATCH
8kΩ
8kΩ
8kΩ
8kΩ
8kΩ
GND
Figure 8. Internal Mux B-Mode Data Test and Latch
______________________________________________________________________________________ 21
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
2.7V TO 5.5V
1kΩ
1kΩ
100kΩ
MAX1717
D4
D3
D2
D1
D0
A/B
1kΩ
1kΩ
A/B = LOW = 1.60V
A/B = HIGH = 1.35V
NOTE: USE PULLUP FOR A-MODE 1, PULLDOWN FOR A-MODE 0.
USE ≥ 100kΩ FOR B-MODE 1, ≤ 1kΩ FOR B-MODE 0.
Figure 9. Using the Internal Mux with Both VID Codes Resistor Programmed
additional slew-rate clock period has passed. The slew-
rate clock frequency (set by resistor R ) must be set
fast enough to ensure that VGATE goes high within the
allowed 100µs. Alternatively, the slew-rate clock can be
set faster than necessary and VGATE’s rising edge can
be detected so that normal system operation can
resume even earlier.
Output Voltage Transition Timing
The MAX1717 is designed to perform output voltage
transitions in a controlled manner, automatically mini-
mizing input surge currents. This feature allows the cir-
cuit designer to achieve nearly ideal transitions,
guaranteeing just-in-time arrival at the new output volt-
age level with the lowest possible peak currents for a
given output capacitance. This makes the IC very suit-
able for CPUs featuring SpeedStep technology and
other ICs that operate in two or more modes with differ-
ent core voltage levels.
TIME
The output voltage transition is performed in 25mV
steps, preceded by a 4µs delay and followed by one
additional clock period after which VGATE goes high if
the output voltage is in regulation. The total time for a
transition depends on R
, the voltage difference,
Intel’s mobile Pentium III CPU with SpeedStep technol-
ogy operates at two distinct clock frequencies and
requires two distinct core voltages. When transitioning
from one clock frequency to the other, the CPU first
goes into a low-power state, then the output voltage
and clock frequency are changed. The change must
be accomplished in 100µs or the system may halt.
TIME
and the accuracy of the MAX1717’s slew-rate clock,
and is not dependent on the total output capacitance.
The greater the output capacitance, the higher the
surge current required for the transition. The MAX1717
will automatically control the current to the minimum
level required to complete the transition in the calculat-
ed time, as long as the surge current is less than the
current limit set by ILIM.
At the beginning of an output voltage transition, the
MAX1717 brings the VGATE output low, indicating that
a transition is beginning. VGATE remains low during the
transition and goes high when the slew-rate controller
has set the internal DAC to the final value and one
22 ______________________________________________________________________________________
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
3.15 TO 5.5V
*OPTIONAL
4.7nF
1MΩ
1kΩ
1kΩ
1kΩ
1kΩ
1kΩ
MAX1717
D4
D3
D2
D1
D0
100kΩ
CPU
A/B
A/B = LOW = 1.60V
A/B = HIGH = 1.35V
CPU VID =
01101 → 1.35V
(A-MODE)
B-MODE VID =
01000 → 1.6V
*TO REDUCE QUIESCENT CURRENT, 1kΩ PULLUP RESISTORS CAN BE REPLACED BY 1MΩ RESISTORS WITH 4.7nF CAPACATORS IN PARALLEL.
Figure 10. Using the Internal Mux with CPU Driving the A-Mode VID Code
The transition time is given by:
is then latched high until SKP/SDN is toggled or V
CC
power is cycled below 1V. This action turns on the syn-
chronous-rectifier MOSFET with 100% duty and, in turn,
rapidly discharges the output filter capacitor and forces
the output to ground. If the condition that caused the
overvoltage (such as a shorted high-side MOSFET)
persists, the battery fuse will blow. DL is also kept high
⎡
⎢
⎤
⎥
⎛
⎞
V
− V
NEW
1
OLD
≤ 4μs +
1+
⎜
⎟
⎢
⎥
f
25mV
⎝
⎠
SLEW
⎣
⎦
where f
= 150kHz x 120kΩ / R
original output voltage, and V
age. See Time Frequency Accuracy in the Electrical
Characteristics for f accuracy.
, V
is the
TIME
OLD
SLEW
is the new output volt-
NEW
continuously when V
UVLO is active, as well as in
CC
shutdown mode (Table 5).
SLEW
Overvoltage protection can be defeated through the
NO FAULT test mode (see the NO FAULT Test Mode
section).
The practical range of R
is 47kΩ to 470kΩ, corre-
TIME
sponding to 2.6µs to 26µs per 25mV step. Although the
DAC takes discrete 25mV steps, the output filter makes
the transitions relatively smooth. The average inductor
current required to make an output voltage transition is:
Output Undervoltage Shutdown
The output UVP function is similar to foldback current
limiting, but employs a timer rather than a variable cur-
rent limit. If the MAX1717 output voltage is under 70% of
the nominal value, the PWM is latched off and won’t
I ≅ C
L
x 25mV x f
SLEW
OUT
Output Overvoltage Protection
The overvoltage protection (OVP) circuit is designed to
protect against a shorted high-side MOSFET by draw-
ing high current and blowing the battery fuse. The out-
put voltage is continuously monitored for overvoltage. If
the output is more than 2.25V, OVP is triggered and the
circuit shuts down. The DL low-side gate-driver output
restart until V
power is cycled or SKP/SDN is tog-
CC
gled. To allow startup, UVP is ignored during the under-
voltage fault-blanking time (the first 256 cycles of the
slew rate after startup).
UVP can be defeated through the NO FAULT test mode
(see the NO FAULT Test Mode section).
______________________________________________________________________________________ 23
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
Table 5. Operating Mode Truth Table
DL
MODE
COMMENT
Low-power shutdown state. DL is forced to V , enforcing
SKP/SDN
DD
GND
High
Shutdown
OVP. I
+ I
= 2µA (typ).
CC
DD
Test mode with faults disabled and fault latches cleared, includ-
ing thermal shutdown. Otherwise, normal operation, with auto-
matic PWM/PFM switchover for pulse-skipping at light loads.
12V to 15V
Float
Switching
No Fault
Low-noise operation with no automatic switchover. Fixed-
frequency PWM action is forced regardless of load. Inductor
current reverses at light load levels.
Switching
Switching
High
Run (PWM, low noise)
Run (PFM/PWM,
normal operation)
Normal operation with automatic PWM/PFM switchover for
pulse-skipping at light loads.
V
CC
Fault latch has been set by OVP, UVP, or thermal shutdown.
Device will remain in FAULT mode until V power is cycled or
V
or Float
Fault
CC
CC
SKP/SDN is forced low.
MOSFETs, and other critical heat-contributing com-
ponents. Modern notebook CPUs generally exhibit
LOAD
NO FAULT Test Mode
The over/undervoltage protection features can compli-
cate the process of debugging prototype breadboards
since there are (at most) a few milliseconds in which to
determine what went wrong. Therefore, a test mode is
provided to disable totally the OVP, UVP, and thermal
shutdown features, and clear the fault latch if it has
been set. The PWM operates as if SKP/SDN were high
(SKIP mode). The NO FAULT test mode is entered by
forcing 12V to 15V on SKP/SDN.
I
= I
x 80%.
LOAD(MAX)
3) Switching Frequency. This choice determines the
basic trade-off between size and efficiency. The opti-
mal frequency is largely a function of maximum input
voltage, due to MOSFET switching losses that are pro-
2
portional to frequency and V . The optimum frequen-
IN
cy is also a moving target, due to rapid improvements
in MOSFET technology that are making higher frequen-
cies more practical.
Design Procedure
4) Inductor Operating Point. This choice provides trade-
offs between size vs. efficiency. Low inductor values
cause large ripple currents, resulting in the smallest
size, but poor efficiency and high output noise. The
minimum practical inductor value is one that causes
the circuit to operate at the edge of critical conduction
(where the inductor current just touches zero with
every cycle at maximum load). Inductor values lower
than this grant no further size-reduction benefit.
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switch-
ing frequency and inductor operating point, and the fol-
lowing four factors dictate the rest of the design:
1) Input Voltage Range. The maximum value (V
)
IN(MAX)
must accommodate the worst-case high AC adapter
voltage. The minimum value (V ) must account
IN(MIN)
The MAX1717’s pulse-skipping algorithm initiates
skip mode at the critical conduction point. So, the
inductor operating point also determines the load-
current value at which PFM/PWM switchover occurs.
The optimum point is usually found between 20%
and 50% ripple current.
for the lowest battery voltage after drops due to con-
nectors, fuses, and battery selector switches. If there
is a choice at all, lower input voltages result in better
efficiency.
2) Maximum Load Current. There are two values to con-
sider. The peak load current (I
) deter-
LOAD(MAX)
5) The inductor ripple current also impacts transient-
mines the instantaneous component stresses and
filtering requirements, and thus drives output capaci-
tor selection, inductor saturation rating, and the
design of the current-limit circuit. The continuous load
response performance, especially at low V - V
IN
OUT
differentials. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load
step.
current (I
) determines the thermal stresses and
thus drives the selection of input capacitors,
LOAD
24 ______________________________________________________________________________________
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
The amount of output sag is also a function of the
maximum duty factor, which can be calculated from
the on-time and minimum off-time:
ture. A good general rule is to allow 0.5% additional
resistance for each °C of temperature rise.
Examining the Figure 1 example with a Q maximum
2
R
= 5.5mΩ at T = +25°C and 7.5mΩ at T =
DS(ON)
J J
⎛
⎞
V
2
OUT
+100°C reveals the following:
(I
− I
LOAD2
)
× L K
+ t
LOAD1
⎜
OFF(MIN)⎟
V
⎝
⎠
IN
I
LIMIT(LOW)
= 90mV / 7.5mΩ = 11.9A
V
=
SAG
⎡
⎤
⎥
⎛
⎞
V
− V
OUT
IN
⎢
2 × C
× V
K
− t
and the required valley current limit is:
> 14A - (0.3012) 14A = 11.9A
⎜
⎟
OUT
OUT
OFF(MIN)
⎢
⎥
V
⎝
⎠
IN
⎣
⎦
I
LIMIT(LOW)
where t
is the minimum off-time (see Electrical
Therefore, the circuit can deliver the full-rated 14A
using the default ILIM threshold.
OFF(MIN)
Characteristics) and K is from Table 3.
When delivering 14A of output current, the worst-case
power dissipation of Q2 is 1.48W. With a thermal resis-
tance of 60°C/W and each MOSFET dissipating 0.74W,
the temperature rise of the MOSFETs is 60°C/W x
0.74W = 44.5°C, and the maximum ambient tempera-
ture is +100°C - 44.5°C = +55.5°C. To operate at a
Inductor Selection
The switching frequency and operating point (% ripple or
LIR) determine the inductor value as follows:
V
V
V
OUT
(
IN − OUT
)
L =
V
× fSW × LIR × I
higher ambient temperature, choose lower R
DS(ON)
IN
LOAD(MAX)
MOSFETs or reduce the thermal resistance. You could
also raise the current-limit threshold, allowing operation
with a higher MOSFET junction temperature.
Example: I
f
= 14A, V = 7V, V
= 1.6V,
OUT
LOAD(MAX)
IN
SW = 300kHz, 30% ripple current or LIR = 0.30.
Connect ILIM to V
for a default 100mV current-limit
CC
threshold. For an adjustable threshold, connect a resistor
divider from REF to GND, with ILIM connected to the cen-
ter tap. The external adjustment range of 0.5V to 3V cor-
responds to a current-limit threshold of 50mV to 300mV.
When adjusting the current limit, use 1% tolerance resis-
tors and a 10µA divider current to prevent a significant
increase of errors in the current-limit tolerance.
1.6V(7V − 1.6V)
L =
= 0.98μH
7V × 300kHz × 0.30 × 14A
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at 200kHz. The
core must be large enough not to saturate at the peak
Output Capacitor Selection
The output filter capacitor must have low enough effective
series resistance (ESR) to meet output ripple and load-
transient requirements, yet have high enough ESR to
satisfy stability requirements. Also, the capacitance
value must be high enough to absorb the inductor energy
going from a full-load to no-load condition without tripping
the OVP circuit.
inductor current (I
).
PEAK
+ (LIR / 2) I
LOAD(MAX) LOAD(MAX)
I
= I
PEAK
Setting the Current Limit
The minimum current-limit threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The valley
In CPU V
converters and other applications where
CORE
the output is subject to violent load transients, the output
capacitor’s size typically depends on how much ESR is
needed to prevent the output from dipping too low
under a load transient. Ignoring the sag due to finite
capacitance:
of the inductor current occurs at I
of the ripple current; therefore:
minus half
LOAD(MAX)
I
> I
- (LIR / 2) I
LOAD(MAX) LOAD(MAX)
LIMIT(LOW)
where I
equals the minimum current-limit
LIMIT(LOW)
R
ESR
≤ V
/ I
STEP LOAD(MAX)
threshold voltage divided by the R
of Q2. For the
DS(ON)
MAX1717, the minimum current-limit threshold (100mV
default setting) is 90mV. Use the worst-case maximum
The actual microfarad capacitance value required
relates to the physical size needed to achieve low ESR,
as well as to the chemistry of the capacitor technology.
value for R
from the MOSFET Q2 data sheet, and
DS(ON)
add some margin for the rise in R
with tempera-
DS(ON)
______________________________________________________________________________________ 25
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
Thus, the capacitor is usually selected by ESR and volt-
age rating rather than by capacitance value (this is true
of tantalums, OS-CONs, and other electrolytics).
Do not put high-value ceramic capacitors directly
across the fast-feedback inputs (FB to GND) without
taking precautions to ensure stability. Ceramic capaci-
tors have a high ESR zero frequency and may cause
erratic, unstable operation. However, it’s easy to add
enough series resistance by placing the capacitors a
couple of inches downstream from the junction of the
inductor and FB pin, or use a voltage-positioned circuit
(see the Voltage Positioning and Effective Efficiency sec-
tion).
When using low-capacity filter capacitors such as
ceramic or polymer types, capacitor size is usually deter-
mined by the capacity needed to prevent V
SOAR
and
SAG
V
from causing problems during load transients.
Generally, once enough capacitance is added to meet
the overshoot requirement, undershoot at the rising load
edge is no longer a problem (see the V
equation in
SAG
the Design Procedure section). The amount of overshoot
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and fast-feed-
back loop instability.
due to stored inductor energy can be calculated as:
2
L× I
PEAK
Double-pulsing occurs due to noise on the output or
because the ESR is so low that there isn’t enough voltage
ramp in the output voltage signal. This “fools” the error
comparator into triggering a new cycle immediately
after the minimum off-time period has expired. Double-
pulsing is more annoying than harmful, resulting in noth-
ing worse than increased output ripple. However, it can
indicate the possible presence of loop instability, which
is caused by insufficient ESR.
V
≈
SOAR
2 × C × V
OUT
where I
is the peak inductor current.
PEAK
Output Capacitor Stability
Considerations
Stability is determined by the value of the ESR zero rela-
tive to the switching frequency. The voltage-positioned
circuits in this data sheet have their ESR zero frequencies
lowered due to the external resistor in series with the
output capacitor ESR, guaranteeing stability. For voltage-
positioned circuits, the minimum ESR requirement of the
output capacitor is reduced by the voltage-positioning
resistor value.
Loop instability can result in oscillations at the output
after line or load perturbations that can cause the output
voltage to rise above or fall below the tolerance limit.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage ripple envelope for over-
shoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Don’t
allow more than one cycle of ringing after the initial
step-response under/overshoot.
For nonvoltage-positioned circuits, the following criteria
must be satisfied. The boundary of instability is given
by the following equation:
f
≤ f
/ π
SW
ESR
Input Capacitor Selection
1
The input capacitor must meet the ripple current
where:
f
=
ESR
requirement (I
) imposed by the switching currents
defined by the following equation:
RMS
2 × π × R
× C
OUT
ESR
For a standard 300kHz application, the ESR zero fre-
quency must be well below 95kHz, preferably below
50kHz. Tantalum and OS-CON capacitors in widespread
use at the time of publication have typical ESR zero fre-
quencies of 15kHz. In the standard application used for
V
V
− V
OUT
OUT
(
IN
)
I
= I
LOAD
RMS
V
IN
For most applications, nontantalum chemistries (ceramic,
aluminum, or OS-CON) are preferred due to their resis-
tance to inrush surge currents typical of systems with a
mechanical switch or a connector in series with the bat-
tery. If the MAX1717 is operated as the second stage of
a two-stage power-conversion system, tantalum input
capacitors are acceptable. In either configuration,
choose an input capacitor that exhibits less than +10°C
temperature rise at the RMS input current for optimal
circuit longevity.
inductor selection, the ESR needed to support 50mV
P-P
ripple is 50mV/4.2A = 11.9mΩ. Six 470µF/4V Kemet
T510 low-ESR tantalum capacitors in parallel provide
5mΩ (max) ESR. Their typical combined ESR results in a
zero at 17kHz, well within the bounds of stability.
26 ______________________________________________________________________________________
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
Calculating the power dissipation in Q1 due to switch-
ing losses is difficult since it must allow for difficult
quantifying factors that influence the turn-on and turn-
off times. These factors include the internal gate resis-
tance, gate charge, threshold voltage, source induc-
tance, and PC board layout characteristics. The following
switching-loss calculation provides only a very rough
estimate and is no substitute for breadboard evalua-
tion, preferably including verification using a thermo-
couple mounted on Q1:
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
(>12A) when using high-voltage (>20V) AC adapters.
Low-current applications usually require less attention.
For maximum efficiency, choose a high-side MOSFET
(Q1) that has conduction losses equal to the switching
losses at the optimum battery voltage (15V). Check to
ensure that the conduction losses at minimum input
voltage don’t exceed the package thermal limits or violate
the overall thermal budget. Check to ensure that con-
duction losses plus switching losses at the maximum
input voltage don’t exceed the package ratings or vio-
late the overall thermal budget.
2
C
× V
× f × I
LOAD
SW
RSS
IN(MAX)
PD(Q1Switching) =
I
GATE
where C
GATE
(1A typ).
is the reverse transfer capacitance of Q1
RSS
Choose a low-side MOSFET (Q2) that has the lowest
and I
is the peak gate-drive source/sink current
possible R
, comes in a moderate-sized package
DS(ON)
(i.e., one or two SO-8s, DPAK or D2PAK), and is reason-
ably priced. Ensure that the MAX1717 DL gate driver
can drive Q2; in other words, check that the dv/dt
caused by Q1 turning on does not pull up the Q2 gate
due to drain-to-gate capacitance, causing cross-con-
duction problems. Switching losses aren’t an issue for
the low-side MOSFET since it’s a zero-voltage switched
device when used in the buck topology.
For the low-side MOSFET (Q2), the worst-case power
dissipation always occurs at maximum battery voltage:
⎛
⎞
V
OUT
2
PD(Q2) = 1 −
I
× R
DS(ON)
⎜
⎟
LOAD
⎜
⎝
⎟
V
IN(MAX) ⎠
The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than
LOAD(MAX)
the current limit and cause the fault latch to trip. To pro-
tect against this possibility, you can “overdesign” the
circuit to tolerate:
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET, the worst-case
power dissipation due to resistance occurs at minimum
battery voltage:
I
but are not quite high enough to exceed
I
= I
+ (LIR / 2) x I
LIMIT(HIGH) LOAD(MAX)
LOAD
V
OUT
2
PD (Q1 Resistive) =
× I
× R
DS(ON)
LOAD
where I
is the maximum valley current
LIMIT(HIGH)
V
IN
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. This means that
the MOSFETs must be very well heatsinked. If short-cir-
cuit protection without overload protection is enough, a
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
required to stay within package
power-dissipation limits often limits how small the
MOSFET can be. Again, the optimum occurs when the
switching losses equal the conduction (R
High-side switching losses don’t usually become an
issue until the input is greater than approximately 15V.
However, the R
DS(ON)
normal I
nent stresses.
value can be used for calculating compo-
LOAD
) losses.
DS(ON)
Choose a Schottky diode (D1) having a forward voltage
low enough to prevent the Q2 MOSFET body diode
from turning on during the dead time. As a general rule,
a diode having a DC current rating equal to 1/3 of the
load current is sufficient. This diode is optional and can
be removed if efficiency isn’t critical.
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
switching-loss equation. If the high-side
MOSFET you’ve chosen for adequate R
CV2f
SW
at low
DS(ON)
battery voltages becomes extraordinarily hot when sub-
jected to V , reconsider your choice of MOSFET.
IN(MAX)
______________________________________________________________________________________ 27
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
Effective efficiency is defined as the efficiency required
Application Issues
Voltage Positioning and
Effective Efficiency
of a nonvoltage-positioned circuit to equal the total dis-
sipation of a voltage-positioned circuit for a given CPU
operating condition.
Powering new mobile processors requires new tech-
niques to reduce cost, size, and power dissipation.
Voltage positioning reduces the total number of output
capacitors to meet a given transient response require-
ment. Setting the no-load output voltage slightly higher
allows a larger step down when the output current sud-
denly increases, and regulating at the lower output volt-
age under load allows a larger step up when the output
current suddenly decreases. Allowing a larger step size
means that the output capacitance can be reduced
and the capacitor’s ESR can be increased.
Calculate effective efficiency as follows:
1) Start with the efficiency data for the positioned circuit
(V , I , V
, I
).
IN IN OUT OUT
2) Model the load resistance for each data point:
R
= V / I
LOAD
OUT OUT
3) Calculate the output current that would exist for each
data point in a nonpositioned application:
R
LOAD
I
= V / R
NP LOAD
NP
The no-load output voltage is raised by adding a fixed
offset to GNDS through a resistor divider from REF. A
27mV nominal value is appropriate for 1.6V applications.
This 27mV corresponds to a 0.9 x 27mV = 24mV =
where V = 1.6V (in this example).
NP
4) Calculate effective efficiency as:
Effective efficiency = (V
x I ) / (V x I ) =
NP IN IN
NP
1.5% increase with a V
of 1.6V. In the voltage-posi-
calculated nonpositioned power output divided by
the measured voltage-positioned power input.
OUT
tioned circuit (Figure 3), this is realized with resistors R4
and R5. Use a 10µA resistor divider current.
5) Plot the efficiency data point at the nonpositioned
Adding a series output resistor positions the full-load out-
put voltage below the actual DAC programmed voltage.
Connect FB and FBS directly to the inductor side of the
voltage-positioning resistor (R6, 5mΩ). The other side of
the voltage-positioning resistor should be tied directly to
the output filter capacitor with a short, wide PC board
trace. With a 14A full-load current, R6 causes a 70mV
drop. This 70mV is a -4.4% error, but it is compensated
by the +1.5% error from the GNDS offset, resulting in a
net error of -2.9%. This is well within the typical specifica-
tion for voltage accuracy.
current, I
.
NP
The effective efficiency of voltage-positioned circuits is
shown in the Typical Operating Characteristics.
V
BATT
DH
DL
An additional benefit of voltage positioning is reduced
power consumption at high load currents. Because the
output voltage is lower under load, the CPU draws less
current. The result is lower power dissipation in the
CPU, though some extra power is dissipated in R6. For
a nominal 1.6V, 12A output, reducing the output volt-
age 2.9% gives an output voltage of 1.55V and an out-
put current of 11.65A. Given these values, CPU power
consumption is reduced from 19.2W to 18.1W. The
additional power consumption of R6 is:
V
OUT
MAX1717
R1
R2
FB
180kΩ
FBS
R2
1kΩ
2
GND
5mΩ x 11.65A = 0.68W
and the overall power savings is as follows:
GNDS
19.2 - (18.1 + 0.68) = 0.42W
R1
)
R2 || 180kΩ
In effect, 1W of CPU dissipation is saved and the power
supply dissipates much of the savings, but both the net
savings and the transfer of dissipation away from the
hot CPU are beneficial.
V
= V
x 1 +
OUT
FB
(
Figure 11. Adjusting V
with a Resistor-Divider
OUT
28 ______________________________________________________________________________________
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
K = 1.8µs, worst-case K = 1.58µs
= 500ns
Dropout Performance
The output voltage adjust range for continuous-conduc-
tion operation is restricted by the nonadjustable 500ns
(max) minimum off-time one-shot (375ns max at
1000kHz). For best dropout performance, use the slower
(200kHz) on-time settings. When working with low input
voltages, the duty-factor limit must be calculated using
worst-case values for on- and off-times. Manufacturing
tolerances and internal propagation delays introduce
an error to the TON K-factor. This error is greater at
higher frequencies (Table 3). Also, keep in mind that
transient response performance of buck regulators
operated close to dropout is poor, and bulk output
capacitance must often be added (see the VSAG equa-
tion in the Design Procedure section).
T
OFF(MIN)
V
= V
= 100mV
DROP1
DROP2
h = 1.5
V
= (1.6V + 0.1V) / (1-0.5µs x 1.5/1.58µs) + 0.1V
- 0.1V = 3.2V
IN(MIN)
Calculating again with h = 1 gives the absolute limit of
dropout:
✕
V
= (1.6V + 0.1V) / (1-1.0 0.5µs/1.58µs) - 0.1V
+ 0.1V = 2.5V
IN(MIN)
Therefore, V must be greater than 2.5V, even with very
IN
large output capacitance, and a practical input voltage
with reasonable output capacitance would be 3.2V.
The absolute point of dropout is when the inductor cur-
Adjusting V
with a Resistor-Divider
OUT
rent ramps down during the minimum off-time (ΔI
)
DOWN
The output voltage can be adjusted with a resistor-
divider rather than the DAC if desired (Figure 11). The
drawback is that the on-time doesn’t automatically
receive correct compensation for changing output voltage
levels. This can result in variable switching frequency
as the resistor ratio is changed, and/or excessive
switching frequency. The equation for adjusting the output
voltage is:
as much as it ramps up during the on-time (ΔI ). The
UP
ratio h = ΔI /ΔI
is an indicator of ability to slew
UP DOWN
the inductor current higher in response to increased
load, and must always be greater than 1. As h
approaches 1, the absolute minimum dropout point, the
inductor current will be less able to increase during
each switching cycle and V
will greatly increase
SAG
unless additional output capacitance is used.
⎛
⎞
R
1
A reasonable minimum value for h is 1.5, but this may
be adjusted up or down to allow tradeoffs between
V
OUT
= V
1+
FB
⎜
⎟
R
2
R
INT
⎝
⎠
V
, output capacitance, and minimum operating
SAG
voltage. For a given value of h, the minimum operating
voltage can be calculated as:
where V
INT
is the currently selected DAC value, and
FB
R
is the FB input resistance. When using external
resistors, FBS remote sensing is not recommended, but
GNDS remote sensing is still possible. Connect FBS to
FB, and GNDS to a remote ground location. In resistor-
adjusted circuits, the DAC code should be set as close
as possible to the actual output voltage in order to mini-
mize the shift in switching frequency.
V
+ V
DROP1
(
1−
OUT
)
V
=
+ V
− V
IN(MIN)
DROP2 DROP1
⎛
⎜
⎜
⎝
⎞
x h
T
OFF(MIN)
K
⎟
⎟
⎠
where V
and V
are the parasitic voltage
DROP2
DROP1
Adjusting V
Above 2V
OUT
drops in the discharge and charge paths (see On-Time
The feed-forward circuit that makes the on-time depen-
dent on battery voltage maintains a nearly constant
One-Shot), T
is from the Electrical Character-
OFF(MIN)
istics, and K is taken from Table 3. The absolute minimum
switching frequency as V , I
, and the DAC code
IN LOAD
input voltage is calculated with h = 1.
are changed. This works extremely well as long as FB
is connected directly to the output. When the output is
adjusted with a resistor divider, the switching frequency
is increased by the inverse of the divider ratio.
If the calculated V
minimum input voltage, then operating frequency must
be reduced or output capacitance added to obtain an
acceptable V
ed, calculate V
response.
is greater than the required
IN(MIN)
. If operation near dropout is anticipat-
SAG
SAG
This change in frequency can be compensated with the
addition of a resistor-divider to the battery-sense input
(V+). Attach a resistor-divider from the battery voltage
to V+ on the MAX1717, with the same attenuation factor
as the output divider. The V+ input has a nominal input
impedance of 600kΩ, which should be considered
when selecting resistor values.
to be sure of adequate transient
Dropout Design Example:
= 1.6V
V
OUT
f
= 550kHz
SW
______________________________________________________________________________________ 29
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
Table 1 and the Typical Operating Characteristics
One-Stage (Battery Input) vs. Two-Stage
(5V Input) Applications
The MAX1717 can be used with a direct battery connec-
tion (one stage) or can obtain power from a regulated 5V
supply (two stage). Each approach has advantages,
and careful consideration should go into the selection of
the final design.
include two circuits using ceramic capacitors with
1000kHz switching frequencies. The efficiency of the
+5V input circuit (circuit 4) is substantially higher than
circuit 5, which accommodates the full battery voltage
range. Circuit 4 is an excellent choice for two-stage
conversion applications if the goal is to minimize size
and power dissipation near the CPU.
The one-stage approach offers smaller total inductor
size and fewer capacitors overall due to the reduced
demands on the 5V supply. The transient response of
the single stage is better due to the ability to ramp the
inductor current faster. The total efficiency of a single
stage is better than the two-stage approach.
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 12). If possible, mount all of the power compo-
nents on the top side of the board with their ground ter-
minals flush against one another. Follow these
guidelines for good PC board layout:
The two-stage approach allows flexible placement due
to smaller circuit size and reduced local power dissipa-
tion. The power supply can be placed closer to the
CPU for better regulation and lower I2R losses from PC
board traces. Although the two-stage design has worse
transient response than the single stage, this can be
offset by the use of a voltage-positioned converter.
1) Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-
free operation.
2) All analog grounding is done to a separate solid cop-
per plane, which connects to the MAX1717 at the
Ceramic Output Capacitor
Applications
GND pin. This includes the V , REF, and CC
CC
capacitors, the TIME resistor, as well as any other
resistor-dividers.
Ceramic capacitors have advantages and disadvan-
tages. They have ultra-low ESR and are noncombustible,
relatively small, and nonpolarized. They are also expen-
sive and brittle, and their ultra-low ESR characteristic can
result in excessively high ESR zero frequencies (affecting
stability in nonvoltage-positioned circuits). In addition,
their relatively low capacitance value can cause output
overshoot when going abruptly from full-load to no-load
conditions, unless the inductor value can be made small
(high switching frequency), or there are some bulk tanta-
lum or electrolytic capacitors in parallel to absorb the
stored energy in the inductor. In some cases, there may
be no room for electrolytics, creating a need for a DC-DC
design that uses nothing but ceramics.
3) Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PC boards (2oz vs. 1oz) can enhance full-
load efficiency by 1% or more. Correctly routing PC
board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single mΩ of excess trace resistance causes
a measurable efficiency penalty.
4) LX and GND connections to Q2 for current limiting
must be made using Kelvin sense connections to
guarantee the current-limit accuracy. With SO-8
MOSFETs, this is best done by routing power to the
MOSFETs from outside using the top copper layer,
while connecting GND and LX inside (underneath)
the SO-8 package.
The MAX1717 can take full advantage of the small size
and low ESR of ceramic output capacitors in a voltage-
positioned circuit. The addition of the positioning resistor
increases the ripple at FB, lowering the effective ESR
zero frequency of the ceramic output capacitor.
5) When trade-offs in trace lengths must be made, it’s
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it’s better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-side
MOSFET or between the inductor and the output filter
capacitor.
Output overshoot (V
) determines the minimum
SOAR
output capacitance requirement (see Output Capacitor
Selection section). Often the switching frequency is
increased to 550kHz or 1000kHz, and the inductor value
is reduced to minimize the energy transferred from induc-
tor to capacitor during load-step recovery. The efficiency
penalty for operating at 550kHz is about 2% to 3% and
about 5% at 1000kHz when compared to the 300kHz
voltage-positioned circuit, primarily due to the high-side
MOSFET switching losses.
6) Ensure the FB connection to the output is short and
direct. In voltage-positioned circuits, the FB connection
30 ______________________________________________________________________________________
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
V
BATT
GND IN
ALL ANALOG GROUNDS
CONNECT TO LOCAL PLANE ONLY
VIA TO GND
NEAR Q2 SOURCE
MAX1717
V
CC
CIN
GND
OUT
CC
Q1
REF
V
DD
Q2
D1
COUT
V
OUT
GND
VIA TO SOURCE
OF Q2
R6
CONNECT LOCAL ANALOG GROUND PLANE DIRECTLY TO GND FROM
THE SIDE OPPOSITE THE V CAPACITOR GND TO AVOID V GROUND
DD
DD
VIA TO FB
AND FBS
CURRENTS FROM FLOWING IN THE ANALOG GROUND PLANE.
L1
VIA TO LX
NOTES: "STAR" GROUND IS USED.
D1 IS DIRECTLY ACROSS Q2.
INDUCTOR DISCHARGE PATH HAS LOW DC RESISTANCE
Figure 12. Power-Stage PC Board Layout Example
is at the junction of the inductor and the positioning
resistor.
4) Make the DC-DC controller ground connections as
shown in Figure 12. This diagram can be viewed as
having three separate ground planes: output ground,
where all the high-power components go; the GND
7) Route high-speed switching nodes away from sensitive
analog areas (CC, REF, ILIM). Make all pin-strap
control input connections (SKP/SDN, ILIM, etc.) to ana-
plane, where the GND pin and V
bypass capacitors
DD
go; and an analog ground plane where sensitive
analog components go. The analog ground plane
and GND plane must meet only at a single point
directly beneath the IC. These two planes are then
connected to the high-power output ground with a
short connection from GND to the source of the low-
side MOSFET Q2 (the middle of the star ground).
This point must also be very close to the output
capacitor ground terminal.
log ground or V rather than power ground or V
.
CC
DD
Layout Procedure
1) Place the power components first, with ground termi-
nals adjacent (Q2 source, CIN-, COUT-, D1 anode).
If possible, make all these connections on the top
layer with wide, copper-filled areas.
2) Mount the controller IC adjacent to MOSFET Q2,
preferably on the back side opposite Q2 in order to
keep LX-GND current-sense lines and the DL drive line
short and wide. The DL gate trace must be short and
wide, measuring 10 to 20 squares (50mils to 100mils
wide if the MOSFET is 1 inch from the controller IC).
5) Connect the output power planes (VCORE and system
ground planes) directly to the output filter capacitor
positive and negative terminals with multiple vias.
Place the entire DC-DC converter circuit as close to
the CPU as is practical.
3) Group the gate-drive components (BST diode and
capacitor, V
bypass capacitor) together near the
DD
controller IC.
______________________________________________________________________________________ 31
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
Pin Configuration
Chip Information
TRANSISTOR COUNT: 7151
TOP VIEW
V+
SKP/SDN
TIME
1
2
3
4
5
6
7
8
9
24 DH
23 LX
22 BST
21 D0
FB
MAX1717
FBS
20 D1
19 D2
18 D3
17 D4
16 A/B
CC
V
CC
TON
REF
ILIM 10
GNDS 11
VGATE 12
15 V
DD
14 DL
13 GND
QSOP
32 ______________________________________________________________________________________
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600_____________________33
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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