MAX15569GTG+_技术文档

EVALUATION KIT AVAILABLE

MAX15569

2-Phase/1-Phase QuickTune-PWM Controller

2

with Serial I C Interface

General Description

Beneﬁts and Features

●ꢀ MultiphaseꢀControllerꢀMaximizesꢀProcessorꢀ

The MAX15569 step-down controller consists of one

multiphase regulator. The multiphase CPU regulator uses

Maxim’s unique 2-phase QuickTune-PWM constant “on-

time” architecture. The 2-phase CPU regulator runs 180°

out-of-phase for true interleaved operation, minimizing

input capacitance.

Performance

• 2-Phase QuickTune-PWM CPU Core Regulator

• Output-Voltage Control

• Active Load-Line Amplifier with Adjustable Gain

• ±5mV FB Accuracy Over Line and Load

• Programmable Slew Rate and Soft-Start

• Accurate Current Balance and Current Limit

•ꢀ TrueꢀDifferentialꢀRemoteꢀOutputꢀSense

•ꢀ 8-BitꢀADCꢀDigitizesꢀCurrentꢀSenseꢀtoꢀStoreꢀinꢀ

Current Monitor Register

The device’s VR is controlled by writing appropriate

data into a function-mapped register file. Output volt-

ages are dynamically changed through a 2-wire, fast I C

2

interface (clock, data), allowing the switching regula-

tor to be programmed to different voltages. A slew-

rate controller allows controlled voltage transition and

controlled soft-start. The regulator runs in a unique

smart, low-power pulse-skipping-state algorithm for

best efficiency over the full load range and the best

transient response with respect to common pulse-

skipping methods.

●ꢀ TransientꢀPhaseꢀOverlapꢀReducesꢀOutputꢀ

Capacitance

●ꢀ ProgrammableꢀFunctionalityꢀAllowsꢀOptimizedꢀDesignꢀ

Performance

• Programmable 300kHz to 1400kHz Switching

Frequency

•ꢀ ProgrammableꢀSoft-Shutdownꢀ(2kΩꢀDischargeꢀꢀ

The device includes multiple fault-protection features:

Output overvoltage protection (OVP), undervoltage pro-

tection (UVP), and thermal protection. When any of these

fault-protection features detect a fault condition, the con-

troller shuts down. A multifunction INT output monitors

output voltage, overcurrent (OC), overrange (VOUTMAX),

and thermal faults (VRHOT).

Switch)

2

• I C Serial-Interface Control

●ꢀ RobustꢀProtectionꢀforꢀReliableꢀOperation

• Overcurrent, Output-Voltage Overrange,

Overvoltage, Undervoltage, and Thermal-Fault

Protection

• System Status Register

The controller has a programmable switching frequency,

allowing 300kHz to 1400kHz per each phase of opera-

tion. The controller operates with a wide variety of drivers

and MOSFETs, such as the MAX15492 MOSFET driver

with standard MOSFETs, or with the power stage that

integrates the drivers and MOSFETs together in a single

device.

• Multifunction INT Output

• 4.5V to 24V Battery Input Range

Applications

●ꢀ ARMꢀCoreꢀPowerꢀSupply

Ordering Information appears at end of data sheet.

●ꢀ Ultrabook™ꢀandꢀTabletꢀCoreꢀSupplies

●ꢀ Voltage-PositionedꢀStep-DownꢀConverter

●ꢀ MultiphaseꢀDC-DCꢀControllers

Ultrabook is a trademark of Intel Corporation.

19-6646; Rev 1; 2/15

MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

Absolute Maximum Ratings

V

ꢀtoꢀAGND........................................ -0.3V to (V

+ 0.3V)

PGNDꢀtoꢀAGND....................................................-0.3V to +0.3V

TONꢀtoꢀAGND........................................................-0.3V to +26V

TT

BIAS

BIASꢀtoꢀAGND.........................................................-0.3V to +6V

EN,ꢀSCL,ꢀSDAꢀtoꢀAGND..........................................-0.3V to +6V

CSP1,ꢀCSN1,ꢀCSP2,ꢀCSN2ꢀtoꢀAGND.....................-0.3V to +6V

FB,ꢀFBAC,ꢀIMONꢀtoꢀAGND ....................-0.3V to (V

DRVPWM1,ꢀDRVPWM2ꢀtoꢀPGND .........-0.3V to (V

DRVSKPꢀtoꢀPGND .................................-0.3V to (V

INT,ꢀTHERMꢀtoꢀAGND............................................-0.3V to +6V

ICꢀtoꢀAGND..............................................................-0.3V to +6V

GNDSꢀtoꢀAGND....................................................-0.3V to +0.3V

ContinuousꢀPowerꢀDissipationꢀ(T = +70°C)

A

TQFN (derate 27.8mW above +70°C).............................2.2W

Operating Temperature Range......................... -40°C to +105°C

Junction Temperature......................................................+150°C

Storage Temperature Range............................ -65°C to +165°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow).......................................+260°C

+ 0.3V)

BIAS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

(Note 1)

Package Thermal Characteristics

TQFN

Junction-to-AmbientꢀThermalꢀResistanceꢀ(θ ) ..........36°C/W

JA

Junction-to-CaseꢀThermalꢀResistanceꢀ(θ )……..........3°C/W

JC

Note 1:ꢀ PackageꢀthermalꢀresistancesꢀwereꢀobtainedꢀusingꢀtheꢀmethodꢀdescribedꢀinꢀJEDECꢀspecificationꢀJESD51-7,ꢀusingꢀaꢀfour-layerꢀ

board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Electrical Characteristics (0°C to +85°C)

(Circuit of Figure 1. V = 10V, V

= 5V, V ꢀ=ꢀ1.8V,ꢀENꢀ=ꢀBIAS,ꢀGNDSꢀ=ꢀAGND,ꢀV

= V = V

= V

= 1V [SETVOUT

IN

BIAS

TT

FBAC

FB

CSP_

CSN_

register 0x07h set to 0x33h]. T = 0°C to +85°C, unless otherwise noted. Typical values are at +25°C. All devices 100% tested at

A

+25°C. Limits over temperature are guaranteed by design.)

PARAMETER

BIAS CURRENTS

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

BIAS Voltage Range

V

4.75

1.6

5.25

4.0

V

BIAS

2

I C Interface Supply (V

)

V

TT

Skip mode, measured at BIAS,

Quiescent Supply Current

(BIAS)

I

V

= 1.8V; FB forced above the regulation

2

5

mA

BIAS

TT

point, EN = BIAS

Shutdown Supply Current

(BIAS)

MeasuredꢀatꢀBIAS,ꢀENꢀ=ꢀGND,

6

µA

V

ꢀ=ꢀ1.8VꢀorꢀGND,ꢀT = +25°C

A

TT

V

= high, EN = low, T = +25°C

3

BIAS

A

V

BIAS Current

I

VTT

TT

= high, EN = high, T = +25°C

50

BIAS

A

PWM CONTROLLER

T

= +25°C; measured at

A

DCꢀOutputꢀVoltageꢀAccuracyꢀ

(Note 2)

FB,ꢀwithꢀrespectꢀtoꢀGNDS;ꢀ DACꢀcodesꢀfromꢀ

-5

+5

mV

includes load regulation

error

0.50V to 1.60V

DACꢀcodesꢀfromꢀ

0.50V to 1.40V

-8

+8

Measured at FB, with

respectꢀtoꢀGNDS;ꢀincludesꢀ

load regulation error

DCꢀOutputꢀVoltageꢀAccuracyꢀ

(Note 2)

DACꢀcodesꢀfromꢀ

1.40V to 1.60V

-0.7

+0.7

%

Line Regulation Error

V

= 4.75V to 5.25V, V = 5.5V to 20V

0.1

mV

BIAS

IN

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

Electrical Characteristics (0°C to +85°C) (continued)

(Circuit of Figure 1. V = 10V, V

= 5V, V ꢀ=ꢀ1.8V,ꢀENꢀ=ꢀBIAS,ꢀGNDSꢀ=ꢀAGND,ꢀV

= V = V

= V

= 1V [SETVOUT

IN

BIAS

TT

FBAC

FB

CSP_

CSN_

register 0x07h set to 0x33h]. T = 0°C to +85°C, unless otherwise noted. Typical values are at +25°C. All devices 100% tested at

A

+25°C. Limits over temperature are guaranteed by design.)

PARAMETER

GNDSꢀInputꢀRange

SYMBOL

CONDITIONS

MIN

-200

0.97

-0.5

TYP

MAX

+200

1.03

+0.5

UNITS

mV

GNDSꢀGain

A

1.00

V/V

GNDS

GNDSꢀInputꢀBIASꢀCurrent

I

T

= +25°C

µA

GNDS

A

ENꢀ=ꢀAGND,ꢀV = 24V,

IN

TON Shutdown Current

0.01

71

0.1

82

µA

ns

V

= 0V or 5V, T = +25°C

A

BIAS

MeasuredꢀatꢀDRVPWM_,ꢀ

ꢀ=ꢀ136.3kΩꢀ(1400kHz)

60

92

R

TON

DRVPWM_ꢀOn-Time

(Note 3)

MeasuredꢀatꢀDRVPWM_,ꢀ

R ꢀ=ꢀ200kΩꢀ(1000kHz)

TON

t

104

114

ON

MeasuredꢀatꢀDRVPWM_,ꢀ

ꢀ=ꢀ326.7kΩꢀ(600kHz)

141

166

100

192

133

R

TON

Minimum Off-Time (Note 3)

t

MeasuredꢀatꢀDRVPWM_

ns

%

OFF(MIN)

Slew rate = 3.5mV/µs , 4.5mV/µs, 5.5mV/µs,

7mV/µs, 9mV/µs, 11mV/µs, 14mV/µs,

18mV/µs, 22mV/µs, 28mV/µs, 36mV/µs,

44mV/µs (nominal)

Slew-Rate Accuracy (see Table

8 for Soft-Start and Regular

Slew-Rate Combinations)

-20

FAULT PROTECTION

Upper INT and Output

Overvoltage-Protection Trip

Threshold

V

Soft-start completed, measured at FB

FB forced 25mV above trip threshold

1.78

1.83

5

1.88

V

OVP

Upper INT and Output

OvervoltageꢀPropagationꢀDelay

t

µs

OVP

Lower INT and Output

Undervoltage-Protection Trip

Threshold

Measured at FB, with respect to unloaded

output voltage

V

-300

100

-250

-200

350

mV

UVP

Lower INTꢀPropagationꢀDelay

FB forced 25mV below trip threshold

5

µs

Output Undervoltage

PropagationꢀDelay

t

200

UVP

INT Output Low Voltage

INT Leakage Current

I

= 4mA

0.3

1

V

SINK

High state, INT forced to 5V, T = +25°C

µA

A

INTꢀStartupꢀDelayꢀandꢀ

Transitions Blanking Time

Measured from the time when FB reaches the

target voltage

t

4

µs

V

INT

V

Undervoltage-Lockout

Rising edge, 50mV typical hysteresis, controller

disabled below this level

BIAS

V

4.3

4.5

4.7

UVLO

Threshold

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

Electrical Characteristics (0°C to +85°C) (continued)

(Circuit of Figure 1. V = 10V, V

= 5V, V ꢀ=ꢀ1.8V,ꢀENꢀ=ꢀBIAS,ꢀGNDSꢀ=ꢀAGND,ꢀV

= V = V

= V

= 1V [SETVOUT

IN

BIAS

TT

FBAC

FB

CSP_

CSN_

register 0x07h set to 0x33h]. T = 0°C to +85°C, unless otherwise noted. Typical values are at +25°C. All devices 100% tested at

A

+25°C. Limits over temperature are guaranteed by design.)

PARAMETER

THERMAL PROTECTION

THERM Resistor

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

R

Internal pullup resistance

Measured at THERM, with respect to V

5.24

5.35

5.48

kΩ

THERM

BIAS

falling edge; specify as % error for all temp max

DACꢀcodeꢀsettings;ꢀtypicalꢀhysteresisꢀ=ꢀ100mV,ꢀ

VRHOT Trip Threshold

49.5

50.5

1.1

%

T

= +25°C to +100°C

A

THERM Sampling Period

5% duty cycle

0.75

160

ms

Internal Thermal-Fault

Shutdown Threshold

T

Typical hysteresis = +15°C

°C

TSHDN

VALLEY CURRENT LIMIT AND DROOP

Valley Current-Limit Threshold

Voltage (Positive)

V

- V

CSN_

35

20

38

23

41

26

mV

ILIM

CSP_

OC_ALARM Valley Current

Threshold Voltage (Positive,

CSP1 Only)

V

OC_ALARM CSP1 - VCSN1

Current-Balance Offset Voltage

-1.8

0.5

+1.8

1.6

mV

V

Current-Sense Common-Mode

Input Range

CSP1, CSN1, CSP2, CSN2

Current-Sense Input Current

DischargeꢀSwitchꢀResistance

FB Input Current

CSP1, CSN1, CSP2, CSN2, T = +25°C

A

-0.12

+0.12

µA

kΩ

µA

CSN1 only

2

T

= +25°C

-0.2

3

+0.2

A

V

BIAS

- 0.4

BIAS

- 1.0

Phaseꢀ2ꢀDisableꢀThreshold

DroopꢀAmpliﬁerꢀ(GMD)ꢀOffset

CSP2

V

Average (V

- V

) at I = 0mA

FBAC

-1.0

1.182

+1.0

mV

CSP_

CSN_

DroopꢀAmpliﬁerꢀ(GMD)ꢀ

Transconductance

DI

/∑D (V

- V

), measured at

FBAC

CSP_

CSN_

G

1.2

1.218 µA/mV

m(FBAC)

FBAC

CURRENT MONITOR (IMON)

Current Monitor Output Current

for Typical Full-Load Conditions

I

∑(V

- V ) = 25mV

CSN_

124.2

4.8

128

131.8

µA

IMON

CSP_

DI

/∑D (V

- V

), measured at

IMON

CSP_ CSN_

Current Monitor Gain

G

5.12

3.2

5.44

3.6

µA/mV

V

m(IMON)

IMON

Current Monitor Clamp Voltage

IMON

DRIVER CONTROL

DRVPWM_,ꢀDRVSKP#ꢀOutputꢀ

Logic-High Voltage

V

BIAS

- 0.4

V

I

= 3mA

SOURCE

V

OH_DRV

DRVPWM_,ꢀDRVSKP#ꢀOutputꢀ

Logic-Low Voltage

V

= 3mA

SINK

0.4

2.3

OL_DRV

DRVPWM_ꢀOutputꢀMidlevelꢀ

Voltage

1.6

Maxim Integrated

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

Electrical Characteristics (0°C to +85°C) (continued)

(Circuit of Figure 1. V = 10V, V

= 5V, V ꢀ=ꢀ1.8V,ꢀENꢀ=ꢀBIAS,ꢀGNDSꢀ=ꢀAGND,ꢀV

= V = V

= V

= 1V [SETVOUT

IN

BIAS

TT

FBAC

FB

CSP_

CSN_

register 0x07h set to 0x33h]. T = 0°C to +85°C, unless otherwise noted. Typical values are at +25°C. All devices 100% tested at

A

+25°C. Limits over temperature are guaranteed by design.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

ENABLE LOGIC (EN)

0.7 x

EN Input High Voltage

V

IH_EN

V

TT

EN Input Low Voltage

EN Input Current

V

0.33

+1

V

IL_EN

I

T

= +25°C

-1

µA

µs

EN

A

Power-UpꢀCalibrationꢀDelay

t

850

150

CAL

ENꢀtoꢀﬁrstꢀswitchingꢀedgeꢀ(fullyꢀdischargedꢀ

output)

EnableꢀtoꢀStartupꢀDelay

t

µs

STRT

2

I C INTERFACE (SDA, SCL)

2

I C Input Low Voltage

V

0.4

V

IL

0.7 x

2

I C Input High Voltage

V

IH

V

TT

2

I C Output Low Level

V

Open-drain output, 3mA pullup to V

0.4

+1

V

OL

TT

(SDAꢀOnly)

2

I C Logic Inputs Leakage

T

= +25°C

-1

µA

A

Current

2

I C TIMING REQUIREMENTS

2

I C Clock Frequency

3.4

MHz

ns

Hold Time Repeated START

Condition

t

(Note 4)

160

HD_STA

SCL Low Period

SCL High Period

t

(Note 4)

160

60

ns

LOW

t

HIGH

Setup Time Repeated START

Condition

(Note 4)

160

ns

SU_STA

SDAꢀHoldꢀTime

t

(Note 4)

0

70

ns

HD_DAT

SDAꢀSetupꢀTime

t

10

SU_DAT

Setup Time for STOP Condition

t

160

SU_STO

Maxim Integrated

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

Electrical Characteristics (-40°C to +105°C)

(Circuit of Figure 1. V = 10V, V

= 5V, V ꢀ=ꢀ1.8V,ꢀENꢀ=ꢀBIAS,ꢀGNDSꢀ=ꢀAGND,ꢀV

= V

FB

= V

CSP_

= V = 1V

CSN_

IN BIAS

TT

FBAC

[SETVOUT register 0x07h set to 0x33h]. T = -40°C to +105°C, unless otherwise noted.)

A

PARAMETER

BIAS CURRENTS

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

BIAS Voltage Range

V

4.75

1.6

5.25

4.0

V

BIAS

2

I C Interface Supply (V

)

V

TT

Quiescent Supply Current

(BIAS)

Skip mode, measured at BIAS, V = 1.8V; FB

TT

forced above the regulation point; EN = BIAS

I

5

mA

BIAS

PWM CONTROLLER

DACꢀcodesꢀfromꢀ0.50Vꢀ

to 1V

Measured at FB,

with respect to

-10

+10

mV

DCꢀOutputꢀVoltageꢀAccuracyꢀ

(Note 2)

GNDS;ꢀincludesꢀloadꢀ

regulation error

1.60V

DACꢀcodesꢀfromꢀ1Vꢀtoꢀ

-1.0

0.97

60

+1.0

1.03

82

%

GNDSꢀGain

A

V/V

GNDS

MeasuredꢀatꢀDRVPWM_,ꢀ

R

ꢀ=ꢀ136.3kΩ,ꢀ(1400kHz)

TON

MeasuredꢀatꢀDRVPWM_,ꢀ

ꢀ=ꢀ200kΩ,ꢀ(1000kHz)

DRVPWM_ꢀOn-Timeꢀ(Noteꢀ3)

Minimum Off-Time (Note 3)

t

92

114

ns

ON

R

TON

MeasuredꢀatꢀDRVPWM_,ꢀ

ꢀ=ꢀ326.7kΩ,ꢀ(600kHz)

141

192

133

R

TON

t

MeasuredꢀatꢀDRVPWM_

ns

%

OFF(MIN)

Slew rate = 3.5mV/µs , 4.5mV/µs, 5.5mV/µs,

7mV/µs, 9mV/µs, 11mV/µs, 14mV/µs, 18mV/µs,

22mV/µs, 28mV/µs, 36mV/µs, 44mV/µs

(nominal)

Slew-Rate Accuracy (see Table

8 for Soft-Start and Regular

Slew-Rate Combinations)

-20

FAULT PROTECTION

Upper INT and Output

Overvoltage-Protection Trip

Threshold

V

Soft-start completed; measured at FB

1.78

1.88

-200

V

OVP

Lower INT and Output

Undervoltage-Protection Trip

Threshold

Measured at FB, with respect to unloaded

output voltage

-300

100

mV

UVP

Output Undervoltage

PropagationꢀDelay

t

FB forced 25mV below trip threshold

350

0.3

4.7

µs

V

UVP

INT Output Low Voltage

I

= 4mA

SINK

V

Undervoltage-Lockout

Rising edge, 50mV typical hysteresis; controller

disabled below this level

BIAS

V

4.3

V

UVLO

Threshold

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

Electrical Characteristics (-40°C to +105°C) (continued)

(Circuit of Figure 1. V = 10V, V

= 5V, V ꢀ=ꢀ1.8V,ꢀENꢀ=ꢀBIAS,ꢀGNDSꢀ=ꢀAGND,ꢀV

= V

FB

= V

CSP_

= V = 1V

CSN_

IN BIAS

TT

FBAC

[SETVOUT register 0x07h set to 0x33h]. T = -40°C to +105°C, unless otherwise noted.)

A

PARAMETER

THERMAL PROTECTION

THERM Resistor

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

R

Internal pullup resistance

Measured at THERM, with respect to V

falling edge; specify as % error for all temp max

DACꢀcodeꢀsettings;ꢀtypicalꢀhysteresisꢀ=ꢀ100mV;ꢀ

5.24

5.48

50.5

kΩ

THERM

BIAS

VRHOT Trip Threshold

49.5

%

T

= +25°C to +105°C

A

VALLEY CURRENT LIMIT AND DROOP

Valley Current-Limit Threshold

Voltage (Positive)

V

- V

35

20

41

26

mV

ILIM

CSP_

CSN_

OC_ALARM Valley Current

Threshold Voltage (Positive,

CSP1 Only)

V

OC_ALARM CSP1

CSN1

Current-Balance Offset Voltage

-2.5

0.5

+2.5

1.6

mV

V

Current-Sense Common-Mode

Input Range

CSP1, CSN1, CSP2, CSN2

CSP2

V

BIAS

- 0.4

Phaseꢀ2ꢀDisableꢀThreshold

DroopꢀAmpliﬁerꢀ(GMD)ꢀOffset

3

V

Average (V

- V

) at I = 0mA

FBAC

-1.0

+1.0

mV

CSP_

CSN_

DroopꢀAmpliﬁerꢀ(GMD)ꢀ

Transconductance

DI

FBAC

/∑D (V

- V

), measured at

FBAC

CSP_

CSN_

G

1.176

1.224 µA/mV

m(FBAC)

CURRENT MONITOR (IMON)

Current Monitor Output Current

for Typical Full-Load Conditions

I

∑(V

- V ) = 25mV

CSN_

122.2

4.8

133.8

5.44

µA

IMON

CSP_

DI

/∑D (V

- V

), measured

IMON

CSP_ CSN_

Current Monitor Gain

G

µA/mV

m(IMON)

at IMON

DRIVER CONTROL

DRVPWM_,ꢀDRVSKP Output

Logic-High Voltage

V

- 0.4

BIAS

V

I

= 3mA

SOURCE

V

OH_DRV

DRVPWM_,ꢀDRVSKP Output

Logic-Low Voltage

V

= 3mA

SINK

0.4

2.3

OL_DRV

DRVPWM_ꢀOutputꢀMidlevelꢀ

Voltage

1.6

ENABLE LOGIC (EN)

EN Input High Voltage

EN Input Low Voltage

0.7 x

V

IH_EN

V

TT

V

0.33

IL_EN

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

Electrical Characteristics (-40°C to +105°C) (continued)

(Circuit of Figure 1. V = 10V, V

= 5V, V ꢀ=ꢀ1.8V,ꢀENꢀ=ꢀBIAS,ꢀGNDSꢀ=ꢀAGND,ꢀV

= V

FB

= V

CSP_

= V = 1V

CSN_

IN BIAS

TT

FBAC

[SETVOUT register 0x07h set to 0x33h]. T = -40°C to +105°C, unless otherwise noted.)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

2

I C TIMING REQUIREMENTS

2

I C Clock Frequency

3.4

MHz

ns

Hold Time Repeated START

Condition

t

(Note 4)

160

HD_STA

SCL Low Period

SCL High Period

t

(Note 4)

160

60

ns

LOW

t

HIGH

Setup Time Repeated START

Condition

t

(Note 4)

160

ns

SU_STA

SDAꢀHoldꢀTime

t

(Note 4)

0

70

ns

HD_DAT

SDAꢀSetupꢀTime

t

10

SU_DAT

Setup Time for STOP Condition

t

160

SU_STO

Note 2: The equation for the target voltage V

is: V

ꢀ=ꢀtheꢀoutputꢀofꢀslewꢀcontrolꢀDAC,ꢀwhereꢀV

= 0V for

TARGET

DAC

shutdown, V

= V

during startup; otherwise V

= SETVOUT. The output voltages for all possible codes are

DAC

BOOT

DAC

given in Table 3.

Note 3:ꢀ On-timeꢀandꢀminimumꢀoff-timeꢀspecificationsꢀareꢀmeasuredꢀfromꢀ50%ꢀriseꢀtoꢀ50%ꢀfallꢀatꢀtheꢀDRVPWM_ꢀpin.ꢀActualꢀin-circuitꢀ

times can be different due to MOSFET driver characteristics.

Note 4: Guaranteed by design. Not production tested.

Pin Conﬁguration

TOP VIEW

18

17

16

15

14

13

12

11

10

9

INT 19

CSP1 20

CSN1 21

N.C. 22

EN

I.C. (BIAS)

MAX15569

SCL

CSN2

CSP2

8

SDA

23

24

*EP

5

+

7

AGND

1

2

3

4

6

TQFN

(4mm x 4mm)

*EP = EXPOSED PAD. CONNECT TO GROUND.

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

Pin Description

NAME

FUNCTION

GroundꢀRemote-SenseꢀInput.ꢀConnectꢀGNDSꢀtoꢀtheꢀground-senseꢀpinꢀofꢀtheꢀCPUꢀlocatedꢀdirectlyꢀ

atꢀtheꢀpointꢀofꢀload.ꢀGNDSꢀinternallyꢀconnectsꢀtoꢀanꢀinternalꢀtransconductanceꢀampliﬁerꢀthatꢀ

adjusts the feedback voltage to compensate for voltage drops between the local controller ground

and the remote load ground.

1

GNDS

OutputꢀofꢀtheꢀACꢀVoltageꢀPositioningꢀTransconductanceꢀAmpliﬁer.ꢀTheꢀeffectiveꢀimpedanceꢀ

(Z

) between this pin and the positive side of the remote-sensed output voltage sets the

FBAC

2

3

FBAC

transient AC droop. See the Load-Line Ampliﬁer (Steady State and AC Droop) section.

FBAC is high impedance in shutdown.

Feedback-Sense Input. An integrator on FB corrects for output ripple and ground-sense offset.

Connect a resistor (R ) between FB and the positive output of the remote sense (output) to

setꢀtheꢀDCꢀsteady-stateꢀdroop.ꢀTheꢀimpedanceꢀfromꢀFBACꢀtoꢀFBꢀsetsꢀtheꢀcurrent-loopꢀgainꢀoverꢀ

frequency, which dominates stability. See the Load-Line Ampliﬁer (Steady State and AC Droop)

section.

FB

Current Monitor Output. The output current at IMON is:

I

= G

x ∑ (CSP_ - CSN_)

IMON

= 5.12mS (typ).

M(IMON)

where G

M(IMON)

An external resistor (R

)ꢀbetweenꢀIMONꢀandꢀGNDSꢀsetsꢀtheꢀcurrentꢀmonitorꢀoutputꢀvoltage:

IMON

= I

4

5

IMON

V

x

x G

x R

IMON

LOAD RSENSE

M(IMON) IMON

where R

is the value of the effective current-sense resistance. Choose R

so that

IMON

SENSE

V

is 2.56V at the desired full current.

IMON

IMON is high impedance when in shutdown.

Thermal-SenseꢀInput.ꢀConnectꢀaꢀ100kΩꢀNTCꢀwithꢀβꢀ=ꢀ4250KꢀfromꢀTHERMꢀtoꢀAGND.ꢀTheꢀNTCꢀatꢀ

THERM is used to determine the temperature of the power stages. Place near the hottest region

of the regulator (typically the MOSFETs and inductor of phase 1).

THERM

TheꢀVRHOTꢀstatusꢀbitꢀ(D5)ꢀactivatesꢀwhenꢀtheꢀNTCꢀresistanceꢀdropsꢀtoꢀ5.68kΩꢀ(100°Cꢀwhenꢀ

usingꢀaꢀ100kΩꢀNTCꢀwithꢀβ = 4250K).

Interface Logic Supply. Power V from a 1.8V to 3.3V ±10% source with a compliance of at least

TT

6

7

8

V

TT

1mA.ꢀDecoupleꢀV with at least 1µF of ceramic capacitance.

TT

AGND

SDA

Analog Ground

2

I CꢀSerial-DataꢀInput/Output.ꢀOpen-DrainꢀI/Oꢀpin.ꢀConnectꢀanꢀexternalꢀpullupꢀresistorꢀbetweenꢀ

2

SDAꢀandꢀtheꢀsupplyꢀusedꢀtoꢀpowerꢀtheꢀI C interface (V ).

TT

2

9

SCL

I.C.

I CꢀSerial-DataꢀClockꢀInput

10, 11

Internally Connected. Connect to BIAS.

ControllerꢀEnableꢀInput.ꢀDriveꢀENꢀhighꢀorꢀconnectꢀENꢀtoꢀBIASꢀforꢀnormalꢀoperation.ꢀPullꢀtoꢀ

2

ground to put the controller into its 7µA (max) standby state (I C interface active, regulator not

switching).

Duringꢀsoft-start,ꢀtheꢀcontrollerꢀslowlyꢀrampsꢀtheꢀoutputꢀvoltageꢀupꢀtoꢀtheꢀbootꢀvoltageꢀwithꢀ

theꢀselectedꢀslewꢀrateꢀ(registerꢀ0x06,ꢀdefaultꢀisꢀ4.5mV/µsꢀforꢀstart-upꢀandꢀ9mV/μsꢀforꢀnormalꢀ

operation).ꢀDuringꢀtheꢀtransitionꢀfromꢀnormalꢀoperationꢀtoꢀstandby,ꢀtheꢀoutputꢀisꢀdischargedꢀ

throughꢀaꢀ2kΩꢀinternalꢀdischargeꢀMOSFETꢀonꢀCSN1.ꢀ

12

EN

Toggling EN does NOT reset the fault latches. Cycle power (V or BIAS) to trigger the power-on

TT

reset (POR) to clear the fault conditions.

The EN input is rated for up to 5.5V.

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

Pin Description (continued)

NAME

FUNCTION

AnalogꢀandꢀDriverꢀSupplyꢀVoltageꢀInput.ꢀBIASꢀprovidesꢀtheꢀsupplyꢀvoltageꢀforꢀtheꢀdriver’sꢀPWMꢀ

and skip control outputs. Connect BIAS to the same supply used by the external drivers (typically

theꢀ4.5Vꢀtoꢀ5.5Vꢀsystemꢀsupplyꢀvoltage).ꢀBypassꢀBIASꢀtoꢀpowerꢀgroundꢀwithꢀaꢀlocalꢀ1μFꢀorꢀ

greater ceramic capacitor.

13

BIAS

14

15

PGND

Power Ground

Direct-DriveꢀPWMꢀOutputꢀforꢀControllingꢀtheꢀExternalꢀFirst-PhaseꢀDriver.ꢀTheꢀDRVPWM1ꢀ

push-pullꢀoutputꢀdrivesꢀtheꢀsignalꢀbetweenꢀBIASꢀandꢀPGND.ꢀDRVPWM1ꢀisꢀhighꢀimpedanceꢀinꢀ

shutdown and after fault conditions (output overvoltage/undervoltage or thermal fault).

DRVPWM1

ExternalꢀDriverꢀSkip-ModeꢀControlꢀOutput.ꢀTheꢀDRVSKP output is low in standby. DRVSKP goes

high when the controller detects an output overvoltage fault condition, or during dynamic output-

voltage transitions.

For applications operating with forced-PWM operation, disable the driver zero-crossing detection

and leave DRVSKP unconnected.

16

17

DRVSKP

Direct-DriveꢀPWMꢀOutputꢀforꢀControllingꢀtheꢀExternalꢀSecond-PhaseꢀDriver.ꢀTheꢀDRVPWM2ꢀ

push-pullꢀoutputꢀdrivesꢀtheꢀsignalꢀbetweenꢀBIASꢀandꢀPGND.ꢀDRVPWM2ꢀisꢀhighꢀimpedanceꢀinꢀ

shutdown and after fault conditions (output overvoltage, output undervoltage, or thermal fault).

DRVPWM2

Switching Frequency Adjustment Input. An external resistor between the input power source and

TON sets the switching period (per phase) according to the following equation:

f

= (R

ꢀ+ꢀ6.5kΩ)ꢀxꢀ5pF

SW

TON

18

19

20

TON

where f

= 1/f ꢀisꢀtheꢀnominalꢀswitchingꢀfrequency.ꢀAꢀ200kΩꢀresistorꢀprovidesꢀaꢀtypicalꢀ

operating frequency of 1MHz.

TON is high impedance in shutdown.

SW

Open-DrainꢀInterruptꢀOutput.ꢀINT is triggered by latched faults (output undervoltage, output

overvoltage, thermal shutdown), sticky alarms (internal overcurrent (OC), non-sticky alarms

(voltageꢀregulatorꢀhotꢀ(VRHOT),ꢀandꢀVIDꢀcodeꢀviolationsꢀ(VOUTMAX)).ꢀTheꢀfaultꢀconditionsꢀandꢀ

alarms can be masked through register 0x05h. Masking these signals only prevents INT from

being asserted; the STATUS register still asserts when any of these conditions occur.

INT remains high in standby mode (EN pulled low) to reduce power through the pullup resistor.

INT is pulled low during soft-start. After completing the soft-start sequence, INT becomes high

impedance as long as FB remains in regulation and there are no active alarms.

INT

To obtain a logic signal, pull up INT with an external resistor connected to a logic supply.

Positive Current-Sense Input for the First Phase.

1) ConnectꢀCSP1ꢀtoꢀtheꢀpositiveꢀsideꢀofꢀtheꢀcurrent-senseꢀresistorꢀorꢀtheꢀDCRꢀsenseꢀﬁlterꢀ

capacitor of phase 1, as shown in Figure 4.

2) Connect CSP1 to the IOUT pin of the smart power stage (MAX15515). A resistor across

CSP1 and CSN1 sets the current-sense gain, as shown in Figure 3.

See the Current Sense section.

CSP1

Negative Current-Sense Input for the First Phase. Connect CSN1 to the negative side of the

current-senseꢀelement,ꢀasꢀshownꢀinꢀFigureꢀ4.ꢀAnꢀinternalꢀ2kΩꢀdischargeꢀMOSFETꢀbetweenꢀCSN1ꢀ

and ground is enabled under an input UVLO or shutdown condition.

21

22

CSN1

N.C.

No Connection Internally

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

Pin Description (continued)

NAME

FUNCTION

Negative Current-Sense Input for the Second Phase. Connect CSN2 to the negative side of the

current-sense element, as shown in Figure 4.

23

CSN2

Positive Current-Sense Input for the Second Phase.

1) ConnectꢀCSP2ꢀtoꢀtheꢀpositiveꢀsideꢀofꢀtheꢀcurrent-senseꢀresistorꢀorꢀtheꢀDCRꢀsenseꢀﬁlterꢀ

capacitor of phase 2, as shown in Figure 4.

2) Connect CSP2 to the IOUT pin of the smart power stage (MAX15515). A resistor across

CSP2 and CSN2 sets the current-sense gain, as shown in Figure 3.

See the Current Sense section. To disable phase 2, short CSP2 to BIAS.

24

—

CSP2

EP

Exposed Pad. The substrate of the controller is internally connected to the exposed pad. Connect

EP to the ground plane through multiple vias to maintain low thermal impedance.

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

R

TON

5V TO 20V

OUTPUT

1% 0402

13

10

11

18

C

IN

5V BIAS

BIAS

I.C.

TON

C

VCC

2.2µF 6V

R

0Ω

BST1

PWR

3

4

2

8

V

5V

BST

DD

I.C.

C

BST1

0.1µF

MAX15492

22

12

DH

GND

N.C.

EN

L1

6

7

15

16

1

5

DRVPWM1

DRVSKP

PWM

SKIP

LX

DL

VR_ENABLE

1.8V

6

EP

V

TT

C

VCC

2.2µF 6V

PWR

20

21

CSP1

CSN1

OUTPUT

R

INT

10kΩ

5% 0402

R

I2C

1kΩ

C

OUT

R

0Ω

BST1

MAX15569

5V

V

IN

3

4

2

8

5% 0402

V

BST

DD

C

BST1

0.1µF

19

8

MAX15492

INT

DH

GND

2

I C

L2

SDA

SCL

6

7

INTERFACE

17

1

5

DRVPWM2

PWM

SKIP

LX

DL

5

THERM

EP

PWR

24

23

CSP2

CSN2

NTC

THERM

PWR

R

FBAC

1% 0402

4

2

3

1

FEEDBACK FILTERS

IMON

FBAC

FB

C

IMON

0402

FBAC

0402

R

R10 10Ω

5% 0402

FB

IMON

1% 0402

REMOTE OUTPUT SENSE

REMOTE GROUND SENSE

7

AGND

PGND

C

FB

R11 10Ω

5% 0402

1nF 6V

0402

14

GNDS

PWR

C

GNDS

1nF 6V

0402

POWER GROUND

ANALOG GROUND

PWR

EP

AGND

Figure 1. MAX15569 Typical Application Circuit (with MAX15492 Driver and MOSFET)

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

Table 1. Components for Typical Application Circuit

2-PHASE DESIGN EXAMPLE

TYPE

REF

(1MHz OPERATION)

OPERATING CONDITIONS

Input Voltage

V

5V to 20V

IN

Output Voltage

Output Current

Load Transient

Current Limit

V

1V

OUT

I

20A (max), 14A RMS

OUT

DI

25A

40A

1MHz

2

OUT

I

OCP

Switching Frequency

Number of Phases

COMPONENTS

TON

f

SW

N

PH

R

200kΩꢀ1%

TON

L

0.2µH/9.5mΩ/9.5Aꢀinductor

(4.06mm x 4.55mm x 1.2mm)

Vishay IHLP-1616AB-1A

Inductor

MOSFETꢀDriver

DRV

MAX15492

—

High-Side MOSFET

N

H

Low-Side MOSFET

N

L

Current Sense

R

—

CS

Bulk Output Capacitors (Mid Frequency)

Ceramic Output Capacitors (High Frequency)

Input Capacitors

C

—

OUT

20 x 22µF ceramic capacitors

2 x 10µF, 16V X5R ceramic capacitors

C

IN

R

= R ꢀ=ꢀ1kΩꢀ1%

FB

FBAC

C

= 4.7nF

FBAC

FBꢀDroopꢀSetting

—

AC droop = -1.5mV/A

DCꢀdroopꢀ=ꢀ0mV/A

R

ꢀ=ꢀ5.62kΩꢀ1%

IMON

C

R

C

,

IMON

= 47nF

IMON

(260µs time constant)

100kΩ,ꢀ5%ꢀNTCꢀthermistor

β = 4250K (0603)

THERM NTC

R

Murata NCP18WF104J03RB

TDKꢀNTCG163JF104Jꢀ(0402)ꢀor

Panasonic ERT-J1VR104J

THERM

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

CSP2

CSN2

ILIM

BIAS

DRVPWM2

PHASE 2

CONTROL

CSP1

CSN1

Q

TRIG

MAX15569

IMON

FBAC

ON-TIME

CSP2

CSN2

CSP1

CSN2

G

m(CCI)

ONE-SHOT

(PHASE 2)

CSP2

CSN2

∑

TRIG

Q

m(CCI)

MINIMUM

OFF-TIME

ONE-SHOT

FB

ONE-SHOT

ON-TIME

CSP1

CSN1

ILIM

TON

(PHASE 1)

Q

TRIG

BIAS

R

S

DRVPWM1

DRVSKP

BIAS

EN

Q

SET

TARGET

2

1

BIAS

DAC

PHASE

SELECT

TRIG

TARGET

CCV

THERM

INT

THERM

AMP

SKIP

PHASE CONTROL

SLOPE

DIGITAL

CORE

SCL

SDA

FB

SET DAC

TARGET

GNDS

AGND

PGND

Figure 2. Functional Block Diagram

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

For SETVOUT voltages below 0.9V, the device uses a

fixed 0.9V instead to determine the on-time. Switching

frequency is reduced, improving low-voltage efficiency.

Detailed Description

For system power management, the MAX15569 controller

includes a current gauge and thermal status (VRHOT)

that can be monitored over the I C interface. In addition,

the device’s multiple fault-protection features include:

Output overvoltage protection (OVP), undervoltage

protection (UVP), and thermal protection. When any of

these fault-protection features detect a fault condition, the

controller shuts down.

2

t

(0.9V+0.075V)

SW

t

=

ON

V

IN

The one-shot for the second phase varies the on-time in

response to the input voltage and the difference between

the main and the second inductor currents. Two identi-

cal transconductance amplifiers integrate the difference

between the first and second current-sense signals. The

respective error signals are used to correct the on-time

of the high-side MOSFETs for the second phase and to

maintain current balanced between the two phases.

Free-Running Constant On-Time Controller

with Input Feed-Forward

The QuickTune-PWM control architecture consists of a

pseudo-fixed frequency, constant on-time, and current-

mode regulator with voltage feed-forward (Figure 2). The

control algorithm is simple; the high-side switch on-time is

determined solely by a one-shot, whose period is inversely

proportional to input voltage and directly proportional to

the feedback voltage or the difference between the main

and secondary inductor currents (see the On-Time One-

Shot section). Another one-shot sets a minimum off-time.

On-times translate only roughly to switching frequencies.

The on-times guaranteed in the Electrical Characteristics

section are influenced by parasitics in the conduction

paths and propagation delays. The following equation

shows the effect of the propagation delays on t

:

ON

t

(V +0.075V)

SW FB

t

=

+ t

- t

ON

D(OFF) D(ON)

V

IN

The on-time one-shot triggers when the inverting input

to the error comparator falls below the target voltage,

the inductor current of the selected phase is below the

valley current-limit threshold, and the minimum off-time

one-shot times out. The regulator maintains 180° out-of-

phase operation by alternately triggering the two phases

after the error comparator drops below the output-voltage

set point.

where t

is the delay from the falling edge of the PWM

D(OFF)

signal to the to the time that the high-side MOSFET turns

off. t is the delay from the rising edge of the PWM

D(ON)

signal to the time that the high-side MOSFET turns on.

For loads above the critical conduction point, where the

dead-time effect (LX flying high and conducting through

the high-side FET body diode) is no longer a factor, the

actual switching frequency (per phase) is:

Switching Frequency

Connect a resistor (R

) between TON and the input

TON

(V

+ V

)

OUT

DIS

supply (V ) to set the switching period (t

= 1/f ) per

f

=

IN

SW

t

(V + V

+ V

)

CHG

phase using the following equation:

ON IN

DIS

where V

is the sum of the parasitic voltage drops in the

t

(R

+ 6.5kΩ) x 5pF

DIS

SW

TON

inductor discharge and charge paths, including MOSFET,

High-frequency (600kHz to 1.4MHz) operation optimizes

the application for the smallest component size. A 200kΩ

resistor sets a typical operating frequency of 1MHz.

inductor, and PCB resistances; V is the sum of the

CHG

parasitic voltage drops in the inductor charge path, includ-

ing high-side switch, inductor, and PCB resistances; and

On-Time One-Shot

t

is the on-time as determined in the prior equation.

ON

The device contains fast, low-jitter, adjustable one-shots

that set the respective high-side MOSFET on-times

through the DRVPWM_ outputs. The one-shot for the

main phase varies the on-time in response to the input

180° Out-of-Phase Operation

The two phases in the device operate 180° out-of-phase

to minimize input and output filtering requirements,

reduce EMI, and improve efficiency. This effectively low-

ers component count—reducing cost, board space, and

component power requirements—making this device

ideal for high-power applications. The device shares the

current between two phases that operate 180° out-of-

phase under steady-state conditions.

and feedback voltage (V ). V

equals the SETVOUT

FB

voltage in steady-state. The main high-side switch

on-time is inversely proportional to the input voltage as

measured at V , and proportional to V

:

IN

FB

t

(V +0.075V)

SW FB

t

=

(Ignoring propagation delays)

ON

V

IN

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

The instantaneous input current of each phase is

effectively reduced, resulting in reduced input-voltage

ripple, ESR power loss, and RMS ripple current (see

the Input Capacitor Selection section). Therefore, the

same performance can be achieved with fewer or less-

expensive input capacitors.

Current Sense

The device senses the inductor current of each phase,

allowing the use of current-sense resistors, inductor

DCR,ꢀorꢀtheꢀcurrent-senseꢀsignalꢀprovidedꢀbyꢀtheꢀexternalꢀ

power stage (MAX15515). Low-offset amplifiers are used

for current balance, load-line gain, current monitor, and

current limit.

5V Bias Supply

The QuickTune-PWM controller requires an external 5V

bias supply in addition to the system supply. Typically,

the system has a regulated 5V bias for interface (USB)

or hard-drive support that can be used. The maximum

current drawn from the 5V bias supply is provided in the

Electrical Characteristics section. If the 5V bias supply is

powered up prior to the system supply, the enable signal

(EN going from low to high) should be delayed until the

system voltage is present to ensure startup.

Power Stage Current-Sense Support

(MAX15515 Only)

The MAX15515 features a transconductance current-

sense amplifier with a current monitor output (I

an output current of:

) with

OUT

I

= A × I

LX

OUT

-5

where A is 10 (typ) and I is the inductor current. I

LX

OUT

is internally temperature compensated and therefore,

external temperature compensation is not required. Refer

to the MAX15515 data sheet for more information.

A resistor between CSP_ and CSN_ (see Figure 3) sets

the gain of the current-sense signal to the controller.

CSP1

IMON

BST

C

L

MAX15515

BST

R

ILIM1

LX

CSN1

CSP2

IMON

BST

C

MAX15515

R

ILIM2

MAX15569

LX

C

OUT

CSN2

FB

R

DROOP

FBAC

(MAX15515) – WITH DC LOAD REGULATION

A) MAX15569 AND SMART POWER STAGE

CSP1

IMON

BST

C

BST

L

MAX15515

R

ILIM1

LX

CSN1

CSP2

IMON

BST

C

BST

R

ILIM2

MAX15515

MAX15569

LX

CSN2

FB

C

OUT

R

FB

C

FB

R

FBAC

(MAX15515) – NO DC LOAD REGULATION

B) MAX15569 AND SMART POWER STAGE

Figure 3. The MAX15569 Using the MAX15515 Internal Current-Sense Method

Maxim Integrated

│ 16

www.maximintegrated.com

MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

INDUCTOR

R

BST

LX

C

BST

DCR

L

R2

R

=

R

CS

DCR

+

R1 + R2

C

OUT

MAX15569

POWER

STAGE

L

1

=

R1

R2

DCR

C

R1 R2

EQ

C

EQ

FOR THERMAL COMPENSATION:

R2 SHOULD CONSIST OF AN NTC RESISTOR

IN SERIES WITH A STANDARD THIN-FILM RESISTOR

CSP_

CSN_

A) LOSSLESS INDUCTOR SENSING

SENSE RESISTOR

R

BST

LX

C

BST

SENSE

L

ESL

L

ESL

C

R

=

EQ EQ

R

SENSE

MAX15569

POWER

STAGE

R1

C

EQ

CSP_

CSN_

B) OUTPUT SERIES RESISTOR SENSING

Figure 4. Sense Resistor and DCR Current-Sense Methods

inputs (I

and I

), choose R1||R2 to be less than

Inductor DCR and Sense Resistor Current Sense

Usingꢀ theꢀ DCꢀ resistanceꢀ (R ) of the output inductor

CSP_

CSN_

2kΩꢀ andꢀ useꢀ theꢀ previousꢀ equationꢀ toꢀ determineꢀ theꢀ

sense capacitance (C ). Choose capacitors with 5%

tolerance and resistors with 1% tolerance specifications.

Temperature compensation is recommended for this cur-

rent-sense method. See the Load-Line Amplifier (Steady

State and AC Droop) section for detailed information.

DCR

EQ

allows higher efficiency compared to using a current-

sense resistor. The initial tolerance and temperature

coefficientꢀ ofꢀ theꢀ inductor’sꢀ DCRꢀ mustꢀ beꢀ accountedꢀ

for in the output-voltage droop-error budget and current

monitor. This current-sense method uses an RC filter

network to extract the current information from the output

inductor (see Figure 4).

When using a current-sense resistor for accurate output

load-line control, the circuit requires a differential RC filter

to eliminate the AC voltage step caused by the equivalent

series inductance (L

(see Figure 4). The ESL-induced voltage step might affect

the average current-sense voltage. The time constant

of the RC filter should match the L

constant formed by the parasitic inductance of the

current-sense resistor:

The RC network should match the time constant of the

) of the current-sense resistor

ESL

inductor (L/R

):

DCR

R2





R

=

R

DCR

CS







R1+ R2

/R

time



ESL SENSE

and:

L

1





L

R

=

+

ESL

DCR









= C

R

EQ EQ

C

R1 R2

EQ

R

SENSE

where R

is the required current-sense resistance and

CS

where L

current-sense resistor, R

resistance value, and C

matching components.

is the equivalent series inductance of the

ESL

R

ꢀ isꢀ theꢀ inductor’sꢀ seriesꢀ DCꢀ resistance.ꢀ Useꢀ theꢀ

DCR

is the current-sense

SENSE

typical inductance and R

inductor manufacturer. To minimize the current-sense

error, due to the leakage current of the current-sense

values provided by the

DCR

and R

are the time-constant

EQ

Maxim Integrated

│ 17

www.maximintegrated.com

MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

The positive valley current-limit threshold is preset for the

MAX15569. See the Electrical Characteristics section.

Current Balance

The device integrates the difference between the current-

sense voltages and adjusts the on-time of the second

phase to maintain current balance. The current balance

relies on the accuracy of the current-sense signals across

theꢀ current-senseꢀ resistor,ꢀ inductorꢀ DCR,ꢀ orꢀ providedꢀ

by the power stage (MAX15515). With active current

balancing, the current mismatch is determined by the

current-sense element values and the offset voltage of the

transconductance amplifiers:

Current Limit Using Inductor DCR

or Sense Resistors

Whenꢀ usingꢀ senseꢀ resistorsꢀ orꢀ inductorꢀ DCRꢀ asꢀ

current-sensing elements, calculate the required sense

resistance (R

) with the following equation:

SENSE

V

LIM(MIN)

R

=

SENSE

I

LX(VALLEY)

V

where I

is the inductor valley current at OCP,

is 38mV ±3mV.

LX(VALLEY)

OS(IBAL)

I

= I

-I

=

OS(IBAL)

LMAIN LSEC

and V

ILIM(MIN)

R

SENSE

Carefully observe the PCB layout guidelines to ensure

that noise and trace errors do not corrupt the current-

sense signals seen by the current-sense inputs (CSP_,

CSN_).

where R

CSP_, CSN_, and V

is the equivalent sense resistance across

SENSE

is the current-balance off-

OS(IBAL)

set specification in the Electrical Characteristics section.

The worst-case current mismatch occurs immediately

after a load transient due to inductor value mismatches,

resulting in different dI/dt for the two phases. The time it

takes for the current-balance loop to correct the transient

imbalance depends on the mismatch between the

inductor values and switching frequency.

Current Limit with the MAX15515 Current Sense

When using the current-sensing method of the MAX15515,

calculate the CSP_ - CSN_ resistor (R

) using the

CSP_

following equation:

V

LIM(MIN)

R

=

CSP_

A×I

LX(VALLEY)

Current Limit

The current-limit circuit employs a “valley” current-sensing

algorithm that senses the voltage across the current-

sense inputs (CSP_ and CSN_). If the current-sense

-5

where A is 10 , I

is the inductor valley current

is 38mV ±3mV.

LX(VALLEY)

at OCP, and V

ILIM(MIN)

Current Monitoring (IMON)

signal (V

, V

or V

, V

) of the selected

CSP2 CSN2

CSP1 CSN1

phase is above the current-limit threshold (V

), the

The device includes a current monitoring function. A

simplified data-acquisition system is employed to convert

the analog signals from the current-sense inputs to 8-bit

values in the IMON register (see Figure 5).ꢀTheꢀADCꢀcon-

verter filters the current-sense signal by averaging over

eight samples. The acquisition rate is 100µs. The content

of the IMON register is updated every 400µs.

ILIM

PWM controller does not initiate a new cycle for that

phase until its inductor current drops below the valley

current-limit threshold. Since only the valley current is

actively limited, the actual peak current is greater than

the current-limit threshold by an amount equal to 1/2 the

inductor ripple current:

DI

2

The device includes a unidirectional transconductance

amplifier that sources current proportional to the posi-

tive current-sense voltage. The IMON output current is

defined by:

I

=I

+

LOAD

LX PEAK

(

)

DI

2

I

=I

-

LOAD

LX VALLEY

(

)

I

= G

x ∑(V

- V

)

IMON

m(IMON)

CSP_

CSN_

where :

= G

x I

x R

LOAD SENSE

m(IMON)

t

(V - V

)

OUT

ON IN

DI =

where G

is the transconductance-amplifier

m(IMON)

L

gain, as defined in the Electrical Characteristics section

(5.12µA/mV typ).

where L is the inductance value, t

is the on-time of

ON

the high-side MOSFET, V

is the output voltage, and

An external resistor (R

)ꢀbetweenꢀIMONꢀandꢀAGNDꢀ

OUT

IMON

V

IN

is the input voltage. Therefore, the exact current-limit

sets the current monitor output voltage:

= I x R

IMON

characteristic and maximum load capability are functions

of the current-sense resistance, inductor value, and

battery voltage.

V

IMON

Maxim Integrated

│ 18

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

MAX15569

IMON REGISTER

8-BIT DAC

R

C

= 2.56V/(R

x G

x I

)

IMON

SENSE_

m(IMON) OUT(MAX)

0 TO 2.56V RANGE

x R

= 150µs

IMON

CSP1

CSN1

I

IMON

G

m(IMON)

R

I

IMON

SENSE1

(V

- V

)

V

IMON

CSP1 CSN1

NETWORK

R

C

IMON

CSP2

CSN2

R

SENSE2

(V

- V

)

CSP2 CSN2

NETWORK

3.2V

IMON CLAMP

Figure 5. IMON Network

where R

is the value of the effective current-sense

V

= V

- (R

× I

)

SENSE

OUT

TARGET

DROOP

FBAC

resistance. Choose R

full load current.

so that V

is 2.56V at the

IMON

where the target voltage (V

Nominal Output-Voltage Selection section, and FBAC

) is defined in the

TARGET

C

is the IMON averaging capacitor. IMON is

amplifier’s output current (I ) is determined by the

FBAC

IMON

sampled every 400µs. Choose C

such that R

current-sense voltage:

IMON

x C

(see Figure 5).

gives a time constant of approximately 150µs

IMON

I

= G

ꢀ×ꢀΣ(V

- V

)

FBAC

m(FBAC)

CSP_

CSN_

where G

= 1.2µA/mV (typ), as defined in the

m(FBAC)

The IMON voltage is internally clamped to a maximum

3.2V (typ), preventing the IMON output from exceeding

the IMON voltage rating even under overload or short-

circuit conditions. IMON is high impedance when in

shutdown.

Electrical Characteristics section. Since the feedback

voltage (V ) is regulated to the SETVOUT voltage, the

output voltage changes in response to the FBAC current

) to create a load-line with accuracy defined by the

characteristics of the R

FB

(I

FBAC

network and G

.

DROOP

m(FBAC)

Feedback Adjustment Ampliﬁer

TheꢀdeviceꢀsupportsꢀflexibleꢀcombinationsꢀofꢀACꢀandꢀDCꢀ

load-lines:ꢀAnꢀACꢀload-lineꢀ>ꢀDCꢀload-line,ꢀanꢀACꢀload-lineꢀ

=ꢀDCꢀload-line,ꢀandꢀanꢀACꢀload-lineꢀ<ꢀDCꢀload-line.

Load-Line Ampliﬁer (Steady State and AC Droop)

The device includes a transconductance amplifier for

controlling the load-line regardless of the sense imped-

ance value. The input signal of the amplifier is the sum of

●ꢀ The effective impedance (Z

) between the output

FBAC

of the load-line transconductance amplifier (FBAC)

and the positive side of the remote-sensed output

voltage sets the transient AC droop.

the current-sense voltages (V

, V

, and V

,

CSP1 CSN1

CSP2

V

CSN2

), which differentially sense the current-sense volt-

age. See Figure 6.

●ꢀ Theꢀeffectiveꢀimpedanceꢀ(Z ) between the feedback-

FB

sense input (FB) and the positive side of the feedback

remoteꢀsenseꢀsetsꢀtheꢀstaticꢀ(DC)ꢀdroop.

The AC-droop amplifier output (FBAC) connects to the

remote-sense point of the output through a resistor network

(R

)ꢀthatꢀsetsꢀtheꢀDCꢀandꢀACꢀcurrent-loopꢀgain:

DROOP

Maxim Integrated

│ 19

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

●ꢀ A capacitor from FBAC to FB (C

) couples the AC

outputꢀ(forꢀACꢀdroop)ꢀorꢀtheꢀFBꢀinputꢀ(forꢀDCꢀdroop)ꢀandꢀ

the positive side of the remote-sensed output voltage.

See Table 2ꢀforꢀAC-ꢀandꢀDC-droopꢀ settingsꢀcircuitꢀcon-

figuration.

FBAC

ripple from the output of the load-line transconduc-

tance amplifier to the feedback sense input.

•ꢀ An integrator on FB corrects for output ripple and

ground-sense offset (see Figure 6).

Whenꢀ theꢀ inductor’sꢀ DCRꢀ isꢀ usedꢀ asꢀ theꢀ current-senseꢀ

element, the current-sense inputs should include an NTC

thermistor to minimize the temperature dependence of

theꢀload-lineꢀvariationꢀdueꢀtoꢀtheꢀDCRꢀtemperatureꢀcoef-

ficient. FBAC and FB are high impedance in shutdown.

When the device is used with differential current sensing:

R

ꢀ≈ꢀR

× R

× G

LL

DROOP

SENSE

m(FBAC)

where R

is the load-line, R

is the effective

LL

SENSE

current-sense resistance across CSP_ and CSN_.

is the effective resistance between the FBAC

R

DROOP

Z

x I

SETS THE AC LOAD-LINE

FBAC FBAC

MAX15569

C

x R

= t TO (10 x t

DROOP SW

)

FBAC

SW

RIPPLE-

COMPENSATION

CAPACITOR

R

DROOP

I

R

FBAC

OUTPUT

C

FBAC

FB

Σ(CSP_ - CSN_)

R

FB

C

10Ω

FBAC

R

OUT

10Ω

FBS

TO ERROR

AMPLIFIER

CPU V

CC

SENSE

C

FB

1nF

Z

x I

SETS THE STATIC LOAD-LINE

FB FBAC

10Ω

GNDS

CPU GND

SENSE

C

GNDS

1nF

HIGH-FREQUENCY CATCH RESISTORS

FILTER

SO FB REMAINS

CLOSED LOOPED

WITHOUT CPU

PRESENT

Figure 6. FB Network (Load-Line Control and Remote Sensing)

Table 2. AC-Droop and DC-Droop Settings

DC LOAD-LINE AC LOAD-LINE

R

C

FBAC

NOTE

= R

DROOP_AC

DROOP_DC

FB

(mV/A)

0

R

║R

*

0Ω

Open

C

R

*

FBS

LL_AC

FBAC

FBS

FBAC

R

* + R

R

*

FBS

FB

FBS

R

C

DCꢀload-lineꢀ<ꢀACꢀload-line

DCꢀload-lineꢀ=ꢀACꢀload-line

LL_DC

FB

(R

= open)

(R

= open)

FBAC

R

Open

R *

FBS

0Ω

Open

LL

*See Figure 6.

Maxim Integrated

│ 20

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

ground-sense adjustment (V

following equation:

), as defined in the

Differential Output-Voltage Remote Sense

GNDS

The device includes differential, remote-sense inputs

to eliminate the effects of voltage drops along the PCB

traces and through the power pins of the processor. The

feedback-sense node connects to the load-line resistor/

V

= V - V

+ V

TARGET

FB

DACꢀ GNDS

where V

is the selected output voltage.

DAC

On startup, the device slews the target voltage from

ground to the default 1V boot voltage unless a different

voltage code is selected before EN is pulled high.

capacitor network (R

/C

). The ground-sense

DROOP FBAC

(GNDS)ꢀ inputꢀ connectsꢀ toꢀ anꢀ amplifierꢀ thatꢀ adjustsꢀ theꢀ

feedback voltage to counteract the voltage drop in the

ground plane. Connect the load-line resistor (R

)

DROOP

Dynamic Output-Voltage Transitions

andꢀ ground-senseꢀ (GNDS)ꢀ inputꢀ directlyꢀ toꢀ theꢀ remote-

sense outputs of the processor, as shown in Figure 6. The

correction range is bounded to less than ±200mV. The

remote-sense lines draw less than ±0.5µA to minimize

the offset errors.

The device’s transition time depends on the slew-rate

setting, the selected SETVOUT voltage difference, and

the accuracy of the slew-rate controller (see the slew rate

section in the Electrical Characteristics section). The slew

rate is not dependent on the total output capacitance, as

long as the required transition current plus existing load

currentꢀremainsꢀbelowꢀtheꢀcurrentꢀlimit.ꢀForꢀdynamicꢀVIDꢀ

Steady-State Integrator Ampliﬁer

The device utilizes internal integrator amplifiers that force

theꢀ DCꢀ averageꢀ ofꢀ theꢀ FBꢀ voltageꢀ toꢀ equalꢀ theꢀ targetꢀ

voltage,ꢀ allowingꢀ accurateꢀ DCꢀ output-voltageꢀ regula-

tion regardless of the output voltage. The integrator is

designed to correct for the steady-state offsets/errors.

transitions, the transition time (t ) is given by:

TRAN

V

-V

NEW OLD

t

=

TRAN

dV

TARGET

dt

(

)

Nominal Output-Voltage Selection

where dV

/dt is the slew rate (register 0x06h),

TARGET

The nominal no-load output voltage (V

) is defined

TARGET

V

is the original output voltage, and V

is the new

OLD

NEW

by the selected voltage reference, plus the remote

target voltage (see Table 3).

Table 3. Output-Voltage Selection

LINE

0

BIT 7*

X

BIT 6

0

BIT 5

0

BIT 4

0

BIT 3

0

BIT 2

0

BIT 1

0

BIT 0

0

HEX

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

VOLTAGE

0.000

0.500

0.510

0.520

0.530

0.540

0.550

0.560

0.570

0.580

0.590

0.600

0.610

0.620

0.630

0.640

0.650

0.660

1

X

0

1

2

X

0

1

0

3

X

0

1

4

X

0

1

0

5

X

0

1

0

1

6

X

0

1

0

7

X

0

1

8

X

0

1

0

9

X

0

1

0

1

10

11

12

13

14

15

16

17

X

0

1

0

1

0

X

0

1

0

1

X

0

1

0

X

0

1

0

1

X

0

1

0

X

0

1

X

0

1

0

X

0

1

0

1

Maxim Integrated

│ 21

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

Table 3. Output-Voltage Selection (continued)

LINE

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

BIT 7*

X

BIT 6

0

BIT 5

0

1

BIT 4

1

0

1

BIT 3

0

1

0

1

0

BIT 2

0

1

0

1

0

1

0

1

0

1

BIT 1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

BIT 0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

HEX

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

VOLTAGE

0.670

0.680

0.690

0.700

0.710

0.720

0.730

0.740

0.750

0.760

0.770

0.780

0.790

0.800

0.810

0.820

0.830

0.840

0.850

0.860

0.870

0.880

0.890

0.900

0.910

0.920

0.930

0.940

0.950

0.960

0.970

0.980

0.990

1.000

1.010

1.020

1.030

1.040

Maxim Integrated

│ 22

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

Table 3. Output-Voltage Selection (continued)

LINE

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

BIT 7*

X

BIT 6

0

1

BIT 5

1

0

BIT 4

1

0

1

BIT 3

1

0

1

0

1

BIT 2

0

1

0

1

0

1

0

1

0

1

BIT 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

BIT 0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

HEX

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

40h

41h

42h

43h

44h

45h

46h

47h

48h

49h

4Ah

4Bh

4Ch

4Dh

4Eh

4Fh

50h

51h

52h

53h

54h

55h

56h

57h

58h

59h

5Ah

5Bh

5Ch

5Dh

VOLTAGE

1.050

1.060

1.070

1.080

1.090

1.100

1.110

1.120

1.130

1.140

1.150

1.160

1.170

1.180

1.190

1.200

1.210

1.220

1.230

1.240

1.250

1.260

1.270

1.280

1.290

1.300

1.310

1.320

1.330

1.340

1.350

1.360

1.370

1.380

1.390

1.400

1.410

1.420

Maxim Integrated

│ 23

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

Table 3. Output-Voltage Selection (continued)

LINE

94

BIT 7*

X

BIT 6

1

BIT 5

0

1

BIT 4

1

0

1

BIT 3

1

0

1

0

1

BIT 2

1

0

1

0

1

0

1

0

1

BIT 1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

BIT 0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

HEX

5Eh

5Fh

60h

61h

62h

63h

64h

65h

66h

67h

68h

69h

6Ah

6Bh

6Ch

6Dh

6Eh

6Fh

70h

71h

72h

73h

74h

75h

76h

77h

78h

79h

7Ah

7Bh

7Ch

7Dh

7Eh

7Fh

VOLTAGE

1.430

1.440

1.450

1.460

1.470

1.480

1.490

1.500

1.510

1.520

1.530

1.540

1.550

1.560

1.570

1.580

1.590

1.600

1.610

1.620

1.630

1.640

1.650

1.660

1.670

1.680

1.690

1.700

1.710

1.720

1.730

1.740

1.750

1.760

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

*Bit 7 is ignored (don’t care), but listed here to match the VOUTMAX register.

X = Don’t care.

Note: DAC codes above 1.6V are not advised due to proximity to the overvoltage threshold.

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

Soft-start uses the slow slew rate, as set by the default

setting in the SRREG register, which is a fraction of the

fast slew rate. See the slew-rate accuracy specification in

the Electrical Characteristics section. The average induc-

tor current per phase that is required to make an output-

voltage transition is given by:

threshold between pulse-skipping PFM and non-skipping

PWM operation to coincide with the boundary between

continuous and discontinuous inductor-current operation.

The PFM/PWM crossover occurs when the load current of

each phase is equal to 1/2 the peak-to-peak ripple current

that is a function of the inductor value. Even for wide 4.5V

to 14V input voltage ranges, this crossover is relatively

constant, with only a minor dependence on the input volt-

age due to the typically low duty cycles. The total load cur-

C

dV

OUT

TARGET

dt

I =

×

L

N

PH

rent at the PFM/PWM crossover threshold (I

is approximately:

))

LOAD(SKIP

where dV

the total output capacitance, and N

active phases.

/dt is the required slew rate, C

is

TARGET

OUT

is the number of

PH

(V -V

)t

IN OUT ON

2L

I

=

LOAD(SKIP)

At the beginning of an output-voltage transition, the

device blanks the INT, so the open-drain output enters a

high-impedance state during output-voltage transitions.

The controller releases the INT output approximately

4µs (typ) after the slew-rate controller reaches the target

output voltage.

Power-Up Sequence (POR, UVLO)

Power-on reset (POR) occurs when V

and V

TT

BIAS

rise above approximately 2V. POR resets the fault

latch and loads the default register settings. The V

UVLO circuitry inhibits switching until V

BIAS

rises

BIAS

Automatic Pulse-Skipping Operation

above 4.5V. The controller powers up the reference

once the system enables the controller, V is above

BIAS

The device automatically operates with a 2-phase pulse-

skipping control scheme. A logic-low level on DRVSKP

enables the zero-crossing comparator of the driver

(MAX17492) or power stage (MAX15515). Therefore,

these devices disable their low-side MOSFETs when they

detect “zero” inductor current. This keeps the inductor

from discharging the output capacitors and forces the

controller to skip pulses under light-load conditions to

avoid overcharging the output.

4.5V, and EN is driven high (see Figure 2). With the

reference in regulation, the controller ramps up to the

selected output voltage (register 0x07h) at the selected

slow slew rate (register 0x06h)

After this initialization, the PWM controller begins

switching:

V

BOOT

t

=

TRAN(START)

(dV

/dt)

TARGET

IfꢀtheꢀsystemꢀchangesꢀtheꢀVIDꢀcodeꢀtoꢀaꢀlowerꢀvoltage,ꢀtheꢀ

device drives DRVSKP high to disable the pulse-skipping

mode. This allows the regulator to actively discharge the

output at the programmed slew rate.

where dV

/dt is the slew rate. The soft-start slew

TARGET

rate is the slow slew rate set by the default setting in the

SRREG register. The soft-start circuitry does not use a

variable current limit, so full output current is available

immediately.

To disable pulse-skipping mode so the regulator continu-

ally operates in forced-PWM operation, leave DRVSKP

unconnected and connect the pulse-skipping control input

on the driver or power stage to ground.

Interrupt (INT)

The device provides an active-low interrupt output (INT)

to indicate that the startup sequence is complete and

the output voltageꢀ hasꢀ movedꢀ toꢀ theꢀ programmedꢀ VIDꢀ

value. This signal is intended for system monitoring of

the device. INT remains high impedance during normal

DC-DCꢀoperation.ꢀTheꢀcontrollerꢀassertsꢀINT to alert the

system of an alarm event or if a fault condition occurs.

See the Alarms and Fault Protection (Latched) sections

for details (and Figure 7).

Automatic Pulse-Skipping Switchover

In pulse-skipping mode, an inherent automatic switchover

to PFM takes place at light loads. This switchover is affect-

ed by a comparator that truncates the low-side switch

on-time at the inductor current’s zero crossing. The zero-

crossing detection is designed into the MAX17492 driver

and the MAX15515 power stage. They sense the inductor

current across the low-side MOSFET. Once the LX volt-

age crosses the zero-crossing comparator threshold, the

low-side MOSFET turns off. This mechanism causes the

Use an external pullup resistor between INT and 3.3V to

deliver a valid logic-level output.

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

t

≥ = 0ns

EN

V

BIAS

V

TT

ENABLE

INT

V

OUT

t

SS

STRT

t

SS

CAL

Figure 7. Startup Sequence

The fixed 23mV OC_ALARM threshold is 15mV

lower than the valley current-limit threshold to provide

sufficientdesignmarginbeforetheregulatorlimitstheoutput

current. Additionally, the controller includes a IMON

register that can be monitored by the system.

Alarms

Temperature Comparator (VRHOT)

The device features an independent comparator with

input at THERM. This comparator has an accurate thresh-

old of 0.5 x V

TheꢀNTCꢀresistanceꢀdropsꢀtoꢀ5.68kΩꢀwhenꢀtheꢀtempera-

ture reaches +100°C. The NTC forms a divider with the

internalꢀ 5.35kΩꢀ pullupꢀ resistance,ꢀ soꢀ theꢀ voltageꢀ dropsꢀ

.ꢀUseꢀaꢀ100kΩꢀNTCꢀwithꢀaꢀβꢀofꢀ4250K.ꢀ

BIAS

Output-Code Violation (VOUTMAX)

The controller includes a maximum output register

(VOUTMAX register 0x02h) to protect against target

output voltage codes that could violate the absolute maxi-

mum rating of the load. The value of this configuration

register limits the output range. If a target output voltage

is loaded into register 0x07h, the regulator sets the appro-

priate status bit. If the warning is not masked, the control-

ler asserts the INT output to alert the system to the over-

current condition. The output voltage attempts to ramp to

the new target, but the regulator effectively clamps the

output to the VOUTMAX voltage to avoid an overvoltage

below the 0.5 x V

threshold. VRHOT is then asserted.

BIAS

Theꢀinternalꢀ5.35kΩꢀresistorꢀisꢀdisconnectedꢀinꢀshutdown,ꢀ

saving power.

Overcurrent Warning (OC)

The device includes an overcurrent-warning threshold

that samples the phase 1 current-sense signal before

each phase 1 on-time. When the CSP1 - CSN1 voltage

exceedsꢀtheꢀ23mVꢀ(typ)ꢀthreshold,ꢀtheꢀstatusꢀbitꢀ(D2)ꢀinꢀ

register 0x04h) is asserted. If the warning is not masked,

the controller asserts the INT output to alert the system to

the overcurrent condition.

2

condition. See the I C Commands and Registers section

for additional details.

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

DRVPWM_ꢀoutputsꢀgoꢀtoꢀtheꢀhigh-impedanceꢀmodeꢀandꢀ

DRVSKP is pulled low.

Fault Protection (Latched)

TON Open-Circuit Protection

The TON input includes open-circuit protection to avoid

long, uncontrolled on-times that could result in an over-

voltage condition on the output. The device detects an

open-circuit fault if the TON current drops below 6µA

2

After the fault condition occurs, the I C interface remains

active so the STATUS register can be read to determine

what triggered the fault. Toggle EN or cycle power (BIAS)

below 1V to clear the fault latch. With the fault latch

cleared and the fault condition removed, the regulator

powers back up and the fault conditions are deasserted

in the STATUS register.

(typ) for any reason (e.g., the TON resistor (R

) is

TON

unpopulated, a high-resistance value is used, the input

voltage is low, etc.). Under these conditions, the device

stopsꢀswitchingꢀ(DRVPWM_ꢀoutputsꢀbecomeꢀhighꢀimped-

ance and DRVSKP is pulled low) and immediately sets

the fault latch.

Thermal-Fault Protection (TSHDN)

The device features an internal thermal-fault protec-

tion circuit. When the junction temperature rises above

+160°C, a thermal sensor sets the fault latch and

DRVPWM_ꢀbecomesꢀhighꢀimpedance.

Toggle EN or cycle power (BIAS) below 1V to clear the

fault latch and reactivate the controller. The TON open-

circuit fault is not indicated in the STATUS register.

2

After the fault condition occurs, the I C interface remains

active so the STATUS register can be read to determine

what triggered the fault. Toggle EN or cycle power (BIAS)

below 1V to clear the fault latch. With the fault latch

cleared, the regulator powers back up and the fault condi-

tions are deasserted in the STATUS register, as long as

the regulator has cooled by 15°C (typ).

Output Overvoltage Protection (OVP)

The OVP circuit is designed to protect the load against a

shorted high-side MOSFET by drawing high current and

activating the adapter or battery protection circuits. The

device continuously monitors the output for an overvolt-

age fault. An OVP fault is detected if the output voltage

exceedsꢀtheꢀVIDꢀDACꢀvoltageꢀbyꢀmoreꢀthanꢀ300mVꢀ(min),ꢀ

orꢀtheꢀfixedꢀ1.83Vꢀ(typ)ꢀthresholdꢀduringꢀaꢀdownwardꢀVIDꢀ

transition in skip mode.

External Driver and Disabling Phases

The device supports an external driver (MAX15515) for

bothꢀphases.ꢀTheꢀDRVPWM_ꢀoutputsꢀprovideꢀtheꢀsignalsꢀ

to trigger the drivers. Connecting CSP2 to BIAS of the

device disables the second phase.

Duringꢀ pulse-skippingꢀ operation,ꢀ theꢀ OVPꢀ thresholdꢀ

tracksꢀtheꢀVIDꢀDACꢀvoltageꢀasꢀsoonꢀasꢀtheꢀoutputꢀisꢀinꢀ

regulation; otherwise, the fixed 1.83V (typ) threshold is

used. When the OVP circuit detects an overvoltage fault,

theꢀDRVPWM_ꢀoutputsꢀbecomeꢀhighꢀimpedanceꢀandꢀtheꢀ

DRVSKP output is pulled high. OVP is disabled in the

standby power state (EN pulled low).

The device provides a pulse-skipping-mode control output

(DRVSKP) for the external driver control. DRVSKP goes

high when the controller detects an output overvoltage-

fault condition. DRVSKP is high during output-voltage

transitions. The DRVSKP output is unconnected in shut-

down.

2

After the fault condition occurs, the I C interface remains

active so the STATUS register can be read to determine

what triggered the fault. Toggle EN or cycle power (BIAS)

below 1V to clear the fault latch. With the fault latch

cleared and the fault condition removed, the regulator

powers back up and the fault conditions are deasserted

in the STATUS register.

2

I C Interface, Commands, Registers,

and Digital Control

A simplified register summery of the I C interface for the

device is shown in Table 4. The I C interface consists of

a high-speed transceiver capable of 3.4MHz data rate.

2

Output Undervoltage Protection (UVP)

Regulator Address

The device does not feature programmable addressing.

These devices are hard-coded with bus address 70h.

If the output voltage is 200mV (min) below the target volt-

age and stays below this level for 200µs (typ), the con-

troller activates the shutdown sequence. The regulator

turnsꢀonꢀaꢀ2kΩꢀdischargeꢀresistorꢀandꢀsetsꢀtheꢀfaultꢀlatch.ꢀ

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

2

Table 4. I C Command and Data Register Summary

MASTER

PAYLOAD

SLAVE

PAYLOAD

COMMAND

DESCRIPTION

HEX NAME

WRITE

—

READ

—

00h

01h

—

Reserved.

—

The maximum allowable output voltage (0.510V to 1.76V) that can

2

Conﬁguresꢀ

maximum output

code

Returns maximum be set by user. In case the I C interface receives a set voltage

02h

03h

VOUTMAX

—

output code

command higher than the VOUTMAX value, the regulator slews the

outputꢀtoꢀVOUTMAXꢀsetꢀvoltage.ꢀDefaultꢀisꢀ51hꢀ(1.3V).

—

Reserved.

BitsꢀD[5:0]ꢀofꢀthisꢀregisterꢀconsistꢀofꢀtheꢀVRHOTꢀﬂagꢀ(bitꢀD5),ꢀ

undervoltageꢀﬂagꢀ(bitꢀD4),ꢀovervoltageꢀﬂagꢀ(bitꢀD3),ꢀovercurrentꢀ

ﬂagꢀ(bitꢀD2),ꢀVOUTMAXꢀﬂagꢀ(bitꢀD1),ꢀandꢀINTꢀﬂagꢀ(bitꢀD0).ꢀBitsꢀ

D[7:6]ꢀareꢀnotꢀusedꢀandꢀreturnꢀ0.ꢀForꢀaꢀdetailedꢀdescription,ꢀseeꢀ

the Regulator Status (0x04h) section. The STATUS register is set

regardless of the MASK register (0x05) content.

Regulator

status

04h

05h

STATUS

MASK

—

Writing to this register prevents the assertion of the INT output when

theꢀspeciﬁcꢀfaultꢀorꢀalarmꢀisꢀmasked.ꢀThisꢀregisterꢀdoesꢀnotꢀmaskꢀ

the STATUS register indication.

Conﬁguresꢀmaskꢀ

Current mask

status

Defaultꢀisꢀ00hꢀ(noꢀmasking).

Writing to this register sets the slew rate (volt/second) of the

output voltage during the initial startup and dynamic output-voltage

transitions.

Defaultꢀisꢀ04hꢀ(4.5mV/µsꢀforꢀsoft-startꢀandꢀ9mV/µsꢀforꢀdynamicꢀ

transitions).

Conﬁguresꢀtheꢀ

output-voltage

slew rate

Returns the

output-voltage

slew rate

06h SLEW_RATE

The 07h command sets the target output voltage. The regulator

transitions up or down to the new output voltage 0.5µs after the

command is acknowledged.

Selects the

output code

Returns the

output code

07h

08h

SETVOUT

IMON

Defaultꢀisꢀ33hꢀ(1V).

Returns the output This register returns the average output current value. IMON is

—

current value

updated every 400µs.

2

Regulator Status (0x04h)

I C Commands and Registers

This register consists of six flags that determine the status

of the regulator in case of thermal warning, overvoltage

fault, undervoltage fault, output overcurrent warning, and

maximum output violation. The INTꢀbitꢀ(D0)ꢀisꢀassertedꢀinꢀ

case of any unmasked event. See Table 6 for bit descrip-

tions.

The device supports the following commands and

registers shown in Table 4.

VOUTMAX Control (0x02h)

This register is programmed by the bus master to the

maximum output voltage the regulator is allowed to sup-

port. Any attempts to set the SETVOUT above VOUTMAX

are acknowledged by setting the output voltage to the

content of the VOUTMAX register. The default value is

51h (1.3V). See Table 5 for bit descriptions.

1)ꢀ Theꢀ VRHOTꢀ bitꢀ (D5)ꢀ isꢀ setꢀ whenꢀ theꢀ voltageꢀ atꢀ

THERM pin goes below its nominal threshold (see the

Electrical Characteristics section).

2)ꢀ TheꢀUVꢀbitꢀ(D4)ꢀisꢀsetꢀwhenꢀtheꢀoutputꢀvoltageꢀdropsꢀ

200mV lower than SETVOUT value for 200µs.

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

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Serial I C Interface

Table 5. VOUTMAX (Maximum Output Voltage Allowed)

2

I C

DEFAULT

D7

D6

D5

D4

D3

D2

D1

D0

COMMAND

TYPE

0x02h

BIT

D7

0x51h

VMAX_7 VMAX_6 VMAX_5 VMAX_4 VMAX_3 VMAX_2 VMAX_1 VMAX_0

DESCRIPTION

NAME

VMAX_7

VMAX_6

VMAX_5

VMAX_4

VMAX_3

VMAX_2

VMAX_1

VMAX_0

R/W

Don’tꢀcareꢀbit.ꢀReturnsꢀ0ꢀwhenꢀread.

D6

MSB of the maximum allowed output voltage code.

D5

—

D4

—

D3

D2

D1

D0

LSB of the maximum allowed output voltage code. 10mV resolution.

Table 6. STATUS (Regulator Status)

2

I C

DEFAULT

D7

D6

D5

D4

D3

D2

D1

D0

COMMAND

TYPE

0x04h

BIT

D7

0x00h

NAME

—

X

VRHOT

UV

OV

OC

VMERR

INT#

DESCRIPTION

R

Always reads 0.

VRHOT

D6

—

D5

VRHOT

UV

D4

UV (V

undervoltage)

overvoltage)

OUT

D3

OV

OV (V

OC (output current over current limit). This bit is sticky and cleared when read if the OC fault

is no longer present.

D2

OC

R

D1

D0

VMERR

R

VOUTMAX error.ꢀSetꢀ=ꢀ1ꢀifꢀ(VIDꢀ>ꢀVOUTMAX)

NORedꢀbitsꢀD[5:1],ꢀread-only,ꢀsetsꢀtheꢀINT output.

INT

X = Don’t care.

3)ꢀ TheꢀOVꢀbitꢀ(D3)ꢀisꢀsetꢀwhenꢀtheꢀoutputꢀvoltageꢀrisesꢀ

is still set if the fault occurs, regardless of the status

maskꢀsetting.ꢀTheꢀOCꢀbitꢀ(D2)ꢀisꢀsticky,ꢀbutꢀitꢀdoesꢀnotꢀ

hold INT low when the OC fault goes away. This allows

the system to determine what event triggered INT to

go low. All other fault bits are not sticky. Reading the

register after the OC event clears the flag.

300mV above (or 1.83V fixed) the output voltage.

4)ꢀ TheꢀOCꢀbitꢀ(D2)ꢀisꢀsetꢀwhenꢀtheꢀvalleyꢀofꢀ(∑CSP1ꢀ-ꢀ

CSN1) current signal exceeds 23mV (OC_ALARM).

The current-limit protection threshold is 15mV higher

than the OC_ALARM.

Mask Status (0x05h)

5)ꢀ Theꢀ VMERRꢀ bitꢀ (D1)ꢀ isꢀ setꢀ inꢀ caseꢀ theꢀ SETVOUTꢀ

exceeds the content of VOUTMAX. Changing SETVOUT

to values lower than VOUTMAX clears the VMERR warn-

ing.

Masking of the status bit only prevents the INTꢀbitꢀ(D0)ꢀ

from being set by the specific status bit. The status bit is

still set if the fault occurs, regardless of the Status Mask

setting. See Table 7 for bit descriptions.

6) Masking of the status bit only prevents the INTꢀbitꢀ(D0)ꢀ

from being set by the specific status bit. The status bit

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

Table 7. MASK (Regulator Status Mask Register)

2

I C COMMAND

DEFAULT

0x00h

D7

D6

D5

D4

D3

D2

D1

D0

0x05h

TYPE

X

VRHMSK UVMSK OVMSK OCMSK VMERRMSK Reserved

BIT

NAME

DESCRIPTION

D7

—

R

Always reads 0.

D6

—

D5

VRHMSK

UVMSK

OVMSK

OCMSK

VMERRMSK

—

R/W VRHOT masking bit.

D4

R/W Undervoltage-fault masking bit.

R/W Overvoltage-fault masking bit.

R/W Overcurrent-fault masking bit.

R/W VOUTMAX error masking bit.

D3

D2

D1

D0

R

Always reads 0.

X = Don’t care.

Note: In the event of UV, OC, OV, VRHOT, or VMERR, the signal is ANDed by the complement of the MASK register content.

STATUS REGISTER

STATUS BIT 0

FAULT OR ALARM EVENT

MASK REGISTER

INT

OUTPUT PIN

(INT STATE)

OTHER STATUS

LOGIC

Figure 8. Status Bit Masking

Table 8. SRREG (Slew-Rate Setting Register)

2

I C COMMAND

DEFAULT

0x04h

D7

D6

D5

D4

D3

D2

D1

D0

0x06h

TYPE

X

SRREG_5 SRREG_4 SRREG_3 SRREG_2 SRREG_1 SRREG_0

BIT

NAME

DESCRIPTION

D7

—

R/W

See Table 9

D6

—

D5

SRREG_5

SRREG_4

SRREG_3

SRREG_2

SRREG_1

SRREG_0

D4

D3

D2

D1

D0

X = Don’t care.

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

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Serial I C Interface

rates (4.5mV/µs to 44mV/µs) that cover the initial startup

Slew-Rate Conﬁguration (0x06h)

(soft-start) and dynamic output-voltage transition with

different slew rates in one setting. See Table 8 for bit

descriptions and Table 9 for slew-rate selections.

The content of the SRREG register determines the slew

rate at both initial startup and dynamic output-voltage

transition. There are 52 possibilities of selectable slew

Table 9. Slew-Rate Selections (Register 0x06h)

SOFT-START SLEW RATE

(mV/µs)

REGULAR SLEW RATE

D7

D6

D5

D4

D3

D2

D1

D0

(mV/µs)

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

1

0

1

0

1

0

1

0

1

X

0

1

0

1

0

1

18

9

18

9

4.5

9

4.5*

36

18

9

9*

36

4.5

9

4.5

22

11

9

22

11

44

5.5

11

14

7

5.5

11

5.5

44

22

11

5.5

14

7

3.5

7

3.5

28

7

28

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

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Serial I C Interface

Table 9. Slew-Rate Selections (Register 0x06h) (continued)

SOFT-START SLEW RATE

REGULAR SLEW RATE

D7

D6

D5

D4

D3

D2

D1

D0

(mV/µs)

X

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

14

7

28

3.5

7

3.5

18

9

7

18

9

4.5

9

4.5

36

18

9

36

4.5

9

4.5

9

*POR default setting.

X = Don’t care.

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

Output-Voltage Set Register (0x07h)

Current Monitor Register (0x08h)

The SETVOUT register slews the output voltage 0.5µs

after the SETVOUT command is acknowledged. The

slew rate of the change in output voltage is equal to the

valueꢀ setꢀ byꢀ SRREG.ꢀ Theꢀ deviceꢀ DACꢀ supportsꢀ volt-

ages between 0.5V and 1.6V. See Table 3 for the output-

voltage codes and Table 10 for bit descriptions.

The device includes a current monitoring function. An

internalꢀADCꢀconvertsꢀtheꢀanalogꢀsignalsꢀfromꢀtheꢀIMONꢀ

pinꢀoutputꢀtoꢀ8-bitꢀvaluesꢀinꢀtheꢀIMONꢀregister.ꢀTheꢀADCꢀ

converter filters the current-sense signal by averaging

over four samples. The acquisition rate is 100µs. The

content of this register is updated every 400µs. For more

information on how to set the desired value for IMON

resolution, see the Current Monitoring (IMON) section.

See Table 11 for bit descriptions.

Table 10. SETVOUT (Output-Voltage Set Register)

2

I C COMMAND

DEFAULT

0x33

D7

D6

D5

D4

D3

D2

D1

D0

0x07

BIT

D7

D6

D5

D4

D3

D2

D1

D0

TYPE

VID_7

VID_6

VID_5

VID_4

VID_3

VID_2

VID_1

VID_0

NAME

VID_7

VID_6

VID_5

VID_4

VID_3

VID_2

VID_1

VID_0

DESCRIPTION

R

Don’tꢀcareꢀbit.ꢀReturnsꢀ0ꢀwhenꢀread.

MSB of the maximum allowed output voltage code

See Table 3 for the actual output-voltage code.

LSB of the maximum allowed output-voltage code. 10mV resolution.

Table 11. IMON (Current Monitor Register)

2

I C COMMAND

DEFAULT

0x00h

NAME

IM_7

D7

D6

D5

D4

D3

D2

D1

D0

0x08h

BIT

D7

TYPE

—

DESCRIPTION

R

—

D6

IM_6

—

D5

IM_5

D4

IM_4

D3

IM_3

D2

IM_2

D1

IM_1

D0

IM_0

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

current just touches zero with every cycle at maximum

Multiphase QuickTune-PWM Design

Procedure

Firmly establish the input voltage range and maximum

load current before choosing a switching frequency

and inductor operating point (ripple-current ratio). The

primary design trade-off lies in choosing a good switching

frequency and inductor operating point, and the following

four factors dictate the rest of the design:

load). Inductor values lower than this grant no further

size-reduction benefit. The optimum operating point is

usually between 30% and 50% ripple current. For a

multiphase core regulator, select an LIR value of ~0.4.

Inductor Selection

The switching frequency and operating point (% ripple

current or LIR) determine the inductor value as follows:

1) Input Voltage Range: The maximum value (V

)





IN(MAX)











V

- V

V

OUT

IN

OUT









L = N

must accommodate the worst-case high AC adapt-

er voltage. The minimum value (V ) must

PH

f

×I

×LIR

V

SW LOAD(MAX)

IN 

IN(MIN)

account for the lowest input voltage after drops due to

connectors, fuses, and battery selector switches. If

there is a choice at all, lower input voltages result in

better efficiency.

where N

is the total number of phases. Find a low-loss

PH

inductorꢀhavingꢀtheꢀlowestꢀpossibleꢀDCꢀresistanceꢀthatꢀfitsꢀ

in the allotted dimensions. The core must not saturate at

the peak-inductor current (I

):

PEAK

2) Maximum Load Current: There are two values to

I





LIR

2





LOAD(MAX)

consider. The peak load current (I

) deter-

I

=

1+





LOAD(MAX)

PEAK









N



mines the instantaneous component stresses and

filtering requirements, and drives output-capacitor

selection, inductor saturation rating, and the design of

the current-limit circuit. The continuous-load current



PH



Output Capacitor Selection

Output capacitor selection is determined by the controller

stability and the transient soar and sag requirements of

the application.

(I

) determines the thermal stresses and drives

LOAD

the selection of the input capacitors, MOSFETs, and

other critical heat-contributing components. Modern

Output Capacitor ESR

notebook CPUs generally exhibit I

= 0.8 x

LOAD

The output filter capacitor must have low enough

effective series resistance (ESR) to meet output-ripple

and load-transient requirements, yet have high enough

I

. For multiphase systems, each phase

LOAD(MAX)

supports a fraction of the load, depending on the

current balancing. When properly balanced, the load

current is evenly distributed among phases:

ESR to satisfy stability requirements. In CPU V

CORE

converters and other applications where the output is

subject to large-load transients, the size of the output

capacitor typically depends on how much ESR is needed

to prevent the output from dipping too low under a load

transient. Ignoring the sag due to finite capacitance:

I

LOAD

I

=

LOAD(PHASE)

N

PH

where N

is the total number of active phases.

PH

3) Switching Frequency: This choice determines the

basic trade-off between size and efficiency. The

optimal frequency is largely a function of maximum

V

STEP

LOAD(MAX)

(R

+ R

) ≤

PCB

ESR

DI

input voltage due to MOSFET switching losses

2

The output-voltage ripple of a step-down controller equals

the total inductor ripple current multiplied by the output

capacitor’s ESR. When operating multiphase out-of-

phase systems, the peak inductor currents of each phase

are staggered, resulting in lower output ripple voltage by

reducing the total inductor ripple current. For multiphase

operation, the maximum ESR to meet ripple requirements

is given in the following equation:

that are proportional to frequency and V . The

IN

optimum frequency is also a moving target due to rapid

improvements in MOSFET technology that are making

higher frequencies more practical.

4) Inductor Operation Point: This choice provides trade-

offs between size vs. efficiency and transient respons-

es vs. output noise. Low inductor values provide better

transient response and smaller physical size, but also

result in lower efficiency and higher output noise due

to increased ripple current. The minimum practical

inductor value is one that causes the circuit to operate

at the edge of critical conduction (where the inductor













V

× f

×L

IN SW

R

≤

V

RIPPLE

ESR

(V − (N × V

))V

OUT

IN

PH

OUT

where NPH is the total number of active phases and f

is the switching frequency per phase.

SW

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

The actual capacitance value required relates to the

physical size needed to achieve low ESR, as well as to

the chemistry of the capacitor technology. The capacitor is

usually selected by ESR and voltage rating rather than by

capacitance value (this is true for polymer types). When

using low-capacity ceramic filter capacitors, capacitor size

is usually determined by the capacity needed to prevent

Double Pulsing and Feedback-Loop Instability

Doubleꢀ pulsingꢀ occursꢀ dueꢀ toꢀ noiseꢀ onꢀ theꢀ outputꢀ orꢀ

because the ESR is so low that there is not enough volt-

age ramp in the output-voltage signal. This “fools” the error

comparator into triggering a new cycle immediately after

theꢀminimumꢀoff-timeꢀperiodꢀhasꢀexpired.ꢀDoubleꢀpulsingꢀ

is more annoying than harmful, resulting in nothing worse

than increased output ripple. However, it can indicate the

possible presence of loop instability due to insufficient

ESR. Loop instability can result in oscillations at the out-

put after line or load steps. Such perturbations are usually

damped, but can cause the output voltage to rise above

or fall below the tolerance limits. The easiest method

for checking stability is to apply a very fast 10% to 90%

maximum load transient and carefully observe the output-

voltage ripple envelope for overshoot and ringing. It can

help to simultaneously monitor the inductor current with

anꢀACꢀcurrentꢀprobe.ꢀDoꢀnotꢀallowꢀmoreꢀthanꢀoneꢀcycleꢀ

of ringing after the initial step-response under/overshoot.

V

SAG

and V

from causing problems during load

SOAR

transients. Generally, once enough capacitance is added

to meet the overshoot requirement, undershoot at the

rising load edge is no longer a problem (see the V

SAG

and V

equations in the Transient Response section).

SOAR

Output Capacitor Stability Considerations

For QuickTune-PWM controllers, stability is determined

by the value of the ESR zero relative to the switching

frequency. The boundary of instability is given by the

following equation:

f

SW

π

f

≤

ESR

Transient Response

The inductor-ripple current impacts transient-response

where:

1

performance, especially at low V - V

differentials.

f

=

IN

OUT

ESR

2π ×R

× C

OUT

EFF

Low inductor values allow the inductor current to slew

faster, replenishing charge removed from the output filter

capacitors by a sudden load step. The amount of output

sag is also a function of the maximum duty factor, which

can be calculated from the on-time and minimum off-time.

For a multiphase controller, the worst-case output sag

voltage can be determined by:

and:

R

= R

+ R + R

ESR LL PCB

EFF

where C

is the total output capacitance, R

is the

OUT

ESR

total equivalent series resistance, R is the load-line

LL

gain, and R

is the parasitic board resistance between

PCB

the output capacitors and sense resistors. For a 1MHz

application, the ESR zero frequency must be well below

300kHz, preferably below 100kHz. SANYO POSCAP

and Panasonic SP capacitors are widely used and have

typical ESR zero frequencies below 100kHz.

2

L(DI

)

t

LOAD(MAX)

MIN

- t

V

≈

×

SAG

2N × C

× V

t







PH

OUT

SW MIN



and:

t

= t

+ t

ON OFF(MIN)

MIN

Ceramic capacitors have a high-ESR zero frequency,

butꢀ applicationsꢀ withꢀ significantꢀ load-lineꢀ (DC-coupledꢀ

or AC-coupled) can take advantage of their size and

low ESR. When using only ceramic output capacitors,

where t

is the minimum off-time (see the Electrical

OFF(MIN)

Characteristics section), t

is the programmed switch-

is the total number of active phases.

mustꢀbeꢀlessꢀthanꢀtheꢀtransientꢀdroop,ꢀΔI

x R . The capacitive soar voltage due to stored inductor

SW

ing period, and N

PH

output overshoot (V ) typically determines the mini-

SOAR

V

SAG

LOAD(MAX)

mum output-capacitance requirement. Their relatively

low capacitance value favors high-switching-frequency

operation with small inductor values to minimize the

energy transferred from inductor to capacitor during load-

step recovery. Unstable operation manifests itself in two

relatedꢀbutꢀdistinctlyꢀdifferentꢀways:ꢀDoubleꢀpulsingꢀandꢀ

feedback-loop instability.

LL

energy can be calculated as:

2

(DI

) L

LOAD(MAX)

V

≈

SOAR

2N × C

× V

OUT

PH

OUT

The actual peak of the soar voltage depends on the time

where the decaying ESR step and rising capacitive soar

are at their maximum. This is best simulated or measured.

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

●ꢀ Connectꢀ allꢀ analogꢀ groundsꢀ toꢀ aꢀ separateꢀ solid-

Input Capacitor Selection

copper plane that connects to the ground pin of the

The input capacitor must meet the ripple-current require-

ment (I ) imposed by the switching currents. The

QuickTune-PWM controller. This includes the V

BIAS

RMS

bypassꢀcapacitor,ꢀFB,ꢀandꢀGNDSꢀbypassꢀcapacitors.

multiphase QuickTune-PWM controllers operate out-of

phase, reducing the RMS input. The I requirements

can be determined by the following equation:

●ꢀ Keepꢀ theꢀ powerꢀ tracesꢀ andꢀ loadꢀ connectionsꢀ short.ꢀ

This is essential for high efficiency. The use of thick

copper PCB (2oz vs. 1oz) can enhance full-load

efficiency by 1% or more. Correctly routing PCB traces

is a difficult task that must be approached in terms of

fractionsꢀofꢀcentimeters,ꢀwhereꢀaꢀsingleꢀmΩꢀofꢀexcessꢀ

trace resistance causes a measurable efficiency

penalty.

RMS











I

LOAD

× V

I

=

N

× V

V

- N × V

(

)

(

RMS

PH

OUT IN PH OUT

N

PH

IN 

The worst-case RMS current requirement occurs when

operating with V = 2 (N

× V

). Therefore, the

OUT

IN

PH

above equation simplifies to I

= 0.5 x (I

).

RMS

LOAD/NPH

●ꢀ CSP_ꢀandꢀCSN_ꢀconnectionsꢀforꢀcurrentꢀlimiting,ꢀload-

line control, and current monitoring must be made

using Kelvin-sense connections to guarantee the

current-sense accuracy.

Choose an input capacitor that exhibits less than 10°C

temperature rise at the RMS input current for optimal

circuit longevity.

Applications Information

●ꢀ Whenꢀtrade-offsꢀinꢀtraceꢀlengthsꢀmustꢀbeꢀmade,ꢀitꢀisꢀ

preferable to allow the inductor charging path to be

made longer than the discharge path. For example,

it is better to allow some extra distance between the

input capacitors and the high-side MOSFET than to

allow distance between the inductor and the low-side

MOSFET, or between the inductor and the output filter

capacitor.

PCB Layout Guidelines

Careful PCB layout is critical to achieve low switching

losses and clean, stable operation. The switching power

stage requires particular attention. If possible, mount

all the power components on the top side of the board,

with their ground terminals flush against one another.

The layout of the device is intimately related to the

layout of the CPU. The high-current output paths from the

regulator must flow cleanly into the high-current inputs

on the processor. For VR12.6 processors, these inputs

are orthogonal. This arrangement effectively forces the

regulator to be located diagonally, with respect to the

processor. Refer to the MAX15569 evaluation kit speci-

fications for layout examples and follow these guidelines

for good PCB layout:

●ꢀ Routeꢀhigh-speedꢀswitchingꢀnodesꢀawayꢀfromꢀsensi-

tive analog areas (i.e., FB, FBAC, CSP_, CSN_, etc.).

See Table 12 for layout procedures.

●ꢀ Keepꢀ theꢀ high-currentꢀ pathsꢀ short,ꢀ especiallyꢀ atꢀ theꢀ

ground terminals. This is essential for stable, jitter-free

operation.

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

Table 12. Layout Procedures

COMPONENTS

DESCRIPTION

Theꢀgeneralꢀruleꢀisꢀthatꢀcapacitorsꢀtakeꢀpriorityꢀoverꢀresistorsꢀsinceꢀtheyꢀprovideꢀaꢀﬁlteringꢀfunction.ꢀTheꢀlistꢀ

below is in order of priority:

1)

V

Capacitors:ꢀPlaceꢀtheseꢀnearꢀtheꢀICꢀpinsꢀwithꢀwideꢀtracesꢀandꢀgoodꢀconnectionꢀtoꢀPGND.ꢀ

BIAS

2) CSP_ - CSN_ Differential Filter Capacitors: Place the capacitors and the step resistor near the IC pins.

These inputs are critical because they are used for regulation and load-line, as well as current limit and

current balance.

Capacitors

3) Common-Mode Capacitors:ꢀTheꢀcapacitorsꢀtoꢀAGNDꢀtakeꢀtheꢀnextꢀpriority.ꢀ

4) FB and GNDS Capacitors: The FB capacitor can be slightly farther away from the IC since the FB resistor

has priority to be closer to the IC.

FB and FBAC

Current Sense

The FB and FBAC resistors should be near the respective pins. Keep the trace short to reduce any inductance.

Use Kelvin-sense connection to the sense element (inductor or sense resistor).

Route CSP_ traces near CSN_. Avoid any switching signals, especially LX when routing these current-sensing

signals.

Thermistors

TheꢀNTCꢀforꢀTHERMꢀsensingꢀshouldꢀbeꢀplacedꢀnearꢀtheꢀpowerꢀcomponentsꢀofꢀtheꢀﬁrstꢀphase.ꢀ

Catch resistors should be placed near the point of load so that the output-voltage trace does not need to route

backꢀtoꢀtheꢀIC.ꢀTheꢀgroundꢀcatchꢀresistorꢀisꢀlessꢀcriticalꢀasꢀitꢀonlyꢀrequiresꢀaꢀviaꢀtoꢀconnectꢀtoꢀtheꢀPGNDꢀplane.ꢀ

Catch Resistors

Remote Sense

Route together in a quiet layer, avoiding any switching signals, especially LX.

2

Pullups for I C Interface and INT do not need to be too close to the IC and can be placed farther away to make

space for other more important components near the IC.

2

I C

Place a small 0.1µF decoupling capacitor for the V near the pullup resistors.

TT

KeepꢀtheꢀAGNDꢀpolygonꢀjustꢀlargeꢀenoughꢀtoꢀcoverꢀAGNDꢀcomponents.ꢀDoꢀnotꢀmakeꢀitꢀanyꢀlargerꢀthanꢀ

necessary.ꢀTheꢀAGNDꢀpolygonꢀshouldꢀnotꢀrunꢀunderꢀanyꢀhigh-voltageꢀswitchingꢀtracesꢀsinceꢀallꢀAGNDꢀ

connections should be on the other side of the IC, away from the driver pins.

AGND

AGND-PGNDꢀconnectionꢀshouldꢀbeꢀmadeꢀawayꢀfromꢀtheꢀPGNDꢀpinsꢀsoꢀasꢀnotꢀtoꢀbeꢀinꢀtheꢀpathꢀofꢀtheꢀ

DRVPWM_ꢀdriveꢀcurrents.ꢀAꢀgoodꢀlocationꢀisꢀnearꢀtheꢀBIASꢀpin.ꢀ

AGND-PGND

Exposed Pad

ConnectꢀtoꢀAGND.

Power

Components

Place the power components close to keep the current loop small. Avoid large LX nodes. Use multiple vias to

keep the impedance low and to carry the high currents.

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MAX15569

2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

Chip Information

Package Information

For the latest package outline information and land patterns

(footprints), go to www.maximintegrated.com/packages. Note

thatꢀaꢀ“+”,ꢀ“#”,ꢀorꢀ“-”ꢀinꢀtheꢀpackageꢀcodeꢀindicatesꢀRoHSꢀstatusꢀ

only. Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

PROCESS: BiCMOS

Ordering Information

PART

TEMP RANGE

-40°C to +105°C

PIN-PACKAGE

24 TQFN-EP*

MAX15569GTG+

PACKAGE PACKAGE

TYPE CODE

OUTLINE

NO.

LAND PATTERN

NO.

+Denotes a lead(Pb)-free/RoHS-compliant package.

*EP = Exposed pad.

24 TQFN-EP T2444+4

21-0139

90-0022

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2-Phase/1-Phase QuickTune-PWM Controller with

2

Serial I C Interface

Revision History

REVISION REVISION

PAGES

DESCRIPTION

CHANGED

NUMBER

DATE

0

1

3/13

2/15

Initial release

Updated the Beneﬁts and Features section

—

1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and speciﬁcations without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

©

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

2015 Maxim Integrated Products, Inc.

│ 39


型号：	MAX15569GTG+
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Switching Controller, Current-mode, 1400kHz Switching Freq-Max, BICMOS, TQFN-24 信息通信管理开关
文件：	总39页 (文件大小：905K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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