MAX14895E [MAXIM]

Enhanced VGA Port Protector DDC Outputs have Internal Pullups; 增强型的VGA端口保护DDC输出具有内部上拉电阻
MAX14895E
型号: MAX14895E
厂家: MAXIM INTEGRATED PRODUCTS    MAXIM INTEGRATED PRODUCTS
描述:

Enhanced VGA Port Protector DDC Outputs have Internal Pullups
增强型的VGA端口保护DDC输出具有内部上拉电阻

文件: 总11页 (文件大小:1200K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
19-5819; Rev 0; 3/11  
E V A L U A T I O N K I T A V A I L A B L E  
General Description  
Benefits and Features  
The MAX14895E integrates level-translating buffers and  
features RED, GRN, and BLU (RGB) port protection for  
VGA signals.  
S Saves Power in Portable Applications  
Low Quiescent Supply Current: 430µA (typ)  
S Eliminates Need for Costly External Components  
High-ESD Protection on SDA1, SCL1, SYNCH1,  
The device has horizontal sync (SYNCH_) and vertical  
sync (SYNCV_) translating buffers that convert low-level  
CMOS inputs from a graphics controller to meet full 5V,  
TTL-compatible outputs. Each output can drive Q10mA  
and meets the VESASM specification. In addition, the  
device translates the direct digital control (DDC) signals  
to a lower level that is safe for the graphics controller.  
SYNCV1, RED, GRN, BLU, EN, V  
±1ꢀ5V Human Body Model (HBM)  
S
±±5V IEC 61000-4-2 Contact Discharge  
S Innovative Design Enables a High Level of  
Integration for Performance  
Output Current-Limit Switch with Power-Off  
Protection  
Low Capacitance on RGB Ports (2.2pF typ)  
10mA Drive on SYNCH1, SYNCV1  
The device features both EN and EN inputs, accepting  
active-high or active-low enable inputs. The device also  
switches and current limits the 5V supply to a VGA con-  
nector or monitor.  
S Fully Integrated Solutions Saves Space in Portable  
Applications  
The RED, GRN, and BLU terminals protect graphics con-  
troller outputs against electrostatic discharge (ESD) events.  
All eight outputs and EN have high-level ESD protection.  
DDC Outputs have Internal Pullups  
3mm x 3mm, 16-Pin TQFN Pac5age  
The MAX14895E is specified over the extended -40NC to  
+85NC temperature range and is available in a 16-pin,  
3mm x 3mm TQFN package with exposed pad.  
Ordering Information appears at end of data sheet.  
Applications  
For related parts and recommended products to use with this part,  
refer to www.maxim-ic.com/MAX14895E.related.  
Notebook Computers  
Desktops  
Servers  
Graphics Cards  
Typical Operating Circuit  
+5V  
1µF  
V
CC  
V
EN  
S
1µF  
EN  
SYNCH0, SYNCV0  
2
2
SYNCH1, SYNCV1  
SDA1, SCL1  
2
2
SDA0, SCL0  
RED  
VGA  
VGA  
OUTPUTS  
PORT  
MAX14895E  
GRN  
BLU  
GND  
VESA is a service mark of the Video Electronics Standards Association Corporation.  
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1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-±±±-629-4642,  
or visit Maxim’s website at www.maxim-ic.com.  
MAX14895E  
Enhanced VGA Port Protector  
ABSOLUTE MAXIMUM RATINGS  
(Voltages referenced to GND.)  
Continuous Power Dissipation (T = +70NC)  
A
V
, V , EN, SDA0, SCL0 ......................................-0.3V to +6V  
TQFN (derate 20.8mW/NC above +70NC)..................1667mW  
Operating Temperature Range.......................... -40NC to +85NC  
Junction Temperature .....................................................+150NC  
Storage Temperature Range............................ -65NC to +150NC  
Lead Temperature (soldering, 10s) ................................+300NC  
Soldering Temperature (reflow) ......................................+260NC  
CC  
S
SDA1, SCL1 ................................................ -0.3V to (V + 0.3V)  
EN, RED, GRN, BLU, SYNCH0,  
S
SYNCH1, SYNCV0, SYNCV1................ -0.3V to (V  
+ 0.3V)  
CC  
Continuous Current through SDA_, SCL_....................... Q30mA  
Continuous Short-Circuit Current SYNCH1, SYNCV1..... Q20mA  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-  
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect device reliability.  
PACKAGE THERMAL CHARACTERISTICS (Note 1)  
TQFN  
Junction-to-Ambient Thermal Resistance (B ) ..........48NC/W  
JA  
Junction-to-Case Thermal Resistance (B ).................7NC/W  
JC  
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-  
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.  
ELECTRICAL CHARACTERISTICS  
(V  
= +4.75V to +5.25V, T = -40NC to +85NC, unless otherwise noted. Typical values are at V  
= +5V, T = +25NC.) (Note 2)  
CC  
A
CC A  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
POWER SUPPLY  
Power-Supply Range  
V
4.75  
5.25  
800  
V
CC  
EN = V , EN = GND,  
SYNCH0 = SYNCV0 = GND,  
SDA0 = SCL0 = unconnected  
CC  
Quiescent Supply Current  
Shutdown Supply Current  
I
430  
FA  
Q
EN = GND, EN = V  
,
CC  
I
8
FA  
SYNCH0 = SYNCV0 = GND,  
SDA0 = SCL0 = unconnected  
SHDN  
Undervoltage Lockout Threshold  
Undervoltage Lockout Hysteresis  
V
V
rising  
4.3  
V
V
UVLO  
CC  
0.1  
2.2  
V
= +4.75V to +5.25V, SDA1/SCL1 =  
CC  
1.6  
1.6  
2.9  
2.8  
unconnected, measure SDA0/SCL0  
V = +4.75V to +5.25V, SDA0/SCL0 =  
CC  
200kI to GND, measure SDA0/SCL0,  
Internal Logic Supply Voltage  
V
V
L
SDA1/SCL1 = unconnected  
RED, GRN, BLU  
RED, GRN, BLU Capacitance  
RED, GRN, BLU Leakage Current  
C
f = 1MHz, V  
= 1V  
P-P  
pF  
OUT  
RED, GRN, BLU  
-1  
+1  
FA  
SYNCH0, SYNCV0, EN, EN  
Input Logic-High  
V
2.0  
V
V
IH  
Input Logic-Low  
V
0.8  
IL  
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*The parametric values (min, typ, max limits) shown in the Electrical Characteristics table supersede values quoted elsewhere in this data sheet.  
MAX14895E  
Enhanced VGA Port Protector  
ELECTRICAL CHARACTERISTICS* (continued)  
(V  
= +4.75V to +5.25V, T = -40NC to +85NC, unless otherwise noted. Typical values are at V  
= +5V, T = +25NC.) (Note 2)  
CC  
A
CC A  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
+1  
UNITS  
FA  
SYNCH0, SYNCV0 Leakage  
Current  
SYNCH0/SYNCV0 = GND or V  
-1  
CC  
200  
800  
kI  
EN, EN Input Resistance  
SYNCH1, SYNCV1  
Output Logic-High  
Output Logic-Low  
EN = V , EN = GND  
CC  
V
V
V
= +4.75V, source 10mA  
= +4.75V, sink 10mA  
2.4  
V
V
OH  
CC  
V
0.5  
4
OL  
CC  
R = 2.2kI, C = 10pF, 10% to 90% of V  
L
L
CC  
Rising Time  
t
ns  
ns  
ns  
Fs  
R
(Note 3)  
R = 2.2kI, C = 10pF, 90% to 10% of V  
L
L
CC  
Falling Time  
t
4
F
(Note 3)  
R = 2.2kI, C = 10pF, EN = V , EN =  
L
L
CC  
Propagation Delay  
Enable Time  
t
t
16  
17  
PD  
EN  
GND (Figure 1)  
R = 2.2kI, C = 10pF, V V  
SYNCH1, SYNCV1  
L
L
= +4.75V (Figure 1)  
SDA�, SCL� (DDC)  
On-Resistance  
R
V
= V  
= 0.5V, I = 10mA  
LOAD  
55  
+1  
I
ON  
SDA0  
SCL0  
EN = GND, EN = V  
SDA0 = SCL0 = V , SDA1 = SCL1 = GND  
,
CC  
SDA0, SCL0 Off-Leakage Current  
-1  
FA  
CC  
SDA1, SCL1 Reverse-Leakage  
Current  
V
V
= 0V, V = +5.25V,  
CC S  
-10  
+10  
4.0  
FA  
kI  
= V  
= +5.25V  
SDA1  
SCL1  
V
= +4.75V, SDA0 = SCL0 =  
CC  
SDA1, SCL1 Pullup Resistor  
R
unconnected, EN = V  
, EN = GND,  
1.25  
200  
2.5  
PULLUP  
CC  
I
= 100FA  
LOAD  
V
OUTPUT  
S
Forward Voltage Drop  
Reverse-Leakage Current  
Current Limit  
I
= 60mA, V  
= 5V  
0.25  
10  
V
FA  
mA  
I
LOAD  
CC  
V
= 0V, V = 5.25V  
S
CC  
I
600  
500  
LIM  
Discharge Resistor  
R
I
= 1mA  
300  
VS  
LOAD  
THERMAL SHUTDOWN  
Thermal Shutdown Threshold  
Thermal Shutdown Hysteresis  
ESD PROTECTION  
+150  
10  
NC  
NC  
HBM  
IEC 61000-4-2 Contact  
15  
8
kV  
kV  
SDA1, SCL1, SYNCH1, SYNCV1,  
RED, GRN, BLU, EN, V  
S
Note 2: All devices are 100% production tested at T = +25NC. Limits over the operating temperature range are guaranteed by  
A
design and not production tested.  
Note 3: Guaranteed by design.  
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*The parametric values (min, typ, max limits) shown in the Electrical Characteristics table supersede values quoted elsewhere in this data sheet.  
MAX14895E  
Enhanced VGA Port Protector  
2.4V  
V
V
/V  
SYNCH0 SYNCV0  
50%  
50%  
0V  
OUTPUT HIGH  
50%  
/V  
50%  
SYNCH1 SYNCV1  
OUTPUT LOW  
t
t
PHL  
PLH  
t
= MAX(t , t  
)
PD  
PLH PHL  
2.4V  
V
50%  
50%  
EN  
0V  
2.4V  
V
EN  
0V  
OUTPUT HIGH  
V
/V  
50%  
SYNCH1 SYNCV1  
OUTPUT LOW  
t
EN  
Figure 1. Timing Diagram  
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MAX14895E  
Enhanced VGA Port Protector  
Typical Operating Characteristics  
(V  
= +5V, T = +25NC, unless otherwise noted.)  
CC  
A
HV BUFFER OUTPUT-VOLTAGE HIGH  
vs. TEMPERATURE  
ON-RESISTANCE vs. SDA0 VOLTAGE  
6.0  
80  
I
= 8mA  
OUT  
SDA0, SCL0 ARE  
5.8  
5.6  
5.4  
5.2  
5.0  
4.8  
4.6  
4.4  
4.2  
4.0  
70  
60  
50  
40  
30  
20  
10  
0
INTERCHANGEABLE  
T = +25°C  
A
T = +85°C  
A
T = -40°C  
A
-40  
-15  
10  
35  
60  
85  
0
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
TEMPERATURE (°C)  
V
(V)  
SDA0  
HV BUFFER OUTPUT-VOLTAGE LOW  
vs. TEMPERATURE  
1.0  
I
= 8mA  
OUT  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
-40  
-15  
10  
35  
60  
85  
TEMPERATURE (°C)  
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MAX14895E  
Enhanced VGA Port Protector  
Pin Configuration  
TOP VIEW  
12  
11  
10  
9
SYNCV0 13  
SYNCV1 14  
15  
8
7
6
5
SDA1  
SDA0  
EN  
MAX14895E  
V
CC  
*EP  
4
EN 16  
V
S
+
1
2
3
TQFN  
(3mm x 3mm)  
*CONNECT EP TO GND.  
Pin Description  
PIN  
1
NAME  
RED  
FUNCTION  
High-ESD Protection Diodes for RGB Signals  
High-ESD Protection Diodes for RGB Signals  
High-ESD Protection Diodes for RGB Signals  
Ground  
2
GRN  
BLU  
3
4
GND  
Supply Voltage Output with Current-Limit Switch. V provides a current-limited voltage from V  
when the  
S
CC  
5
V
S
device is enabled. Bypass V to GND with a 1FF or larger ceramic capacitor as close as possible to the device.  
S
6
7
EN  
Active-Low Enable Input. Drive EN high and EN low to disable the device. EN is weakly pulled up internally.  
SDA0  
SDA1  
SCL0  
SCL1  
DDC Data Input from Graphics Controller  
8
DDC Data Output to VGA Monitor. Internally pulled up to V  
.
CC  
9
DDC Clock Input from Graphics Controller  
10  
11  
12  
13  
14  
DDC Clock Output to VGA Monitor. Internally pulled up to V  
.
CC  
SYNCH0 Horizontal Sync Input  
SYNCH1 Horizontal Sync Output  
SYNCV0 Vertical Sync Input  
SYNCV1 Vertical Sync Output  
Supply Voltage Input. Apply a voltage between +4.75V and +5.25V to V  
to GND with a 1FF or larger ceramic capacitor as close as possible to the device.  
to power the device. Bypass V  
CC  
CC  
15  
16  
V
CC  
EN  
EP  
Active-High Enable Input. Drive EN low and EN high to disable the device. EN is weakly pulled down internally.  
Exposed Pad. Connect EP to GND. For enhanced thermal dissipation, connect EP to a large ground plane.  
Do not use EP as the only ground connection.  
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MAX14895E  
Enhanced VGA Port Protector  
Functional Diagram/Truth Table  
V
CC  
THERMAL  
SHUTDOWN  
MAX14895E  
CURRENT-LIMIT  
SWITCH  
V
S
EN  
EN  
LOGIC  
SDA/SCL PULLUP  
RESISTOR  
SWITCHES  
HIGH ESD  
R
VS  
HIGH ESD  
V
PULLUP-TO-GND  
S
R
R
PULLUP  
PULLUP  
SWITCHES  
SDA0  
SCL0  
SDA1  
HIGH ESD  
2
I C LEVEL SHIFTER  
SCL1  
HIGH ESD  
SYNCH0  
SYNCH1  
HIGH ESD  
SYNCV0  
SYNCV1  
HIGH ESD  
RED  
GRN  
BLU  
HIGH ESD  
HIGH ESD  
HIGH ESD  
GND  
EN EN DEVICE LOGIC  
0
0
1
1
0
1
0
1
Enable  
Disable  
Enable  
Enable  
2
DEVICE LOGIC/ SYNCH_/SYNCV_ I C LEVEL CURRENT-LIMIT  
SDA/SCL PULLUP  
RESISTOR SWITCHES  
V
PULL-TO-GND  
SWITCH  
S
EVENT  
BUFFER  
SHIFTER  
SWITCH  
Enable  
No Overcurrent  
On  
On  
On  
On  
On  
Off  
Off  
Enable  
Overcurrent  
On  
On  
Off  
Current Limit  
Off  
Enable  
Overcurrent  
Output 0V  
Off  
On  
Thermal Shutdown  
Disable  
Output 0V  
Off  
Off  
Off  
Off  
Off  
Off  
Off  
On  
Off  
V
= 0V  
CC  
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MAX14895E  
Enhanced VGA Port Protector  
V
Output  
S
S
Detailed Description  
The device provides a current-limited voltage on V when  
The MAX14895E integrates level-translating buffers and  
features RED, GRN, and BLU port protection for VGA sig-  
nals. Horizontal and vertical synchronization (SYNCH0,  
SYNCV0) inputs feature level-shifting buffers to support  
low-voltage CMOS or standard TTL-compatible graphics  
controllers. Each output can drive Q10mA and meets  
the part is enabled. V is used as the pullup voltage for  
internal pullup resistors on SDA1 and SCL1, and can be  
used as an external supply. The internal pullup resistors  
from SDA1 and SCL1 to V are active when the device is  
enabled, and are disabled when the device is in thermal  
S
S
shutdown (see the Functional Diagram/Truth Table).  
2
VESA specifications. The device also features I C level  
The V supply includes an internal resistor to discharge  
S
the supply when the device is in thermal shutdown or is  
shifting using two nMOS devices.  
The device generates its own internal bias supply to  
clamp SCL0 and SDA0 to a safe level, removing the need  
for another external supply. The device also provides a  
disabled (see the Functional Diagram/Truth Table). V is  
current limited to prevent damage to host devices. When  
S
power is off (V  
leakage current up to V = +5.25V.  
= 0V), V is protected against reverse-  
CC  
S
current-limited V  
output with power-off protection. This  
CC  
S
output can be used to switch power to a VGA connector  
or the VGA interface of a monitor.  
Thermal Shutdown  
Thermal-shutdown circuitry protects the device from  
overheating. The device enters thermal shutdown when  
the junction temperature exceeds +150NC (typ) and  
returns to normal operation when the temperature drops  
by approximately +10NC (typ) below the thermal-shut-  
down threshold. When the device is in thermal shutdown,  
both SYNCH1 and SYNCV1 are pulled down to ground,  
Horizontal/Vertical Sync Level Shifter  
SYNCH0 and SYNCV0 are buffered to provide level shift-  
ing and drive capability to meet the VESA specification.  
The level-shifted outputs (SYNCH1, SYNCV1) are pulled  
low when EN is low and EN is high, or when the device  
is in thermal shutdown (see the Functional Diagram/  
2
Truth Table). Logic-level outputs (V , V ) are 5V TTL-  
the I C level shifters are disabled, the SDA1 and SCL1  
pullups are off, and the V discharge resistor is on (see  
OL OH  
compatible. These two buffers are identical and each  
can drive either the horizontal or the vertical synch signal.  
S
the Functional Diagram/Truth Table).  
Applications Information  
Power-Supply Decoupling  
Display Data Channel Switches  
2
The device incorporates two nMOS switches for I C  
level shifting. The SDA0 and SCL0 terminals are voltage  
clamped to a diode drop less than the internal V volt-  
L
Bypass V  
and V to ground with 1FF ceramic capaci-  
tors as close as possible to the device.  
CC  
S
age. Voltage clamping provides protection and compat-  
ibility with the SDA0 and SCL0 signals and low-voltage  
PCB Layout  
ASICs. When power is off (V  
are protected against reverse-leakage current up to V =  
+5.25V. The SDA_ and SCL_ switches are identical, and  
each switch can be used to route SDA_ or SCL_ signals.  
= 0V), SDA1 and SCL1  
CC  
High-speed switches such as the MAX14895E require  
proper PCB layout for optimum performance. Ensure that  
impedance-controlled PCB traces for high-speed signals  
are matched in length and are as short as possible.  
Connect the exposed pad to a solid ground plane.  
S
RGB Ports  
The device includes three terminals for RED, GRN, and  
BLU signals. These terminals provide high-level ESD pro-  
tection to the RGB lines while keeping the capacitance  
on the RGB lines to a minimum. The RED, GRN, BLU  
terminals are identical, and any of the three terminals  
can be used to protect red, green, or blue video signals.  
ESD Protection  
As with all Maxim devices, ESD protection structures  
are incorporated on all terminals to protect against elec-  
trostatic discharges encountered during handling and  
assembly. Additionally, the device is protected to Q15kV  
on the RED, GRN, BLU, EN, V , SYNCH1, SYNCV1,  
SCL1, and SDA1 terminals by the HBM. For optimum  
S
EN, EN  
The device has dual complementary EN and EN enable  
inputs and can accept either active-low or active-high  
enable signals. Pull EN low and EN high to place the device  
in shutdown (see the Functional Diagram/Truth Table).  
ESD performance, bypass V  
ceramic capacitor.  
to ground with a 1FF  
CC  
����������������������������������������������������������������� Maxim Integrated Products  
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MAX14895E  
Enhanced VGA Port Protector  
ESD protection can be tested in various ways. The RED,  
IEC 61000-4-2  
The IEC 6100-4-2 standard covers ESD testing and per-  
formance of finished equipment. However, it does not  
specifically refer to integrated circuits. The device assists  
in designing equipment to meet IEC 61000-4-2 without  
the need for additional ESD protection components.  
GRN, BLU, EN, V , SYNCH1, SYNCV1, SCL1, and SDA1  
S
terminals of the device are characterized for protection to  
the following limits:  
•ꢀ Q15kV using the HBM  
•ꢀ Q8kV using IEC 61000-4-2 Contact Discharge  
The major difference between tests done using the HBM  
and IEC 61000-4-2 is higher peak current in IEC 61000-  
4-2 because series resistance is lower in the IEC 61000-  
4-2 model. Hence, the ESD withstand voltage measured  
to IEC 61000-4-2 is generally lower than that measured  
using the HBM. Figure 4 shows the IEC 61000-4-2 model,  
and Figure 5 shows the current waveform for the IEC  
61000-4-2 ESD Contact Discharge test.  
Human Body Model  
Figure 2 shows the HBM. Figure 3 shows the current  
waveform it generates when discharged into a low-  
impedance state. This model consists of a 100pF capaci-  
tor charged to the ESD voltage of interest that is then  
discharged into the device through a 1.5kI resistor.  
R
R
R
R
D
C
D
C
1M  
1.5kΩ  
50MTO 100MΩ  
330Ω  
CHARGE-CURRENT-  
LIMIT RESISTOR  
DISCHARGE  
RESISTANCE  
CHARGE-CURRENT-  
LIMIT RESISTOR  
DISCHARGE  
RESISTANCE  
HIGH-  
VOLTAGE  
DC  
HIGH-  
VOLTAGE  
DC  
DEVICE  
UNDER  
TEST  
DEVICE  
UNDER  
TEST  
C
100pF  
STORAGE  
CAPACITOR  
C
150pF  
STORAGE  
CAPACITOR  
S
S
SOURCE  
SOURCE  
Figure 2. Human Body ESD Test Model  
Figure 4. IEC 61000-4-2 ESD Test Model  
I
(AMPS)  
PEAK  
I
(AMPS)  
PEAK  
100%  
90%  
PEAK-TO-PEAK RINGING  
(NOT DRAWN TO SCALE)  
I
100%  
90%  
r
36.8%  
10%  
0
10%  
TIME  
t
0
t = 0.7ns TO 1ns  
t
RL  
R
t
DL  
30ns  
60ns  
Figure 3. Human Body Current Waveform  
Figure 5. IEC 61000-4-2 ESD Generator Current Waveform  
����������������������������������������������������������������� Maxim Integrated Products  
9
MAX14895E  
Enhanced VGA Port Protector  
Ordering Information  
Package Information  
For the latest package outline information and land patterns  
(footprints), go to www.maxim-ic.com/packages. Note that a  
“+”, “#”, or “-” in the package code indicates RoHS status only.  
Package drawings may show a different suffix character, but  
the drawing pertains to the package regardless of RoHS status.  
PART  
TEMP RANGE  
PIN-PACKAGE  
MAX14895EETE+T  
-40NC to +85NC  
16 TQFN-EP*  
+Denotes lead(Pb)-free/RoHS-compliant package.  
T = Tape and reel.  
*EP = Exposed pad.  
PACKAGE  
TYPE  
PACKAGE  
CODE  
OUTLINE  
NO.  
LAND  
PATTERN NO.  
Chip Information  
16 TQFN-EP  
T1633+4  
21-0136  
90-0031  
PROCESS: BiCMOS  
���������������������������������������������������������������� Maxim Integrated Products 10  
MAX14895E  
Enhanced VGA Port Protector  
Revision History  
REVISION REVISION  
PAGES  
DESCRIPTION  
CHANGED  
NUMBER  
DATE  
0
3/11  
Initial release  
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.  
Maxim reserves the right to change the circuitry and specifications without notice at any time.  
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600  
11  
©
2011 Maxim Integrated Products  
Maxim is a registered trademark of Maxim Integrated Products, Inc.  

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