MAX145BEPA [MAXIM]
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin レMAX; + 2.7V ，低功耗， 2通道， 108ksps ，串行12位ADC ，采用8引脚μMAX封装
| 型号： | MAX145BEPA |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | +2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin レMAX |
| 文件： | 总16页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1387; Rev 0; 11/98
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l, 1 0 8 k s p s ,
S e ria l 1 2 -Bit ADCs in 8 -P in µMAX
/MAX145
Ge n e ra l De s c rip t io n
Fe a t u re s
The MAX144/MAX145 low-p owe r, 12-b it a na log -to-
digital converters (ADCs) are available in 8-pin µMAX
and DIP packages. Both devices operate with a single
+2.7V to +5.25V supply and feature a 7.4µs succes-
sive-approximation ADC, automatic power-down, fast
wake-up (2.5µs), an on-chip clock, and a high-speed,
3-wire serial interface.
♦ Single-Supply Operation (+2.7V to +5.25V)
♦ Two Single-Ended Channels (MAX144)
One Pseudo-Differential Channel (MAX145)
♦ Low Power
0.9mA (108ksps, +3V Supply)
100µA (10ksps, +3V Supply)
10µA (1ksps, +3V Supply)
0.2µA (Power-Down Mode)
Power consumption is only 3.2mW (V = +3.6V) at the
DD
maximum sampling rate of 108ksps. At slower through-
p ut ra te s , the a utoma tic s hutd own (0.2µA) furthe r
reduces power consumption.
♦ Internal Track/Hold
The MAX144 provides 2-channel, single-ended opera-
♦ 108ksps Sampling Rate
tion and accepts input signals from 0 to V
. The
REF
♦ SPI/QSPI/MICROWIRE-Compatible 3-Wire
MAX145 accepts pseudo-differential inputs ranging
from 0 to V . An e xte rna l c loc k a c c e s s e s d a ta -
Serial Interface
REF
throug h the 3-wire s e ria l inte rfa c e , whic h is SPI™,
QSPI™, and MICROWIRE™-compatible.
♦ Space-Saving 8-Pin µMAX Package
♦ Pin-Compatible 10-Bit Versions Available
Excellent dynamic performance and low power, com-
bined with ease of use and small package size, make
these converters ideal for battery-powered and data-
a c q uis ition a p p lic a tions , or for othe r c irc uits with
demanding power-consumption and space require-
me nts . For p in-c omp a tib le 10-b it ADCs , s e e the
MAX157 and MAX159.
Ord e rin g In fo rm a t io n
INL
(LSB)
PART
TEMP. RANGE PIN-PACKAGE
MAX144ACUA 0°C to +70°C 8 µMAX
±0.5
±1
MAX144BCUA 0°C to +70°C 8 µMAX
Ap p lic a t io n s
Instrumentation
MAX144ACPA
MAX144BCPA
MAX144BC/D
0°C to +70°C 8 Plastic DIP
0°C to +70°C 8 Plastic DIP
0°C to +70°C Dice*
±0.5
±1
Battery-Powered Systems
Portable Data Logging
±1
Test Equipment
MAX144AEUA -40°C to +85°C
MAX144BEUA -40°C to +85°C
MAX144AEPA -40°C to +85°C
MAX144BEPA -40°C to +85°C
8 µMAX
±0.5
±1
Isolated Data Acquisition
Process-Control Monitoring
Medical Instruments
System Supervision
8 µMAX
8 Plastic DIP
8 Plastic DIP
±0.5
±1
MAX144AMJA -55°C to +125°C 8 CERDIP**
MAX144BMJA -55°C to +125°C 8 CERDIP**
MAX145ACUA 0°C to +70°C 8 µMAX
MAX145BCUA 0°C to +70°C 8 µMAX
±0.5
±1
P in Co n fig u ra t io n
±0.5
±1
TOP VIEW
MAX145ACPA
MAX145BCPA
MAX145BC/D
0°C to +70°C 8 Plastic DIP
0°C to +70°C 8 Plastic DIP
0°C to +70°C Dice*
±0.5
±1
V
1
2
3
4
8
7
6
5
SCLK
DOUT
CS/SHDN
REF
DD
CH0 (CH+)
CH1 (CH-)
GND
±1
MAX144
MAX145
MAX145AEUA -40°C to +85°C
MAX145BEUA -40°C to +85°C
MAX145AEPA -40°C to +85°C
MAX145BEPA -40°C to +85°C
8 µMAX
±0.5
±1
8 µMAX
8 Plastic DIP
8 Plastic DIP
±0.5
±1
( ) ARE FOR MAX145 ONLY
µMAX/DIP
MAX145AMJA -55°C to +125°C 8 CERDIP**
MAX145BMJA -55°C to +125°C 8 CERDIP**
±0.5
±1
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
*Dice are specified at T = +25°C, DC parameters only.
A
**Contact factory for availability.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l, 1 0 8 k s p s ,
S e ria l 1 2 -Bit ADCs in 8 -P in µMAX
ABSOLUTE MAXIMUM RATINGS
V
to GND..............................................................-0.3V to +6V
Plastic DIP (derate 9.09mW/°C above +70°C) ............727mW
CERDIP (derate 8.00mW/°C above +70°C) ............... 640mW
DD
CH0, CH1 (CH+, CH-) to GND ................. -0.3V to (V + 0.3V)
DD
REF to GND .............................................. -0.3V to (V + 0.3V)
Operating Temperature Ranges (T )
DD
A
Digital Inputs to GND. ............................................. -0.3V to +6V
MAX144/MAX145_C_A .......................................0°C to +70°C
MAX144/MAX145_E_A. ...................................-40°C to +85°C
MAX144/MAX145_M_A ................................ -55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
DOUT to GND............................................ -0.3V to (V + 0.3V)
DD
DOUT Sink Current ........................................................... 25mA
Continuous Power Dissipation (T = +70°C)
A
µMAX (derate 4.1mW/°C above +70°C) .................... 330mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +2.7V to +5.25V, V
= 2.5V, 0.1µF c a p a c itor a t REF, f
= 2.17MHz, 16 c loc ks /c onve rs ion c yc le (108ks p s ),
DD
REF
SCLK
CH- = GND for MAX145, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
/MAX145
PARAMETER
DC ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
12
TYP
MAX
UNITS
RES
INL
Bits
MAX14_A
MAX14_B
±0.5
±1
Relative Accuracy (Note 2)
LSB
Differential Nonlinearity
Offset Error
DNL
No missing codes over temperature
±0.75
±3
LSB
LSB
Gain Error (Note 3)
Gain Temperature Coefficient
±3
LSB
±0.8
ppm/°C
Channel-to-Channel Offset
Matching
±0.05
LSB
LSB
Channel-to-Channel Gain
Matching
±0.05
DYNAMIC SPECIFICATIONS (f
= 10kHz, V = 2.5Vp-p, 108ksps, f
SCLK
= 2.17MHz, CH- = GND for MAX145)
70
IN(sine-wave)
IN
Signal-to-Noise Plus
Distortion Ratio
SINAD
dB
dB
Total Harmonic Distortion
(including 5th-order harmonic)
THD
-80
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
Small-Signal Bandwidth
Full-Power Bandwidth
SFDR
80
dB
dB
f
= 65kHz, V = 2.5Vp-p (Note 4)
-85
2.25
1.0
IN
IN
-3dB rolloff
MHz
MHz
CONVERSION RATE
External clock, f
16 clocks/conversion cycle
= 2.17MHz,
SCLK
7.4
Conversion Time (Note 5)
t
µs
CONV
Internal clock
5
7
T/H Acquisition Time
Aperture Delay
Aperture Jitter
t
2.5
µs
ns
ps
ACQ
25
<50
External clock mode
0.1
0
2.17
5
Serial Clock Frequency
f
MHz
SCLK
Internal clock mode, for data transfer only
2
_______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l, 1 0 8 k s p s ,
S e ria l 1 2 -Bit ADCs in 8 -P in µMAX
/MAX145
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.7V to +5.25V, V
= 2.5V, 0.1µF c a p a c itor a t REF, f
= 2.17MHz, 16 c loc ks /c onve rs ion c yc le (108ks p s ),
REF
SCLK
CH- = GND for MAX145, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUTS
Analog Input Voltage Range
(Note 6)
V
IN
0
V
REF
V
Multiplexer Leakage Current
Input Capacitance
On/off leakage current, V = 0 to V
±0.01
16
±1
µA
pF
IN
DD
C
IN
EXTERNAL REFERENCE
0
V
DD
+ 50mV
Input Voltage Range (Note 7)
V
REF
V
Input Current
V
REF
= 2.5V
100
25
140
µA
kΩ
µA
Input Resistance
18
Shutdown REF Input Current
0.01
10
DIGITAL INPUTS (CS/SHDN) AND OUTPUT (DOUT)
V
≤ 3.6V
2.0
3.0
DD
Input High Voltage
V
IH
V
V
DD
> 3.6V
Input Low Voltage
Input Hysteresis
V
0.8
V
V
IL
V
HYS
0.2
0.5
Input Leakage Current
Input Capacitance
I
IN
V
= 0 or V
DD
±1
15
µA
pF
IN
C
(Note 8)
= 5mA
IN
I
0.4
SINK
Output Low Voltage
Output High Voltage
V
OL
V
V
I
= 16mA
SINK
V
OH
I
= 0.5mA
V
DD
- 0.5
SOURCE
Three-State Output Leakage
Current
±10
15
µA
pF
CS/SHDN = V
DD
Three-State Output Capacitance
POWER REQUIREMENTS
Positive Supply Voltage
C
OUT
CS/SHDN = V (Note 8)
DD
V
DD
2.7
5.25
2.0
5
V
Operating mode
0.9
0.2
mA
µA
Positive Supply Current
I
DD
Shutdown, CS/SHDN = GND
Power-Supply Rejection
(Note 9)
V
V
REF
= 2.7V to 5.25V,
= 2.5V, full-scale input
DD
PSR
±0.15
mV
_______________________________________________________________________________________
3
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l, 1 0 8 k s p s ,
S e ria l 1 2 -Bit ADCs in 8 -P in µMAX
TIMING CHARACTERISTICS (Figure 7)
(V
= +2.7V to +5.25V, V
= 2.5V, 0.1µF c a p a c itor a t REF, f
= 2.17MHz, 16 c loc ks /c onve rs ion c yc le (108ks p s ),
DD
REF
SCLK
CH- = GND for MAX145, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
µs
Wake-Up Time (Note 10)
t
2.5
WAKE
t
C
C
C
= 100pF
120
120
120
2.17
5
ns
CS/SHDN Fall to Output Enable
CS/SHDN Rise to Output Disable
SCLK Fall to Output Data Valid
DV
L
L
L
t
= 100pF, Figure 1
= 100pF, Figure 1
ns
TR
t
20
0.1
0
ns
DO
External clock
SCLK Clock Frequency
f
MHz
SCLK
Internal clock, SCLK for data transfer only
External clock
215
SCLK Pulse Width High
t
ns
CH
Internal clock, SCLK for data transfer only
(Note 8)
50
215
50
External clock
/MAX145
SCLK Pulse Width Low
t
ns
CL
Internal clock, SCLK for data transfer only
(Note 8)
t
60
60
ns
ns
SCLK to CS/SHDN Setup
CS/SHDN Pulse Width
SCLKS
t
CS
Note 1: Tested at V = +2.7V.
DD
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been
calibrated.
Note 3: Offset nulled.
Note 4: “On” channel is grounded; sine wave applied to “off” channel (MAX144 only).
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from GND to V (MAX145 only).
DD
Note 7: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 8: Guaranteed by design. Not subject to production testing.
Note 9: Measured as V
- V
.
FS(2.7V)
FS(5.25V)
Note 10: SCLK must remain stable during this time.
4
_______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l, 1 0 8 k s p s ,
S e ria l 1 2 -Bit ADCs in 8 -P in µMAX
/MAX145
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
= 2.5V, 0.1µF at REF, f = 2.17MHz, 16 clocks/conversion cycle (108ksps), CH- = GND for MAX145, T = +25°C,
SCLK A
(V = +3.0V, V
DD
REF
unless otherwise noted.)
SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs.
SAMPLING RATE
10,000
1000
100
10
1500
1250
1000
750
1500
1300
1100
900
V
= V
V
= V
DD
DD REF
REF
V
= V
DD
REF
C = 20pF
R = ∞
L
L
R = ∞
L
CODE = 101010100000
C = 50pF
L
C = 50pF
L
CODE = 101010100000
CODE = 101010100000
700
1
500
500
0.1
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-60 -40 -20
0
20 40 60 80 100 120 140
0.1
1
10
100
1k
10k 100k
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SAMPLING RATE (sps)
SHUTDOWN CURRENT
vs. TEMPERATURE
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
OFFSET ERROR
vs. SUPPLY VOLTAGE
1000
800
600
400
200
0
1000
800
600
400
200
0
1.0
V
= V
DD
REF
V
= V
DD
REF
0.8
0.6
0.4
0.2
0
-60 -40 -20
0
20 40 60 80 100 120 140
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
GAIN ERROR
GAIN ERROR
OFFSET ERROR
vs. SUPPLY VOLTAGE
vs. TEMPERATURE
vs. TEMPERATURE
0.5
0.5
1.0
0.4
0.3
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.4
0.3
0.2
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
-60 -35 -10 15 40 65 90 115 140
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
-60 -35 -10 15 40 65 90 115 140
V
TEMPERATURE (°C)
TEMPERATURE (°C)
DD
_______________________________________________________________________________________
5
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l, 1 0 8 k s p s ,
S e ria l 1 2 -Bit ADCs in 8 -P in µMAX
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +3.0V, V
= 2.5V, 0.1µF at REF, f
= 2.17MHz, 16 clocks/conversion cycle (108ksps), CH- = GND for MAX145, T = +25°C,
DD
REF
SCLK A
unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
INTEGRAL NONLINEARITY
vs. TEMPERATURE
0.20
0.15
0.10
0.05
0
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
-0.05
-0.10
-0.15
-0.20
/MAX145
-60 -35 -10 15 40 65 90 115 140
TEMPERATURE (°C)
0
1024
2048
3072
4096
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
OUTPUT CODE
V
DD
EFFECTIVE NUMBER OF BITS
vs. FREQUENCY
FFT PLOT
20
0
12.0
V
= +2.7V
= 10kHz
DD
V
DD
= +2.7V
f
IN
f
= 108ksps
SAMPLE
11.8
11.6
11.4
11.2
-20
-40
-60
-80
-100
-120
-140
11.0
0
27
FREQUENCY (kHz)
54
1
10
100
FREQUENCY (kHz)
P in De s c rip t io n
PIN
NAME
FUNCTION
1
2
3
4
V
Positive Supply Voltage, +2.7V to +5.25V
DD
CH0 (CH+)
CH1 (CH-)
GND
Analog Input: MAX144 = single-ended (CH0); MAX145 = differential (CH+)
Analog Input: MAX144 = single-ended (CH1); MAX145 = differential (CH-)
Analog and Digital Ground
External Reference Voltage Input. Sets the analog voltage range. Bypass with a 100nF capacitor close to
the device.
5
6
REF
Active-Low Chip-Select Input/Active-High Shutdown Input. Pulling CS/SHDN high puts the device into
shutdown with a maximum current of 5µA.
CS/SHDN
Serial Data Output. Data changes state at SCLK’s falling edge. High impedance when CS/SHDN
is high.
7
8
DOUT
SCLK
Serial Clock Input. DOUT changes on the falling edge of SCLK.
6
_______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l, 1 0 8 k s p s ,
S e ria l 1 2 -Bit ADCs in 8 -P in µMAX
/MAX145
V
DD
DOUT
6k
DOUT
6k
C
L
C
L
GND
a) HIGH-Z TO V , V TO V , AND V TO HIGH-Z
GND
b) HIGH-Z TO V , V TO V , AND V TO HIGH-Z
0H 0L
0H
OH
0L 0H
0L
OL
Figure 1. Load Circuits for Enable and Disable Time
_______________De t a ile d De s c rip t io n
CS/SHDN
SCLK
The MAX144/MAX145 a na log -to-d ig ita l c onve rte rs
(ADCs) use a successive-approximation conversion
(SAR) te c hniq ue a nd on-c hip tra c k-a nd -hold (T/H)
structure to convert an analog signal to a serial 12-bit
digital output data stream.
INTERNAL
CLOCK
DOUT
CONTROL
LOGIC
OUTPUT
REGISTER
This flexible serial interface provides easy interface to
microprocessors (µPs). Figure 2 shows a simplified
functional diagram of the internal architecture for both
the MAX144 (2 channels, single-ended) and the MAX145
(1 channel, pseudo-differential).
CH0
(CH+)
SCLK
ANALOG
INPUT
12-BIT
SAR
ADC
T/H
IN
OUT
MAX144
MAX145
CH1
(CH-)
MUX
(2 CHANNEL)
REF
( ) ARE FOR MAX145
An a lo g In p u t s : S in g le -En d e d (MAX1 4 4 )
a n d P s e u d o -Diffe re n t ia l (MAX1 4 5 )
Figure 2. Simplified Functional Diagram
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit of
Figure 3. In single-ended mode (MAX144), both chan-
nels CH0 and CH1 are referred to GND and can be
connected to two different signal sources. Following the
power-on reset, the ADC is set to convert CH0. After
CH0 has been converted, CH1 will be converted and
the c onve rs ions will c ontinue to a lte rna te b e twe e n
channels. Channel switching is performed by toggling
the CS/SHDN pin. Conversions can be performed on
the same channel by toggling CS/SHDN twice between
conversions. If only one channel is required, CH0 and
CH1 may be connected together; however, the output
d a ta will s till c onta in the c ha nne l id e ntific a tion b it
(before the MSB).
12-BIT CAPACITIVE DAC
REF
MAX144
MAX145
CH0
(CH+)
C
16pF
HOLD
INPUT
MUX
COMPARATOR
TO SAR
ZERO
CH1
(CH-)
R
IN
9kΩ
C
SWITCH
TRACK
HOLD
T/H
GND
CONTROL LOGIC
( ) ARE FOR MAX145
SINGLE-ENDED MODE: CH0, CH1 = IN+; GND = IN-
DIFFERENTIAL-ENDED MODE: CH+ = IN+; CH- = IN-
For the MAX145, the input channels form a single differ-
ential channel pair (CH+, CH-). This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side IN- must remain stable
within ± 0.5LSB (± 0.1LSB for op timum re s ults ) with
respect to GND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- to GND.
Figure 3. Analog Input Channel Structure
clock mode) or from when CS/SHDN falls to the first
falling edge of SCLK (internal clock mode). At the end
of the acquisition interval, the T/H switch opens, retain-
ing charge on C
as a sample of the signal at IN+.
HOLD
During the acquisition interval, the channel selected as
The conversion interval begins with the input multiplex-
er switching C from the positive input (IN+) to the
negative input (IN-). This unbalances node ZERO at the
comparator’s positive input.
the positive input (IN+) charges capacitor C
. The
HOLD
HOLD
acquisition interval spans from when CS/SHDN falls to
the falling edge of the second clock cycle (external
_______________________________________________________________________________________
7
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l, 1 0 8 k s p s ,
S e ria l 1 2 -Bit ADCs in 8 -P in µMAX
The c a p a c itive d ig ita l-to-a na log c onve rte r (DAC)
adjusts during the remainder of the conversion cycle
to restore node ZERO to 0V within the limits of 12-bit
resolution. This action is equivalent to transferring a
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Tog e the r with the inp ut imp e d a nc e , this c a p a c itor
forms an RC filter, limiting the ADC’s signal bandwidth.
16pF · [(V ) - (V )] charge from C to the bina-
ry-weighted capacitive DAC, which in turn forms a digi-
tal representation of the analog input signal.
IN+
IN-
HOLD
In p u t Ba n d w id t h
The MAX144/MAX145 T/H s ta g e offe rs a 2.25MHz
small-signal and a 1MHz full-power bandwidth, which
make it possible to use the parts for digitizing high-
speed transients and measuring periodic signals with
b a nd wid ths e xc e e d ing the ADCs s a mp ling ra te b y
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended. Most
aliasing problems can be fixed easily with an external
resistor and a capacitor. However, if DC precision is
required, it is usually best to choose a continuous or
s witc he d -c a p a c itor filte r, s uc h a s the MAX7410/
MAX7414 (Figure 4). Their Butterworth characteristic
generally provides the best compromise (with regard to
rolloff and attenuation) in filter configurations, is easy to
design, and provides a maximally flat passband response.
Tra c k /Ho ld (T/H)
The ADC’s T/H stage enters its tracking mode on the
fa lling e d g e of CS/SHDN. For the MAX144 (s ing le -
ended inputs), IN- is connected to GND and the con-
verter samples the positive (“+”) input. For the MAX145
(pseudo-differential inputs), IN- connects to the nega-
tive input (“-”) and the difference of [(V ) - (V )] is
IN+
IN-
sampled. At the end of the conversion, the positive
input connects back to IN+ and C
input signal.
charges to the
HOLD
/MAX145
The time required for the T/H stage to acquire an input
signal is a function of how fast its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
An a lo g In p u t P ro t e c t io n
Internal protection diodes, which clamp the analog input
t
, is the maximum time the device takes to acquire
ACQ
the signal, and is also the minimum time required for
the signal to be acquired. Calculate this with the follow-
ing equation:
to V
and GND, allow each input channel to swing
DD
within GND - 300mV to V + 300mV without damage.
DD
However, for accurate conversions, both inputs must not
t
= 9(R + R )C
S IN IN
exceed V + 50mV or be less than GND - 50mV.
ACQ
DD
where R is the source impedance of the input signal,
If an off-channel analog input voltage exceeds the
supplies, limit the input current to 4mA.
S
R
IN
(9kΩ) is the input resistance, and C (16pF) is the
IN
input capacitance of the ADC. Source impedances
below 1kΩ have no significant impact on the AC perfor-
mance of the MAX144/MAX145.
V
DD
1
4
5
V
DD
7
V
DD
2
EXTERNAL
REFERENCE
0.1µF
CH0
SHDN
REF
470Ω**
5
8
OUT
CLK
MAX7410
MAX7414
MAX144
GND
2
3
8
7
6
IN
CH1
DOUT
f = 15kHz
C
0.01µF**
CS/SHDN
SCLK
µP/µC
COM
OS
GND
1
6
3
4
0.01µF
1.5MHz
OSCILLATOR
**USED TO ATTENUATE SWITCHED-CAPACITOR FILTER CLOCK NOISE
Figure 4. Analog Input with Anti-Aliasing Filter Structure
8
_______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l, 1 0 8 k s p s ,
S e ria l 1 2 -Bit ADCs in 8 -P in µMAX
/MAX145
External Clock (f
= 100kHz to 2.17MHz)
S e le c t in g Clo c k Mo d e
To s ta rt the c onve rs ion p roc e s s on the MAX144/
MAX145, p ull CS/SHDN low. At CS/SHDN’s fa lling
edge, the part wakes up and the internal T/H enters
tra c k mod e . In a d d ition, the s ta te of SCLK a t
CS/SHDN’s falling edge selects internal (SCLK = high)
or external (SCLK = low) clock mode.
SCLK
The external clock mode (Figure 6) is selected by tran-
sitioning CS/SHDN from high to low while SCLK is low.
The external clock signal not only shifts data out, but
also drives the analog-to-digital conversion. The input
is sampled and conversion begins on the falling edge
of the second clock pulse. Conversion must be com-
pleted within 140µs to prevent degradation in the con-
version results caused by droop on the T/H capacitors.
External clock mode provides the best throughput for
clock frequencies between 100kHz and 2.17MHz.
Internal Clock (f
< 100kHz or f
> 2.17MHz)
SCLK
SCLK
In internal clock mode, the MAX144/MAX145 run from
an internal, laser-trimmed oscillator to within 20% of the
2MHz specified clock rate. This releases the system
microprocessor from running the SAR conversion clock
and allows the conversion results to be read back at
the processor’s convenience, at any clock rate from 0
to 5MHz. Operating the MAX144/MAX145 in internal
clock mode is necessary for serial interfaces operating
with clock frequencies lower than 100kHz or greater
than 2.17MHz. Select internal clock mode (Figure 5), by
hold ing SCLK hig h d uring a hig h/low tra ns ition of
CS/SHDN. The first SCLK falling edge samples the data
and initiates a conversion using the integrated on-chip
oscillator. After the conversion, the oscillator shuts off
and DOUT goes high, signaling the end of conversion
(EOC). Data can then be read out with SCLK.
Ou t p u t Da t a Fo rm a t
Table 1 illustrates the 16-bit, serial data stream output
format for both the MAX144 and MAX145. The first
three bits are always logic high (including the EOC bit
for internal clock mode), followed by the channel identi-
fication (CHID = 0 for CH0, CHID = 1 for CH1, CHID = 1
for the MAX145), and then 12 bits of data in MSB-first
format. After the last bit has been read out, additional
SCLK pulses will clock out trailing zeros. DOUT transi-
tions on the falling edge of SCLK. The output remains
high-impedance when CS/SHDN is high.
ACTIVE POWER ACTIVE
DOWN
t
CS
t
t
CONV
WAKE
(t
)
ACQ
CS/SHDN
SCLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
HIGH-Z
HIGH-Z
EOC
1
1
CHID MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DOUT
SAMPLING INSTANT
Figure 5. Internal Clock Mode Timing
ACTIVE POWER ACTIVE
DOWN
ACTIVE POWER
DOWN
SAMPLING INSTANT
t
CS
t
WAKE
(t
)
ACQ
CS/SHDN
SCLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
HIGH-Z
HIGH-Z
CHID MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DOUT
Figure 6. External Clock Mode Timing
_______________________________________________________________________________________
9
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l, 1 0 8 k s p s ,
S e ria l 1 2 -Bit ADCs in 8 -P in µMAX
Table 1. Serial Output Data Stream for Internal and External Clock Mode
SCLK CYCLE
DOUT (Internal Clock)
DOUT (External Clock)
1
EOC
1
2
1
1
3
1
1
4
5
6
7
8
9
10
D6
D6
11
D5
D5
12
D4
D4
13
D3
D3
14
D2
D2
15
D1
D1
16
D0
D0
CHID D11 D10 D9
CHID D11 D10 D9
D8
D8
D7
D7
Ex t e rn a l Re fe re n c e
Effe c t ive Nu m b e r o f Bit s (ENOB)
An external reference is required for both the MAX144
and the MAX145. At REF, the DC input resistance is a
minimum of 18kΩ. During a conversion, a reference
must be able to deliver 250µA of DC load current and
have an output impedance of 10Ω or less. Use a 0.1µF
bypass capacitor for best performance. The reference
ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists only of quantization noise. With an
input range equal to the full-scale range of the ADC, the
effective number of bits can be calculated as follows:
ENOB = (SINAD - 1.76) / 6.02
input structure allows a voltage range of 0 to V
+
DD
50mV, although noise levels will decrease effective res-
olution at lower reference voltages.
To t a l Ha rm o n ic Dis t o rt io n (THD)
THD is the ratio of the RMS sum of the first five harmon-
ics of the input signal to the fundamental itself. This is
expressed as:
/MAX145
Au t o m a t ic P o w e r-Do w n Mo d e
Whe ne ve r the MAX144/MAX145 a re not s e le c te d
(CS/SHDN = V ), the p a rts e nte r the ir s hutd own
DD
2
2
2
2
V
2
+ V + V + V
3 4 5
mode. In shutdown all internal circuitry turns off, reduc-
ing supply current to typically less than 0.2µA. With an
external reference stable to within 1LSB, the wake-up
time is 2.5µs. If the external reference is not stable with-
in 1LSB, the wake-up time must be increased to allow
the reference to stabilize.
THD = 20 log
V
1
where V is the fundamental amplitude, and V through
1
2
V
are the amplitudes of the 2nd- through 5th-order
5
__________Ap p lic a t io n s In fo rm a t io n
harmonics.
S ig n a l-t o -No is e Ra t io (S NR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
error only and results directly from the ADC’s resolution
(N bits):
S p u rio u s -Fre e Dyn a m ic Ra n g e (S FDR)
SFDR is the ratio of RMS amplitude of the fundamental
(maximum signal component) to the RMS value of the
next largest spurious component, excluding DC offset.
Co n n e c t io n t o S t a n d a rd In t e rfa c e s
The MAX144/MAX145 interface is fully compatible with
SPI, QSPI, and MICROWIRE standard serial interfaces.
If a serial interface is available, establish the CPU’s seri-
al interface as master so that the CPU generates the
serial clock for the MAX144/MAX145. Select a clock fre-
quency from 100kHz to 2.17MHz (external clock mode).
SNR
= (6.02 · N + 1.76)dB
(MAX)
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. Therefore, SNR is computed by taking the ratio of
the RMS signal to the RMS noise which includes all
spectral components minus the fundamental, the first
five harmonics, and the DC offset.
1) Use a general-purpose I/O line on the CPU to pull
CS/SHDN low while SCLK is low.
2) Wait for the minimum wake-up time (t
fied before activating SCLK.
) speci-
WAKE
S ig n a l-t o -No is e P lu s Dis t o rt io n (S INAD)
SINAD is the ratio of the fundamental input frequency’s
RMS amplitude to RMS equivalent of all other ADC out-
put signals:
3) Activate SCLK for a minimum of 16 clock cycles.
The serial data stream of three leading ones, the
channel identification, and the MSB of the digitized
input signal begin at the first falling clock edge.
DOUT transitions on SCLK’s falling edge and is
available in MSB-first format. Observe the SCLK to
Signal
RMS
SINAD(dB) = 20 log
(Noise + Distortion)
RMS
10 ______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l, 1 0 8 k s p s ,
S e ria l 1 2 -Bit ADCs in 8 -P in µMAX
/MAX145
DOUT valid timing characteristic. Data should be
clocked into the µP on SCLK’s rising edge.
padded with three leading ones and the channel identi-
fication before the MSB. If the serial clock hasn’t been
id le d a fte r the la s t LSB a nd CS/SHDN is ke p t low,
DOUT sends trailing zeros.
4) Pull CS/SHDN high at or after the 16th falling clock
edge. If CS/SHDN remains low, trailing zeros will be
clocked out after the LSB.
SPI and MICROWIRE Interface
When using SPI (Figure 8a) or MICROWIRE (Figure 8b)
interfaces, set CPOL = 0 and CPHA = 0. Conversion
begins with a falling edge on CS/SHDN (Figure 8c).
Two consecutive 8-bit readings are necessary to obtain
the entire 12-bit result from the ADC. DOUT data transi-
tions on the serial clock’s falling edge and is clocked
into the µP on SCLK’s rising edge. The first 8-bit data
stream contains three leading ones, the channel identi-
5) With CS/SHDN high, wait at least 60ns (t ) before
CS
starting a new conversion by pulling CS/SHDN low.
A conversion can be aborted by pulling CS/SHDN
high before the conversion ends; wait at least 60ns
before starting a new conversion.
Data can be output in two 8-bit sequences or continu-
ously. The bytes will contain the result of the conversion
• • •
CS/SHDN
t
t
CH
t
CS
SCLKS
t
CL
SCLK
• • •
t
DV
t
DO
t
TR
HIGH-2
HIGH-2
DOUT
• • •
Figure 7. Detailed Serial-Interface Timing Sequence
I/O
SCK
CS/SHDN
SCLK
I/O
SK
SI
CS/SHDN
SCLK
MISO
DOUT
DOUT
SPI
MICROWIRE
V
DD
MAX144
MAX145
MAX144
MAX145
SS
8b. MICROWIRE Connections
Figure 8a. SPI Connections
1ST BYTE READ
2ND BYTE READ
12 13
1
2
3
4
5
6
7
8
9
10
11
14
15
16
SCLK
CS/SHDN
HIGH-Z
CHID D11 D10 D9
SAMPLING INSTANT MSB
*WHEN CS/SHDN IS HIGH, DOUT = HIGH-Z
D8
D7
D6
D5
D4
D3
D2
D1
D0
LSB
DOUT*
Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
______________________________________________________________________________________ 11
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l, 1 0 8 k s p s ,
S e ria l 1 2 -Bit ADCs in 8 -P in µMAX
fication, and the first four data bits starting with the
MSB. The s e c ond 8-b it d a ta s tre a m c onta ins the
remaining bits, D7 through D0.
PIC16 with SSP Module and PIC17 Interface
The MAX144/MAX145 are compatible with a PIC16/
PIC17 controller (µC), using the synchronous serial-port
(SSP) module.
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0
and CPHA = 0, the MAX144/MAX145 support a maxi-
To establish SPI communication, connect the controller
as shown in Figure 10a and configure the PIC16/PIC17
as system master by initializing its synchronous serial-
port control register (SSPCON) and synchronous serial-
port status register (SSPSTAT) to the bit patterns shown
in Tables 2 and 3.
mum f
of 2.17MHz. The QSPI circuit in Figure 9a
SCLK
can be programmed to perform a conversion on each
of the two channels for the MAX144. Figure 9b shows
the QSPI interface timing.
In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data
to be synchronously transmitted and received simulta-
neously. Two consecutive 8-bit readings (Figure 10b)
are necessary to obtain the entire 12-bit result from the
ADC. DOUT data transitions on the serial clock’s falling
edge and is clocked into the µC on SCLK’s rising edge.
The first 8-bit data stream contains three leading ones,
the channel identification, and the first four data bits
starting with the MSB. The second 8-bit data stream
contains the remaining bits, D7 through D0.
CS
SCK
CS/SHDN
SCLK
MISO
DOUT
QSPI
V
DD
/MAX145
MAX144
MAX145
SS
Figure 9a. QSPI Connections
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
CS/SHDN
HIGH-Z
CHID D11 D10 D9
SAMPLING INSTANT MSB
*WHEN CS/SHDN IS HIGH, DOUT = HIGH-Z
D8
D7
D6
D5
D4
D3
D2
D1
D0
LSB
DOUT
Figure 9b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
Table 2. Detailed SSPCON Register Contents
MAX144/MAX145
CONTROL BIT
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
SETTINGS
WCOL
BIT7
BIT6
X
X
Write Collision Detection Bit
SSPOV
Receive Overflow Detect Bit
Synchronous Serial-Port Enable Bit.
SSPEN
BIT5
1
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO and SCI pins as serial port pins.
CKP
BIT4
BIT3
BIT2
BIT1
BIT0
0
0
0
0
1
Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
SSPM3
SSPM2
SSPM1
SSPM0
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and selects
f
= f
/ 16.
CLK
OSC
X = Don’t care
12 ______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l, 1 0 8 k s p s ,
S e ria l 1 2 -Bit ADCs in 8 -P in µMAX
/MAX145
Table 3. Detailed SSPSTAT Register Contents
MAX144/MAX145
SETTINGS
CONTROL BIT
SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT)
SPI Data Input Sample Phase. Input data is sampled at the middle of the data output
time.
SMP
BIT7
0
CKE
D/A
P
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
1
SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock.
X
X
X
X
X
X
Data Address Bit
Stop Bit
S
Start Bit
R/W
UA
BF
Read/Write Bit Information
Update Address
Buffer Full Status Bit
X = Don’t care
(analog and digital). For lowest-noise operation, ensure
the ground return to the star ground’s power supply is
low impedance and as short as possible. Route digital
signals far away from sensitive analog and reference
inputs.
La yo u t , Gro u n d in g , a n d Byp a s s in g
For b e s t p e rforma nc e , us e p rinte d c irc uit b oa rd s
(PCBs). Wire-wrap configurations are not recommend-
ed, since the layout should ensure proper separation of
analog and digital traces. Run analog and digital lines
anti-parallel to each other, and don’t lay out digital sig-
nal paths underneath the ADC package. Use separate
analog and digital PCB ground sections with only one
star-point (Figure 11) connecting the two ground systems
High-frequency noise in the power supply V
could
DD
influence the proper operation of the ADC’s fast com-
parator. Bypass V to the star ground with a network
DD
of two parallel capacitors (0.1µF and 1µF) located as
close as possible to the power supply pin of MAX144/
MAX145. Minimize capacitor lead length for best sup-
ply-noise re je c tion a nd a d d a n a tte nua tion re sistor
(10Ω) if the power supply is extremely noisy.
V
DD
V
DD
SCLK
DOUT
SCK
SDI
I/O
CS/SHDN
MAX144
MAX145
PIC16/17
GND
GND
Figure 10a. SPI Interface Connection for a PIC16/PIC17
Controller
1ST BYTE READ
2ND BYTE READ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
CS/SHDN
HIGH-Z
CHID D11 D10 D9
SAMPLING INSTANT MSB
*WHEN CS/SHDN IS HIGH, DOUT = HIGH-Z
D8
D7
D6
D5
D4
D3
D2
D1
D0
LSB
DOUT*
Figure 10b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3–SSPM0 = 0001)
______________________________________________________________________________________ 13
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l, 1 0 8 k s p s ,
S e ria l 1 2 -Bit ADCs in 8 -P in µMAX
POWER SUPPLIES
+3V
+3V
GND
R* = 10Ω
1µF
0.1µF
GND
V
DD
+3V DGND
DIGITAL
CIRCUITRY
MAX144
MAX145
* OPTIONAL FILTER RESISTOR
/MAX145
Figure 11. Power-Supply Bypassing and Grounding
Ch ip In fo rm a t io n
TRANSISTOR COUNT: 2,058
SUBSTRATE CONNECTED TO GND
14 ______________________________________________________________________________________
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l, 1 0 8 k s p s ,
S e ria l 1 2 -Bit ADCs in 8 -P in µMAX
/MAX145
P a c k a g e In fo rm a t io n
______________________________________________________________________________________ 15
+2 .7 V, Lo w -P o w e r, 2 -Ch a n n e l, 1 0 8 k s p s ,
S e ria l 1 2 -Bit ADCs in 8 -P in µMAX
P a c k a g e In fo rm a t io n (c o n t in u e d )
/MAX145
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1998 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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