MAX1279BETC+T [MAXIM]
ADC, Successive Approximation, 12-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, TQFN-12;
| 型号： | MAX1279BETC+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Successive Approximation, 12-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, TQFN-12 信息通信管理 转换器 |
| 文件： | 总18页 (文件大小：828K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3365; Rev 0; 8/04
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
General Description
Features
The MAX1277/MAX1279 are low-power, high-speed, seri-
al-output, 12-bit, analog-to-digital converters (ADCs) with
an internal reference that operates at up to 1.5Msps.
These devices feature true-differential inputs, offering bet-
ter noise immunity, distortion improvements, and a wider
dynamic range over single-ended inputs. A standard
SPI™/QSPI™/MICROWIRE™ interface provides the clock
necessary for conversion. These devices easily interface
with standard digital signal processor (DSP) synchronous
serial interfaces.
♦ 1.5Msps Sampling Rate
♦ Only 22mW (typ) Power Dissipation
♦ Only 1µA (max) Shutdown Current
♦ High-Speed, SPI-Compatible, 3-Wire Serial Interface
♦ 68.5dB S/(N + D) at 525kHz Input Frequency
♦ Internal True-Differential Track/Hold (T/H)
♦ Internal 2.048V Reference
♦ No Pipeline Delays
The MAX1277/MAX1279 operate from a single +2.7V to
+3.6V supply voltage. The MAX1277/MAX1279 include a
2.048V internal reference. The MAX1277 has a unipolar
analog input, while the MAX1279 has a bipolar analog
input. These devices feature a partial power-down mode
and a full power-down mode for use between conver-
sions, which lower the supply current to 2mA (typ) and
1µA (max), respectively. Also featured is a separate
♦ Small 12-Pin TQFN Package
Ordering Information
power-supply input (V ), which allows direct interfacing to
L
PIN-
PACKAGE
PART
TEMP RANGE
INPUT
+1.8V to V
digital logic. The fast conversion speed,
DD
low-power dissipation, excellent AC performance, and DC
accuracy ( 1 LSꢀ IꢁL) make the MAX1277/MAX1279
ideal for industrial process control, motor control, and
base-station applications.
MAX1277ACTC-T
0°C to +70°C 12 TQFꢁ-12
0°C to +70°C 12 TQFꢁ-12
Unipolar
Unipolar
Unipolar
Unipolar
ꢀipolar
ꢀipolar
ꢀipolar
ꢀipolar
MAX1277ꢀCTC-T
MAX1277AETC-T -40°C to +85°C 12 TQFꢁ-12
MAX1277ꢀETC-T -40°C to +85°C 12 TQFꢁ-12
The MAX1277/MAX1279 come in a 12-pin TQFꢁ pack-
age, and are available in the commercial (0°C to +70°C)
and extended (-40°C to +85°C) temperature ranges.
MAX1279ACTC-T
0°C to +70°C 12 TQFꢁ-12
0°C to +70°C 12 TQFꢁ-12
MAX1279ꢀCTC-T
MAX1279AETC-T -40°C to +85°C 12 TQFꢁ-12
MAX1279ꢀETC-T -40°C to +85°C 12 TQFꢁ-12
Applications
Data Acquisition
ꢀill Validation
Motor Control
Communications
Portable Instruments
Typical Operating Circuit
Pin Configuration
+1.8V TO V
DD
+2.7V TO +3.6V
TOP VIEW
AIN+
12
N.C.
SCLK
10
0.01µF
0.01µF
10µF
10µF
11
V
V
L
DD
AIN-
REF
1
2
3
9
8
7
CNVST
DOUT
DIFFERENTIAL
INPUT
+
-
DOUT
AIN+
AIN-
VOLTAGE
MAX1277
MAX1279
µC/DSP
MAX1277
MAX1279
RGND
V
L
CNVST
SCLK
REF
4
5
6
RGND
GND
V
N.C.
GND
4.7µF
0.01µF
DD
TQFN
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1.5Ms ps , Single -Supply, Low -Pow e r, True -
Diffe re ntia l, 12-Bit ADCs w ith Inte rna l Re fe re nc e
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND..............................................................-0.3V to +6V
Maximum Current into Any Pin............................................50mA
V to GND ................-0.3V to the lower of (V + 0.3V) and +6V
Continuous Power Dissipation (T = +70°C)
L
DD
A
Digital Inputs
12-Pin TQFN (derate 16.9mW/°C above +70°C) ......1349mW
Operating Temperature Ranges
to GND .................-0.3V to the lower of (V + 0.3V) and +6V
DD
Digital Output
MAX127_ _ CTC.................................................0°C to +70°C
MAX127_ _ ETC ..............................................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
to GND....................-0.3V to the lower of (V + 0.3V) and +6V
Analog Inputs and
REF to GND..........-0.3V to the lower of (V + 0.3V) and +6V
RGND to GND .......................................................-0.3V to +0.3V
L
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = +2.7V to +3.6V, V = V , f
= 24MHz, 50% duty cycle, T = T
to T , unless otherwise noted. Typical values are at
MAX
DD
L
DD SCLK
A
MIN
T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
12
Bits
MAX127_A
MAX127_B
MAX127_A
MAX127_B
-1.0
-1.5
-1.0
-1.0
+1.0
+1.5
+1.0
+1.5
±8.0
Relative Accuracy (Note 1)
INL
LSB
Differential Nonlinearity (Note 2)
Offset Error
DNL
LSB
LSB
Offset-Error Temperature
Coefficient
±1
±2
ppm/°C
Gain Error
Offset nulled
±6.0
LSB
Gain Temperature Coefficient
ppm/°C
DYNAMIC SPECIFICATIONS (f = 525kHz sine wave, V = V , unless otherwise noted.)
REF
IN
IN
SINAD
THD
66
68.5
-80
-83
-78
15
dB
dB
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
Up to the 5th harmonic
= 250kHz, f = 300kHz
-76
-76
SFDR
IMD
dB
f
IN1
dB
IN2
-3dB point, small-signal method
S/(N + D) > 68dB, single ended
MHz
MHz
Full-Linear Bandwidth
1.2
CONVERSION RATE
Minimum Conversion Time
Maximum Throughput Rate
Minimum Throughput Rate
t
(Note 3)
0.667
µs
Msps
ksps
ns
CONV
1.5
10
(Note 4)
(Note 5)
Track-and-Hold Acquisition Time
Aperture Delay
t
125
5
ACQ
ns
Aperture Jitter
(Note 6)
(Note 7)
30
ps
External Clock Frequency
f
24
MHz
SCLK
2
_______________________________________________________________________________________
1.5Ms ps , Single -Supply, Low -Pow e r, True -
Diffe re ntia l, 12-Bit ADCs w ith Inte rna l Re fe re nc e
ELECTRICAL CHARACTERISTICS (continued)
(V = +2.7V to +3.6V, V = V , f
= 24MHz, 50% duty cycle, T = T
to T , unless otherwise noted. Typical values are at
MAX
DD
L
DD SCLK
A
MIN
T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUTS (AIN+, AIN-)
AIN+ - AIN-, MAX1277
0
V
REF
Differential Input Voltage Range
V
IN
V
AIN+ - AIN-, MAX1279
-V
/ 2
+V
/ 2
REF
REF
Absolute Input Voltage Range
DC Leakage Current
0
V
V
DD
±1
µA
pF
µA
Input Capacitance
Per input pin
16
75
Input Current (Average)
REFERENCE OUTPUT (REF)
REF Output Voltage Range
Voltage Temperature Coefficient
Time averaged at maximum throughput rate
Static, T = +25°C
2.038
2.048
±50
0.35
1.0
2.058
V
A
ppm/°C
I
= 0 to 2mA
SOURCE
Load Regulation
mV/mA
mV/V
I
= 0 to 100µA
SINK
Line Regulation
V
DD
= 2.7V to 3.6V, static
0.25
DIGITAL INPUTS (SCLK, CNVST)
Input Voltage Low
VIL
VIH
0.3 x V
V
V
L
Input Voltage High
0.7 x V
L
Input Leakage Current
DIGITAL OUTPUT (DOUT)
Output Load Capacitance
Output Voltage Low
I
0.05
±0.2
±10
µA
IL
C
For stated timing performance
30
pF
V
OUT
V
OL
I
= 5mA, V ≥ 1.8V
0.4
SINK
L
Output Voltage High
V
OH
I
= 1mA, V ≤ 1.8V
V - 0.5V
L
V
SOURCE
L
Output Leakage Current
POWER REQUIREMENTS
Analog Supply Voltage
Digital Supply Voltage
I
OL
Output high impedance
±10
3.6
µA
V
DD
2.7
1.8
V
V
V
V
DD
L
Static, f
= 24MHz
6
5
8
7
9
SCLK
Analog Supply Current,
Normal Mode
I
DD
Static, no SCLK
mA
Operational, 1.5Msps
7
f
= 24MHz
2
SCLK
Analog Supply Current,
Partial Power-Down Mode
I
mA
µA
DD
No SCLK
= 24MHz
2
f
1
SCLK
Analog Supply Current,
Full Power-Down Mode
I
DD
No SCLK
0.3
0.3
0.15
1
1
Operational, full-scale input at 1.5Msps
Static, f
= 24MHz
0.5
SCLK
mA
Digital Supply Current (Note 8)
Positive-Supply Rejection
Partial/full power-down mode,
= 24MHz
0.1
0.3
f
SCLK
Static, no SCLK, all modes
= 3V +20% -10%, full-scale input
0.1
1
µA
PSR
V
±0.2
±3.0
mV
DD
_______________________________________________________________________________________
3
1.5Ms ps , Single -Supply, Low -Pow e r, True -
Diffe re ntia l, 12-Bit ADCs w ith Inte rna l Re fe re nc e
TIMING CHARACTERISTICS
(V = +2.7V to +3.6V, V = V , f
= 24MHz, 50% duty cycle, T = T
to T , unless otherwise noted. Typical values are at
MAX
DD
L
DD SCLK
A
MIN
T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V = 2.7V to V
18.7
L
DD
SCLK Pulse-Width High
SCLK Pulse-Width Low
t
ns
CH
V = 1.8V to V , minimum recommended
(Note 7)
L
DD
22.5
V = 2.7V to V
18.7
L
DD
t
ns
ns
CL
V = 1.8V to V , minimum recommended
L
DD
22.5
(Note 7)
C
C
= 30pF, V = 2.7V to V
DD
17
24
L
L
L
SCLK Rise to DOUT Transition
t
DOUT
= 30pF, V = 1.8V to V
L
DD
DOUT Remains Valid After SCLK
CNVST Fall to SCLK Fall
t
V = 1.8V to V
DD
4
ns
ns
DHOLD
L
t
V = 1.8V to V
L DD
10
20
SETUP
CNVST Pulse Width
t
V = 1.8V to V
L DD
ns
CSW
Power-Up Time; Full Power-Down
Restart Time; Partial Power-Down
t
2
ms
PWR-UP
t
16
Cycles
RCV
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset
error have been nulled.
Note 2: No missing codes over temperature.
Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period.
Note 4: At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz.
Note 5: The listed value of three SCLK cycles is given for full-speed continuous conversions. Acquisition time begins on the 14th ris-
ing edge of SCLK and terminates on the next falling edge of CNVST. The IC idles in acquisition mode between conversions.
Note 6: Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SINAD performance.
Note 7: 1.5Msps operation guaranteed for V > 2.7V. See the Typical Operating Characteristics section for recommended sampling
L
speeds for V < 2.7V.
L
Note 8: Digital supply current is measured with the V level equal to V , and the V level equal to GND.
IH
L
IL
V
L
CNVST
SCLK
t
CSW
6kΩ
t
CL
t
SETUP
t
CH
DOUT
DOUT
6kΩ
C
L
C
L
t
DHOLD
t
DOUT
DOUT
GND
b) HIGH-Z TO V , V TO V ,
GND
a) HIGH-Z TO V , V TO V
,
OH
OH OL
OL OH
OL
AND V TO HIGH-Z
OH
AND V TO HIGH-Z
OL
Figure 1. Detailed Serial-Interface Timing
Figure 2. Load Circuits for Enable/Disable Times
4
_______________________________________________________________________________________
1.5Ms ps , Single -Supply, Low -Pow e r, True -
Diffe re ntia l, 12-Bit ADCs w ith Inte rna l Re fe re nc e
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = +3V, V = V , f
= 24MHz, f
= 1.5Msps, T = T
to T
, unless otherwise noted. Typical values are measured
MIN
MAX
DD
L
DD SCLK
SAMPLE
A
at T = +25°C.)
A
INTEGRAL NONLINEARITY
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1277)
MAXIMUM RECOMMENDED f
vs. V
vs. DIGITAL OUTPUT CODE (MAX1279)
SCLK
L
1.00
0.75
0.50
0.25
0
25
23
21
19
17
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
0
1024
2048
3072
4096
1.8
2.1
2.4
2.7
3.0
3.3
3.6
-2048
-1024
0
1024
2048
DIGITAL OUTPUT CODE
V (V)
L
DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1277)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1279)
OFFSET ERROR
vs. TEMPERATURE (MAX1277)
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
0
-1
-2
-3
-4
-5
-6
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
0
1024
2048
3072
4096
-2048
-1024
0
1024
2048
-40
-15
10
35
60
85
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
TEMPERATURE (°C)
GAIN ERROR
OFFSET ERROR
GAIN ERROR
vs. TEMPERATURE (MAX1279)
vs. TEMPERATURE (MAX1279)
vs. TEMPERATURE (MAX1277)
2
0
4
3
1
0
-1
-2
-3
-4
-5
-6
2
-1
-2
-3
-4
1
0
-1
-2
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
1.5Ms ps , Single -Supply, Low -Pow e r, True -
Diffe re ntia l, 12-Bit ADCs w ith Inte rna l Re fe re nc e
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +3V, V = V , f
= 24MHz, f
= 1.5Msps, T = T
to T
, unless otherwise noted. Typical values are measured
MIN
MAX
DD
L
DD SCLK
SAMPLE
A
at T = +25°C.)
A
DYNAMIC PERFORMANCE
DYNAMIC PERFORMANCE
vs. INPUT FREQUENCY (MAX1279)
vs. INPUT FREQUENCY (MAX1277)
70.0
69.5
69.0
68.5
68.0
70.0
69.5
69.0
68.5
SNR
SNR
SINAD
SINAD
68.0
100
100
200
300
400
500
500
750
200
300
400
500
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
THD vs. INPUT FREQUENCY
SFDR vs. INPUT FREQUENCY
-80
-84
-88
-92
92
90
88
86
84
82
MAX1277
MAX1279
MAX1277
MAX1279
-96
100
200
300
400
500
100
200
300
400
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
FFT PLOT (MAX1277)
FFT PLOT (MAX1279)
0
-20
0
-20
f
IN
= 500kHz
f = 500kHz
IN
SINAD = 68.7dB
SNR = 68.9dB
THD = -83.1dB
SFDR = 85.0dB
SINAD = 69.0dB
SNR = 69.1dB
THD = -88.9dB
SFDR = 85.9dB
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
-140
-140
0
125
250
375
500
625
750
0
125
250
375
500
625
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
6
_______________________________________________________________________________________
1.5Ms ps , Single -Supply, Low -Pow e r, True -
Diffe re ntia l, 12-Bit ADCs w ith Inte rna l Re fe re nc e
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +3V, V = V , f
= 24MHz, f
= 1.5Msps, T = T
to T
, unless otherwise noted. Typical values are measured
MIN
MAX
DD
L
DD SCLK
SAMPLE
A
at T = +25°C.)
A
TOTAL HARMONIC DISTORTION
vs. SOURCE IMPEDANCE
TWO-TONE IMD PLOT (MAX1277)
-50
-60
-70
-80
-90
0
-20
f
= 250.102kHz
= 299.966kHz
IN1
f
IN2
IMD = -88.4dB
f
IN
= 500kHz
-40
f
IN1
f
IN2
-60
-80
-100
-120
-140
f
IN
= 100kHz
-100
10
100
1000
0
125
250
375
500
625
750
SOURCE IMPEDANCE (Ω)
ANALOG INPUT FREQUENCY (kHz)
V /V FULL POWER-DOWN
DD L
SUPPLY CURRENT vs. TEMPERATURE
TWO-TONE IMD PLOT (MAX1279)
1.00
0.80
0.60
0.40
0.20
0
0
-20
f
= 250.102kHz
= 299.966kHz
IN1
f
IN2
IMD = -85.2dB
-40
f
IN1
f
IN2
-60
V , NO SCLK
L
V
, NO SCLK
DD
-80
V
, SCLK = 24MHz
DD
-100
-120
-140
0
-40
-15
10
35
60
85
125
250
375
500
625
750
TEMPERATURE (°C)
ANALOG INPUT FREQUENCY (kHz)
V
DD
SUPPLY CURRENT
V PARTIAL/FULL POWER-DOWN
L
vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
9.0
7.5
6.0
4.5
3.0
1.5
0
100
75
CONVERSION
V , = 1.8V, SCLK = 24MHz
L
V , = 3V, SCLK = 24MHz
L
50
PARTIAL POWER-DOWN
25
0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
1.5Ms ps , Single -Supply, Low -Pow e r, True -
Diffe re ntia l, 12-Bit ADCs w ith Inte rna l Re fe re nc e
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +3V, V = V , f
= 24MHz, f
= 1.5Msps, T = T
to T
, unless otherwise noted. Typical values are measured
MIN
MAX
DD
L
DD SCLK
SAMPLE
A
at T = +25°C.)
A
V
DD
SUPPLY CURRENT
V SUPPLY CURRENT
L
vs. CONVERSION RATE
vs. TEMPERATURE
8
6
4
2
0.50
0.40
0.30
0.20
0.10
0
CONVERSION, V = 3V
L
CONVERSION, V = 1.8V
L
0
0
250
500
750 1000 1250 1500
(kHz)
-40
-15
10
35
60
85
f
TEMPERATURE (°C)
SAMPLE
V SUPPLY CURRENT
L
vs. CONVERSION RATE
REFERENCE VOLTAGE
vs. TEMPERATURE
250
200
150
100
50
2.06
2.05
2.04
2.03
2.02
2.01
2.00
V = 3V
L
V = 1.8V
L
0
0
250
500
750 1000 1250 1500
(kHz)
-40
-15
10
35
60
85
f
TEMPERATURE (°C)
SAMPLE
REFERENCE VOLTAGE
vs. LOAD CURRENT (SOURCE)
REFERENCE VOLTAGE
vs. LOAD CURRENT (SINK)
2.05
2.04
2.03
2.02
2.08
2.07
2.06
2.05
2.04
2.01
0
2
4
6
8
0
50
100
150
200
LOAD CURRENT (mA)
LOAD CURRENT (µA)
8
_______________________________________________________________________________________
1.5Ms ps , Single -Supply, Low -Pow e r, True -
Diffe re ntia l, 12-Bit ADCs w ith Inte rna l Re fe re nc e
P in De s c rip t io n
PIN
NAME
FUNCTION
1
AIN-
Negative Analog Input
Reference Voltage Output. Internal 2.048V reference output. Bypass REF with a 0.01µF capacitor and
a 4.7µF capacitor to RGND.
2
3
4
REF
RGND
Reference Ground. Connect RGND to GND.
Positive Analog Supply Voltage (+2.7V to +3.6V). Bypass V with a 0.01µF capacitor and a 10µF
DD
capacitor to GND.
V
DD
5, 11
6
N.C.
No Connection
GND
Ground. GND is internally connected to EP.
Positive Logic Supply Voltage (1.8V to V ). Bypass V with a 0.01µF capacitor and a 10µF capacitor
to GND.
DD
L
7
8
9
V
L
DOUT
Serial Data Output. Data is clocked out on the rising edge of SCLK.
Convert Start. Forcing CNVST high prepares the part for a conversion. Conversion begins on the
falling edge of CNVST. The sampling instant is defined by the falling edge of CNVST.
CNVST
10
12
—
SCLK
AIN+
EP
Serial Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed.
Positive Analog Input
Exposed Paddle. EP is internally connected to GND.
V
L
CAPACITIVE
DAC
V
DD
C
IN+
R
IN+
REF
REF
AIN+
AIN-
2.048V
AIN +
12-BIT
SAR
ADC
CONTROL
LOGIC
OUTPUT
BUFFER
TRACK AND
HOLD
COMP
V
AZ
DOUT
AIN -
R
IN-
C
IN-
ACQUISITION MODE
CNVST
SCLK
CONTROL
LOGIC AND
TIMING
CAPACITIVE
DAC
RGND
MAX1277
MAX1279
C
IN+
R
IN+
AIN+
AIN-
GND
CONTROL
LOGIC
COMP
V
AZ
Figure 3. Functional Diagram
De t a ile d De s c rip t io n
R
IN-
C
IN-
The MAX1277/MAX1279 use an input T/H and succes-
sive-approximation register (SAR) circuitry to convert
an analog input signal to a digital 12-bit output. The
serial interface requires only three digital lines (SCLK,
CNVST, and DOUT) and provides easy interfacing to
microprocessors (µPs) and DSPs. Figure 3 shows the
simplified internal structure for the MAX1277/MAX1279.
HOLD/CONVERSION MODE
Figure 4. Equivalent Input Circuit
_______________________________________________________________________________________
9
1.5Ms ps , Single -Supply, Low -Pow e r, True -
Diffe re ntia l, 12-Bit ADCs w ith Inte rna l Re fe re nc e
signal bandwidth, making it possible to digitize high-
s p e e d tra ns ie nt e ve nts a nd me a s ure p e riod ic
signals with bandwidths exceeding the ADC’s sampling
ra te b y us ing und e rs a mp ling te c hniq ue s . To a void
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Tru e -Diffe re n t ia l An a lo g In p u t T/H
The equivalent circuit of Figure 4 shows the input archi-
tecture of the MAX1277/MAX1279, which is composed
of a T/H, a comparator, and a switched-capacitor digi-
tal-to-analog converter (DAC). The T/H enters its track-
ing mode on the 14th SCLK rising edge of the previous
conversion. Upon power-up, the T/H enters its tracking
mode immediately. The positive input capacitor is con-
nected to AIN+. The negative input capacitor is con-
nected to AIN-. The T/H enters its hold mode on the
falling edge of CNVST and the difference between the
sampled positive and negative input voltages is convert-
ed. The time required for the T/H to acquire an input sig-
nal is determined by how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens. The acquisition time,
An a lo g In p u t P ro t e c t io n
Internal protection diodes that clamp the analog input
to V
and GND allow the analog input pins to swing
DD
from GND - 0.3V to V
+ 0.3V without damage. Both
DD
inputs must not exceed V
or be lower than GND for
DD
accurate conversions.
S e ria l In t e rfa c e
In it ia liza t io n Aft e r P o w e r-Up
a n d S t a rt in g a Co n ve rs io n
t
, is the minimum time needed for the signal to be
ACQ
Upon initial power-up, the MAX1277/MAX1279 require a
complete conversion cycle to initialize the internal cali-
bration. Following this initial conversion, the part is ready
for normal operation. This initialization is only required
after a hardware power-up sequence and is not required
after exiting partial or full power-down mode.
acquired. It is calculated by the following equation:
t
≥ 9 × (RS + R ) × 16pF
IN
ACQ
where R = 200Ω, and RS is the source impedance of
IN
the input signal.
Note: t
is never less than 125ns and any source
ACQ
impedance below 12Ω does not significantly affect the
To start a conversion, pull CNVST low. At CNVST’s
falling edge, the T/H enters its hold mode and a conver-
sion is initiated. SCLK runs the conversion and the data
can then be shifted out serially on DOUT.
ADC’s AC performance.
In p u t Ba n d w id t h
The ADC’s input-tracking circuitry has a 15MHz small-
CNVST
t
SETUP
t
POWER-MODE SELECTION WINDOW
8
ACQUIRE
CONTINUOUS-CONVERSION
SELECTION WINDOW
1
2
3
4
14
16
SCLK
HIGH IMPEDANCE
DOUT
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5. Interface-Timing Sequence
CONVST MUST GO HIGH AFTER THE 3RD BUT BEFORE THE 14TH SCLK RISING EDGE
DOUT GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH
CNVST
ONE 8-BIT TRANSFER
SCLK
1ST SCLK RISING EDGE
DOUT
0
0
0
D11
D10
D9
D8
D7
MODE
REF
NORMAL
PPD
ENABLED (2.048V)
Figure 6. SPI Interface—Partial Power-Down Mode
10 ______________________________________________________________________________________
1.5Ms ps , Single -Supply, Low -Pow e r, True -
Diffe re ntia l, 12-Bit ADCs w ith Inte rna l Re fe re nc e
Full power-down mode is ideal for infrequent data sam-
pling and very low supply current applications. The
MAX1277/MAX1279 have to be in partial power-down
mod e to e nte r full p owe r-d own mod e . Pe rform the
SCLK/CNVST sequence described above to enter par-
tia l p owe r-d own mod e . The n re p e a t the s a me
sequence to enter full power-down mode (see Figure
7). Drive CNVST low, and allow at least 14 SCLK cycles
to elapse before driving CNVST high to exit full power-
down mode. While in full power-down mode, the refer-
ence is disabled to minimize power consumption. Be
sure to allow at least 2ms recovery time after exiting full
p owe r-d own mod e for the re fe re nc e to s e ttle . In
partial/full power-down mode, maintain a logic low or a
logic high on SCLK to minimize power consumption.
Tim in g a n d Co n t ro l
Conversion-start and data-read operations are con-
trolled by the CNVST and SCLK digital inputs. Figures 1
and 5 show timing diagrams, which outline the serial-
interface operation.
A CNVST falling edge initiates a conversion sequence;
the T/H stage holds the input voltage, the ADC begins
to convert, and DOUT changes from high impedance to
log ic low. SCLK is us e d to d rive the c onve rs ion
process, and it shifts data out as each bit of the conver-
sion is determined.
SCLK begins shifting out the data after the 4th rising
e d g e of SCLK. DOUT tra ns itions t
a fte r e a c h
DOUT
SCLK’s rising edge and remains valid 4ns (t
)
DHOLD
after the next rising edge. The 4th rising clock edge
produces the MSB of the conversion at DOUT, and the
MSB remains valid 4ns after the 5th rising edge. Since
there are 12 data bits and 3 leading zeros, at least 16
rising clock edges are needed to shift out these bits.
For continuous operation, pull CNVST high between the
14th and the 16th SCLK rising edges. If CNVST stays
low after the falling edge of the 16th SCLK cycle, the
DOUT line goes to a high-impedance state on either
CNVST’s rising edge or the next SCLK’s rising edge.
Tra ns fe r Func tion
Figure 8 shows the unipolar transfer function for the
MAX1277. Figure 9 shows the bipolar transfer function for
the MAX1279. The MAX1277 output is straight binary,
while the MAX1279 output is two’s complement.
Applic a tions Inform a tion
In t e rn a l Re fe re n c e
The MAX1277/MAX1279 have an on-chip voltage refer-
ence trimmed to 2.048V. The internal reference output
is connected to REF and also drives the internal capac-
itive DAC. The output can be used as a reference volt-
age source for other components and can source up to
2mA. Bypass REF with a 0.01µF capacitor and a 4.7µF
capacitor to RGND.
P a rt ia l P o w e r-Do w n a n d
Fu ll P o w e r-Do w n Mo d e s
Power consumption can be reduced significantly by plac-
ing the MAX1277/MAX1279 in either partial power-down
mode or full power-down mode. Partial power-down
mode is ideal for infrequent data sampling and fast wake-
up time applications. Pull CNVST high after the 3rd SCLK
rising edge and before the 14th SCLK rising edge to
enter and stay in partial power-down mode (see Figure
6). This reduces the supply current to 2mA. While in par-
tial power-down mode, the reference remains enabled to
allow valid conversions once the IC is returned to normal
mode. Drive CNVST low and allow at least 14 SCLK
cycles to elapse before driving CNVST high to exit partial
power-down mode.
The internal reference is continuously powered up dur-
ing both normal and partial power-down modes. In full
power-down mode, the internal reference is disabled.
Be sure to allow at least 2ms recovery time after hard-
ware power-up or exiting full power-down mode for the
reference to reach its intended value.
EXECUTE PARTIAL POWER-DOWN TWICE
SECOND 8-BIT TRANSFER
CNVST
FIRST 8-BIT TRANSFER
SCLK
DOUT ENTERS TRI-STATE ONCE CNVST GOES HIGH
1ST SCLK RISING EDGE
D11
1ST SCLK RISING EDGE
D8 D7
DOUT
0
0
0
D10
D9
0
0
0
0
0
0
0
0
MODE
REF
NORMAL
PPD
ENABLED (2.048V)
RECOVERY
FPD
DISABLED
Figure 7. SPI Interface—Full Power-Down Mode
______________________________________________________________________________________ 11
1.5Ms ps , Single -Supply, Low -Pow e r, True -
Diffe re ntia l, 12-Bit ADCs w ith Inte rna l Re fe re nc e
How to Sta rt a Conve rs ion
An analog-to-digital conversion is initiated by CNVST,
OUTPUT CODE
clocked by SCLK, and the resulting data is clocked out on
DOUT by SCLK. With SCLK idling high or low, a falling
FULL-SCALE
TRANSITION
111...111
111...110
edge on CNVST begins a conversion. This causes the
analog input stage to transition from track to hold mode,
and for DOUT to transition from high impedance to being
actively driven low. A total of 16 SCLK cycles are required
to complete a normal conversion. If CNVST is low during
the 16th falling SCLK edge, DOUT returns to high imped-
ance on the next rising edge of CNVST or SCLK, enabling
the serial interface to be shared by multiple devices. If
CNVST returns high after the 14th, but before the 16th
SCLK rising edge, DOUT remains active so continuous
conversions can be sustained. The highest throughput is
achieved when performing continuous conversions. Figure
10 illustrates a conversion using a typical serial interface.
111...101
FS = V
REF
ZS = 0
V
4096
REF
1 LSB =
000...011
000...010
000...001
000...000
Conne c tion to
Sta nda rd Inte rfa c e s
The MAX1277/MAX1279 serial interface is fully compati-
ble with SPI/QSPI and MICROWIRE (see Figure 11). If a
serial interface is available, set the CPU’s serial interface
in master mode so the CPU generates the serial clock.
Choose a clock frequency up to 24MHz.
0
1
2
3
FS
FS - 3/2 LSB
DIFFERENTIAL INPUT
VOLTAGE (LSB)
Figure 8. Unipolar Transfer Function (MAX1277 Only)
SPI a nd MICROWIRE
When using SPI or MICROWIRE, the MAX1277/ MAX1279
are compatible with all four modes programmed with the
CPHA and CPOL bits in the SPI or MICROWIRE control
register. Conversion begins with a CNVST falling edge.
DOUT goes low, indicating a conversion is in progress.
Two consecutive 1-byte reads are required to get the full
12 bits from the ADC. DOUT transitions on SCLK rising
OUTPUT CODE
V
2
ZS = 0
FULL-SCALE
TRANSITION
REF
FS =
011...111
011...110
-V
2
REF
- FS =
V
REF
1 LSB =
edges. DOUT is guaranteed to be valid t
later and
DOUT
000...010
000...001
4096
remains valid until t
after the following SCLK rising
DHOLD
edge. When using CPOL = 0 and CPHA = 0, or CPOL = 1
and CPHA = 1, the data is clocked into the µP on the fol-
lowing rising edge. When using CPOL = 0 and CPHA = 1,
or CPOL = 1 and CPHA = 0, the data is clocked into the
µP on the next falling edge. See Figure 11 for connections
a nd Fig ure s 12 a nd 13 for timing . Se e the Timing
Characteristics section to determine the best mode to use.
000...000
111...111
111...110
111...101
QS P I
Unlike SPI, which requires two 1-byte reads to acquire
the 12 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles necessary to clock in the
data. The MAX1277/MAX1279 require 16 clock cycles
from the µP to clock out the 12 bits of data. Figure 14
shows a transfer using CPOL = 1 and CPHA = 1. The
conversion result contains three zeros, followed by the
12 data bits, and a trailing zero with the data in MSB-
first format.
100...001
100...000
-FS
0
FS
FS - 3/2 LSB
DIFFERENTIAL INPUT
VOLTAGE (LSB)
Figure 9. Bipolar Transfer Function (MAX1279 Only)
12 ______________________________________________________________________________________
1.5Ms ps , Single -Supply, Low -Pow e r, True -
Diffe re ntia l, 12-Bit ADCs w ith Inte rna l Re fe re nc e
CNVST
SCLK
1
14
16
1
DOUT
0
0
0
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
Figure 10. Continuous Conversion with Burst/Continuous Clock
I/O
CNVST
SCLK
DOUT
SCK
MISO
+3V TO +5V
MAX1277
MAX1279
SS
A) SPI
CS
CNVST
SCK
SCLK
DOUT
MISO
+3V TO +5V
MAX1277
MAX1279
SS
B) QSPI
I/O
SK
SI
CNVST
SCLK
DOUT
MAX1277
MAX1279
C) MICROWIRE
Figure 11. Common Serial-Interface Connections to the MAX1277/MAX1279
______________________________________________________________________________________ 13
1.5Ms ps , Single -Supply, Low -Pow e r, True -
Diffe re ntia l, 12-Bit ADCs w ith Inte rna l Re fe re nc e
CNVST
8
9
16
1
SCLK
DOUT
HIGH-Z
HIGH-Z
D11
D8
D7
D6
D5
D4
D3
D2
D1
D0
D10
D9
Figure 12. SPI/MICROWIRE Serial-Interface Timing—Single Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
CNVST
SCLK
DOUT
14
16
1
1
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
Figure 13. SPI/MICROWIRE Serial-Interface Timing—Continuous Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
CNVST
2
16
SCLK
DOUT
HIGH-Z
HIGH-Z
D1
D11
D8
D7
D6
D5
D4
D3
D2
D0
D10 D9
Figure 14. QSPI Serial-Interface Timing—Single Conversion (CPOL = 1, CPHA = 1)
mit a clock, and pulse the frame sync signal for a clock
period before data transmission. The serial-port config-
uration (SPC) register should be set up with internal
frame sync (TXM = 1), CLKX driven by an on-chip clock
source (MCM = 1), burst mode (FSM = 1), and 16-bit
word length (FO = 0).
DS P In t e rfa c e t o t h e TMS 3 2 0 C5 4 _
The MAX1277/MAX1279 can be directly connected
to the TMS320C54_ fa mily of DSPs from Te xa s
Ins trume nts , Inc . Se t the DSP to g e ne ra te its own
clocks or use external clock signals. Use either the
standard or buffered serial port. Figure 15 shows the
simplest interface between the MAX1277/MAX1279 and
the TMS320C54_, whe re the tra ns mit s e ria l c loc k
(CLKX) d rive s the re c e ive s e ria l c loc k (CLKR) a nd
SCLK, and the transmit frame sync (FSX) drives the
receive frame sync (FSR) and CNVST.
This setup allows continuous conversions provided that
the data transmit register (DXR) and the data-receive
register (DRR) are serviced before the next conversion.
Alternatively, autobuffering can be enabled when using
the buffered serial port to execute conversions and
read the data without CPU intervention. Connect the V
For continuous conversion, set the serial port to trans-
L
14 ______________________________________________________________________________________
1.5Ms ps , Single -Supply, Low -Pow e r, True -
Diffe re ntia l, 12-Bit ADCs w ith Inte rna l Re fe re nc e
p in to the TMS320C54_ s up p ly volta g e whe n the
MAX1277/MAX1279 are operating with an analog sup-
ply voltage higher than the DSP supply voltage. The
word length can be set to 8 bits with FO = 1 to imple-
ment the power-down modes. The CNVST pin must idle
high to remain in either power-down state.
CLKR, and SCLK and the convert signal (CONVERT)
drive the FSR and CNVST.
The serial port must be set up to accept an external
receive-clock and external receive-frame sync.
The SPC register should be written as follows:
TXM = 0, external frame sync
Another method of connecting the MAX1277/MAX1279
to the TMS320C54_ is to generate the clock signals
external to either device. This connection is shown in
Fig ure 16, whe re s e ria l c loc k (CLOCK) d rive s the
MCM = 0, CLKX is taken from the CLKX pin
FSM = 1, burst mode
FO = 0, data transmitted/received as 16-bit words
This setup allows continuous conversion, provided that
the DRR is s e rvic e d b e fore the ne xt c onve rs ion.
Alternatively, autobuffering can be enabled when using
the buffered serial port to read the data without CPU
V
L
DV
DD
intervention. Connect the V pin to the TMS320C54_
L
MAX1277
MAX1279
TMS320C54_
SCLK
CLKX
CLKR
FSX
FSR
supply voltage when the MAX1277/MAX1279 are oper-
ating with an analog supply voltage higher than the
DSP supply voltage.
CNVST
DOUT
The MAX1277/MAX1279 can also be connected to the
TMS320C54_ by using the data transmit (DX) pin to
drive CNVST and the CLKX generated internally to
drive SCLK. A pullup resistor is required on the CNVST
signal to keep it high when DX goes high impedance
and 0001hex should be written to the DXR continuously
for continuous conversions. The power-down modes
may be entered by writing 00FFhex to the DXR (see
Figures 17 and 18).
DR
Figure 15. Interfacing to the TMS320C54_ Internal Clocks
V
L
DV
DD
DS P In t e rfa c e t o t h e ADS P 2 1 _ _ _
The MAX1277/MAX1279 can be directly connected to
the ADSP21_ _ _ family of DSPs from Analog Devices,
Inc . Fig ure 19 s hows the d ire c t c onne c tion of the
MAX1277/MAX1279 to the ADSP21_ _ _. There are two
modes of operation that can be programmed to interface
with the MAX1277/MAX1279. For continuous conver-
sions, idle CNVST low and pulse it high for one clock
cycle during the LSB of the previous transmitted word.
The ADSP21_ _ _ STCTL and SRCTL registers should be
configured for early framing (LAFR = 0) and for an
MAX1277
MAX1279
TMS320C54_
SCLK
CNVST
DOUT
CLKR
FSR
DR
CLOCK
CONVERT
Figure 16. Interfacing to the TMS320C54_ External Clocks
CNVST
SCLK
DOUT
1
1
D0
0
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
Figure 17. DSP Interface—Continuous Conversion
______________________________________________________________________________________ 15
1.5Ms ps , Single -Supply, Low -Pow e r, True -
Diffe re ntia l, 12-Bit ADCs w ith Inte rna l Re fe re nc e
CNVST
SCLK
DOUT
1
1
0
0
0
0
0
D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
Figure 18. DSP Interface—Single-Conversion, Continuous/Burst Clock
and for an active-low frame (LTFS = 1, LRFS = 1) signal.
This is also the best way to enter the power-down modes
by setting the word length to 8 bits (SLEN = 1001).
V
L
VDDINT
TCLK
RCLK
TFS
Connect the V pin to the ADSP21_ _ _ supply voltage
MAX1277
MAX1279
L
SCLK
ADSP21_ _ _
when the MAX1277/MAX1279 are operating with a sup-
ply voltage higher than the DSP supply voltage (see
Figures 17 and 18).
CNVST
DOUT
RFS
DR
La yo u t , Gro u n d in g , a n d Byp a s s in g
For b e s t p e rforma nc e , us e PC b oa rd s . Wire -wra p
boards are not recommended. Board layout should
ensure that digital and analog signal lines are separat-
e d from e a c h othe r. Do not run a na log a nd d ig ita l
(especially clock) lines parallel to one another, or digital
lines underneath the ADC package.
Figure 19. Interfacing to the ADSP21_ _ _
Figure 20 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at GND, separate from the logic
ground. Connect all other analog grounds and DGND
to this star ground point for further noise reduction. The
g round re turn to the p owe r s up p ly for this g round
should be low impedance and as short as possible for
noise-free operation.
SUPPLIES
GND
V
L
10µF
10µF
0.1µF
0.1µF
High-frequency noise in the V
power supply can
DD
affect the ADC’s high-speed comparator. Bypass this
supply to the single-point analog ground with 0.01µF
and 10µF bypass capacitors. Minimize capacitor lead
lengths for best supply-noise rejection.
V
DD
V
L
GND RGND
DGND
V
L
DIGITAL
CIRCUITRY
De finitions
MAX1277
MAX1279
Inte gra l Nonline a rity
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The static
linearity parameters for the MAX1277/MAX1279 are mea-
sured using the end-points method.
Figure 20. Power-Supply Grounding Condition
active-high frame (LTFS = 0, LRFS = 0) signal. In this
mode, the data-independent frame-sync bit (DITFS = 1)
can be selected to eliminate the need for writing to the
transmit-data register more than once. For single conver-
sions, idle CNVST high and pulse it low for the entire
conversion. The ADSP21_ _ _ STCTL and SRCTL regis-
ters should be configured for late framing (LAFR = 1)
16 ______________________________________________________________________________________
1.5Ms ps , Single -Supply, Low -Pow e r, True -
Diffe re ntia l, 12-Bit ADCs w ith Inte rna l Re fe re nc e
Diffe re ntia l Nonline a rity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A DNL
error specification of 1 LSB or less guarantees no missing
codes and a monotonic transfer function.
Tota l Ha rm onic Dis tortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
Ape rture J itte r
Aperture jitter (t ) is the sample-to-sample variation in
⎛
⎜
⎞
⎟
2
2
2
2
4
2
V + V + V + V
5
3
AJ
THD = 20 x log
⎜
⎜
⎝
⎟
⎟
⎠
the time between the samples.
V
1
Ape rture De la y
Aperture delay (t ) is the time defined between the
falling edge of CNVST and the instant when an actual
sample is taken.
AD
whe re V is the fund a me nta l a mp litud e , a nd V
2
1
through V are the amplitudes of the 2nd- through 5th-
5
order harmonics.
Signa l-to-Nois e Ra tio
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SNR) is the ratio of the full-
scale analog input (RMS value) to the RMS quantization
error (residual error). The theoretical minimum analog-to-
digital noise is caused by quantization error, and results
directly from the ADC’s resolution (N bits):
Spurious -Fre e Dyna m ic Ra nge
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest distor-
tion component.
Fu ll-P o w e r Ba n d w id t h
Full-power bandwidth is the frequency at which the
input signal amplitude attenuates by 3dB for a full-scale
input.
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantiza-
tion noise, including thermal noise, reference noise, clock
jitter, etc. Therefore, SNR is computed by taking the ratio
of the RMS signal to the RMS noise, which includes all
spectral components minus the fundamental, the first five
harmonics, and the DC offset.
Fu ll-Lin e a r Ba n d w id t h
Full-linear bandwidth is the frequency at which the sig-
nal to noise plus distortion (SINAD) is equal to 68dB.
In t e rm o d u la t io n Dis t o rt io n (IMD)
Any device with nonlinearities creates distortion prod-
ucts when two sine waves at two different frequencies
(f1 and f2) are input into the device. Intermodulation
distortion (IMD) is the total power of the IM2 to IM5
intermodulation products to the Nyquist frequency rela-
tive to the total input power of the two input tones, f1
and f2. The individual input tone levels are at -7dBFS.
The intermodulation products are as follows:
Signa l-to-Nois e Plus Dis tortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
SINAD(dB) = 20 x log (Signal
/ Noise
)
RMS
RMS
Effe c tive Num be r of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantiza-
tion noise only. With an input range equal to the full-scale
range of the ADC, calculate the ENOB as follows:
• 2nd-order intermodulation products (IM2): f + f ,
1
2
f - f
2
1
• 3rd-order intermodulation products (IM3): 2f - f ,
1
2
2f - f , 2f + f , 2f + f
2
1
1
2
2
1
• 4th-order intermodulation products (IM4): 3f - f ,
1
2
3f - f , 3f + f , 3f + f
(SINAD − 1.76)
ENOB =
2
1
1
2
2
1
• 5th-order intermodulation products (IM5): 3f - 2f ,
6.02
1
2
3f - 2f , 3f + 2f , 3f + 2f
2
1
1
2
2
1
Ch ip In fo rm a t io n
TRANSISTOR COUNT: 13,016
PROCESS: BiCMOS
PACKAGE CODE: T1244-3
______________________________________________________________________________________ 17
1.5Ms ps , Single -Supply, Low -Pow e r, True -
Diffe re ntia l, 12-Bit ADCs w ith Inte rna l Re fe re nc e
P a c k a g e In fo rm a t io n
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
12, 16, 20, 24L THIN QFN, 4x4x0.8mm
1
C
21-0139
2
PACKAGE OUTLINE
12, 16, 20, 24L THIN QFN, 4x4x0.8mm
2
C
21-0139
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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