MAX127ACAI+T [MAXIM]
Analog Circuit, 1 Func, PDSO28, SSOP-28;
| 型号： | MAX127ACAI+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Analog Circuit, 1 Func, PDSO28, SSOP-28 |
| 文件： | 总16页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4773; Rev 0; 7/98
Mu lt ira n g e , +5 V, 1 2 -Bit DAS w it h
2 -Wire S e ria l In t e rfa c e
7/MAX128
Ge n e ra l De s c rip t io n
Fe a t u re s
The MAX127/MAX128 a re multira ng e , 12-b it d a ta
acquisition systems (DAS) that require only a single
+5V supply for operation, yet accept signals at their
analog inputs that may span above the power-supply
rail and below ground. These systems provide eight
analog input channels that are independently software
programmable for a variety of ranges: ±10V, ±5V, 0 to
+10V, 0 to +5V for the MAX127; and ±V , ±V /2, 0
♦ 12-Bit Resolution, 1/2 LSB Linearity
♦ +5V Single-Supply Operation
♦ I2C-Compatible, 2-Wire Serial Interface
♦ Four Software-Selectable Input Ranges
MAX127: 0 to +10V, 0 to +5V, ±10V, ±5V
MAX128: 0 to +V
, 0 to +V
/2, ±V
,
REF
REF
REF
REF
REF
to +V
, 0 to +V
/2 for the MAX128. This range
REF
REF
±V
/2
REF
switching increases the effective dynamic range to 14
bits and provides the flexibility to interface 4–20mA,
±12V, and ±15V-powered sensors directly to a single
+5V system. In addition, these converters are fault pro-
tected to ±16.5V; a fault condition on any channel will
not affect the conversion result of the selected channel.
Other features include a 5MHz bandwidth track/hold,
an 8ksps throughput rate, and the option of an internal
4.096V or external reference.
♦ 8 Analog Input Channels
♦ 8ksps Sampling Rate
♦ ±16.5V Overvoltage-Tolerant Input Multiplexer
♦ Internal 4.096V or External Reference
♦ Two Power-Down Modes
♦ 24-Pin Narrow DIP or 28-Pin SSOP Packages
The MAX127/MAX128 feature a 2-wire, I2C-compatible
serial interface that allows communication among multi-
ple devices using SDA and SCL lines.
Typ ic a l Op e ra t in g Circ u it
A hardware shutdown input (SHDN) and two software-
programmable power-down modes (standby and full
power-down) are provided for low-current shutdown
between conversions. In standby mode, the reference-
buffer remains active, eliminating start-up delays.
+5V
0.1µF
The MAX127/MAX128 are available in 24-pin DIP or
space-saving 28-pin SSOP packages.
µC
V
DD
SCL SDA
SHDN
Ap p lic a t io n s
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
Industrial Control Systems
Data-Acquisition Systems
Robotics
1k
ANALOG
INPUTS
MAX127
MAX128
Automatic Testing
SCL
SDA
A0
Battery-Powered Instruments
Medical Instruments
REF
A1
REFADJ
A2
4.7µF
0.01µF
AGND
DGND
Ord e rin g In fo rm a t io n
INL
(LSB)
PART
TEMP. RANGE
PIN-PACKAGE
MAX127ACNG 0°C to +70°C 24 Narrow Plastic DIP ±1/2
MAX127ACNG 0°C to +70°C 24 Narrow Plastic DIP ±1
Ordering Information continued at end of data sheet.
Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
Mu lt ira n g e , +5 V, 1 2 -Bit DAS w it h
2 -Wire S e ria l In t e rfa c e
ABSOLUTE MAXIMUM RATINGS
V
DD
to AGND............................................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
AGND to DGND.....................................................-0.3V to +0.3V
CH0–CH7 to AGND ......................................................... ±16.5V
24-Pin Narrow DIP (derate 13.33mW/°C above +70°C)..1067mW
28-Pin SSOP (derate 9.52mW/°C above +70°C) ...............762mW
Operating Temperature Ranges
REF to AGND..............................................-0.3V to (V + 0.3V)
DD
REFADJ to AGND.......................................-0.3V to (V + 0.3V)
MAX127_ C_ _/MAX128_ C_ _.............................0°C to +70°C
MAX127_ E_ _/MAX128_ E_ _ ..........................-40°C to +85°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10sec) ............................+300°C
DD
A0, A1, A2 to DGND...................................-0.3V to (V + 0.3V)
DD
SHDN, SCL, SDA to DGND......................................-0.3V to +6V
Max Current into Any Pin ....................................................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +5V ±5%; unipolar/bipolar range; external reference mode, V
= 4.096V; 4.7µF at REF; external clock, f
= 400kHz;
REF
CLK
DD
7/MAX128
T
A
= T
to T
; unless otherwise noted. Typical values are at T = +25°C.)
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY (Note 1)
Resolution
12
Bits
LSB
LSB
MAX127A/MAX128A
MAX127B/MAX128B
±1/2
±1
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
±1
MAX127A/MAX128A
±3
Unipolar
Bipolar
MAX127B/MAX128B
MAX127A/MAX128A
MAX127B/MAX128B
±5
Offset Error
LSB
LSB
±5
±10
Unipolar
Bipolar
±0.1
±0.3
Channel-to-Channel Offset
Error Matching
MAX127A/MAX128A
MAX127B/MAX128B
MAX127A/MAX128A
MAX127B/MAX128B
±7
±10
±7
Unipolar
Bipolar
Gain Error (Note 2)
LSB
±10
Unipolar
Bipolar
3
5
Gain Tempco (Note 2)
ppm/°C
dB
DYNAMIC SPECIFICATIONS (800Hz sine-wave input, ±10Vp-p (MAX127) or ±4.096Vp-p (MAX128), f
= 8ksps)
SAMPLE
Signal-to-Noise plus Distortion
Ratio
SINAD
70
Total Harmonic Distortion
Spurious-Free Dynamic Range
THD
Up to the 5th harmonic
-87
-80
dB
dB
SFDR
81
4kHz, V = ±5V (Note 3)
-86
-96
200
10
IN
Channel-to-Channel Crosstalk
dB
DC, V = ±16.5V
IN
Aperture Delay
Aperture Jitter
ns
ns
2
_______________________________________________________________________________________
Mu lt ira n g e , +5 V, 1 2 -Bit DAS w it h
2 -Wire S e ria l In t e rfa c e
7/MAX128
ELECTRICAL CHARACTERISTICS (continued)
(V = +5V ±5%; unipolar/bipolar range; external reference mode, V
= 4.096V; 4.7µF at REF pin; external clock, f
= 400kHz;
REF
CLK
DD
T
A
= T
to T
; unless otherwise noted. Typical values are at T = +25°C.)
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Track/Hold Acquisition Time
3
µs
±10V or ±V
range
5
REF
±5V or ±V /2 range
2.5
2.5
1.25
REF
-3dB
rolloff
Small-Signal Bandwidth
MHz
0 to 10V or 0 to V
range
REF
0 to 5V or 0 to V /2 range
REF
0
0
10
5
MAX127
MAX128
MAX127
MAX128
Unipolar,
Table 3
0
V
REF
0
V
/2
REF
Input Voltage Range
V
IN
V
-10
-5
10
5
Bipolar,
Table 3
-V
REF
V
REF
-V /2
REF
V
/2
REF
0 to 10V range
MAX127
-10
-10
720
360
10
Unipolar
Bipolar
0 to 5V range
MAX128
-10
0.1
Input Current
I
IN
±10V range
MAX127
-1200
-600
-1200
-600
720
360
10
µA
±5V range
±V
range
REF
MAX128
±V /2 range
10
REF
Unipolar
Bipolar
21
16
∆V
∆I
IN
IN
Input Resistance
kΩ
Input Capacitance
(Note 4)
40
pF
INTERNAL REFERENCE
REFOUT Voltage
V
T
= +25°C
4.076
4.096
±15
4.116
V
REF
A
MAX127_C/MAX128_C
MAX127_E/MAX128_E
REFOUT Tempco
TC V
ppm/°C
REF
±30
Output Short-Circuit Current
Load Regulation (Note 5)
Capacitive Bypass at REF
REFADJ Output Voltage
REFADJ Adjustment Range
Buffer Voltage Gain
30
10
mA
mV
µF
0 to 0.5mA output current
Figure 12
4.7
2.465
2.500
±1.5
2.535
V
%
1.638
V/V
_______________________________________________________________________________________
3
Mu lt ira n g e , +5 V, 1 2 -Bit DAS w it h
2 -Wire S e ria l In t e rfa c e
ELECTRICAL CHARACTERISTICS (continued)
(V = +5V ±5%; unipolar/bipolar range; external reference mode, V
= 4.096V; 4.7µF at REF pin; external clock, f
= 400kHz;
REF
CLK
DD
T
A
= T
to T
; unless otherwise noted. Typical values are at T = +25°C.)
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
REFERENCE INPUT (buffer disabled, reference input applied to REF)
Input Voltage Range
2.4
4.18
400
1
V
Normal, or STANDBY
power-down mode
V
4.18V
=
REF
Input Current
µA
FULL power-down mode
Normal or STANDBY power-down mode
FULL power-down mode
10
5
kΩ
Input Resistance
MΩ
REFADJ Threshold for
Buffer Disable
V
DD
- 0.5
V
POWER REQUIREMENTS
7/MAX128
Supply Voltage
V
4.75
5.25
18
V
DD
Normal mode, bipolar ranges
Normal mode, unipolar ranges
STANDBY power-down mode (Note 6)
FULL power-down mode
mA
6
10
Supply Current
I
DD
700
120
±0.1
±0.5
850
220
±0.5
µA
External reference = 4.096V
Internal reference
Power-Supply Rejection Ratio
(Note 7)
PSRR
LSB
TIMING
External Clock Frequency Range
Conversion Time
f
0.4
10.0
8
MHz
µs
CLK
t
6.0
7.7
CONV
Throughput Rate
ksps
Bandgap Reference
Start-Up Time
Power-up (Note 8)
200
µs
C
C
= 4.7µF
= 33µF
8
REF
REF
To 0.1mV, REF bypass
capacitor fully discharged
Reference Buffer Settling Time
ms
60
DIGITAL INPUTS (SHDN, A2, A1, A0)
Input High Threshold Voltage
Input Low Threshold Voltage
Input Leakage Current
Input Capacitance
V
2.4
V
V
IH
V
IL
0.8
I
IN
V
= 0 or V
DD
±0.1
0.2
±10
15
µA
pF
V
IN
C
(Note 4)
IN
Input Hysteresis
V
HYS
4
_______________________________________________________________________________________
Mu lt ira n g e , +5 V, 1 2 -Bit DAS w it h
2 -Wire S e ria l In t e rfa c e
7/MAX128
ELECTRICAL CHARACTERISTICS (continued)
(V = +5V ±5%; unipolar/bipolar range; external reference mode, V
= 4.096V; 4.7µF at REF pin; external clock, f
= 400kHz;
REF
CLK
DD
T
A
= T
to T
; unless otherwise noted. Typical values are at T = +25°C.)
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (SDA, SCL)
Input High Threshold Voltage
Input Low Threshold Voltage
Input Hysteresis
V
0.7 x V
V
IH
DD
V
IL
0.3 x V
V
V
DD
V
HYS
0.05 x V
DD
Input Leakage Current
Input Capacitance
I
V
= 0 or V
±0.1
±10
15
µA
pF
IN
IN
DD
C
(Note 4)
IN
DIGITAL OUTPUTS (SDA)
I
= 3mA
0.4
0.6
15
SINK
Output Low Voltage
V
V
OL
I
= 6mA
SINK
Three-State Output Capacitance
C
(Note 4)
pF
OUT
TIMING CHARACTERISTICS
(V
= +4.75V to +5.25V; unipolar/bipolar range; external reference mode, V
= 4.096V; 4.7µF at REF pin; T = T
to T
;
REF
A
MIN
MAX
DD
unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETERS
2-WIREFASTMODE
SCL Clock Frequency
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
f
400
kHz
µs
SCL
Bus Free Time Between a
STOP and START Condition
t
1.3
0.6
BUF
Hold Time (Repeated)
START Condition
t
t
µs
HD,STA
Low Period of the SCL Clock
High Period of the SCL Clock
t
1.3
0.6
µs
µs
LOW
t
HIGH
Set-Up Time for a Repeated
START Condition
0.6
µs
SU,STA
Data Hold Time
Data Setup Time
t
0
0.9
µs
ns
HD,DAT
t
100
SU,DAT
20 +
0.1 x C
300
300
250
Rise Time for Both SDA and SCL
Signals (Receiving)
t
C
C
C
= Total capacitance of one bus line in pF
= Total capacitance of one bus line in pF
= Total capacitance of one bus line in pF
ns
ns
R
b
b
b
b
b
b
20 +
0.1 x C
Fall Time for Both SDA and SCL
Signals (Receiving)
t
F
F
20 +
0.1 x C
Fall Time for Both SDA and SCL
Signals (Transmitting)
t
ns
µs
pF
ns
Set-Up Time for STOP Condition
t
0.6
SU,STO
Capacitive Load for Each
Bus Line
C
400
50
b
Pulse Width of Spike Suppressed
t
SP
0
_______________________________________________________________________________________
5
Mu lt ira n g e , +5 V, 1 2 -Bit DAS w it h
2 -Wire S e ria l In t e rfa c e
TIMING CHARACTERISTICS (continued)
(V
= +4.75V to +5.25V; unipolar/bipolar range; external reference mode, V
= 4.096V; 4.7µF at REF pin; T = T
to T
MIN MAX;
DD
REF
A
unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETERS
2-WIRE STANDARD MODE
SCL Clock Frequency
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
100
kHz
µs
SCL
Bus Free Time Between a STOP
and START Condition
t
4.7
4.0
BUF
Hold Time (Repeated) START
Condition
t
µs
HD,STA
Low Period of the SCL Clock
High Period of the SCL Clock
t
4.7
4.0
µs
µs
LOW
t
HIGH
Setup Time for a Repeated
START Condition
t
4.7
µs
SU, STA
7/MAX128
Data Hold Time
Data Setup Time
t
0
0.9
µs
ns
HD, DAT
t
250
SU, DAT
Rise Time for Both SDA and SCL
Signals (Receiving)
t
1000
ns
ns
R
Fall Time for Both SDA and SCL
Signals (Receiving)
t
t
300
250
F
F
20 +
0.1 x C
Fall Time for Both SDA and SCL
Signals (Transmitting)
C = total capacitance of one bus line in pF,
b
up to 6mA sink
ns
µs
pF
ns
b
Setup Time for STOP Condition
t
4.0
SU, STO
Capacitive Load for Each
Bus Line
C
400
50
b
Pulse Width of Spike Suppressed
t
SP
0
Note 1: Accuracy specifications tested at V = 5.0V. Performance at power-supply tolerance limits is guaranteed by Power-
DD
Supply Rejection test.
Note 2: External reference: V
= 4.096V, offset error nulled, ideal last-code transition = FS - 3/2LSB.
REF
Note 3: Ground “on” channel, sine wave applied to all “off” channels.
Note 4: Guaranteed by design. Not tested.
Note 5: Use static external load during conversion for specified accuracy.
Note 6: Tested using internal reference.
Note 7: PSRR measured at full scale. Tested for the ±10V (MAX127) and ±4.096V (MAX128) input ranges.
Note 8: Not subject to production testing. Provided for design guidance only.
6
_______________________________________________________________________________________
Mu lt ira n g e , +5 V, 1 2 -Bit DAS w it h
2 -Wire S e ria l In t e rfa c e
7/MAX128
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
= 4.096V; 4.7µF at REF; external clock, f = 400kHz; T = +25°C; unless otherwise noted.)
CLK
A
(V = +5V, external reference mode, V
DD
REF
STANDBY SUPPLY CURRENT
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
vs. TEMPERATURE
25
6.5
6.3
6.1
5.9
5.7
5.5
750
650
20
15
10
5
INTERNAL
REFERENCE
550
450
350
250
EXTERNAL
REFERENCE
150
50
0
0
1
2
3
4
5
6
7
-40
-15
10
35
60
85
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
CHANNEL-TO-CHANNEL OFFSET-ERROR
MATCHING vs. TEMPERATURE
FULL POWER-DOWN SUPPLY CURRENT
vs. TEMPERATURE
NORMALIZED REFERENCE VOLTAGE
vs. TEMPERATURE
0.35
0.30
0.25
150
130
1.001
1.000
BIPOLAR MODE
EXTERNAL
REFERENCE
110
90
0.999
0.998
0.997
0.996
0.20
0.15
0.10
0.05
0
INTERNAL
REFERENCE
UNIPOLAR MODE
70
50
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
CHANNEL-TO-CHANNEL GAIN-ERROR
MATCHING vs. TEMPERATURE
INTEGRAL NONLINEARITY vs.
DIGITAL CODE
FFT PLOT
0.8
0.7
0.6
0.15
0.10
0.05
0
0
-20
V
= 5V
= 800Hz
DD
f
IN
f
= 8kHz
SAMPLE
UNIPOLAR MODE
BIPOLAR MODE
-40
0.5
0.4
-60
-0.05
-0.10
-0.15
-80
0.3
0.2
0.1
-100
-110
-40
-15
10
35
60
85
0
819
1638
2457
3276
4095
0
800
1600
2400
3200
4000
TEMPERATURE (°C)
DIGITAL CODE
FREQUENCY (Hz)
_______________________________________________________________________________________
7
Mu lt ira n g e , +5 V, 1 2 -Bit DAS w it h
2 -Wire S e ria l In t e rfa c e
P in De s c rip t io n
PIN
NAME
FUNCTION
DIP
SSOP
1, 2
1, 2
V
+5V Supply. Bypass with a 0.1µF capacitor to AGND.
No Connect. No internal connection.
DD
4, 7, 8, 11, 22,
24, 25, 28
3, 9, 22, 24
N.C.
4
5
3
5
DGND
SCL
Digital Ground
Serial Clock Input
Address Select Inputs
6, 8, 10
6, 10, 12
A0, A2, A1
Open-Drain Serial Data I/O. Input data is clocked in on the rising edge of SCL,
and output data is clocked out on the falling edge of SCL. External pull-up
resistor required.
7
9
SDA
Shutdown Input. When low, device is in full power-down (FULLPD) mode.
Connect high for normal operation.
7/MAX128
11
13
SHDN
12
14
AGND
Analog Ground
13–20
15–21, 23
CH0–CH7
Analog Input Channels
Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01µF
capacitor to AGND. Connect to V when using an external reference at REF.
DD
21
23
26
27
REFADJ
REF
Reference Buffer Output/ADC Reference Input. In internal reference mode, the
reference buffer provides a 4.096V nominal output, externally adjustable at
REFADJ. In external reference mode, disable the internal reference by pulling
REFADJ to V and applying the external reference to REF.
DD
8
_______________________________________________________________________________________
Mu lt ira n g e , +5 V, 1 2 -Bit DAS w it h
2 -Wire S e ria l In t e rfa c e
7/MAX128
SDA
A2
A1
A0
SCL
SERIAL INTERFACE LOGIC
SHDN
INT
V
DD
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CLOCK
AGND
DGND
ANALOG
INPUT
MUX
AND SIGNAL
CONDITIONING
OUT
IN
CLOCK
T/H
12-BIT SAR ADC
REF
REF
10k
A =
V
1.638
2.5V
REFERENCE
MAX127
MAX128
REFADJ
Figure 1. Block Diagram
De t a ile d De s c rip t io n
BIPOLAR
VOLTAGE
REFERENCE
Co n ve rt e r Op e ra t io n
S1
The MAX127/MAX128 multirange, fault-tolerant ADCs
use successive approximation and internal track/hold
(T/H) circuitry to convert an analog signal to a 12-bit
digital output. Figure 1 shows the block diagram for
these devices.
UNIPOLAR
OFF
5.12k
R1
CH_
C
HOLD
S2
R2
T/H
OUT
ON
S3
An a lo g -In p u t Tra c k /Ho ld
The T/H circuitry enters its tracking/acquisition mode on
the falling edge of the sixth clock in the 8-bit input con-
trol word and enters its hold/conversion mode when the
master issues a STOP condition. For timing information,
see the Start a Conversion section.
TRACK
TRACK S4
HOLD
HOLD
S1 = BIPOLAR/UNIPOLAR SWITCH
S2 = INPUT MUX SWITCH
S3, S4 = T/H SWITCH
R1 = 12.5kΩ (MAX127) OR 5.12kΩ (MAX128)
R2 = 8.67kΩ (MAX127) OR ∞ (MAX128)
In p u t Ra n g e a n d P ro t e c t io n
The MAX127/MAX128 have software-selectable input
ranges. Each analog input channel can be indepen-
dently programmed to one of four ranges by setting the
appropriate control bits (RNG, BIP) in the control byte
(Table 1). The MAX127 has selectable input ranges
Figure 2. Equivalent Input Circuit
the d e vic e ma y b e c onfig ure d for unip ola r mod e .
Overvoltage protection is active even if the device is in
power-down mode or V = 0.
DD
extending to ±10V (±V
has selectable input ranges extending to ±V . Note
that when an external reference is applied at REFADJ,
the voltage at REF is given by V
x 2.441), while the MAX128
REF
Dig it a l In t e rfa c e
REF
The MAX127/MAX128 feature a 2-wire serial interface
consisting of the SDA and SCL pins. SDA is the data
I/O and SCL is the serial clock input, controlled by the
ma s te r d e vic e . A2–A0 a re us e d to p rog ra m the
MAX127/MAX128 to different slave addresses. (The
MAX127/MAX128 only work as slaves.) The two bus
lines (SDA and SCL) must be high when the bus is not
in use. External pull-up resistors (1kΩor greater) are
required on SDA and SCL to maintain I2C compatibility.
Table 1 shows the input control-byte format.
= 1.638 x V
REF
REFADJ
(2.4 < V
< 4.18). Figure 2 shows the equivalent
REF
input circuit.
A resistor network on each analog input provides a
±16.5V fault protection for all channels. This circuit lim-
its the current going into or out of the pin to less than
1.2mA, whether or not the channel is on. This provides
an added layer of protection when momentary over-
voltages occur at the selected input channel, and when
a negative signal is applied at the input even though
_______________________________________________________________________________________
9
Mu lt ira n g e , +5 V, 1 2 -Bit DAS w it h
2 -Wire S e ria l In t e rfa c e
Table 1. Control-Byte Format
BIT 7
(MSB)
BIT 0
(LSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
START
SEL2
SEL1
SEL0
RNG
BIP
PD1
PD0
BIT
NAME
DESCRIPTION
The logic "1" received after acknowledge of a write bit (R/W = 0) defines the
beginning of the control byte.
7 (MSB)
START
SEL2, SEL1,
SEL0
6, 5, 4
These three bits select the desired "ON" channel (Table 2).
3
RNG
BIP
Selects the full-scale input voltage range (Table 3).
Selects unipolar or bipolar conversion mode (Table 3).
These two bits select the power-down modes (Table 4).
2
1, 0 (LSB)
PD1, PD0
7/MAX128
Table 2. Channel Selection
Table 4. Power-Down and Clock
Selection
SEL2
SEL1
SEL0
CHANNEL
CH0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PD1
PD0
MODE
CH1
0
1
1
X
0
Normal Operation (always on)
CH2
Standby Power-Down Mode (STBYPD)
Full Power-Down Mode (FULLPD)
CH3
1
CH4
CH5
CH6
CH7
Table 3. Range and Polarity Selection
NEGATIVE FULL
SCALE (V)
ZERO
INPUT RANGE (V)
RNG
BIP
FULL SCALE (V)
SCALE (V)
MAX127
0 to 5
0 to 10
±5
0
1
0
1
0
0
1
1
–
–
0
0
0
0
V
x 1.2207
REF
V
REF x 2.4414
V x 1.2207
REF
-V
x 1.2207
REF
±10
-V
V
REF x 2.4414
REF x 2.4414
MAX128
0 to V /2
0
1
0
1
0
0
1
1
–
–
0
0
0
0
V
/2
REF
REF
0 to V
V
REF
REF
±V /2
-V /2
REF
V
REF
/2
REF
±V
-V
REF
V
REF
REF
10 ______________________________________________________________________________________
Mu lt ira n g e , +5 V, 1 2 -Bit DAS w it h
2 -Wire S e ria l In t e rfa c e
7/MAX128
S la ve Ad d re s s
The MAX127/MAX128 have a 7-bit-long slave address.
The first four bits (MSBs) of the slave address have
been factory programmed and are always 0101. The
logic state of the address input pins (A2–A0) determine
the three LSBs of the device address (Figure 3). A max-
imum of eight MAX127/MAX128 devices can therefore
be connected on the same bus at one time.
Co n ve rs io n Co n t ro l
The master signals the beginning of a transmission with
a START condition (S), which is a high-to-low transition
on SDA while SCL is high. When the master has fin-
ished communicating with the slave, the master issues
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high (Figure 4). The bus is then
free for another transmission. Figure 5 shows the timing
d ia g ra m for s ig na ls on the 2-wire inte rfa c e . The
address-byte, control-byte, and data-byte are transmit-
ted between the START and STOP conditions. The SDA
state is allowed to change only while SCL is low, except
for the START and STOP conditions. Data is transmitted
in 8-bit words. Nine clock cycles are required to trans-
fer the data in or out of the MAX127/MAX128. (Figures
9 and 10).
A2–A0 may be connected to V
or DGND, or they
DD
may be actively driven by TTL or CMOS logic levels.
The eighth bit of the address byte determines whether
the master is writing to or reading from the MAX127/
MAX128 (R/W = 0 selects a write condition. R/W = 1
selects a read condition).
SLAVE ADDRESS
0
1
0
1
A2
A1
A0 R/W
LSB
ACK
SDA
SCL
SDA
SCL
START CONDITION
STOP CONDITION
SLAVE ADDRESS BITS A2, A1, AND A0 CORRESPOND TO THE LOGIC STATE
OF THE ADDRESS INPUT PINS A2, A1, AND A0.
Figure 3. Address Byte
Figure 4. START and STOP Conditions
SDA
t
BUF
t
,
t ,
SU STA
SU DAT
t
,
HD STA
t
,
SU STO
t
t ,
HD DAT
LOW
SCL
t
HIGH
t
,
HD STA
t
R
t
F
START CONDITION
REPEATED START CONDITION
STOP CONDITION START CONDITION
Figure 5. 2-Wire Serial-Interface Timing Diagram
______________________________________________________________________________________ 11
Mu lt ira n g e , +5 V, 1 2 -Bit DAS w it h
2 -Wire S e ria l In t e rfa c e
Start a Conversion (Write Cycle)
A conversion cycle begins with the master issuing a
START c ond ition followe d b y s e ve n a d d re s s b its
(Figure 3) and a write bit (R/W = 0). Once the eighth bit
MASTER TO SLAVE
SLAVE TO MASTER
1
7
1
1
8
1 1
NO. OF BITS
ha s b e e n re c e ive d a nd the a d d re s s ma tc he s , the
MAX127/MAX128 (the slave) issues an acknowledge
by pulling SDA low for one clock cycle (A = 0). The
master then writes the input control byte to the slave
(Figure 8). After this byte of data, the slave issues
another acknowledge, pulling SDA low for one clock
cycle. The master ends the write cycle by issuing a
STOP condition (Figure 6).
S SLAVE ADDRESS W A CONTROL-BYTE A P
START CONDITION
STOP CONDITION
ACKNOWLEDGE
WRITE
ACKNOWLEDGE
Figure 6. Write Cycle
When the write bit is set (R/W = 0), acquisition starts as
soon as Bit 2 (BIP) of the input control-byte has been
latched and ends when a STOP condition has been
issued. Conversion starts immediately after acquisition.
The MAX127/MAX128’s internal conversion clock fre -
quency is 1.56MHz, resulting in a typical conversion
time of 7.7µs. Figure 9 shows a complete write cycle.
MASTER TO SLAVE
SLAVE TO MASTER
1
7
1
1
8
1
8
1 1
NO. OF BITS
S SLAVE ADDRESS R A DATA-BYTE A DATA-BYTE A P
7/MAX128
STOP CONDITION
NOT ACKNOWLEDGE
ACKNOWLEDGE
READ
START CONDITION
Read a Conversion (Read Cycle)
Once a conversion starts, the master does not need to
wait for the conversion to end before attempting to read
the data from the slave. Data access begins with the
master issuing a START condition followed by a 7-bit
address (Figure 3) and a read bit (R/W = 1). Once the
eighth bit has been received and the address matches,
the slave issues an acknowledge by pulling low on SDA
for one clock cycle (A = 0) followed by the first byte of
serial data (D11–D4, MSB first). After the first byte has
been issued by the slave, it releases the bus for the
master to issue an acknowledge (A = 0). After receiv-
ing the acknowledge, the slave issues the second byte
(D3–D0 and four zeros) followed by a NOT acknowl-
edge (A= 1) from the master to indicate that the last
data byte has been received. Finally, the master issues
a STOP condition (P), ending the read cycle (Figure 7).
Figure 7. Read Cycle
START SEL2 SEL1 SEL0 RNG BIP
PD1
PD0 ACK
LSB
SDA
SCL
MSB
START: FIRST LOGIC “1” RECEIVED AFTER ACKNOWLEDGE OF A WRITE.
ACK:
ACKNOWLEDGE BIT. THE MAX127/MAX128 PULL SDA LOW DURING THE
9TH CLOCK PULSE.
Figure 8. Command Byte
SLAVE ADDRESS BYTE
CONTROL BYTE
0
1
A
9
S
BIP
15
PD1 PD0
LSB
A
W
SDA
MSB
LSB
MSB
SCL
1
2
7
8
10
11
16
17
18
ACQUISITION
CONVERSION
A/D STATE
START
CONDITION
STOP
CONDITION
Figure 9. Complete 2-Wire Serial Write Transmission
12 ______________________________________________________________________________________
Mu lt ira n g e , +5 V, 1 2 -Bit DAS w it h
2 -Wire S e ria l In t e rfa c e
7/MAX128
SLAVE ADDRESS BYTE
1
MSB DATA BYTE
LSB DATA BYTE
FILLED WITH
4 ZEROS
0
A
9
D11
D4
A
D3
D0
A
R
MSB
1
LSB
MSB
LSB
LSB
26
MSB
2
7
8
10
11
17
18
19
22
23
27
STOP
START
CONDITION
CONDITION
Figure 10. Complete 2-Wire Serial Read Transmission
The MAX127/MAX128 ignore acknowledge and NOT-
acknowledge conditions issued by the master during
the read cycle. The device waits for the master to read
the outp ut d a ta or wa its until a STOP c ond ition is
issued. Figure 10 shows a complete read cycle.
External Reference
To use the REF input directly, disable the internal buffer
by connecting REFADJ to V (Figure 11b). Using the
DD
REFADJ input eliminates the need to buffer the refer-
e nc e e xte rna lly. Whe n the re fe re nc e is a p p lie d a t
REFADJ, bypass REFADJ with a 0.01µF capacitor to
AGND (Figure 11c).
In unipolar input mode, the output is straight binary. For
bipolar input mode, the output is two’s complement. For
output binary codes see the Transfer Function section.
At REF and REFADJ, the input impedance is a mini-
mum of 10kΩ for DC currents. During conversions, an
e xte rna l re fe re nc e a t REF mus t b e a b le to d rive a
400µA DC load, and must have an output impedance
of 10Ω or less. If the reference has higher input imped-
ance or is noisy, bypass REF with a 4.7µF capacitor to
AGND as close to the chip as possible.
Ap p lic a t io n s In fo rm a t io n
P o w e r-On Re s e t
The MAX127/MAX128 power up in normal operating
mode, waiting for a START condition followed by the
appropriate slave address. The contents of the input
and output data registers are cleared at power-up.
With an external reference voltage of less than 4.096V
at REF or less than 2.5V at REFADJ, the increase in
RMS noise to the LSB value (full-scale voltage/4096)
results in performance degradation and loss of effec-
tive bits.
In t e rn a l o r Ex t e rn a l Re fe re n c e
The MAX127/MAX128 operate with either an internal or
an external reference (Figures 11a–11c). An external
reference is connected to either REF or to REFADJ.
P o w e r-Do w n Mo d e
To save power, put the converter into low-current shut-
down mode between conversions. Two programmable
power-down modes are available, in addition to the
hardware shutdown. Select STBYPD or FULLPD by pro-
gramming PD0 and PD1 in the input control byte (Table
4). When software power-down is asserted, it becomes
effective only after the end of conversion. In all power-
down modes, the interface remains active and conver-
sion results may be read. Input overvoltage protection
is active in all power-down modes.
The REFADJ internal buffer gain is trimmed to 1.6384 to
provide 4.096V at REF from a 2.5V reference.
Internal Reference
The internally trimmed 2.50V reference is amplified
through the REFADJ buffer to provide 4.096V at REF.
Bypass REF with a 4.7µF capacitor to AGND and bypass
REFADJ with a 0.01µF capacitor to AGND (Figure 11a).
The internal reference voltage is adjustable to ±1.5%
(±65 LSBs) with the reference-adjust circuit of Figure 12.
______________________________________________________________________________________ 13
Mu lt ira n g e , +5 V, 1 2 -Bit DAS w it h
2 -Wire S e ria l In t e rfa c e
REF
C
4.7µF
REF
MAX127
MAX128
+5V
510k
100k
24k
REFADJ
A = 1.638
V
REFADJ
0.01µF
0.01µF
MAX127
MAX128
10k
2.5V
Figure 11a. Internal Reference
Figure 12. Reference-Adjust Circuit
7/MAX128
To power-up from a software initiated power-down, a
START condition followed by the correct slave address
must be received (with R/W = 0). The MAX127/MAX128
power-up after receiving the next bit.
REF
4.096V
C
REF
MAX127
MAX128
4.7µF
For hardware-controlled power-down (FULLPD), pull
SHDN low. When hardware shutdown is asserted, it
becomes effective immediately and any conversion in
progress is aborted.
A = 1.638
V
V
DD
REFADJ
Ch o o s in g P o w e r-Do w n Mo d e s
The bandgap reference and reference buffer remain
active in STBYPD mode, maintaining the voltage on the
4.7µF capacitor at REF. This is a “DC” state that does
not degrade after standby power-down of any duration.
10k
2.5V
In FULLPD mode, only the bandgap reference is active.
Connect a 33µF capacitor between REF and AGND to
maintain the reference voltage between conversions
and to reduce transients when the buffer is enabled
and disabled. Throughput rates down to 1ksps can be
achieved without allotting extra acquisition time for ref-
erence recovery prior to conversion. This allows con-
version to begin immediately after power-down ends. If
the discharge of the REF capacitor during FULLPD
exceeds the desired limits for accuracy (less than a
fraction of an LSB), run a STBYPD power-down cycle
prior to starting conversions. Take into account that the
reference buffer recharges the bypass capacitor at an
80mV/ms slew rate, and add 50µs for settling time.
Figure 11b. External Reference, Reference at REF
REF
C
4.7µF
REF
MAX127
MAX128
A = 1.638
V
REFADJ
2.5V
0.01µF
10k
Auto-Shutdown
Selecting STBYPD on every conversion automatically
shuts the MAX127/MAX128 down after each conversion
without requiring any start-up time on the next conversion.
2.5V
Figure 11c. External Reference, Reference at REFADJ
14 ______________________________________________________________________________________
Mu lt ira n g e , +5 V, 1 2 -Bit DAS w it h
2 -Wire S e ria l In t e rfa c e
7/MAX128
Tra n s fe r Fu n c t io n
Output data coding for the MAX127/MAX128 is binary
in unip ola r mod e with 1LSB = (FS/4096) a nd
two’s complement binary in bipolar mode with 1LSB =
[(2 x FS ) / 4096]. Cod e tra ns itions oc c ur ha lfwa y
between successive-integer LSB values. Figures 13a
and 13b show the input/output (I/O) transfer functions
for unipolar and bipolar operations, respectively. For
full-scale (FS) values, refer to Table 3.
La yo u t , Gro u n d in g , a n d Byp a s s in g
Careful printed circuit board layout is essential for best
s ys te m p e rforma nc e . For b e s t p e rforma nc e , us e a
ground plane. To reduce crosstalk and noise injection,
keep analog and digital signals separate. Connect ana-
log g round s a nd DGND in a s ta r c onfig ura tion to
AGND. For noise-free operation, ensure the ground
return from AGND to the supply ground is low imped-
a nc e a nd a s s hort a s p os s ib le . Conne c t the log ic
|
|
grounds directly to the supply ground. Bypass V with
DD
0.1µF and 4.7µF capacitors to AGND to minimize high-
and low-frequency fluctuations. If the supply is exces-
sively noisy, connect a 5Ω resistor between the supply
OUTPUT CODE
FS
1 LSB =
FULL-SCALE
4096
11... 111
TRANSITION
11... 110
11... 101
and V , as shown in Figure 14.
DD
SUPPLY
GND
+5V
4.7µF
R* = 5Ω
00... 011
00... 010
00... 001
00... 000
0.1µF
**
V
DD
+5V
DGND
AGND
DGND
FS
0
1
2
3
DIGITAL
CIRCUITRY
3
FS - / LSB
INPUT VOLTAGE (LSB)
2
MAX127
MAX128
Figure 13a. Unipolar Transfer Function
* OPTIONAL
** CONNECT AGND AND DGND WITH A GROUND PLANE OR A SHORT TRACE.
OUTPUT CODE
2 FS
4096
1 LSB =
011... 111
011... 110
Figure 14. Power-Supply Grounding Connection
000... 001
000... 000
111... 111
100... 010
100... 001
100... 000
-FS
0
+FS - 1 LSB
INPUT VOLTAGE (LSB)
Figure 13b. Bipolar Transfer Function
______________________________________________________________________________________ 15
Mu lt ira n g e , +5 V, 1 2 -Bit DAS w it h
2 -Wire S e ria l In t e rfa c e
Ord e rin g In fo rm a t io n (c o n t in u e d )
Ch ip In fo rm a t io n
TRANSISTOR COUNT: 4219
INL
(LSB)
PART
TEMP. RANGE
PIN-PACKAGE
SUBSTRATE CONNECTED to AGND
MAX127ACAI
MAX127BCAI
0°C to +70°C
0°C to +70°C
28 SSOP
28 SSOP
±1/2
±1
MAX127AENG -40°C to +85°C 24 Narrow Plastic DIP ±1/2
MAX127BENG -40°C to +85°C 24 Narrow Plastic DIP ±1
MAX127AEAI -40°C to +85°C 28 SSOP
MAX127BEAI -40°C to +85°C 28 SSOP
±1/2
±1
MAX128ACNG 0°C to +70°C
24 Narrow Plastic DIP ±1/2
24 Narrow Plastic DIP ±1
MAX128BCNG 0°C to +70°C
MAX128ACAI
MAX128BCAI
0°C to +70°C
0°C to +70°C
28 SSOP
28 SSOP
±1/2
±1
7/MAX128
MAX128AENG -40°C to +85°C 24 Narrow Plastic DIP ±1/2
MAX128BENG -40°C to +85°C 24 Narrow Plastic DIP ±1
MAX128AEAI -40°C to +85°C 28 SSOP
MAX128BEAI -40°C to +85°C 28 SSOP
±1/2
±1
P in Co n fig u ra t io n s
TOP VIEW
V
1
2
3
4
5
6
7
8
28 N.C.
27 REF
26 REFADJ
25 N.C.
24 N.C.
23 CH7
22 N.C.
21 CH6
20 CH5
19 CH4
18 CH3
17 CH2
16 CH1
15 CH0
DD
V
1
2
3
4
5
6
7
8
9
24 N.C.
23 REF
DD
V
DD
V
DD
DGND
N.C.
SCL
A0
N.C.
DGND
SCL
A0
22 N.C.
21 REFADJ
MAX127
MAX128
MAX127
MAX128
20 CH7
19 CH6
18 CH5
17 CH4
16 CH3
15 CH2
14 CH1
13 CH0
N.C.
N.C.
SDA
A2
SDA 9
A2 10
N.C.
A1 10
SHDN 11
AGND 12
N.C. 11
A1 12
SHDN 13
AGND 14
DIP
SSOP
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1998 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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