MAX1270BCAI [MAXIM]
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs; 多量程， + 5V，8通道，串行12位ADC
| 型号： | MAX1270BCAI |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Multirange, +5V, 8-Channel, Serial 12-Bit ADCs |
| 文件： | 总20页 (文件大小：688K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4782; Rev 2; 9/04
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
General Description
Features
The MAX1270/MAX1271 are multirange, 12-bit data-
acquisition systems (DAS) that require only a single
+5V supply for operation, yet accept signals at their
analog inputs that can span above the power-supply
rail and below ground. These systems provide eight
analog input channels that are independently software
programmable for a variety of ranges: ±10V, ±5V, 0 to
+10V, 0 to +5V for the MAX1270; ±V , ±V /2, 0 to
♦ 12-Bit Resolution, 0.5 LSB Linearity
♦ +5V Single-Supply Operation
♦ SPI/QSPI and MICROWIRE-Compatible
3-Wire Interface
♦ Four Software-Selectable Input Ranges
MAX1270: 0 to +10V, 0 to +5V, 10V, 5V
REF
REF
V
, 0 to V /2 for the MAX1271. This range switch-
MAX1271: 0 to V
, 0 to V
/2, V
,
REF
REF
REF
REF
REF
ing increases the effective dynamic range to 14 bits and
provides the flexibility to interface 4–20mA, ±12V, and
±15V powered sensors directly to a single +5V system.
In addition, these converters are fault protected to
±16.5V; a fault condition on any channel will not affect
the conversion result of the selected channel. Other fea-
tures include a 5MHz bandwidth track/hold, software-
selectable internal/external clock, 110ksps throughput
rate, and internal 4.096V or external reference operation.
V
/2
REF
♦ Eight Analog Input Channels
♦ 110ksps Sampling Rate
♦
1ꢀ.5V Oꢁerꢁoltage-ꢂolerant Input Multipleꢃer
♦ Internal 4.09ꢀV or Eꢃternal Reference
♦ ꢂwo Power-Down Modes
♦ Internal or Eꢃternal Clock
The MAX1270/MAX1271 s e ria l inte rfa c e d ire c tly
connects to SPI™/QSPI™ and MICROWIRE™ devices
without external logic.
♦ 24-Pin Narrow PDIP or 28-Pin SSOP Packages
A hardware shutdown input (SHDN) and two software-
programmable power-down modes, standby (STBYPD)
or full power-down (FULLPD), are provided for low-cur-
rent shutdown between conversions. In standby mode,
the reference buffer remains active, eliminating startup
delays.
Typical Operating Circuit
+5V
0.1µF
The MAX1270/MAX1271 are available in 24-pin narrow
PDIP or space-saving 28-pin SSOP packages.
V
DD
SHDN
Applications
Industrial Control Systems Automatic Testing
Data-Acquisition Systems Robotics
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
ANALOG
INPUTS
MAX1270
MAX1271
Battery-Powered
Instruments
Medical Instruments
MC68HCXX
CS
SCLK
DIN
DOUT
SSTRB
I/O
Ordering Information
SCK
MOSI
MISO
INL
ꢂEMP RANGE PIN-PACKAGE
(LSB)
REF
REFADJ
PARꢂ
0.01µF
MAX1270ACNG
MAX1270BCNG
MAX1270ACAI
MAX1270BCAI
0°C to +70°C 24 Narrow PDIP
0°C to +70°C 24 Narrow PDIP
0°C to +70°C 28 SSOP
±0.5
±1
4.7µF
AGND
DGND
±0.5
±1
0°C to +70°C 28 SSOP
Ordering Information continued at end of data sheet.
Pin Configurations appear at end of data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
ABSOLUꢂE MAXIMUM RAꢂINGS
DD
V
to AGND............................................................-0.3V to +6V
Operating Temperature Ranges
AGND to DGND.....................................................-0.3V to +0.3V
CH0–CH7 to AGND ......................................................... ±16.5V
MAX127_C_ _......................................................0°C to +70°C
MAX127_E_ _......................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
REF, REFADJ to AGND ..............................-0.3V to (V + 0.3V)
DD
SSTRB, DOUT to DGND.............................-0.3V to (V + 0.3V)
DD
SHDN, CS, DIN, SCLK to DGND..............................-0.3V to +6V
Max Current into Any Pin ....................................................50mA
Continuous Power Dissipation (T = +70°C)
A
24-Pin Narrow DIP (derate 13.33mW/°C above +70°C)..1067mW
28-Pin SSOP (derate 9.52mW/°C above +70°C) ..........762mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECꢂRICAL CHARACꢂERISꢂICS
DD
(V = +5.0V ±5%; unipolar/bipolar range; external reference mode, V
= +4.096V; 4.7µF at REF; external clock; f
= 2.0MHz,
REF
CLK
50% duty cycle (MAX127_B); f
= 1.8MHz, 50% duty cycle (MAX127_A); 18 clock/conversion cycle, T = T
to T , unless
CLK
A
MIN
MAX
otherwise noted. Typical values are T = +25°C.)
A
PARAMEꢂER
ACCURACY (Note 1)
Resolution
SYMBOL
CONDIꢂIONS
MIN
ꢂYP
MAX
UNIꢂS
12
Bits
LSB
LSB
MAX127_A
MAX127_B
±0.5
±1.0
±1
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
No missing codes over temperature
MAX127_A
Unipolar
±3
MAX127_B
±5
Offset Error
LSB
LSB
MAX127_A
±5
Bipolar
MAX127_B
±10
Unipolar
Bipolar
±0.1
±0.3
Channel-to-Channel Offset Error
Matching
MAX127_A
Unipolar
±7
±10
±7
MAX127_B
Gain Error (Note 2)
LSB
MAX127_A
Bipolar
MAX127_B
±10
Unipolar, external reference
Bipolar, external reference
±3
±5
Gain Error Temperature
Coefficient (Note 2)
ppm/°C
DYNAMIC SPECIFICAꢂIONS (10kHz sine-waꢁe input, 10V
(MAX1270), or 4.09ꢀV
(MAX1271), f
= 110ksps
P-P
P-P
SAMPLE
(MAX127_B), f
= 100ksps (MAX127_A))
SAMPLE
Signal-to-Noise + Distortion Ratio
Total Harmonic Distortion
SINAD
THD
70
dB
dB
dB
Up to the 5th harmonic
50kHz (Note 3)
-87
-78
Spurious-Free Dynamic Range
SFDR
80
-86
-96
15
Channel-to-Channel Crosstalk
Aperture Delay
dB
DC, V = ±16.5V
IN
External clock mode
External clock mode
Internal clock mode
ns
ps
ns
<50
10
Aperture Jitter
2
_______________________________________________________________________________________
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
ELECꢂRICAL CHARACꢂERISꢂICS (continued)
DD
(V = +5.0V ±5%; unipolar/bipolar range; external reference mode, V
= +4.096V; 4.7µF at REF; external clock; f
= 2.0MHz,
REF
CLK
50% duty cycle (MAX127_B); f
= 1.8MHz, 50% duty cycle (MAX127_A); 18 clock/conversion cycle, T = T
to T , unless
MAX
CLK
A
MIN
otherwise noted. Typical values are T = +25°C.)
A
PARAMEꢂER
ANALOG INPUꢂ
SYMBOL
CONDIꢂIONS
MIN
ꢂYP
MAX
UNIꢂS
MAX127_A, f
MAX127_B, f
= 1.8MHz
= 2.0MHz
3.3
3.0
CLK
Track/Hold Acquisition Time
Small-Signal Bandwidth
t
µs
ACQ
CLK
±10V or ±V
range
REF
5
±5V or ±V /2
range
REF
2.5
2.5
1.25
-3dB rolloff
MHz
0 to 10V or 0 to
V
REF
range
0 to 5V or 0 to
/2 range
V
REF
RNG = 1
0
0
10
5
MAX1270
MAX1271
MAX1270
RNG = 0
RNG = 1
RNG = 0
RNG = 1
RNG = 0
RNG = 1
Unipolar (BIP =
0), Table 3
0
V
REF
0
V
/2
REF
Input Voltage Range
(Table 3)
V
IN
-10
-5
+10
+5
V
Bipolar (BIP =
1), Table 3
-V
REF
+V
REF
MAX1271
MAX1270
+V
/
REF
2
RNG = 0
-V /2
REF
0 to 10V
range
-10
+720
Unipolar
0 to 5V
range
-10
-10
+360
+10
MAX1271
MAX1270
0.1
±10V
range
-1200
-600
-1200
+720
+360
+10
Input Current
I
IN
µA
±5V range
Bipolar
±V
REF
range
MAX1271
±V /2
REF
range
-600
+10
Unipolar
Bipolar
21
16
Dynamic Resistance
Input Capacitance
∆V /∆I
kΩ
IN IN
(Note 4)
40
pF
_______________________________________________________________________________________
3
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
ELECꢂRICAL CHARACꢂERISꢂICS (continued)
DD
(V = +5.0V ±5%; unipolar/bipolar range; external reference mode, V
= +4.096V; 4.7µF at REF; external clock; f
= 2.0MHz,
REF
CLK
50% duty cycle (MAX127_B); f
= 1.8MHz, 50% duty cycle (MAX127_A); 18 clock/conversion cycle, T = T
to T , unless
CLK
A
MIN
MAX
otherwise noted. Typical values are T = +25°C.)
A
PARAMEꢂER
INꢂERNAL REFERENCE
REF Output Voltage
SYMBOL
CONDIꢂIONS
MIN
ꢂYP
MAX
UNIꢂS
V
REF
T
= +25°C
4.076
4.096
±15
±30
30
4.116
V
A
MAX1270_C/MAX1271_C
MAX1270_E/MAX1271_E
REF Output Tempco
TC V
ppm/°C
REF
Output Short-Circuit Current
Load Regulation
mA
mV
µF
µF
V
0 to 0.5mA output current (Note 5)
10
Capacitive Bypass at REF
Capacitive Bypass at REFADJ
REFADJ Output Voltage
REFADJ Adjustment Range
Buffer Voltage Gain
4.7
0.01
2.465
2.500
±1.5
2.535
Figure 1
%
1.638
V/V
REFERENCE INPUꢂ (Reference buffer disabled, reference input applied to REF)
Input Voltage Range
2.40
4.18
400
1
V
Normal or STBYPD
Input Current
V
= 4.18V
= 4.18V
µA
REF
FULLPD
Normal or STBYPD
FULLPD
10
kΩ
Input Resistance
V
REF
4.18
MΩ
REFADJ Threshold for Buffer
Disable
V
0.5
-
DD
V
POWER REQUIREMENꢂ
Supply Voltage
V
4.75
5.25
18
V
DD
Bipolar range
Normal
mA
Unipolar range
6
10
Supply Current
I
DD
STBYPD power-down mode (Note 6)
FULLPD power-down mode
External reference = 4.096V
Internal reference
700
120
±0.1
±0.5
850
220
±0.5
µA
Power-Supply Rejection
Ratio (Note 7)
PSRR
LSB
ꢂIMING
MAX127_A
MAX127_B
0.1
0.1
3.3
3.0
3
1.8
2.0
External Clock Frequency Range
f
MHz
µs
SCLK
MAX127_A
MAX127_B
External clock mode
(Note 8)
Acquisition Phase
Internal clock mode, Figure 9
5
4
_______________________________________________________________________________________
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
ELECꢂRICAL CHARACꢂERISꢂICS (continued)
DD
(V = +5.0V ±5%; unipolar/bipolar range; external reference mode, V
= +4.096V; 4.7µF at REF; external clock; f
= 2.0MHz,
REF
CLK
50% duty cycle (MAX127_B); f
= 1.8MHz, 50% duty cycle (MAX127_A); 18 clock/conversion cycle, T = T
to T , unless
MAX
CLK
A
MIN
otherwise noted. Typical values are T = +25°C.)
A
PARAMEꢂER
SYMBOL
CONDIꢂIONS
MIN
6.6
6.0
6
ꢂYP
MAX
UNIꢂS
MAX127_A
MAX127_B
External clock mode
(Note 8)
Conversion Time
t
µs
CONV
Internal clock mode, Figure 9
7.7
11
100
110
43
MAX127_A
MAX127_B
External clock mode
Throughput Rate
ksps
µs
Internal clock mode
Power-up (Note 9)
Bandgap Reference Startup Time
Reference Buffer Settling Time
200
8
To 0.1mV, REF bypass
capacitor fully
C
C
= 4.7µF
= 33µF
REF
REF
ms
60
discharged
DIGIꢂAL INPUꢂS (DIN, SCLK, CS, and SHDN)
Input High Threshold Voltage
Input Low Threshold Voltage
Input Hysteresis
V
2.4
V
V
IH
V
IL
0.8
-10
V
HYS
0.2
V
Input Leakage Current
I
IN
V
= 0 to V
DD
+10
15
µA
pF
IN
Input Capacitance
C
(Note 4)
IN
DIGIꢂAL OUꢂPUꢂS (DOUꢂ, SSꢂRB)
I
= 5mA
0.4
SINK
Output Voltage Low
Output Voltage High
V
V
V
OL
I
= 16mA
0.4
SINK
V
DD -
0.5
V
OH
I
= 0.5mA
SOURCE
Tri-State Leakage Current
I
CS = V
-10
+10
15
µA
pF
L
DD
Tri-State Output Capacitance
C
CS = V (Note 4)
DD
OUT
_______________________________________________________________________________________
5
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
ꢂIMING CHARACꢂERISꢂICS
DD
(V
= +4.75V to +5.25V; unipolar/bipolar range; external reference mode, V
= +4.096V; 4.7µF at REF; external clock; f
=
REF
CLK
2.0MHz (MAX127_B); f
(Figures 2, 5, 7, 10)
= 1.8MHz (MAX127_A); T = T
to T , unless otherwise noted. Typical values are T = +25°C.)
MAX A
CLK
A
MIN
PARAMEꢂER
DIN to SCLK Setup
SYMBOL
CONDIꢂIONS
MIN
ꢂYP
MAX
UNIꢂS
ns
t
100
DS
DH
DO
DIN to SCLK Hold
t
0
ns
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
t
20
170
120
100
ns
t
C
C
= 100pF
= 100pF
ns
DV
LOAD
LOAD
t
ns
TR
t
100
0
ns
CSS
CSH
t
ns
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Fall to SSTRB
t
200
200
ns
CH
t
ns
CL
t
C
C
C
= 100pF
200
200
200
ns
SSTRB
LOAD
LOAD
LOAD
CS to SSTRB Output Enable
CS to SSTRB Output Disable
SSTRB Rise to SCLK Rise
t
= 100pF, external clock mode only
= 100pF, external clock mode only
ns
SDV
t
ns
STR
t
Internal clock mode only (Note 4)
0
ns
SCK
Note 1: Accuracy specifications tested at V = +5.0V. Performance at power-supply tolerance limit is guaranteed by power-supply
DD
rejection test.
Note 2: External reference: V
= 4.096V, offset error nulled. Ideal last-code transition = FS - 3/2 LSB.
REF
Note 3: Ground “on” channel; sine wave applied to all “off” channels. V = ±5V (MAX1270), V = ±4V (MAX1271).
IN
IN
Note 4: Guaranteed by design, not production tested.
Note 5: Use static external loads during conversion for specified accuracy.
Note ꢀ: Tested using internal reference.
Note 7: PSRR measured at full scale. Tested for the ±10V (MAX1270) and ±4.096V (MAX1271) input ranges.
Note 8: Acquisition phase and conversion time are dependent on the clock period; clock has 50% duty cycle (Figure 6).
Note 9: Not production tested. Provided for design guidance only.
ꢀ
_______________________________________________________________________________________
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
Typical Operating Characteristics
(Typical Operating Circuit, V
= +5V; external reference mode, V
= +4.096V; 4.7µF at REF; external clock, f
= 2MHz;
DD
REF
CLK
110ksps; T = +25°C, unless otherwise noted.)
A
STANDBY SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
6.5
6.3
6.1
5.9
5.7
5.5
750
650
550
25
20
15
10
5
INTERNAL
REFERENCE
450
350
250
EXTERNAL
REFERENCE
150
50
0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
0
1
2
3
4
5
6
7
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
NORMALIZED REFERENCE VOLTAGE
vs. TEMPERATURE
CHANNEL-TO-CHANNEL OFFSET-ERROR
MATCHING vs. TEMPERATURE
FULL POWER-DOWN SUPPLY CURRENT
vs. TEMPERATURE
1.001
1.000
0.35
0.30
0.25
150
130
BIPOLAR MODE
EXTERNAL
REFERENCE
0.999
0.998
0.997
0.996
110
90
0.20
0.15
0.10
0.05
0
INTERNAL
REFERENCE
UNIPOLAR MODE
70
50
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
CHANNEL-TO-CHANNEL GAIN-ERROR
MATCHING vs. TEMPERATURE
INTEGRAL NONLINEARITY vs.
DIGITAL CODE
FTT PLOT
0.8
0.7
0.6
0.15
0.10
0.05
0
0
f
= 10kHz
IN
f
= 110ksps
SAMPLE
-20
-40
UNIPOLAR MODE
BIPOLAR MODE
0.5
0.4
-60
-0.05
-0.10
-0.15
-80
0.3
0.2
0.1
-100
-120
-40
-15
10
35
60
85
0
819
1638
2457
3276
4095
0
10k
20k
30k
40k
50k
TEMPERATURE (°C)
DIGITAL CODE
FREQUENCY (Hz)
_______________________________________________________________________________________
7
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
Typical Operating Characteristics (continued)
(Typical Operating Circuit, V
= +5V; external reference mode, V
= +4.096V; 4.7µF at REF; external clock, f
= 2MHz;
DD
REF
CLK
110ksps; T = +25°C, unless otherwise noted.)
A
AVERAGE SUPPLY CURRENT vs.
CONVERSION RATE (USING FULLPD)
AVERAGE SUPPLY CURRENT vs.
CONVERSION RATE (USING STANDBY)
8
7
6
5
4
3
2
1
0
8
V
= 5V, INTERNAL REFERENCE,
= 2MHz
DD
V
f
= 5V, INTERNAL REFERENCE,
= 2MHz
CLK
DD
f
CLK
7
6
5
4
3
2
1
0
EXTERNAL CLOCK MODE.
LOW-RANGE UNIPOLAR MODE.
V
CH_
EXTERNAL CLOCK MODE.
LOW-RANGE UNIPOLAR MODE.
V
CH_
= 0
= 0
0.1
1
10
100
1000
0.1
1
10
100
1000
CONVERSION RATE (ksps)
CONVERSION RATE (ksps)
Pin Description
PIN
SSOP
NAME
FUNCꢂION
PDIP
1
1
V
DD
+5V Supply. Bypass with a 0.1µF capacitor to AGND.
Digital Ground
2, 4
2, 3
DGND
4, 7, 8,
11, 22,
24, 25, 28
3, 9,
22, 24
N.C.
No Connection. No internal connection.
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also
sets the conversion speed.
5
5
SCLK
Active-Low Chip-Select Input. Data is not clocked into DIN unless CS is low. When CS is high,
DOUT is high impedance.
6
7
6
9
CS
DIN
Serial Data Input. Data is clocked in on the rising edge of SCLK.
Serial Strobe Output. In internal clock mode, SSTRB goes low after the falling edge of the eighth
SCLK and returns high when the conversion is done. In external clock mode, SSTRB pulses high
for one clock period before the MSB decision. High impedance when CS is high in external
clock mode.
8
10
SSTRB
DOUT
Serial Data Output. Data is clocked out on the falling edge of SCLK. High impedance when CS is
high.
10
12
11
12
13
14
SHDN
Shutdown Input. When low, device is in FULLPD mode. Connect high for normal operation.
Analog Ground
AGND
13–20 15–21, 23 CH0–CH7 Analog Input Channels
Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01µF capacitor to AGND.
Connect to V when using an external reference at REF.
DD
21
26
REFADJ
Reference-Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer
provides a 4.096V nominal output, externally adjustable to REFADJ. In external reference mode,
23
27
REF
disable the internal reference by pulling REFADJ to V and applying the external reference to REF.
DD
8
_______________________________________________________________________________________
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
+5V
5mA
DOUT
+5V
OR
SSTRB
DOUT
OR
SSTRB
MAX1270
MAX1271
510kΩ
100kΩ
24kΩ
REFADJ
C
LOAD
0.5mA
C
LOAD
0.01µF
a)
HIGH IMPEDANCE TO V , V TO
b) HIGH IMPEDANCE TO V , V TO
OH OL
OH OL
V
OH
AND V TO HIGH IMPEDANCE
V AND V TO HIGH IMPEDANCE
OH OH
OH
Figure 1. Reference-Adjust Circuit
Figure 2. Output Load Circuit for Timing Characteristics
When operating in bipolar (MAX1270 and MAX1271) or
unipolar mode (MAX1270) the signal applied at the
input channel is rescaled through the resistor-divider
network formed by R1, R2, and R3 (Figure 4); a low
impedance (<4Ω) input source is recommended to
minimize gain error. When the MAX1271 is configured
Detailed Description
Converter Operation
The MAX1270/MAX1271 multirange, fault-tolerant ADCs
use successive approximation and internal track/hold
(T/H) circuitry to convert an analog signal to a 12-bit
digital output. Figure 3 shows the block diagram of the
MAX1270/MAX1271.
for unipolar mode, the channel input resistance (R
)
IN
becomes a fixed 5.12kΩ (typ). Source impedances
below 15kΩ (0 to V ) and 5kΩ (0 to V /2) do not
REF
REF
Analog-Input Track/Hold
The T/H enters tracking/acquisition mode on the falling
edge of the sixth clock in the 8-bit input control word,
a nd e nte rs hold /c onve rs ion mod e whe n the time d
acquisition interval (six clock cycles, 3µs minimum)
ends. In internal clock mode, the acquisition is timed by
two external clock cycles and four internal clock cycles.
significantly affect the AC performance of the ADC.
The acquisition time (t ) is a function of the source
ACQ
output resistance, the channel input resistance, and the
T/H capacitance. Higher source impedances can be
used if an input capacitor is connected between the
analog inputs and AGND. Note that the input capacitor
forms an RC filter with the input source impedance, lim-
iting the ADC’s signal bandwidth.
DIN
SSTRB DOUT
CS
SCLK
INT
CLOCK
SERIAL INTERFACE LOGIC
SHDN
V
DD
CH0
CH1
AGND
DGND
ANALOG
INPUT
MUX
AND SIGNAL
CONDITIONING
CH2
CH3
CH4
CH5
CH6
CH7
REF
OUT
IN
CLOCK
12-BIT SAR ADC
T/H
REF
+4.096V
10kΩ
Av =
1.638
2.5V
REFERENCE
MAX1270
MAX1271
REFADJ
Figure 3. Block Diagram
_______________________________________________________________________________________
9
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
Input Bandwidth
Digital Interface
The ADC’s input small-signal bandwidth depends on the
selected input range and varies from 1.5MHz to 5MHz
(s e e Electrical Characteristics). The MAX1270B/
MAX1271B maximum sampling rate is 110ksps (100ksps
for the MAX1270A/MAX1271A). By using undersampling
techniques, it is possible to digitize high-speed transient
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate.
The MAX1270/MAX1271 feature a serial interface that is
fully compatible with SPI/QSPI and MICROWIRE devices.
For SPI/QSPI, set CPOL = 0, CPHA = 0 in the SPI control
registers of the microcontroller. Figure 5 shows detailed
serial-interface timing information. See Table 1 for details
on programming the input control byte.
To avoid high-frequency signals being aliased into the
frequency band of interest, anti-aliasing filtering is rec-
ommended.
BIPOLAR
VOLTAGE
REFERENCE
S1
Input Range and Protection
The MAX1270/MAX1271 have software-selectable input
ranges. Each analog input channel can be indepen-
dently programmed to one of four ranges by setting the
appropriate control bits (RNG, BIP) in the control byte
(Table 1). The MAX1270 has selectable input ranges
UNIPOLAR
OFF
R3
5.12kΩ
R1
CH_
C
HOLD
S2
T/H
OUT
extending to ±10V (±V
x 2.441), while the MAX1271
REF
ON
has selectable input ranges extending to ±V . Figure
REF
4 shows the equivalent input circuit.
R2
S3
TRACK
TRACK S4
HOLD
A re s is tor ne twork on e a c h a na log inp ut p rovid e s
±16.5V fault protection for all channels. Whether or not
the channel is on, this circuit limits the current going
into or out of the pin to less than 2mA. This provides an
added layer of protection when momentary overvolt-
ages occur at the selected input channel, when a neg-
ative signal is applied to the input, and when the device
is configured for unipolar mode. The overvoltage pro-
tection is active even if the device is in power-down
HOLD
R1 = 12.5kΩ (MAX1270)
or 5.12kΩ (MAX1271)
R2 = 8.67kΩ (MAX1270)
or ∞ (MAX1271)
S1 = BIPOLAR/UNIPOLAR SWITCH
S2 = INPUT MUX SWITCH
S3, S4 = T/H SWITCH
Figure 4. Equivalent Input Circuit
mode or if V = 0.
DD
CS
t
t
CH
t
CSH
CSS
t
t
CL
CSH
SCLK
t
DS
t
DH
DIN
t
DV
t
DO
t
TR
DOUT
Figure 5. Detailed Serial-Interface Timing
10 ______________________________________________________________________________________
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
ꢂable 1. Control-Byte Format
BIꢂ 7
(MSB)
BIꢂ 0
(LSB)
BIꢂ ꢀ
BIꢂ 5
BIꢂ 4
BIꢂ 3
BIꢂ 2
BIꢂ 1
START
SEL2
SEL1
SEL0
RNG
BIP
PD1
PD0
BIꢂ
NAME
DESCRIPꢂION
7 (MSB)
START
First logic 1 after CS goes low defines the beginning of the control byte.
SEL2, SEL1,
SEL0
6, 5, 4
These 3 bits select the desired “on” channel (Table 2).
3
RNG
BIP
Selects the full-scale input voltage range (Table 3).
Selects the unipolar or bipolar conversion mode (Table 3).
Select clock and power-down modes (Table 4).
2
1, 0 (LSB)
PD1, PD0
ꢂable 2. Channel Selection
ꢂable 4. Power-Down and Clock Selection
PD1 PD0
MODE
SEL2
SEL1
SEL0
CHANNEL
CH0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Normal operation (always on), internal clock
mode.
0
0
1
1
0
1
0
1
CH1
CH2
Normal operation (always on), external clock
mode.
CH3
CH4
Standby power-down mode (STBYPD), clock
mode unaffected.
CH5
CH6
Full power-down mode (FULLPD), clock mode
unaffected.
CH7
ꢂable 3. Range and Polarity Selection for MAX1270/MAX1271
RANGE AND POLARIꢂY SELECꢂION FOR ꢂHE MAX1270
Negatiꢁe
FULL SCALE
ZERO
SCALE (V)
INPUꢂ RANGE
RNG
BIP
FULL SCALE
0 to +5V
0 to +10V
±5V
0
1
0
1
0
0
1
1
—
—
0
0
0
0
V
x 1.2207
x 2.4414
x 1.2207
x 2.4414
REF
V
REF
-V
x 1.2207
x 2.4414
V
REF
REF
±10V
-V
REF
V
REF
RANGE AND POLARIꢂY SELECꢂION FOR ꢂHE MAX1271
Negatiꢁe
FULL SCALE
ZERO
SCALE (V)
INPUꢂ RANGE
0 to V /2
RNG
BIP
FULL SCALE
/2
0
1
0
1
0
0
1
1
—
—
0
0
0
0
V
REF
REF
0 to V
V
REF
REF
±V /2
REF
-V /2
REF
V
REF
/2
±V
REF
-V
REF
V
REF
______________________________________________________________________________________ 11
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
Input Data Format
Input data (control byte) is clocked in at DIN at the ris-
ing edge of SCLK. CS enables communication with the
MAX1270/MAX1271. After CS falls, the first arriving
logic 1 bit represents the start bit (MSB) of the input
control byte. The start bit is defined as:
Keep CS low during successive conversions. If a start-
bit is received after CS transitions from high to low, but
before the output bit 6 (D6) becomes available, the cur-
rent conversion will terminate and a new conversion will
begin.
External Clock Mode (PD1 = 0, PD0 = 1)
In external clock mode, the clock shifts data in and out
of the MAX1270/MAX1271 and controls the acquisition
a nd c onve rs ion timing s . Whe n a c q uis ition is d one ,
SSTRB pulses high for one clock cycle and conversion
begins. Successive-approximation bit decisions appear
at DOUT on each of the next 12 SCLK falling edges
(Figure 6). Additional SCLK falling edges will result in
zeros appearing at DOUT. Figure 7 shows the SSTRB
timing in external clock mode.
The first high bit clocked into DIN with CS low
anytime the converter is idle; e.g., after V is
DD
applied.
OR
The first high bit clocked into DIN after bit 6
(D6) of a conversion in progress is clocked
onto DOUT.
Output Data Format
Output data is clocked out on the falling edge of SCLK
at DOUT, MSB first (D11). In unipolar mode, the output
is straight binary. For bipolar mode, the output is two’s
complement binary. For output binary codes, refer to
the Transfer Function section.
SSTRB a nd DOUT g o into a hig h-imp e d a nc e s ta te
when CS goes high; after the next CS falling edge,
SSTRB and DOUT will output a logic low.
The conversion must be completed in some minimum
time, or droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if
the clock period exceeds 10µs, or if serial-clock inter-
ruptions could cause the conversion interval to exceed
120µs. The fastest the MAX1270/MAX1271 can run is
18 clocks per conversion in external clock mode, and
with a clock rate of 2MHz, the maximum sampling rate
is 111 ksps (Figure 8). In order to achieve maximum
throughput, keep CS low, use external clock mode with
a continuous SCLK, and start the following control byte
after bit 6 (D6) of the conversion in progress is clocked
onto DOUT.
How to Start a Conversion
The MAX1270/MAX1271 use either an external serial
clock or the internal clock to complete an acquisition
and perform a conversion. In both clock modes, the
external clock shifts data in and out. See Table 4 for
details on programming clock modes.
The falling edge of CS does not start a conversion on
the MAX1270/MAX1271; a control byte is required for
each conversion. Acquisition starts after the sixth bit is
p rog ra mme d in the inp ut c ontrol b yte . Conve rs ion
s ta rts whe n the a c q uis ition time , s ix c loc k c yc le s ,
expires.
If CS is low and SCLK is continuous, guarantee a start
bit by first clocking in 18 zeros.
CS
SCLK
1
8
12
13
14
24
25
START SEL2 SEL1 SEL0 RNG BIP PD1 PD0
MSB LSB
DIN
SSTRB
DOUT
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
FILLED WITH
ZEROS
D10 D9
D1 D0
D11
LSB
MSB
ACQUISITION
6 SCLK
CONVERSION
12 SCLK
A/D STATE
Figure 6. External Clock Mode—25 Clocks/Conversion Timing
12 ______________________________________________________________________________________
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
CS
t
t
STR
SDV
SSTRB
HIGH-Z
HIGH-Z
t
SSTRB
t
SSTRB
SCLK
SCLK 12
Figure 7. External Clock Mode—SSTRB Detailed Timing
CS
13
16
19
24
26
31
32
37
1
8
14
SCLK
DIN
CONTROL BYTE 0
CONTROL BYTE 1
CONTROL BYTE 2
MSB
LSB
START SEL2 SEL1 SEL0 RNG BIP PD1 PD0
START SEL2 SEL1 SEL0 RNG BIP PD1 PD0
SEL2
START
18 SCLK
HIGH-Z
SSTRB
RESULT
RESULT 1
MSB
LSB
HIGH-Z
D11 D10 D9 D8 D7 D6 D5
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DOUT
18 SCLK
ACQUISITION
6 SCLK
CONVERSION
12 SCLK
ACQUISITION
6 SCLK
CONVERSION
12 SCLK
A/D STATE
Figure 8. External Clock Mode—18 Clocks/Conversion Timing
Internal Clock Mode (PD1 = 0, PD0 = 0)
In internal clock mode, the MAX1270/MAX1271 gener-
ate their conversion clock internally. This frees the
microprocessor from the burden of running the acquisi-
tion and the SAR conversion clock, and allows the con-
ve rs ion re s ults to b e re a d b a c k a t the p roc e s s or’s
c onve nie nc e , a t a ny c loc k ra te from 0 to typ ic a lly
10MHz.
16th internal clock pulse (12 internal clock cycle pulses
are used for conversion). SSTRB will remain low for a
ma ximum of 15µs, during whic h time SCLK should
remain low for best noise performance. An internal reg-
ister stores data while the conversion is in progress.
The MSB of the result byte (D11) is present at DOUT
starting at the falling edge of the last internal clock of
conversion. Successive falling edges of SCLK will shift
the re ma ining d a ta out of this re g is te r (Fig ure 9).
Additional SCLK edges will result in zeros on DOUT.
SSTRB goes low after the falling edge of the last bit
(PD0) of the c ontrol b yte ha s b e e n s hifte d in, a nd
re turns hig h whe n the c onve rs ion is c omp le te .
Acquisition is completed and conversion begins on the
falling edge of the 4th internal clock pulse after the con-
trol byte; conversion ends on the falling edge of the
When internal clock mode is selected, SSTRB does not
go into a high-impedance state when CS goes high.
Pulling CS high prevents data from being clocked in
and tri-states DOUT, but does not adversely affect a
______________________________________________________________________________________ 13
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
CS
SCLK
1
9
10
19
20
8
SEL2 SEL1 SEL0 RNG BIP PD1 PD0
START
MSB
DIN
LSB
SSTRB
16 INT CLK
HIGH-Z
HIGH-Z
HIGH-Z
FILLED WITH ZEROS
DOUT
D11 D10
MSB
D1 D0
LSB
ACQUISITION CONVERSION
A/D STATE
2 EXT SCLK 12 INT CLK
+4 INT CLK
Figure 9. Internal Clock Mode—20 SCLK/Conversion Timing
CS
t
CSS
t
t
SCK
CSH
SSTRB
t
SSTRB
SCLK
SCLK #8
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
Figure 10. Internal Clock Mode—SSTRB Detailed Timing
conversion in progress. Figure 10 shows the SSTRB
timing in internal clock mode.
Applications Information
Power-On Reset
The MAX1270/MAX1271 power up in normal operation
(all internal circuitry active) and internal clock mode,
waiting for a start bit. The contents of the output data
register are cleared at power-up.
Internal clock mode conversions can be completed
with 13 external clocks per conversion but require a
waiting period of 15µs for the conversion to be com-
pleted (Figure 11).
Most microcontrollers require that conversions occur in
multiples of 8 SCLK clock cycles. Sixteen clock cycles
per conversion (as shown in Figure 12) is typically the
most convenient way for a microcontroller to drive the
MAX1270/MAX1271.
Internal or External Reference
The MAX1270/MAX1271 operate with either an internal
or external reference. An external reference is connect-
ed to either REF or REFADJ (Figure 13). The REFADJ
internal buffer gain is trimmed to 1.638V to provide
4.096V at REF from a 2.5V reference.
14 ______________________________________________________________________________________
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
CS
8
1
9
14
16
22
24
SCLK
CONTROL BYTE Ø
CONTROL BYTE 1
CONTROL BYTE 2
SEL2 SEL1 SEL0 RNG BIP PD1 PD0
SEL2 SEL1 SEL0 RNG BIP PD1 PD0
SEL2 SEL1 SEL0
START
START
START
DIN
13 SCLK
SSTRB
RESULT Ø
RESULT 1
HIGH-Z
DOUT
D11 D10 D9 D8 D7 D6 D5 D4 D3
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
13 SCLK
ACQUISITION CONVERSION
ACQUISITION CONVERSION
A/D STATE
Figure 11. Internal Clock Mode—13 Clocks/Conversion Timing
CS
1
8
9
16
17
24
25
32
SCLK
DIN
CONTROL BYTE Ø
CONTROL BYTE 1
CB 2
SEL2 SEL1 SEL0 RNG BIP PD1 PD0
SEL2 SEL1 SEL0 RNG BIP PD1 PD0
START
START
START
16 SCLK
SSTRB
RESULT Ø
RESULT 1
HIGH-Z
HIGH-Z
HIGH-Z
D11 D10 D9 D8 D7 D6 D5 D4 D3
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DOUT
16 SCLK
ACQUISITION CONVERSION
ACQUISITION CONVERSION
A/D STATE
IDLE
Figure 12. Internal Clock Mode—16 Clocks/Conversion Timing
Internal Reference
The internally trimmed 2.50V reference is amplified
through the REFADJ buffer to provide 4.096V at REF.
Byp a s s REF with a 4.7µF c a p a c itor to AGND a nd
REFADJ with a 0.01µF capacitor to AGND (Figure 13a).
The internal reference voltage is adjustable to ±1.5%
(±65 LSBs) with the reference-adjust circuit of Figure 1.
V
= 1.6384 x V
(2.4 < V
< 4.18)
REF
REFADJ
REF
(Figure 13c). At REF and REFADJ, the input impedance
is a minimum of 10kΩ for DC currents. During conver-
sions, an external reference at REF must be able to deliv-
er 400µA DC load currents and must have an output
impedance of 10Ω or less. If the reference has higher
output impedance or is noisy, bypass REF with a 4.7µF
capacitor to AGND as close to the chip as possible.
External Reference
To use the REF input directly, disable the internal buffer
With an external reference voltage of less than 4.096V
at REF or less than 2.5V at REFADJ, the increase in the
ratio of RMS noise to the LSB value (full-scale / 4096)
results in performance degradation (loss of effective
bits).
b y tying REFADJ to V
(Fig ure 13b ). Us ing the
DD
REFADJ input eliminates the need to buffer the refer-
e nc e e xte rna lly. Whe n a re fe re nc e is a p p lie d a t
REFADJ, bypass REFADJ with a 0.01µF capacitor to
AGND. Note that when an external reference is applied
at REFADJ, the voltage at REF is given by:
______________________________________________________________________________________ 15
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
Power-Down Mode
To save power, configure the converter into low-current
shutdown mode between conversions. Two program-
mable power-down modes are available in addition to a
hardware shutdown. Select STBYPD or FULLPD by pro-
g ra mming PD0 a nd PD1 in the inp ut c ontrol b yte
(Table 4). When software power-down is asserted, it
becomes effective only after the end of conversion. For
example, if the control byte contains PD1 = 0, then the
chip remains powered up. If PD1 = 1, then the chip
powers down at the end of conversion. In all power-
down modes, the interface remains active and conver-
sion results can be read. Input overvoltage protection is
active in all power-down modes.
REF
4.7µF
REF
MAX1270
MAX1271
C
A = 1.638
V
REFADJ
0.01µF
10kΩ
2.5V
The first logical 1 on DIN after CS falls is interpreted as
a s ta rt c ond ition, a nd p owe rs up the MAX1270/
MAX1271 from a software selected STBYPD or FULLPD
condition.
Figure 13a. Internal Reference
For hardware-controlled power-down (FULLPD), pull
SHDN low. When hardware shutdown is asserted, it
becomes effective immediately, and any conversion in
progress is aborted.
REF
4.096V
4.7µF
MAX1270
MAX1271
C
REF
Choosing Power-Down Modes
The bandgap reference and reference buffer remain
active in STBYPD mode, maintaining the voltage on the
4.7µF capacitor at REF. This is a DC state that does not
degrade after power-down of any duration.
A = 1.638
V
DD
V
REFADJ
10kΩ
In FULLPD mode, only the bandgap reference is active.
Connect a 33µF capacitor between REF and AGND to
maintain the reference voltage between conversions
and to reduce transients when the buffer is enabled
and disabled. Throughput rates down to 1ksps can be
achieved without allotting extra acquisition time for ref-
erence recovery prior to conversion. This allows con-
version to begin immediately after power-up. If the
d is c ha rg e of the REF c a p a c itor d uring FULLPD
exceeds the desired limits for accuracy (less than a
fraction of an LSB), run a STBYPD power-down cycle
prior to starting conversions. Take into account that the
reference buffer recharges the bypass capacitor at an
80mV/ms slew rate, and add 50µs for settling time.
2.5V
Figure 13b. External Reference—Reference at REF
REF
4.7µF
REF
MAX1270
MAX1271
C
A = 1.638
V
Auto-Shutdown
Selecting STBYPD on every conversion automatically
shuts down the MAX1270/MAX1271 after each conversion
without requiring any start-up time on the next conversion.
REFADJ
2.5V
0.01µF
10kΩ
2.5V
Figure 13c. External Reference—Reference at REFADJ
1ꢀ ______________________________________________________________________________________
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
OUTPUT CODE
11... 111
OUTPUT CODE
FS
4096
2|FS|
4096
1 LSB =
FULL-SCALE
TRANSITION
1 LSB =
011... 111
011... 110
11... 110
11... 101
000... 001
000... 000
111... 111
00... 011
00... 010
00... 001
00... 000
100... 010
100... 001
100... 000
FS
0
1
2
3
-FS
0
+FS - 1 LSB
3
FS - / LSB
INPUT VOLTAGE (LSB)
2
INPUT VOLTAGE (LSB)
Figure 14a. Unipolar Transfer Function
Figure 14b. Bipolar Transfer Function
Transfer Function
Output data coding for the MAX1270/MAX1271 is bina-
ry in unipolar mode with 1 LSB = (FS / 4096) and two’s
complement binary in bipolar mode with 1 LSB = [(2 x
| FS | ) / 4096]. Code transitions occur halfway between
successive-integer LSB values. Figures 14a and 14b
show the input/output (I/O) transfer functions for unipo-
lar and bipolar operations, respectively. For full-scale
values, refer to Table 3.
SUPPLY
GND
+5V
4.7µF
R* = 5Ω
0.1µF
**
Layout, Grounding, and Bypassing
Careful PC board layout is essential for best system
p e rforma nc e . Us e a g round p la ne for b e s t p e rfor-
mance. To reduce crosstalk and noise injection, keep
analog and digital signals separate. Connect analog
grounds and DGND in a star configuration to AGND.
For noise-free operation, ensure the ground return from
AGND to the supply ground is low impedance and as
short as possible. Connect the logic grounds directly to
V
+5V
DGND
AGND
DGND
DD
DIGITAL
CIRCUITRY
MAX1270
MAX1271
*OPTIONAL
**CONNECT AGND AND DGND WITH A GROUND PLANE OR A SHORT TRACE.
the supply ground. Bypass V
capacitors to AGND to minimize highand low-frequency
fluctuations. If the supply is excessively noisy, connect
with 0.1µF and 4.7µF
DD
Figure 15. Power-Supply Grounding Connections
a 5Ω resistor between the supply and V , as shown in
DD
Figure 15.
______________________________________________________________________________________ 17
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
Pin Configurations
TOP VIEW
V
1
28 N.C.
27 REF
DD
V
1
2
3
4
5
6
7
8
9
24 N.C.
23 REF
22 N.C.
21 REFADJ
20 CH7
19 CH6
18 CH5
17 CH4
16 CH3
15 CH2
14 CH1
13 CH0
DD
DGND 2
DGND 3
DGND
N.C.
26 REFADJ
25 N.C.
N.C.
4
DGND
SCLK
CS
SCLK 5
24 N.C.
MAX1270
MAX1271
MAX1270
MAX1271
CS
N.C.
N.C.
6
7
8
23 CH7
22 N.C.
21 CH6
20 CH5
19 CH4
18 CH3
17 CH2
16 CH1
15 CH0
DIN
SSTRB
N.C.
DIN 9
SSTRB 10
N.C. 11
DOUT 10
SHDN 11
AGND 12
DOUT 12
SHDN 13
AGND 14
PDIP
SSOP
Ordering Information (continued)
Chip Information
INL
(LSB)
TRANSISTOR COUNT: 4219
PARꢂ
ꢂEMP RANGE PIN-PACKAGE
SUBSTRATE CONNECTED TO AGND
MAX1270AENG
MAX1270BENG
MAX1270AEAI
MAX1270BEAI
MAX1271ACNG
MAX1271BCNG
MAX1271ACAI
MAX1271BCAI
MAX1271AENG
MAX1271BENG
MAX1271AEAI
MAX1271BEAI
-40°C to +85°C 24 Narrow PDIP
-40°C to +85°C 24 Narrow PDIP
-40°C to +85°C 28 SSOP
±0.5
±1
±0.5
±1
-40°C to +85°C 28 SSOP
0°C to +70°C 24 Narrow PDIP
0°C to +70°C 24 Narrow PDIP
0°C to +70°C 28 SSOP
±0.5
±1
±0.5
±1
0°C to +70°C 28 SSOP
-40°C to +85°C 24 Narrow PDIP
-40°C to +85°C 24 Narrow PDIP
-40°C to +85°C 28 SSOP
±0.5
±1
±0.5
±1
-40°C to +85°C 28 SSOP
18 ______________________________________________________________________________________
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maꢃim-ic.com/packages.)
______________________________________________________________________________________ 19
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maꢃim-ic.com/packages.)
2
1
INCHES
MILLIMETERS
DIM
A
MIN
0.068
MAX
MIN
1.73
0.05
0.25
0.09
MAX
1.99
0.21
0.38
0.20
INCHES
MAX
MILLIMETERS
MAX
6.33
6.33
7.33
MIN
MIN
6.07
6.07
7.07
8.07
N
0.078
14L
16L
20L
A1
B
D
D
D
D
D
0.239 0.249
0.239 0.249
0.278 0.289
0.317 0.328
0.002 0.008
0.010 0.015
0.004 0.008
C
8.33 24L
E
H
SEE VARIATIONS
0.205 0.212 5.20
0.0256 BSC
D
0.397 0.407 10.07 10.33
28L
E
5.38
e
0.65 BSC
H
0.301 0.311 7.65
0.025 0.037 0.63
7.90
0.95
8∞
L
0∞
8∞
0∞
N
A
C
B
L
e
A1
D
NOTES:
1. D&E DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").
3. CONTROLLING DIMENSION: MILLIMETERS.
4. MEETS JEDEC MO150.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, SSOP, 5.3 MM
APPROVAL
DOCUMENT CONTROL NO.
REV.
5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
1
21-0056
C
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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