MAX1271 [MAXIM]
Multirange.+5V.8-Channel.Serial 12-Bit ADCs ; 多量程， + 5V.8 - Channel.Serial 12位ADC\n
| 型号： | MAX1271 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Multirange.+5V.8-Channel.Serial 12-Bit ADCs
|
| 文件： | 总20页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4782; Rev 1; 3/99
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
General Description
Features
The MAX1270/MAX1271 are multirange, 12-bit data-
acquisition systems (DAS) that require only a single +5V
supply for operation, yet accept signals at their analog
inputs that may span above the power-supply rail and
below ground. These systems provide eight analog
input channels that are independently software pro-
grammable for a variety of ranges: 10V, 5V, 0 to
ꢀ 12-Bit Resolution, 1/2LSB Linearity
ꢀ +5V Single-Supply Operation
ꢀ SPI/QSPI and MICROWIRE-Compatible
3-Wire Interface
ꢀ Four Software-Selectable Input Ranges
+10V, 0 to +5V for the MAX1270;
V
,
V
/2, 0 to
MAX1270: 0 to +10V, 0 to +5V, 10V, 5V
REF
REF
V
, 0 to V /2 for the MAX1271. This range switch-
MAX1271: 0 to V
, 0 to V
/2, V
,
REF
REF
REF
REF
REF
ing increases the effective dynamic range to 14 bits and
provides the flexibility to interface 4–20mA, 12V, and
15V powered sensors directly to a single +5V system.
In addition, these converters are fault protected to
1ꢀ.5V; a fault condition on any channel will not affect
the conversion result of the selected channel. Other fea-
tures include a 5MHz bandwidth track/hold, software-
selectable internal/external clock, 110ksps throughput
rate, and internal 4.09ꢀV or external reference opera-
tion.
V
/2
REF
ꢀ Eight Analog Input Channels
ꢀ 110ksps Sampling Rate
ꢀ
16.5V Overvoltage-Tolerant Input Multiplexer
ꢀ Internal 4.096V or External Reference
ꢀ Two Power-Down Modes
ꢀ Internal or External Clock
The MAX1270/MAX1271 serial interface directly con-
nects to SPI™/QSPI™ and MICROWIRE™ devices with-
out external logic.
ꢀ 24-Pin Narrow DIP or 28-Pin SSOP Packages
A hardware shutdown input (SHDN) and two software-
programmable power-down modes, standby (STBYPD)
or full power-down (FULLPD), are provided for low-cur-
rent shutdown between conversions. In standby mode,
the reference buffer remains active, eliminating start-up
delays.
Typical Operating Circuit
+5V
0.1µF
The MAX1270/MAX1271 are available in 24-pin narrow
DIP or space-saving 28-pin SSOP packages.
V
DD
SHDN
Applications
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
Industrial Control Systems
Data-Acquisition Systems
Robotics
ANALOG
INPUTS
MAX1270
MAX1271
MC68HCXX
Automatic Testing
CS
SCLK
DIN
DOUT
SSTRB
I/O
Battery-Powered Instruments
Medical Instruments
SCK
MOSI
MISO
REF
REFADJ
Ordering Information
4.7µF
0.01µF
AGND
DGND
TEMP.
RANGE
INL
(LSB)
PART
PIN-PACKAGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
1/2
MAX1270ACNG
MAX1270BCNG
MAX1270ACAI
MAX1270BCAI
24 Narrow Plastic DIP
24 Narrow Plastic DIP
28 SSOP
1
Pin Configurations appear at end of data sheet.
1/2
1
SPI and QSPI are trademarks of Motorola, Inc.
0°C to +70°C 28 SSOP
MICROWIRE is a trademark of National Semiconductor Corp.
Ordering Information continued at end of data sheet.
____________________________________________________________ Maxim Integrated Products 7-169
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
DD
V
to AGND............................................................-0.3V to +ꢀV
Operating Temperature Ranges
AGND to DGND.....................................................-0.3V to +0.3V
CH0–CH7 to AGND ......................................................... 1ꢀ.5V
MAX127_C_ _ ......................................................0°C to +70°C
MAX127_E_ _....................................................-40°C to +85°C
Storage Temperature Range ............................-ꢀ5°C to +150°C
Lead Temperature (soldering, 10sec) ............................+300°C
REF, REFADJ to AGND ..............................-0.3V to (V
SSTRB, DOUT to DGND.............................-0.3V to (V
+ 0.3V)
+ 0.3V)
DD
DD
SHDN, CS, DIN, SCLK to DGND..............................-0.3V to +ꢀV
Max Current into Any Pin ....................................................50mA
Continuous Power Dissipation (T = +70°C)
A
24-Pin Narrow DIP (derate 13.33mW/°C above +70°C)..10ꢀ7mW
28-Pin SSOP (derate 9.52mW/°C above +70°C) ..........7ꢀ2mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
DD
(V
= +5.0V 5ꢁ; unipolar/bipolar range; external reference mode, V
= +4.09ꢀV; 4.7µF at REF; external clock, f
= 2.0MHz
REF
CLK
(50ꢁ duty cycle), 18 clock/conversion cycle, 110ksps; T = T
to T
; unless otherwise noted. Typical values are T = +25°C.)
MAX A
A
MIN
PARAMETERS
ACCURACY(Note1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
12
bits
LSB
LSB
MAX127_A
MAX127_B
0.5
1.0
1
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
No missing codes over temperature
MAX127_A
3
Unipolar
MAX127_B
5
Offset Error
LSB
LSB
MAX127_A
5
Bipolar
MAX127_B
10
Unipolar
Bipolar
0.1
0.3
Channel-to-Channel Offset
Error Matching
MAX127_A
7
10
7
Unipolar
MAX127_B
Gain Error
(Note 2)
LSB
MAX127_A
Bipolar
MAX127_B
10
Unipolar, external reference
Bipolar, external reference
3
5
Gain Error Temperature
Coefficient (Note 2)
ppm/°C
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 10Vp-p (MAX1270), or 4.09ꢀVp-p (MAX1271), f
= 110ksps)
-78
SAMPLE
Signal-to-Noise + Distortion
Ratio
SINAD
70
dB
Total Harmonic Distortion
THD
Up to the 5th harmonic
50kHz (Note 3)
-87
dB
dB
Spurious-Free Dynamic Range
SFDR
80
-8ꢀ
-9ꢀ
15
Channel-to-Channel Crosstalk
Aperture Delay
dB
DC, V
= 1ꢀ.5V
IN
External clock mode
External clock mode
Internal clock mode
ns
ps
ns
<50
10
Aperture Jitter
7-170 ___________________________________________________________________________________
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
DD
(V
= +5.0V 5ꢁ; unipolar/bipolar range; external reference mode, V
= +4.09ꢀV; 4.7µF at REF; external clock, f
= 2.0MHz
REF
CLK
(50ꢁ duty cycle), 18 clock/conversion cycle, 110ksps; T = T
to T
; unless otherwise noted. Typical values are T = +25°C.)
MAX A
A
MIN
PARAMETERS
ANALOG INPUT
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Track/Hold Acquisition Time
t
f
= 2.0MHz
3
µs
ACQ
CLK
10V or
5V or
0 to 10V or 0 to V
V
range
5
REF
V
REF 2
/ range
2.5
2.5
1.25
-3dB
rolloff
Small-Signal Bandwidth
MHz
range
REF
0 to 5V or 0 to V
/ range
REF 2
RNG = 1
0
0
10
5
MAX1270
Unipolar
(BIP = 0),
Table 3
RNG = 0
RNG = 1
0
V
REF
MAX1271
MAX1270
MAX1271
RNG = 0
0
V
/2
REF
Input Voltage Range
V
V
IN
RNG = 1
-10
-5
10
5
Bipolar
(BIP = 1),
Table 3
RNG = 0
RNG = 1
-V
V
REF
REF
RNG = 0
-V
/2
V /2
REF
REF
0 to 10V range
0 to 5V range
-10
-10
-10
720
3ꢀ0
10
MAX1270
MAX1271
MAX1270
Unipolar
Bipolar
0.1
Input Current
I
IN
10V range
5V range
-1200
-ꢀ00
720
3ꢀ0
10
µA
V
REF
V
REF
range
-1200
-ꢀ00
MAX1271
/2 range
10
Unipolar
Bipolar
21
1ꢀ
Dynamic Resistance
∆V /∆I
kΩ
IN IN
Input Capacitance
(Note 4)
40
pF
INTERNALREFERENCE
REF Output Voltage
V
T
= +25°C
4.07ꢀ
4.09ꢀ
15
4.11ꢀ
V
REF
A
MAX1270_C/MAX1271_C
MAX1270_E/MAX1271_E
REF Output Tempco
TC V
ppm/°C
REF
30
Output Short Circuit Current
Load Regulation (Note 5)
Capacitive Bypass at REF
Capacitive Bypass at REFADJ
REFADJ Output Voltage
REFADJ Adjustment Range
Buffer Voltage Gain
30
10
mA
mV
µF
µF
V
0 to 0.5mA output current
4.7
0.01
2.4ꢀ5
2.500
1.5
2.535
Figure 1
ꢁ
1.ꢀ38
V/V
REFERENCEINPUT(Reference buffer disabled, reference input applied to REF)
Input Voltage Range
2.40
4.18
400
1
V
Normal or STBYPD
FULLPD
Input Current
V
= 4.18V
µA
REF
____________________________________________________________________________________ 7-171
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
DD
(V
= +5.0V 5ꢁ; unipolar/bipolar range; external reference mode, V
= +4.09ꢀV; 4.7µF at REF; external clock, f
= 2.0MHz
REF
CLK
(50ꢁ duty cycle), 18 clock/conversion cycle, 110ksps; T = T
to T
; unless otherwise noted. Typical values are T = +25°C.)
MAX A
A
MIN
PARAMETERS
Input Resistance
SYMBOL
CONDITIONS
Normal or STBYPD
MIN
10
TYP
MAX
UNITS
kΩ
V
= 4.18V
REF
FULLPD
4.18
MΩ
REFADJ Threshold for Buffer
Disable
V
DD
- 0.5
V
POWERREQUIREMENT
Supply Voltage
V
4.75
5.25
18
V
DD
Bipolar range
Normal
mA
Unipolar range
ꢀ
10
Supply Current
I
DD
STBYPD power down mode (Note ꢀ)
FULLPD power down mode
External reference = 4.09ꢀV
Internal reference
700
120
0.1
0.5
850
220
0.5
µA
Power-Supply Rejection
Ratio (Note 7)
PSRR
LSB
TIMING
External Clock Frequency
Range
f
0.1
2.0
5
MHz
µs
CLK
External clock mode (Note 8)
Internal clock mode, Figure 9
External clock mode (Note 8)
Internal clock mode, Figure 9
External clock mode
3
3
ꢀ
ꢀ
Acquisition Phase
Conversion Time
Throughput Rate
t
µs
CONV
7.7
11
110
43
ksps
µs
Internal clock mode
Bandgap Reference Start-Up
Time (Note 9)
Power-up
200
To 0.1mV, REF
bypass capacitor
fully discharged
C
C
= 4.7µF
= 33µF
8
REF
Reference Buffer Settling Time
ms
ꢀ0
REF
DIGITAL INPUTS: DIN, SCLK, CS, SHDN
Input High Threshold Voltage
Input Low Threshold Voltage
Input Hysteresis
V
2.4
V
V
IH
V
0.8
-10
IL
V
0.2
0.4
V
HYS
Input Leakage Current
I
IN
V
= 0 to V
DD
10
15
µA
pF
IN
Input Capacitance
C
(Note 4)
IN
DIGITAL OUTPUTS:DOUT, SSTRB
I
= 5mA
0.4
SINK
Output Voltage Low
V
V
V
OL
I
I
= 1ꢀmA
= 0.5mA
SINK
Output Voltage High
V
- 0.5
V
SOURCE
OH
DD
Three-State Leakage Current
I
-10
10
15
µA
pF
CS = V
CS = V
L
DD
Three-State Output Capacitance
C
OUT
(Note 4)
DD
7-172 ___________________________________________________________________________________
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
TIMING CHARACTERISTICS
DD
(V
= +4.75V to +5.25; unipolar/bipolar range; external reference mode, V
= +4.09ꢀV; 4.7µF at REF; external clock, f
=
REF
CLK
2MHz; T = T
to T
, unless otherwise noted. Typical values are T = +25°C.) (Figures 2, 5, 7, 10)
MAX A
A
MIN
PARAMETERS
DIN to SCLK Setup
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ns
t
100
DS
DH
DO
DIN to SCLK Hold
t
0
ns
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
t
C
C
C
= 100pF
20
170
120
100
ns
LOAD
LOAD
LOAD
t
= 100pF
= 100pF
ns
DV
t
ns
TR
t
t
100
0
ns
CSS
ns
CSH
t
200
200
ns
CH
t
CL
ns
t
C
C
= 100pF
= 100pF
200
200
ns
SSTRB
LOAD
LOAD
t
ns
ns
ns
CS to SSTRB Output Enable
CS to SSTRB Output Disable
SDV
External clock mode only
C
= 100pF
External clock mode only
LOAD
t
200
STR
SSTRB Rise to SCLK Rise
(Note 4)
t
Internal clock mode only
0
SCK
Note 1: Accuracy specifications tested at V = +5.0V. Performance at power-supply tolerance limit is guaranteed by Power-Supply
DD
Rejection test.
Note 2: External reference: V
= 4.09ꢀV, offset error nulled. Ideal last-code transition = FS - 3/2LSB.
REF
Note 3: Ground “on” channel; sine wave applied to all “off” channels. V
Note 4: Guaranteed by design, not production tested.
=
5V (MAX1270), V
= 4V (MAX1271).
IN
IN
Note 5: Use static external loads during conversion for specified accuracy.
Note 6: Tested using internal reference.
Note 7: PSRR measured at full scale. Tested for the 10V (MAX1270) and 4.09ꢀV (MAX1271) input ranges.
Note 8: Acquisition phase and conversion time are dependent on the clock period; clock has 50ꢁ duty cycle (Figure ꢀ).
Note 9: Not production tested. Provided for design guidance only.
____________________________________________________________________________________ 7-173
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
Typical Operating Characteristics
(Typical Operating Circuit, V
= +5V; external reference mode, V
= +4.09ꢀV; 4.7µF at REF; external clock, f
= 2MHz;
DD
REF
CLK
110ksps; T = +25°C; unless otherwise noted.)
A
STANDBY SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
6.5
6.3
6.1
5.9
5.7
5.5
750
650
550
25
20
15
10
5
INTERNAL
REFERENCE
450
350
250
EXTERNAL
REFERENCE
150
50
0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
0
1
2
3
4
5
6
7
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
NORMALIZED REFERENCE VOLTAGE
vs. TEMPERATURE
CHANNEL-TO-CHANNEL OFFSET-ERROR
MATCHING vs. TEMPERATURE
FULL POWER-DOWN SUPPLY CURRENT
vs. TEMPERATURE
1.001
1.000
0.35
0.30
0.25
150
130
BIPOLAR MODE
EXTERNAL
REFERENCE
0.999
0.998
0.997
0.996
110
90
0.20
0.15
0.10
0.05
0
INTERNAL
UNIPOLAR MODE
REFERENCE
70
50
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
CHANNEL-TO-CHANNEL GAIN-ERROR
MATCHING vs. TEMPERATURE
INTEGRAL NONLINEARITY vs.
DIGITAL CODE
FTT PLOT
0.8
0.7
0.6
0.15
0.10
0.05
0
0
f
f
= 10kHz
SAMPLE
IN
= 110ksps
-20
-40
UNIPOLAR MODE
0.5
0.4
-60
-0.05
-0.10
-0.15
-80
0.3
0.2
0.1
BIPOLAR MODE
-100
-120
-40
-15
10
35
60
85
0
819
1638
2457
3276
4095
0
10k
20k
30k
40k
50k
TEMPERATURE (°C)
DIGITAL CODE
FREQUENCY (Hz)
7-174 ___________________________________________________________________________________
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
Typical Operating Characteristics (continued)
(Typical Operating Circuit, V
= +5V; external reference mode, V
= +4.09ꢀV; 4.7µF at REF; external clock, f
= 2MHz;
DD
REF
CLK
110ksps; T = +25°C; unless otherwise noted.)
A
AVERAGE SUPPLY CURRENT vs.
CONVERSION RATE (USING FULLPD)
AVERAGE SUPPLY CURRENT vs.
CONVERSION RATE (USING STANDBY)
8
7
6
5
4
3
2
1
0
8
V
f
= 5V, INTERNAL REFERENCE,
= 2MHz
DD
CLK
V
f
= 5V, INTERNAL REFERENCE,
= 2MHz
DD
CLK
7
6
5
4
3
2
1
0
EXTERNAL CLOCK MODE.
EXTERNAL CLOCK MODE.
LOW-RANGE UNIPOLAR MODE.
V
LOW-RANGE UNIPOLAR MODE.
V
= 0
CH_
= 0
CH_
0.1
1
10
100
1000
0.1
1
10
100
1000
CONVERSION RATE (ksps)
CONVERSION RATE (ksps)
Pin Description
PIN
NAME
FUNCTION
DIP
1
SSOP
1
V
DD
+5V Supply. Bypass with a 0.1µF capacitor to AGND.
Digital Ground
2, 4
2, 3
DGND
4, 7, 8,
11, 22,
24, 25,
28
3, 9,
22, 24
N.C.
No Connect. No internal connection.
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also
sets the conversion speed.
5
5
SCLK
Active-Low Chip-Select Input. Data is not clocked into DIN unless CS is low. When CS is high,
DOUT is high impedance.
ꢀ
7
ꢀ
9
CS
DIN
Serial Data Input. Data is clocked in on the rising edge of SCLK.
Serial Strobe Output. In internal clock mode, SSTRB goes low after the falling edge of the eighth
SCLK and returns high when conversion is done. In external clock mode, SSTRB pulses high for one
clock period before the MSB decision. High impedance when CS is high in external clock mode.
8
10
SSTRB
10
11
12
12
13
14
DOUT
SHDN
AGND
Serial Data Output. Data is clocked out on the falling edge of SCLK. High impedance when CS is high.
Shutdown Input. When low, device is in FULLPD mode. Connect high for normal operation.
Analog Ground
15–21,
23
CH0–
CH7
13–20
21
Analog Input Channels
Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01µF capacitor to AGND.
2ꢀ
REFADJ
Connect to V
when using an external reference at REF.
DD
Reference-Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer pro-
vides a 4.09ꢀV nominal output, externally adjustable at REFADJ. In external reference mode, disable
23
27
REF
the internal reference by pulling REFADJ to V and applying the external reference to REF.
DD
____________________________________________________________________________________ 7-175
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
+5V
5mA
DOUT
OR
SSTRB
+5V
DOUT
OR
SSTRB
MAX1270
MAX1271
510k
100k
24k
REFADJ
C
LOAD
0.5mA
C
LOAD
0.01µF
a) HIGH-Z TO V , V TO V
,
b) HIGH-Z TO V , V TO V
,
OH
OH OL
AND V TO HIGH-Z
OH
OH OL
AND V TO HIGH-Z
OH
OH
Figure 1. Reference-Adjust Circuit
Figure 2. Output Load Circuit for Timing Characteristics
unipolar mode (MAX1270) the signal applied at the
input channel is rescaled through the resistor-divider
network formed by R1, R2, and R3 (Figure 4); a low-
impedance (<4Ω) input source is recommended to
minimize gain error. When the MAX1271 is configured
for unipolar mode, the channel input resistance (RIN)
becomes a fixed 5.12kΩ (typ). Source impedances
Detailed Description
Converter Operation
The MAX1270/MAX1271 multirange, fault-tolerant ADCs
use successive approximation and internal track/hold
(T/H) circuitry to convert an analog signal to a 12-bit
digital output. Figure 3 shows the block diagram of the
MAX1270/MAX1271.
below 15kΩ (0 to V
) and 5kΩ (0 to V
REF
/2) do not
REF
significantly affect the AC performance of the ADC.
Analog-Input Track/Hold
The T/H enters tracking/acquisition mode on the falling
edge of the sixth clock in the 8-bit input control word,
and enters hold/conversion mode when the timed
acquisition interval (six clock cycles, 3µs minimum)
ends. In internal clock mode, the acquisition is timed by
two external clock cycles and four internal clock cycles.
The acquisition time (t ) is a function of the source
ACQ
output resistance, the channel input resistance, and the
T/H capacitance. Higher source impedances can be
used if an input capacitor is connected between the
analog inputs and AGND. Note that the input capacitor
forms an RC filter with the input source impedance, lim-
iting the ADC’s signal bandwidth.
When operating in bipolar (MAX1270 and MAX1271) or
DIN
SSTRB
DOUT
CS
SCLK
INT
CLOCK
SERIAL INTERFACE LOGIC
SHDN
V
DD
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AGND
DGND
ANALOG
INPUT
MUX
OUT
CLOCK
12-BIT SAR ADC
AND SIGNAL
CONDITIONING
T/H
IN
REF
+4.096V
REF
10k
Av =
1.638
2.5V
REFERENCE
MAX1270
MAX1271
REFADJ
Figure 3. Block Diagram
7-176 ___________________________________________________________________________________
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
Input Bandwidth
Digital Interface
The MAX1270/MAX1271 feature a serial interface that is
fully compatible with SPI/QSPI and MICROWIRE
devices. For SPI/QSPI, set CPOL = 0, CPHA = 0 in the
SPI control registers of the microcontroller. Figure 5
shows detailed serial interface timing information. Refer
to Table 1 for programming the input control byte.
The ADC’s input small-signal bandwidth depends on
the selected input range and varies from 1.5MHz to
5MHz (see Electrical Characteristics). The MAX1270/
MAX1271 maximum sampling rate is 110ksps. By using
undersampling techniques, it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate.
To avoid high-frequency signals being aliased into the
frequency band of interest, anti-aliasing filtering is rec-
ommended.
BIPOLAR
VOLTAGE
REFERENCE
S1
Input Range and Protection
The MAX1270/MAX1271 have software-selectable input
ranges. Each analog input channel can be indepen-
dently programmed to one of four ranges by setting the
appropriate control bits (RNG, BIP) in the control byte
(Table 1). The MAX1270 has selectable input ranges
UNIPOLAR
R3
5.12k
OFF
R1
CH_
C
HOLD
extending to 10V ( V
· 2.441), while the MAX1271
S2
R2
T/H
REF
OUT
ON
has selectable input ranges extending to
4 shows the equivalent input circuit.
V
. Figure
REF
S3
TRACK
HOLD
A resistor network on each analog input provides
1ꢀ.5V fault protection for all channels. Whether or not
the channel is on, this circuit limits the current going
into or out of the pin to less than 2mA. This provides an
added layer of protection when momentary overvolt-
ages occur at the selected input channel, when a neg-
ative signal is applied to the input, and when the device
is configured for unipolar mode. The overvoltage pro-
tection is active even if the device is in power-down
HOLD
TRACK
S4
S1 = BIPOLAR/UNIPOLAR SWITCH
S2 = INPUT MUX SWITCH
S3, S4 = T/H SWITCH
R1 = 12.5kΩ (MAX1270)
or 5.12kΩ (MAX1271)
R2 =
8.67kΩ (MAX1270)
or ∞ (MAX1271)
Figure 4. Equivalent Input Circuit
mode or if V
= 0.
DD
• • •
• • •
CS
t
t
t
CSH
CSS
CH
t
t
CL
CSH
SCLK
t
DS
t
DH
DIN
• • •
• • •
t
t
t
TR
DV
DO
DOUT
Figure 5. Detailed Serial-Interface Timing
____________________________________________________________________________________ 7-177
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
Table 1. Control-Byte Format
Bit 7
(MSB)
Bit 0
(LSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
START
SEL2
SEL1
SEL0
RNG
BIP
PD1
PD0
BIT
NAME
DESCRIPTION
7 (MSB)
START
First logic “1” after CS goes low defines the beginning of the control byte.
SEL2, SEL1,
SEL0
ꢀ, 5, 4
These three bits select the desired “on” channel (Table 2).
3
2
RNG
BIP
Selects the full-scale input voltage range (Table 3).
Selects unipolar or bipolar conversion mode (Table 3).
Select clock and power-down modes (Table 4).
1, 0 (LSB)
PD1, PD0
Table 2. Channel Selection
Table 4. Power Down and Clock Selection
SEL2
SEL1
SEL0
CHANNEL
CH0
PD1
PD0
MODE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Normal Operation (always on),
Internal Clock Mode
0
0
CH1
CH2
Normal Operation (always on),
External Clock Mode
0
1
1
1
0
1
CH3
CH4
Standby Power-Down Mode (STBYPD),
Clock Mode Unaffected
CH5
CHꢀ
Full Power-Down Mode (FULLPD),
Clock Mode Unaffected
CH7
Table 3. Range and Polarity Selection for MAX1270/MAX1271
RANGEANDPOLARITY SELECTION FOR MAX1270
NEGATIVE
INPUT RANGE
RNG
BIP
ZERO SCALE (V)
FULL SCALE
FULL SCALE
0 to 5V
0 to 10V
5V
0
1
0
1
0
0
1
1
—
—
0
0
0
0
V
REF
V
REF
V
REF
V
REF
· 1.2207
· 2.4414
· 1.2207
· 2.4414
-V
-V
· 1.2207
· 2.4414
REF
10V
REF
RANGEANDPOLARITY SELECTION FOR MAX1271
NEGATIVE FULL
SCALE
INPUT RANGE
0 to V /2
RNG
BIP
ZERO SCALE (V)
FULL SCALE
0
1
0
1
0
0
1
1
—
—
0
0
0
0
V /2
REF
REF
0 to V
V
REF
REF
V
/2
REF
-V
REF
/2
V /2
REF
V
REF
-V
REF
V
REF
7-178 ___________________________________________________________________________________
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
Input Data Format
Keep CS low during successive conversions. If a start-
bit is received after CS transitions from high to low, but
before the output bit ꢀ (Dꢀ) becomes available, the cur-
rent conversion will terminate and a new conversion will
begin.
Input data (control byte) is clocked in at DIN at the ris-
ing edge of SCLK. CS enables communication with the
MAX1270/MAX1271. After CS falls, the first arriving
logic “1” bit represents the start bit (MSB) of the input
control byte. The start bit is defined as:
External Clock Mode (PD1 = 0, PD0 = 1)
In external clock mode, the clock shifts data in and out
of the MAX1270/MAX1271 and controls the acquisition
and conversion timings. When acquisition is done,
SSTRB pulses high for one clock cycle and conversion
begins. Successive-approximation bit decisions appear
at DOUT on each of the next 12 SCLK falling edges
(Figure ꢀ). Additional SCLK falling edges will result in
zeros appearing at DOUT. Figure 7 shows the SSTRB
timing in external clock mode.
The first high bit clocked into DIN with CS low
anytime the converter is idle; e.g., after V
applied.
is
DD
OR
The first high bit clocked into DIN after bit ꢀ
(Dꢀ) of a conversion in progress is clocked
onto DOUT.
Output Data Format
Output data is clocked out on the falling edge of SCLK
at DOUT, MSB first (D11). In unipolar mode, the output
is straight binary. For bipolar mode, the output is two’s-
complement binary. For output binary codes, refer to
the Transfer Function section.
SSTRB and DOUT go into a high-impedance state
when CS goes high; after the next CS falling edge,
SSTRB and DOUT will output a logic low.
The conversion must be completed in some minimum
time, or droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if
the clock period exceeds 10µs, or if serial-clock inter-
ruptions could cause the conversion interval to exceed
120µs. The fastest the MAX1270/MAX1271 can run is
18 clocks per conversion in external clock mode, and
with a clock rate of 2MHz, the maximum sampling rate
is 111 ksps (Figure 8). In order to achieve maximum
throughput, keep CS low, use external clock mode with
a continuous SCLK, and start the following control byte
after bit ꢀ (Dꢀ) of the conversion in progress is clocked
onto DOUT.
How to Start a Conversion
The MAX1270/MAX1271 use either an external serial
clock or the internal clock to complete an acquisition
and perform a conversion. In both clock modes, the
external clock shifts data in and out. Refer to Table 4
for programming clock modes.
The falling edge of CS does not start a conversion on
the MAX1270/MAX1271; a control byte is required for
each conversion. Acquisition starts after the sixth bit is
programmed in the input control byte. Conversion
starts when the acquisition time, six clock cycles,
expires.
If CS is low and SCLK is continuous, guarantee a start
bit by first clocking in 18 zeros.
CS
SCLK
1
8
12
13
14
24
25
START SEL2 SEL1 SEL0 RNG BIP PD1 PD0
MSB LSB
DIN
SSTRB
DOUT
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
FILLED WITH
ZEROS
D11
D10 D9
D1 D0
LSB
MSB
ACQUISITION
6 SCLK
CONVERSION
12 SCLK
A/D STATE
Figure 6. External Clock Mode, 25 Clocks/Conversion Timing
____________________________________________________________________________________ 7-179
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
CS
• • •
• • •
t
t
STR
SDV
SSTRB
HIGH-Z
HIGH-Z
• • •
• • •
t
SSTRB
t
SSTRB
SCLK
• • •
•
• • • •
SCLK 12
Figure 7. External Clock Mode SSTRB Detailed Timing
• • •
• • •
CS
1
8
13
16
19
24
26
31
32
37
14
SCLK
DIN
CONTROL BYTE Ø
CONTROL BYTE 1
CONTROL BYTE 2
MSB
LSB
START SEL2 SEL1 SEL0 RNG BIP PD1 PD0
START SEL2 SEL1 SEL0 RNG BIP PD1 PD0
SEL2
START
• • •
• • •
18 SCLK
HIGH-Z
SSTRB
RESULT Ø
RESULT 1
MSB
LSB
HIGH-Z
• • •
D11 D10 D9 D8 D7 D6 D5
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DOUT
18 SCLK
ACQUISITION
6 SCLK
CONVERSION
12 SCLK
ACQUISITION
6 SCLK
CONVERSION
12 SCLK
A/D STATE
Figure 8. External Clock Mode, 18 Clocks/Conversion Timing
Internal Clock Mode (PD1 = 0, PD0 = 0)
In internal clock mode, the MAX1270/MAX1271 gener-
ate their conversion clock internally. This frees the
microprocessor from the burden of running the acquisi-
tion and the SAR conversion clock, and allows the con-
version results to be read back at the processor’s
convenience, at any clock rate from 0 to typically
10MHz.
1ꢀth internal clock pulse (12 internal clock cycle pulses
are used for conversion). SSTRB will remain low for a
maximum of 15µs, during which time SCLK should
remain low for best noise performance. An internal reg-
ister stores data while the conversion is in progress.
The MSB of the result byte (D11) is present at DOUT
starting at the falling edge of the last internal clock of
conversion. Successive falling edges of SCLK will shift
the remaining data out of this register (Figure 9).
Additional SCLK edges will result in zeros on DOUT.
SSTRB goes low after the falling edge of the last bit
(PD0) of the control byte has been shifted in, and
returns high when the conversion is complete.
Acquisition is completed and conversion begins on the
falling edge of the 4th internal clock pulse after the con-
trol byte; conversion ends on the falling edge of the
When internal clock mode is selected, SSTRB does not
go into a high-impedance state when CS goes high.
Pulling CS high prevents data from being clocked in
and three-states DOUT, but does not adversely affect a
7-180 ___________________________________________________________________________________
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
CS
SCLK
1
8
9
10
19
20
START SEL2 SEL1 SEL0 RNG BIP PD1 PD0
MSB LSB
DIN
SSTRB
16 INT CLK
HIGH-Z
HIGH-Z
HIGH-Z
FILLED WITH ZEROS
DOUT
D11 D10
MSB
D1 D0
LSB
ACQUISITION CONVERSION
A/D STATE
2 EXT SCLK 12 INT CLK
+4 INT CLK
Figure 9. Internal Clock Mode, 20 SCLK/Conversion Timing
CS • • •
t
CSS
t
t
SCK
CSH
SSTRB • • •
t
SSTRB
SCLK • • •
SCLK #8
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
Figure 10. Internal Clock Mode SSTRB Detailed Timing
conversion in progress. Figure 10 shows the SSTRB
timing in internal clock mode.
Applications Information
Power-On Reset
The MAX1270/MAX1271 power up in normal operation
(all internal circuitry active) and internal clock mode,
waiting for a start bit. The contents of the output data
register are cleared at power-up.
Internal clock mode conversions can be completed
with 13 external clocks per conversion but require a
waiting period of 15µs for the conversion to be com-
pleted (Figure 11).
Most microcontrollers require that conversions occur in
multiples of 8 SCLK clock cycles; 1ꢀ clock cycles per
conversion, as shown in Figure 12, will typically be the
most convenient way for a microcontroller to drive the
MAX1270/MAX1271.
Internal or External Reference
The MAX1270/MAX1271 operate with either an internal
or external reference. An external reference is connect-
ed to either REF or REFADJ (Figure 13). The REFADJ
internal buffer gain is trimmed to 1.ꢀ38V to provide
4.09ꢀV at REF from a 2.5V reference.
____________________________________________________________________________________ 7-181
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
• • •
• • •
CS
1
8
9
14
16
22
24
SCLK
DIN
CONTROL BYTE Ø
CONTROL BYTE 1
CONTROL BYTE 2
SEL2 SEL1 SEL0 RNG BIP PD1 PD0
SEL2 SEL1 SEL0 RNG BIP PD1 PD0
SEL2 SEL1 SEL0
START
START
START
• • •
• • •
13 SCLK
SSTRB
DOUT
RESULT Ø
RESULT 1
HIGH-Z
• • •
D11 D10 D9 D8 D7 D6 D5 D4 D3
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
13 SCLK
ACQUISITION CONVERSION
ACQUISITION CONVERSION
A/D STATE
Figure 11. Internal Clock Mode, 13 Clocks/Conversion Timing
• • •
CS
1
8
9
16
17
24
25
32
• • •
• • •
• • •
SCLK
DIN
CONTROL BYTE Ø
CONTROL BYTE 1
CB 2
SEL2 SEL1 SEL0 RNG BIP PD1 PD0
SEL2 SEL1 SEL0 RNG BIP PD1 PD0
START
START
START
16 SCLK
SSTRB
RESULT Ø
RESULT 1
HIGH-Z
HIGH-Z
HIGH-Z
• • •
D11 D10 D9 D8 D7 D6 D5 D4 D3
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DOUT
16 SCLK
ACQUISITION CONVERSION
ACQUISITION CONVERSION
A/D STATE
IDLE
Figure 12. Internal Clock Mode, 16 Clocks/Conversion Timing
Internal Reference
The internally trimmed 2.50V reference is amplified
through the REFADJ buffer to provide 4.09ꢀV at REF.
Bypass REF with a 4.7µF capacitor to AGND and
REFADJ with a 0.01µF capacitor to AGND (Figure 13a).
The internal reference voltage is adjustable to 1.5ꢁ
( ꢀ5 LSBs) with the reference-adjust circuit of Figure 1.
V
= 1.ꢀ384 · V
(2.4 < V
< 4.18)
REF
REF
REFADJ
(Figure 13c). At REF and REFADJ, the input impedance
is a minimum of 10kΩ for DC currents. During conver-
sions, an external reference at REF must be able to
deliver 400µA DC load currents and must have an out-
put impedance of 10Ω or less. If the reference has
higher output impedance or is noisy, bypass REF with a
4.7µF capacitor to AGND as close to the chip as possi-
ble.
External Reference
To use the REF input directly, disable the internal buffer
With an external reference voltage of less than 4.09ꢀV
at REF or less than 2.5V at REFADJ, the increase in the
ratio of RMS noise to the LSB value (full-scale / 409ꢀ)
results in performance degradation (loss of effective
bits).
by tying REFADJ to V
(Figure 13b). Using the
DD
REFADJ input eliminates the need to buffer the refer-
ence externally. When a reference is applied at
REFADJ, bypass REFADJ with a 0.01µF capacitor to
AGND. Note that when an external reference is applied
at REFADJ, the voltage at REF is given by:
7-182 ___________________________________________________________________________________
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
Power-Down Mode
To save power, configure the converter into low-current
shutdown mode between conversions. Two program-
REF
4.7µF
REF
mable power-down modes are available in addition to a
hardware shutdown. Select STBYPD or FULLPD by pro-
gramming PD0 and PD1 in the input control byte
(Table 4). When software power-down is asserted, it
becomes effective only after the end of conversion. For
example, if the control byte contains PD1 = 0, then the
chip will remain powered up. If PD1 = 1, then the chip
will power-down at the end of conversion. In all power-
down modes, the interface remains active and conver-
sion results may be read. Input overvoltage protection
is active in all power-down modes.
MAX1270
MAX1271
C
A = 1.638
V
REFADJ
0.01µF
10k
2.5V
The first logical 1 on DIN after CS falls is interpreted as
a start condition, and powers up the MAX1270/
MAX1271 from a software selected STBYPD or FULLPD
condition.
Figure 13a. Internal Reference
For hardware-controlled power-down (FULLPD), pull
SHDN low. When hardware shutdown is asserted, it
becomes effective immediately, and any conversion in
progress is aborted.
REF
4.096V
4.7µF
MAX1270
MAX1271
C
REF
Choosing Power-Down Modes
The bandgap reference and reference buffer remain
active in STBYPD mode, maintaining the voltage on the
4.7µF capacitor at REF. This is a “DC” state that does
not degrade after power-down of any duration.
A = 1.638
V
V
DD
REFADJ
10k
In FULLPD mode, only the bandgap reference is active.
Connect a 33µF capacitor between REF and AGND to
maintain the reference voltage between conversions
and to reduce transients when the buffer is enabled
and disabled. Throughput rates down to 1ksps can be
achieved without allotting extra acquisition time for ref-
erence recovery prior to conversion. This allows con-
version to begin immediately after power-up. If the
discharge of the REF capacitor during FULLPD
exceeds the desired limits for accuracy (less than a
fraction of an LSB), run a STBYPD power-down cycle
prior to starting conversions. Take into account that the
reference buffer recharges the bypass capacitor at an
80mV/ms slew rate, and add 50µs for settling time.
2.5V
Figure 13b. External Reference, Reference at REF
REF
4.7µF
REF
MAX1270
MAX1271
C
A = 1.638
V
REFADJ
2.5V
0.01µF
Auto-Shutdown
Selecting STBYPD on every conversion automatically
shuts down the MAX1270/MAX1271 after each conver-
sion without requiring any start-up time on the next con-
version.
10k
2.5V
Figure 13c. External Reference, Reference at REFADJ
____________________________________________________________________________________ 7-183
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
OUTPUT CODE
2FS
4096
OUTPUT CODE
11... 111
1 LSB =
FS
4096
1 LSB =
FULL-SCALE
TRANSITION
011... 111
011... 110
11... 110
11... 101
000... 001
000... 000
111... 111
100... 010
100... 001
100... 000
00... 011
00... 010
00... 001
00... 000
-FS
0
+FS - 1 LSB
FS
0
1
2
3
INPUT VOLTAGE (LSB)
3
FS - / LSB
INPUT VOLTAGE (LSB)
2
Figure 14b. Bipolar Transfer Function
Figure 14a. Unipolar Transfer Function
Transfer Function
Output data coding for the MAX1270/MAX1271 is bina-
ry in unipolar mode with 1LSB = (FS / 409ꢀ) and two’s
complement binary in bipolar mode with 1LSB = [(2 ·
| FS | ) / 409ꢀ]. Code transitions occur halfway between
successive-integer LSB values. Figures 14a and 14b
show the input/output (I/O) transfer functions for unipo-
lar and bipolar operations, respectively. For full-scale
values, refer to Table 3.
SUPPLY
GND
+5V
4.7µF
R* = 5Ω
0.1µF
**
Layout, Grounding, and Bypassing
Careful printed circuit board layout is essential for best
system performance. Use a ground plane for best per-
formance. To reduce crosstalk and noise injection,
keep analog and digital signals separate. Connect ana-
log grounds and DGND in a star configuration to
AGND. For noise-free operation, ensure the ground
return from AGND to the supply ground is low imped-
ance and as short as possible. Connect the logic
V
+5V
DGND
AGND
DGND
DD
DIGITAL
CIRCUITRY
MAX1270
MAX1271
* OPTIONAL
** CONNECT AGND AND DGND WITH A GROUND PLANE OR A SHORT TRACE.
grounds directly to the supply ground. Bypass V
with
DD
Figure 15. Power-Supply Grounding Connections
0.1µF and 4.7µF capacitors to AGND to minimize high-
and low-frequency fluctuations. If the supply is exces-
sively noisy, connect a 5Ω resistor between the supply
and V , as shown in Figure 15.
DD
7-184 ___________________________________________________________________________________
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
Pin Configurations
TOP VIEW
V
1
2
3
4
5
6
7
8
9
28 N.C.
27 REF
26 REFADJ
25 N.C.
24 N.C.
23 CH7
22 N.C.
21 CH6
20 CH5
19 CH4
18 CH3
17 CH2
16 CH1
15 CH0
DD
V
1
2
3
4
5
6
7
8
9
24 N.C.
23 REF
22 N.C.
21 REFADJ
20 CH7
19 CH6
18 CH5
17 CH4
16 CH3
15 CH2
14 CH1
13 CH0
DD
DGND
DGND
N.C.
SCLK
CS
DGND
N.C.
DGND
SCLK
CS
MAX1270
MAX1271
MAX1270
MAX1271
N.C.
N.C.
DIN
DIN
SSTRB
N.C.
SSTRB 10
N.C. 11
DOUT 10
SHDN 11
AGND 12
DOUT 12
SHDN 13
AGND 14
DIP
SSOP
Ordering Information (continued)
Chip Information
TRANSISTOR COUNT: 4219
TEMP.
RANGE
INL
(LSB)
PART
PIN-PACKAGE
SUBSTRATE CONNECTED TO AGND
24 Narrow Plastic DIP
24 Narrow Plastic DIP
28 SSOP
MAX1270AENG -40°C to +85°C
MAX1270BENG -40°C to +85°C
MAX1270AEAI -40°C to +85°C
MAX1270BEAI -40°C to +85°C
MAX1271ACNG 0°C to +70°C
MAX1271BCNG 0°C to +70°C
1/2
1
1/2
1
28 SSOP
24 Narrow Plastic DIP
24 Narrow Plastic DIP
28 SSOP
1/2
1
MAX1271ACAI
MAX1271BCAI
0°C to +70°C
0°C to +70°C
1/2
1
28 SSOP
24 Narrow Plastic DIP
24 Narrow Plastic DIP
28 SSOP
MAX1271AENG -40°C to +85°C
MAX1271BENG -40°C to +85°C
MAX1271AEAI -40°C to +85°C
MAX1271BEAI -40°C to +85°C
1/2
1
1/2
1
28 SSOP
____________________________________________________________________________________ 7-185
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
________________________________________________________Package Information
7-186 ___________________________________________________________________________________
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
Package Information (continued)
____________________________________________________________________________________ 7-187
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
NOTES
7-188 ___________________________________________________________________________________
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