MAX1246BEPE_技术文档

19-1071; Rev 1; 3/97

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

6/MAX1247

_______________Ge n e ra l De s c rip t io n

____________________________Fe a t u re s

The MAX1246/MAX1247 12-bit data-acquisition systems

c omb ine a 4-c ha nne l multip le xe r, hig h-b a nd wid th

track/hold, and serial interface with high conversion

speed and low power consumption. The MAX1246 oper-

ates from a single +2.7V to +3.6V supply; the MAX1247

operates from a single +2.7V to +5.25V supply. Both

devices’ analog inputs are software configurable for

unipolar/bipolar and single-ended/differential operation.

♦ 4-Channel Single-Ended or 2-Channel

Differential Inputs

♦ Single-Supply Operation:

+2.7V to +3.6V (MAX1246)

+2.7V to +5.25V (MAX1247)

♦ Internal 2.5V Reference (MAX1246)

♦ Low Power: 1.2mA (133ksps, 3V supply)

54µA (1ksps, 3V supply)

The 4-wire serial interface connects directly to SPI™/

QSPI™ and Microwire™ devices without external logic. A

serial strobe output allows direct connection to TMS320-

family digital signal processors. The MAX1246/MAX1247

use either the internal clock or an external serial-interface

clock to perform successive-approximation analog-to-

digital conversions.

1µA (power-down mode)

♦ SPI/QSPI/Microwire/TMS320-Compatible

4-Wire Serial Interface

♦ Software-Configurable Unipolar or Bipolar Inputs

♦ 16-Pin QSOP Package (same area as 8-pin SO)

The MAX1246 has an internal 2.5V reference, while the

MAX1247 requires an external reference. Both parts have

a re fe re nc e -b uffe r a mp lifie r with a ± 1.5% volta g e -

adjustment range.

______________Ord e rin g In fo rm a t io n

These devices provide a hard-wired SHDN pin and a

s oftwa re -s e le c ta b le p owe r-d own, a nd c a n b e p ro-

grammed to automatically shut down at the end of a con-

version. Accessing the serial interface automatically

powers up the MAX1246/MAX1247, and the quick turn-on

time allows them to be shut down between all conver-

sions. This technique can cut supply current to under

60µA at reduced sampling rates.

INL

(LSB)

PART^†

TEMP. RANGE PIN-PACKAGE

MAX1246ACPE 0°C to +70°C

16 Plastic DIP

16 QSOP

±1/2

±1

MAX1246BCPE

MAX1246ACEE

MAX1246BCEE

0°C to +70°C

±1/2

±1

16 QSOP

Ordering Information continued at end of data sheet.

Contact factory for availability of alternate surface-mount

packages.

The MAX1246/MAX1247 are available in a 16-pin DIP and

a small QSOP that occupies the same board area as an

8-pin SO.

†

For 8-c ha nne l ve rs ions of the s e d e vic e s , s e e the

MAX146/MAX147 data sheet.

__________Typ ic a l Op e ra t in g Circ u it

________________________Ap p lic a t io n s

+3V

Portable Data Logging

Medical Instruments

Pen Digitizers

Data Acquisition

V

DD

V

CH0

DD

0.1µF

Battery-Powered Instruments

Process Control

0V TO

+2.5V

ANALOG

INPUTS

DGND

MAX1246

CH3

AGND

COM

CPU

I/O

VREF

CS

4.7µF

SCLK

SCK (SK)

MOSI (SO)

MISO (SI)

DIN

DOUT

REFADJ

0.047µF

SSTRB

SHDN

V

SS

Pin Configuration appears at end of data sheet.

SPI and QSPI are registered trademarks of Motorola, Inc. Microwire is a registered trademark of National Semiconductor Corp.

________________________________________________________________ Maxim Integrated Products

1

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

ABSOLUTE MAXIMUM RATINGS

V

to AGND, DGND................................................. -0.3V to 6V

QSOP (derate 8.36mW/°C above +70°C)................... 667mW

CERDIP (derate 10.00mW/°C above +70°C).............. 800mW

Operating Temperature Ranges

DD

AGND to DGND...................................................... -0.3V to 0.3V

CH0–CH3, COM to AGND, DGND ............ -0.3V to (V + 0.3V)

DD

VREF to AGND........................................... -0.3V to (V + 0.3V)

Digital Inputs to DGND .............................................. -0.3V to 6V

MAX1246_C_E/MAX1247_C_E .......................... 0°C to +70°C

MAX1246_E_E/MAX1247_E_E........................ -40°C to +85°C

MAX1246_MJE/MAX1247_MJE .................... -55°C to +125°C

Storage Temperature Range ............................ -60°C to +150°C

Lead Temperature (soldering, 10sec) ............................ +300°C

DD

Digital Outputs to DGND ........................... -0.3V to (V + 0.3V)

DD

Digital Output Sink Current .................................................25mA

Continuous Power Dissipation (T = +70°C)

A

Plastic DIP (derate 10.53mW/°C above +70°C) ......... 842mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V = +2.7V to +3.6V (MAX1246); V = +2.7V to +5.25V (MAX1247); COM = 0V; f = 2.0MHz; external clock (50% duty cycle);

DD

SCLK

15 clocks/conversion cycle (133ksps); MAX1246—4.7µF capacitor at VREF pin; MAX1247—external reference, VREF = 2.500 V

applied to VREF pin; T = T

to T

; unless otherwise noted.)

A

MIN

MAX

PARAMETER

DC ACCURACY (Note 1)

Resolution

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

6/MAX1247

12

Bits

MAX124_A

MAX124_B

±0.5

LSB

±1.0

Relative Accuracy (Note 2)

Differential Nonlinearity

Offset Error

INL

DNL

No missing codes over temperature

MAX124_A

±1

±3

±4

LSB

±0.5

LSB

MAX124_B

Gain Error (Note 3)

±0.5

LSB

Gain Temperature Coefficient

±0.25

ppm/°C

Channel-to-Channel Offset

Matching

±0.25

LSB

DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.500Vp-p, 133ksps, 2.0MHz external clock, bipolar input mode)

Signal-to-Noise + Distortion Ratio

Total Harmonic Distortion

Spurious-Free Dynamic Range

Channel-to-Channel Crosstalk

Small-Signal Bandwidth

SINAD

THD

70

73

-88

90

dB

Up to the 5th harmonic

-80

SFDR

80

dB

65kHz, 2.500V (Note 4)

p-p

-85

2.25

1.0

dB

-3dB rolloff

MHz

Full-Power Bandwidth

CONVERSION RATE

5.5

35

6

7.5

65

Internal clock, SHDN = FLOAT

Conversion Time (Note 5)

t

µs

Internal clock, SHDN = V

CONV

DD

External clock = 2MHz, 12 clocks/conversion

Track/Hold Acquisition Time

Aperture Delay

t

1.5

µs

ns

ps

ACQ

30

<50

1.8

Aperture Jitter

SHDN = FLOAT

Internal Clock Frequency

External Clock Frequency

MHz

0.225

SHDN = V

DD

0.1

0

2.0

Data transfer only

2

_______________________________________________________________________________________

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

6/MAX1247

ELECTRICAL CHARACTERISTICS (continued)

(V = +2.7V to +3.6V (MAX1246); V = +2.7V to +5.25V (MAX1247); COM = 0V; f = 2.0MHz; external clock (50% duty cycle);

DD

SCLK

15 clocks/conversion cycle (133ksps); MAX1246—4.7µF capacitor at VREF pin; MAX1247—external reference, VREF = 2.500 V

applied to VREF pin; T = T

to T

; unless otherwise noted.)

A

MIN

MAX

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

ANALOG/COM INPUTS

Unipolar, COM = 0V

0 to VREF

Input Voltage Range, Single-

Ended and Differential (Note 6)

V

Bipolar, COM = VREF / 2

±VREF / 2

±1

Multiplexer Leakage Current

Input Capacitance

On/off leakage current, V

= 0V or V

±0.01

16

µA

pF

CH_

DD

INTERNAL REFERENCE (MAX1246 only, reference buffer enabled)

VREF Output Voltage

T

A

= +25°C

2.480

2.500

2.520

30

V

VREF Short-Circuit Current

mA

MAX1246_C

MAX1246_E

MAX1246_M

±30

±50

VREF Temperature Coefficient

±60 ppm/°C

±30

±80

mV

Load Regulation (Note 8)

Capacitive Bypass at VREF

0mA to 0.2mA output load

Internal compensation mode

External compensation mode

±0.35

0

µF

4.7

Capacitive Bypass at REFADJ

REFADJ Adjustment Range

0.047

µF

%

±1.5

EXTERNAL REFERENCE AT VREF (Buffer disabled)

VREF Input Voltage Range

(Note 9)

V

50mV

+

DD

V

1.0

18

VREF Input Current

VREF = 2.500V

100

25

150

µA

kΩ

µA

VREF Input Resistance

Shutdown VREF Input Current

0.01

10

V

0.5

-

DD

REFADJ Buffer Disable Threshold

EXTERNAL REFERENCE AT REFADJ

Capacitive Bypass at VREF

V

Internal compensation mode

External compensation mode

MAX1246

0

µF

V/V

µA

4.7

2.06

2.00

Reference Buffer Gain

REFADJ Input Current

MAX1247

MAX1246

±50

±10

MAX1247

_______________________________________________________________________________________

3

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

ELECTRICAL CHARACTERISTICS (continued)

(V = +2.7V to +3.6V (MAX1246); V = +2.7V to +5.25V (MAX1247); COM = 0V; f = 2.0MHz; external clock (50% duty cycle);

DD

SCLK

15 clocks/conversion cycle (133ksps); MAX1246—4.7µF capacitor at VREF pin; MAX1247—external reference, VREF = 2.500 V

applied to VREF pin; T = T

to T

; unless otherwise noted.)

A

MIN

MAX

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

DIGITAL INPUTS (DIN, SCLK, CS, SHDN)

V

≤ 3.6V

2.0

3.0

DD

V

IH

V

DIN, SCLK, CS Input High Voltage

V

DD

> 3.6V, MAX1247 only

V

0.8

V

DIN, SCLK, CS Input Low Voltage

DIN, SCLK, CS Input Hysteresis

DIN, SCLK, CS Input Leakage

DIN, SCLK, CS Input Capacitance

SHDN Input High Voltage

SHDN Input Mid Voltage

IL

V

HYST

0.2

I

IN

V

= 0V or V

±0.01

±1

15

µA

pF

V

IN DD

C

(Note 7)

IN

V

SH

V

- 0.4

DD

V

SM

1.1

V

DD

- 1.1

0.4

V

SL

V

SHDN Input Low Voltage

6/MAX1247

I

SHDN = 0V or V

±4.0

µA

V

SHDN Input Current

S

DD

V

FLT

SHDN = FLOAT

V

DD

/ 2

SHDN Voltage, Floating

SHDN Maximum Allowed

Leakage, Mid Input

SHDN = FLOAT

±100

nA

DIGITAL OUTPUTS (DOUT, SSTRB)

I

= 5mA

0.4

0.8

SINK

Output Voltage Low

V

OL

V

I

= 16mA

SINK

Output Voltage High

V

OH

I

= 0.5mA

V - 0.5

DD

V

SOURCE

Three-State Leakage Current

Three-State Output Capacitance

POWER REQUIREMENTS

I

±0.01

±10

15

µA

pF

CS = V

L

DD

C

CS = V (Note 7)

OUT

DD

MAX1246

MAX1247

2.70

3.60

5.25

2.0

70

Positive Supply Voltage

V

DD

Operating mode, full-scale input

= 3.6V Fast power-down

1.2

30

mA

µA

Positive Supply Current, MAX1246

I

DD

V

DD

Full power-down

1.2

1.8

0.9

30

10

V

DD

= 5.25V

= 3.6V

2.5

1.5

70

Operating mode,

full-scale input

mA

µA

V

DD

Positive Supply Current, MAX1247

Supply Rejection (Note 10)

I

DD

Fast power-down

Full power-down

V

DD

= 5.25V

= 3.6V

3.5

1.2

15

V

DD

10

V

DD

= 2.7V to V

, full-scale input,

DD(MAX)

PSR

±0.3

mV

external reference = 2.500V

4

_______________________________________________________________________________________

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

6/MAX1247

TIMING CHARACTERISTICS

(V = +2.7V to +3.6V (MAX1246); V = +2.7V to +5.25V (MAX1247); T = T

to T

; unless otherwise noted.)

DD

A

MIN

MAX

PARAMETER

SYMBOL

CONDITIONS

MIN

1.5

TYP

MAX UNITS

Acquisition Time

DIN to SCLK Setup

DIN to SCLK Hold

t

µs

ns

ACQ

t

DS

100

t

0

ns

DH

MAX124_ _C/E

MFigAuXr1e214_ _M

20

200

240

SCLK Fall to Output Data Valid

t

Figure 1

ns

DO

t

Figure 1

Figure 2

ns

CS Fall to Output Enable

CS Rise to Output Disable

CS to SCLK Rise Setup

CS to SCLK Rise Hold

DV

t

TR

t

100

0

CSS

CSH

t

SCLK Pulse Width High

SCLK Pulse Width Low

t

200

CH

t

CL

SCLK Fall to SSTRB

t

Figure 1

240

SSTRB

t

External clock mode only, Figure 1

External clock mode only, Figure 2

Internal clock mode only (Note 7)

CS Fall to SSTRB Output Enable

CS Rise to SSTRB Output Disable

SSTRB Rise to SCLK Rise

SDV

t

STR

t

0

SCK

Note 1: Tested at V = 2.7V; COM = 0V; unipolar single-ended input mode.

DD

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated.

Note 3: MAX1246—internal reference, offset nulled; MAX1247—external reference (VREF = +2.500V), offset nulled.

Note 4: Ground “on” channel; sine wave applied to all “off” channels.

Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.

Note 6: The common-mode range for the analog inputs is from AGND to V

.

DD

Note 7: Guaranteed by design. Not subject to production testing.

Note 8: External load should not change during conversion for specified accuracy.

Note 9: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.

Note 10: Measured as V (2.7V) - V (V

) .

|

FS

|

DD, MAX

__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s

(V = 3.0V, VREF = 2.500V, f

= 2.0MHz, C

= 20pF, T = +25°C, unless otherwise noted.)

A

DD

SCLK

LOAD

INTEGRAL NONLINEARITY

vs. TEMPERATURE

INTEGRAL NONLINEARITY

vs. CODE

INTEGRAL NONLINEARITY

vs. SUPPLY VOLTAGE

0.50

0.5

0.4

0.3

0.50

0.45

0.40

0.35

0.30

0.25

0.20

V

DD

= 2.7V

0.45

0.40

0.35

0.30

0.25

0.20

0.15

MAX1246

MAX1247

0.2

0.1

MAX1246

0

-0.1

MAX1247

-0.2

-0.3

0.15

0.10

0.05

0.00

-0.4

-0.5

0.05

0.00

-60

-20

20

60

100

140

0

1024

2048

3072

4096

2.25 2.75 3.25 3.75 4.25 4.75 5.25

TEMPERATURE (°C)

CODE

V

DD

(V)

_______________________________________________________________________________________

5

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )

(V = 3.0V, VREF = 2.500V, f

= 2.0MHz, C

= 20pF, T = +25°C, unless otherwise noted.)

A

DD

SCLK

LOAD

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

SHUTDOWN SUPPLY CURRENT

vs. SUPPLY VOLTAGE

INTERNAL REFERENCE VOLTAGE

vs. SUPPLY VOLTAGE

2.00

1.75

1.50

1.25

1.00

0.75

0.50

4.0

3.5

3.0

2.5

2.0

2.5020

R = ∞

CODE = 101010100000

L

FULL POWER-DOWN

C

= 50pF

LOAD

2.5015

2.5010

2.5005

2.5000

2.4995

2.4990

MAX1246

1.5

1.0

0.5

0

C

= 20pF

LOAD

MAX1247

2.25 2.75 3.25 3.75 4.25 4.75 5.25

6/MAX1247

SUPPLY VOLTAGE (V)

V

DD

(V)

V

DD

(V)

MAX1246

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

SHUTDOWN CURRENT

vs. TEMPERATURE

SUPPLY CURRENT vs. TEMPERATURE

2.501

2.0

1.3

2.500

2.499

V

DD

= 3.6V

MAX1246

1.6

1.2

0.8

0.4

1.2

1.1

1.0

V

= 2.7V

DD

2.498

2.497

2.496

MAX1247

= ∞

0.9

0.8

2.495

2.494

R

LOAD

CODE = 101010100000

-60 -20 20

TEMPERATURE (°C)

0

-60

-20

20

60

100

140

60

100

140

-60

-20

20

60

100

140

TEMPERATURE (°C)

EFFECTIVE NUMBER OF BITS

vs. FREQUENCY

FFT PLOT

20

12.0

11.8

11.6

11.4

11.2

11.0

V

= 2.7V

= 10k

DD

V

DD

= 2.7V

f

IN

0

f

= 133k

SAMPLE

-20

-40

-60

-80

-100

-120

0

10

20 30

40

50

60

70

1

10

100

FREQUENCY (kHz)

6

_______________________________________________________________________________________

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

6/MAX1247

____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )

(V = 3.0V, VREF = 2.500V, f

= 2.0MHz, C

= 20pF, T = +25°C, unless otherwise noted.)

LOAD A

DD

SCLK

GAIN ERROR

vs. SUPPLY VOLTAGE

CHANNEL-TO-CHANNEL GAIN MATCHING

vs. SUPPLY VOLTAGE

OFFSET vs. SUPPLY VOLTAGE

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

2.75 3.25 3.75 4.25 4.75 5.25

2.25

2.25 2.75 3.25 3.75 4.25 4.75 5.25

2.25

2.75 3.25 3.75 4.25 4.75 5.25

V

DD

(V)

V

DD

(V)

V

DD

(V)

GAIN ERROR

vs. TEMPERATURE

CHANNEL-TO-CHANNEL GAIN MATCHING

vs. TEMPERATURE

OFFSET vs. TEMPERATURE

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

-55

-30

-55 -30 -5

20 45

TEMPERATURE (˚C)

-5 20 45 70 95 120 145

TEMPERATURE (˚C)

-5 20 45 70 95 120 145

TEMPERATURE (˚C)

70 95 120 145

-55 -30

CHANNEL-TO-CHANNEL OFFSET MATCHING

vs. TEMPERATURE

CHANNEL-TO-CHANNEL OFFSET MATCHING

vs. SUPPLY VOLTAGE

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

-30 -5

-55

20 45 70 95 120 145

TEMPERATURE (˚C)

2.25 2.75 3.25 3.75 4.25 4.75 5.25

V

(V)

DD

_______________________________________________________________________________________

7

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

______________________________________________________________P in De s c rip t io n

1

NAME

FUNCTION

V

DD

Positive Supply Voltage

Sampling Analog Inputs

2–5

CH0–CH3

COM

Ground reference for analog inputs. COM sets zero-code voltage in single-ended mode. Must be

stable to ±0.5LSB.

6

7

Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1246/MAX1247 down; otherwise, they

are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation

mode. Letting SHDN float puts the reference-buffer amplifier in external compensation mode.

SHDN

Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.

In internal reference mode (MAX1246 only), the reference buffer provides a 2.500V nominal output,

externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling

8

VREF

REFADJ to V

.

DD

9

REFADJ

AGND

DGND

DOUT

Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to V

.

DD

6/MAX1247

10

11

12

Analog Ground

Digital Ground

Serial Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.

Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1246/MAX1247 begin the

A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB pulses

high for one clock period before the MSB decision. High impedance when CS is high (external clock

mode).

13

SSTRB

14

15

DIN

Serial Data Input. Data is clocked in at SCLK’s rising edge.

Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is

high impedance.

CS

Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets

the conversion speed. (Duty cycle must be 40% to 60%.)

16

SCLK

V

DD

V

DD

6k

DOUT

C

50pF

C

LOAD

50pF

C

50pF

C

50pF

LOAD

6k

DGND

a) High-Z to V and V to V

OH

b) High-Z to V and V to V

OL

OH

OL

OH

a) V to High-Z

OH

b) V to High-Z

OL

Figure 1. Load Circuits for Enable Time

Figure 2. Load Circuits for Disable Time

8

_______________________________________________________________________________________

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

6/MAX1247

input control word has been entered. At the end of the

_______________De t a ile d De s c rip t io n

acquisition interval, the T/H switch opens, retaining

charge on C as a sample of the signal at IN+.

The MAX1246/MAX1247 analog-to-digital converters

(ADCs) use a successive-approximation conversion

technique and input track/hold (T/H) circuitry to convert

an analog signal to a 12-bit digital output. A flexible seri-

al interface provides easy interface to microprocessors

(µPs). Figure 3 is a block diagram of the MAX1246/

MAX1247.

HOLD

The conversion interval begins with the input multiplexer

switching C from the positive input (IN+) to the

HOLD

negative input (IN-). In single-ended mode, IN- is simply

COM. This unbalances node ZERO at the comparator’s

input. The capacitive DAC adjusts during the remainder

of the conversion cycle to restore node ZERO to 0V

within the limits of 12-bit resolution. This action is equiv-

P s e u d o -Diffe re n t ia l In p u t

The sampling architecture of the ADC’s analog com-

p a ra tor is illus tra te d in the e q uiva le nt inp ut c irc uit

(Fig ure 4). In s ing le -e nd e d mod e , IN+ is inte rna lly

switched to CH0–CH3, and IN- is switched to COM. In

differential mode, IN+ and IN- are selected from two

pairs: CH0/CH1 and CH2/CH3. Configure the channels

with Tables 2 and 3. Please note that the codes for

CH0–CH3 in the MAX1246/MAX1247 correspond to the

codes for CH2–CH5 in the eight-channel (MAX146/

MAX147) versions.

alent to transferring a 16pF x [(V_IN+) - (V -)] charge

IN

from C

to the binary-weighted capacitive DAC,

HOLD

which in turn forms a digital representation of the analog

input signal.

Tra c k /Ho ld

The T/H enters its tracking mode on the falling clock

edge after the fifth bit of the 8-bit control word has been

shifted in. It enters its hold mode on the falling clock

edge after the eighth bit of the control word has been

shifted in. If the converter is set up for single-ended

inputs, IN- is connected to COM, and the converter

samples the “+” input. If the converter is set up for dif-

ferential inputs, IN- connects to the “-” input, and the

difference of |IN+ - IN-| is sampled. At the end of the

conversion, the positive input connects back to IN+,

In differential mode, IN- and IN+ are internally switched

to e ithe r of the a na log inp uts . This c onfig ura tion is

pseudo-differential to the effect that only the signal at IN+

is sampled. The return side (IN-) must remain stable within

±0.5LSB (±0.1LSB for best results) with respect to AGND

during a conversion. To accomplish this, connect a 0.1µF

capacitor from IN- (the selected analog input) to AGND.

and C

charges to the input signal.

HOLD

The time required for the T/H to acquire an input signal

is a function of how quickly its input capacitance is

charged. If the input signal’s source impedance is high,

the acquisition time lengthens, and more time must be

During the acquisition interval, the channel selected

as the positive input (IN+) charges capacitor C

.

HOLD

The acquisition interval spans three SCLK cycles and

ends on the falling SCLK edge after the last bit of the

15

CS

16

SCLK

12-BIT CAPACITIVE DAC

VREF

INPUT

SHIFT

REGISTER

INT

CLOCK

14

7

DIN

CONTROL

LOGIC

COMPARATOR

INPUT

C

SHDN

HOLD

MUX

ZERO

–

+

CH0

CH1

CH2

CH3

COM

2

3

4

5

6

12

13

CH0

CH1

CH2

OUTPUT

SHIFT

DOUT

16pF

REGISTER

SSTRB

R

9k

IN

ANALOG

INPUT

MUX

T/H

C

SWITCH

CLOCK

HOLD

IN

12-BIT

SAR

ADC

TRACK

CH3

AT THE SAMPLING INSTANT,

THE MUX INPUT SWITCHES

FROM THE SELECTED IN+

CHANNEL TO THE SELECTED

IN- CHANNEL.

OUT

1

T/H

SWITCH

REF

V

DD

COM

11

A ≈ 2.06*

+1.21V

DGND

AGND

20k

REFERENCE

(MAX1246)

10

9

8

REFADJ

VREF

SINGLE-ENDED MODE: IN+ = CH0–CH3, IN- = COM.

DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF

CH0/CH1 AND CH2/CH3.

MAX1246

MAX1247

+2.500V

*A ≈ 2.00 (MAX1247)

Figure 4. Equivalent Input Circuit

Figure 3. Block Diagram

_______________________________________________________________________________________

9

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

Table 1. Control-Byte Format

BIT 7

(MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

(LSB)

START

SEL2

SEL1

SEL0

UNI/BIP

SGL/DIF

PD1

PD0

BIT

NAME

DESCRIPTION

7(MSB)

START

The first logic “1” bit after CS goes low defines the beginning of the control byte.

6

5

4

SEL2

SEL1

SEL0

These three bits select which of the four channels are used for the conversion (Tables 2 and 3).

3

UNI/BIP

1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an

analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range

from -VREF / 2 to +VREF / 2.

2

SGL/DIF

1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-

ended mode, input signal voltages are referred to COM. In differential mode, the voltage

difference between two channels is measured (Tables 2 and 3).

6/MAX1247

1

PD1

PD0

Selects clock and power-down modes.

0(LSB)

PD1

PD0

Mode

0

1

0

1

0

1

Full power-down

Fast power-down

Internal clock mode

External clock mode

allowed between conversions. The acquisition time,

, is the maximum time the device takes to acquire

An a lo g In p u t P ro t e c t io n

Internal protection diodes, which clamp the analog input

t

ACQ

the signal, and is also the minimum time needed for the

signal to be acquired. It is calculated by the following

equation:

to V and AGND, allow the channel input pins to swing

DD

from AGND - 0.3V to V

+ 0.3V without d a ma g e .

DD

However, for accurate conversions near full scale, the

inputs must not exceed V by more than 50mV or be

lower than AGND by 50mV.

DD

t

= 9 x (R + R ) x 16pF

S IN

ACQ

where R = 9kΩ, R = the source impedance of the

input signal, and t

that source impedances below 1kΩ do not significantly

affect the ADC’s AC performance.

IN

S

If the analog input exceeds 50mV beyond the sup-

plies, do not forward bias the protection diodes of

off channels over 4mA.

is never less than 1.5µs. Note

ACQ

Higher source impedances can be used if a 0.01µF

capacitor is connected to the individual analog inputs.

Note that the input capacitor forms an RC filter with the

inp ut s ourc e imp e d a nc e , limiting the ADC’s s ig na l

bandwidth.

Ho w t o S t a rt a Co n ve rs io n

Start a conversion by clocking a control byte into DIN.

With CS low, each rising edge on SCLK clocks a bit from

DIN into the MAX1246/MAX1247’s internal shift register.

After CS falls, the first arriving logic “1” bit defines the

control byte’s MSB. Until this first “start” bit arrives, any

number of logic “0” bits can be clocked into DIN with no

effect. Table 1 shows the control-byte format.

In p u t Ba n d w id t h

The ADC’s inp ut tra c king c irc uitry ha s a 2.25MHz

small-signal bandwidth, so it is possible to digitize

high-speed transient events and measure periodic sig-

nals with bandwidths exceeding the ADC’s sampling

ra te b y us ing und e rs a mp ling te c hniq ue s . To a void

high-frequency signals being aliased into the frequency

band of interest, anti-alias filtering is recommended.

The MAX1246/MAX1247 are compatible with SPI™/

QSPI™ and Microwire™ devices. For SPI, select the

correct clock polarity and sampling edge in the SPI

control registers: set CPOL = 0 and CPHA = 0. Micro-

wire, SPI, and QSPI all transmit a byte and receive a

byte at the same time. Using the Typical Operating

10 ______________________________________________________________________________________

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

6/MAX1247

DIF

Table 2. Channel Selection in Single-Ended Mode (SGL/

= 1)

SEL2

0

SEL1

0

SEL0

1

CH0

CH1

CH2

CH3

COM

+

–

1

0

1

0

1

0

+

–

+

DIF

Table 3. Channel Selection in Differential Mode (SGL/

= 0)

SEL2

SEL1

SEL0

CH0

CH1

CH2

CH3

0

1

0

1

0

1

0

1

0

+

–

+

–

+

Circuit, the simplest software interface requires only

Digital Output

three 8-bit transfers to perform a conversion (one 8-bit

transfer to configure the ADC, and two more 8-bit trans-

fers to clock out the 12-bit conversion result). See Figure

19 for MAX1246/MAX1247 QSPI connections.

In unipolar input mode, the output is straight binary

(Figure 16). For bipolar inputs, the output is two’s com-

plement (Figure 17). Data is clocked out at the falling

edge of SCLK in MSB-first format.

Simple Software Interface

Make sure the CPU’s serial interface runs in master

mode so the CPU generates the serial clock. Choose a

clock frequency from 100kHz to 2MHz.

Clo c k Mo d e s

The MAX1246/MAX1247 may use either an external

serial clock or the internal clock to perform the succes-

sive-approximation conversion. In both clock modes,

the e xte rna l c loc k s hifts d a ta in a nd out of the

MAX1246/MAX1247. The T/H acquires the input signal

as the last three bits of the control byte are clocked into

DIN. Bits PD1 and PD0 of the control byte program the

clock mode. Figures 6–9 show the timing characteristics

common to both modes.

1) Set up the control byte for external clock mode and

call it TB1. TB1 should be of the format: 1XXXXX11

binary, where the Xs denote the particular channel

and conversion mode selected.

2) Use a general-purpose I/O line on the CPU to pull

CS low.

External Clock

In external clock mode, the external clock not only shifts

data in and out, but it also drives the analog-to-digital

conversion steps. SSTRB pulses high for one clock

period after the last bit of the control byte. Succes-

sive-approximation bit decisions are made and appear

at DOUT on each of the next 12 SCLK falling edges

(Figure 5). SSTRB and DOUT go into a high-impedance

state when CS goes high; after the next CS falling edge,

SSTRB outputs a logic low. Figure 7 shows the SSTRB

timing in external clock mode.

3) Transmit TB1 and, simultaneously, receive a byte

and call it RB1. Ignore RB1.

4) Transmit a byte of all zeros ($00 hex) and, simulta-

neously, receive byte RB2.

5) Transmit a byte of all zeros ($00 hex) and, simulta-

neously, receive byte RB3.

6) Pull CS high.

Figure 5 shows the timing for this sequence. Bytes RB2

and RB3 contain the result of the conversion, padded

with one leading zero and three trailing zeros. The total

conversion time is a function of the serial-clock fre-

q ue nc y a nd the a mount of id le time b e twe e n 8-b it

transfers. To avoid excessive T/H droop, make sure the

total conversion time does not exceed 120µs.

The conversion must complete in some minimum time,

or d roop on the s a mp le -a nd -hold c a p a c itors ma y

degrade conversion results. Use internal clock mode if

the serial clock frequency is less than 100kHz, or if

serial clock interruptions could cause the conversion

interval to exceed 120µs.

______________________________________________________________________________________ 11

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

CS

t

ACQ

SCLK

1

4

8

12

16

20

24

UNI/

BIP

SGL/

DIF

SEL2 SEL1 SEL0

PD1 PD0

DIN

SSTRB

DOUT

START

RB2

B8

RB3

B0

LSB

RB1

FILLED WITH

ZEROS

B11

MSB

B10 B9

B7

B6

B5

B4

B3

B2

B1

ACQUISITION

1.5µs

CONVERSION

A/D STATE

IDLE

(f

SCLK

= 2MHz)

Figure 5. 24-Clock External Clock Mode Conversion Timing (Microwire and SPI Compatible, QSPI Compatible with f

≤ 2MHz)

SCLK

6/MAX1247

• • •

CS

t

CH

t

CSH

CSS

t

CL

CSH

SCLK

• • •

t

DS

t

DH

DIN

• • •

t

DV

t

DO

t

TR

DOUT

• • •

Figure 6. Detailed Serial-Interface Timing

Internal Clock

An internal register stores data when the conversion is

in progress. SCLK clocks the data out of this register at

any time after the conversion is complete. After SSTRB

goes high, the next falling clock edge produces the

MSB of the c onve rs ion a t DOUT, followe d b y the

remaining bits in MSB-first format (Figure 8). CS does

not need to be held low once a conversion is started.

Pulling CS high prevents data from being clocked into

the MAX1246/MAX1247 and three-states DOUT, but it

d oe s not a d ve rs e ly a ffe c t a n inte rna l c loc k mod e

In internal clock mode, the MAX1246/MAX1247 generate

their own conversion clocks internally. This frees the µP

from the burden of running the SAR conversion clock

and allows the conversion results to be read back at the

processor’s convenience, at any clock rate from 0MHz

to 2MHz. SSTRB goes low at the start of the conversion

and then goes high when the conversion is complete.

SSTRB is low for a maximum of 7.5µs (SHDN = FLOAT),

during which time SCLK should remain low for best

noise performance.

12 ______________________________________________________________________________________

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

6/MAX1247

CS

• • •

t

STR

SDV

SSTRB

• • •

t

SSTRB

SCLK

• • • •

PD0 CLOCKED IN

Figure 7. External Clock Mode SSTRB Detailed Timing

CS

SCLK

DIN

1

4

8

18

24

2

3

5

6

7

9

10

11

12

19

20

21

22

23

UNI/ SGL/

BIP DIF

SEL2 SEL1 SEL0

PD1 PD0

START

SSTRB

t

CONV

FILLED WITH

ZEROS

B11

MSB

B0

LSB

DOUT

B10 B9

B2

B1

ACQUISITION

CONVERSION

A/D STATE

1.5µs

IDLE

7.5µs MAX

(f

SCLK

= 2MHz) (SHDN = FLOAT)

Figure 8. Internal Clock Mode Timing

conversion already in progress. When internal clock

mod e is se le c te d, SSTRB d oe s not go into a high-

impedance state when CS goes high.

conversion starts on SCLK’s falling edge, after the eighth

bit of the control byte (the PD0 bit) is clocked into DIN.

The start bit is defined as follows:

Fig ure 9 s hows the SSTRB timing in inte rna l c loc k

mode. In this mode, data can be shifted in and out of

the MAX1246/MAX1247 a t c loc k ra te s e xc e e d ing

The first high bit clocked into DIN with CS low any

time the converter is idle; e.g., after V is applied.

DD

OR

2.0MHz if the minimum acquisition time (t

above 1.5µs.

) is kept

ACQ

The first high bit clocked into DIN after bit 5 of a con-

version in progress is clocked onto the DOUT pin.

Da t a Fra m in g

The falling edge of CS does not start a conversion.

The first logic high clocked into DIN is interpreted as a

start bit and defines the first bit of the control byte. A

If CS is toggled before the current conversion is com-

plete, the next high bit clocked into DIN is recognized as

a start bit; the current conversion is terminated, and a

new one is started.

______________________________________________________________________________________ 13

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

Most microcontrollers (µCs) require that conversions

The fastest the MAX1246/MAX1247 can run with CS held

low between conversions is 15 clocks per conversion.

Figure 10a shows the serial-interface timing necessary to

perform a conversion every 15 SCLK cycles in external

clock mode. If CS is tied low and SCLK is continuous,

guarantee a start bit by first clocking in 16 zeros.

occur in multiples of 8 SCLK clocks; 16 clocks per con-

version is typically the fastest that a µC can drive the

MAX1246/MAX1247. Fig ure 10b s hows the s e ria l-

interface timing necessary to perform a conversion every

16 SCLK cycles in external clock mode.

CS

t

CONV

t

CSS

t

SCK

CSH

SSTRB

SCLK

t

SSTRB

6/MAX1247

t

DO

PD0 CLOCK IN

DOUT

NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.

Figure 9. Internal Clock Mode SSTRB Detailed Timing

CS

1

8

15

1

8

15 1

SCLK

DIN

S

CONTROL BYTE 2

S

CONTROL BYTE 0

S

CONTROL BYTE 1

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

CONVERSION RESULT 0

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

CONVERSION RESULT 1

DOUT

SSTRB

Figure 10a. External Clock Mode, 15 Clocks/Conversion Timing

• • •

CS

1

8

16

1

8

16

SCLK

DIN

S

CONTROL BYTE 0

S

CONTROL BYTE 1

DOUT

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

CONVERSION RESULT 0

B11 B10 B9 B8

CONVERSION RESULT 1

Figure 10b. External Clock Mode, 16 Clocks/Conversion Timing

14 ______________________________________________________________________________________

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

6/MAX1247

(Tables 1 and 5). In both software power-down modes,

__________ Ap p lic a t io n s In fo rm a t io n

the serial interface remains operational, but the ADC

does not convert. Pull SHDN low at any time to shut

down the converter completely. SHDN overrides bits 1

and 0 of the control byte.

P o w e r-On Re s e t

When power is first applied, and if SHDN is not pulled

low, inte rna l p owe r-on re s e t c irc uitry a c tiva te s the

MAX1246/MAX1247 in internal clock mode, ready to

convert with SSTRB = high. After the power supplies

stabilize, the internal reset time is 10µs, and no conver-

sions should be performed during this phase. SSTRB is

high on power-up and, if CS is low, the first logical 1 on

DIN is interpreted as a start bit. Until a conversion takes

place, DOUT shifts out zeros. (Also see Table 4.)

Full power-down mode turns off all chip functions that

draw quiescent current, reducing supply current to 2µA

(typ ). Fa s t p owe r-d own mod e turns off a ll c irc uitry

except the bandgap reference. With fast power-down

mode, the supply current is 30µA. Power-up time can be

shortened to 5µs in internal compensation mode.

Table 4 shows how the choice of reference-buffer com-

pensation and power-down mode affects both power-up

delay and maximum sample rate. In external compensa-

tion mode, power-up time is 20ms with a 4.7µF compen-

sation capacitor when the capacitor is initially fully

discharged. From fast power-down, start-up time can be

eliminated by using low-leakage capacitors that do not

discharge more than 1/2LSB while shut down. In power-

down, leakage currents at VREF cause droop on the ref-

erence bypass capacitor. Figures 11a and 11b show

the various power-down sequences in both external and

internal clock modes.

Re fe re n c e -Bu ffe r Co m p e n s a t io n

In addition to its shutdown function, SHDN selects inter-

na l or e xte rna l c omp e ns a tion. The c omp e ns a tion

affects both power-up time and maximum conversion

speed. The100kHz minimum clock rate is limited by

droop on the sample-and-hold and is independent of

the compensation used.

Floa t SHDN to s e le c t e xte rna l c omp e ns a tion. The

Typical Operating Circuit uses a 4.7µF capacitor at

VREF. A 4.7µF value ensures reference-buffer stability

and allows converter operation at the 2MHz full clock

spe e d . Exte rna l c ompe nsa tion inc re a se s powe r-up

time (see the Choosing Power-Down Mode section and

Table 4).

Software Power-Down

Software power-down is activated using bits PD1 and PD0

of the control byte. As shown in Table 5, PD1 and PD0

also specify the clock mode. When software shutdown is

asserted, the ADC operates in the last specified clock

mode until the conversion is complete. Then the ADC

powers down into a low quiescent-current state. In internal

clock mode, the interface remains active and conversion

results may be clocked out after the MAX1246/MAX1247

enter a software power-down.

Pull SHDN hig h to s e le c t inte rna l c omp e ns a tion.

Internal compensation requires no external capacitor at

VREF and allows for the shortest power-up times. The

maximum clock rate is 2MHz in internal clock mode

and 400kHz in external clock mode.

Ch o o s in g P o w e r-Do w n Mo d e

You can save power by placing the converter in a low-

current shutdown state between conversions. Select full

power-down mode or fast power-down mode via bits 1

and 0 of the DIN control byte with SHDN high or floating

The first logical 1 on DIN is interpreted as a start bit

a nd p owe rs up the MAX1246/MAX1247. Following

the start bit, the data input word or control byte also

Table 4. Typical Power-Up Delay Times

REFERENCE-

VREF

POWER-UP

DELAY

(µs)

MAXIMUM

SAMPLING RATE

(ksps)

REFERENCE

BUFFER

COMPENSATION

MODE

POWER-DOWN

MODE

CAPACITOR

(µF)

Enabled

Disabled

Internal

External

Fast

Full

Fast

Full

Fast

Full

5

26

300

26

4.7

See Figure 13c

133

See Figure 13c

2

______________________________________________________________________________________ 15

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

CLOCK

MODE

EXTERNAL

SHDN

SETS SOFTWARE

POWER-DOWN

SETS EXTERNAL

CLOCK MODE

SETS EXTERNAL

CLOCK MODE

DIN

S X X X X X 1 1

S X X X X X 0 0

S X X X X X 1 1

DOUT

VALID

DATA

INVALID

DATA

12 DATA BITS

POWERED UP

12 DATA BITS

HARDWARE

POWER-

DOWN

POWERED UP

MODE

SOFTWARE

POWERED UP

POWER-DOWN

6/MAX1247

Figure 11a. Timing Diagram Power-Down Modes, External Clock

CLOCK

MODE

INTERNAL

SETS

POWER-DOWN

SETS INTERNAL

CLOCK MODE

DIN

S X X X X X 1 0

S X X X X X 0 0

S

DOUT

DATA VALID

SSTRB

MODE

CONVERSION

POWER-DOWN

POWERED UP

Figure 11b. Timing Diagram Power-Down Modes, Internal Clock

determines clock mode and power-down states. For

example, if the DIN word contains PD1 = 1, then the

c hip re ma ins p owe re d up . If PD0 = PD1 = 0, a

power-down resumes after one conversion.

controls the clock frequency in internal clock mode.

Letting SHDN float sets the internal clock frequency to

1.8MHz. When returning to normal operation with SHDN

floating, there is a t delay of approximately 2MΩ x C ,

RC

L

where C is the capacitive loading on the SHDN pin.

L

Hardware Power-Down

Pulling SHDN low places the converter in hardware

power-down (Table 6). Unlike software power-down

mode, the conversion is not completed; it stops coin-

cidentally with SHDN being brought low. SHDN also

Pulling SHDN high sets internal clock frequency to

225kHz. This feature eases the settling-time requirement

for the reference voltage. With an external reference, the

MAX1246/MAX1247 can be considered fully powered up

within 2µs of actively pulling SHDN high.

16 ______________________________________________________________________________________

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

6/MAX1247

Figure 13a depicts the MAX1246 power consumption

for one or four channel conversions utilizing full power-

down mode and internal-reference compensation. A

0.047µF bypass capacitor at REFADJ forms an RC filter

with the internal 20kΩ reference resistor with a 0.9ms

time constant. To achieve full 12-bit accuracy, 10 time

constants or 9ms are required after power-up. Waiting

this 9ms in FASTPD mode instead of in full power-up

can reduce power consumption by a factor of 10 or

more. This is achieved by using the sequence shown in

Figure 14.

P o w e r-Do w n S e q u e n c in g

The MAX1246/MAX1247 auto power-down modes can

save considerable power when operating at less than

maximum sample rates. Figures 12, 13a, and 13b show

the average supply current as a function of the sam-

pling rate. The following discussion illustrates the vari-

ous power-down sequences.

Lowest Power at up to 500

Conversions/Channel/Second

The following examples show two different power-down

sequences. Other combinations of clock rates, compen-

sation modes, and power-down modes may give lowest

power consumption in other applications.

AVERAGE SUPPLY CURRENT

vs. CONVERSION RATE

WITH EXTERNAL REFERENCE

10,000

AVERAGE SUPPLY CURRENT

vs. CONVERSION RATE

(USING FULLPD)

100

VREF = V = 3.0V

DD

R

= ∞

LOAD

R

LOAD

= ∞

CODE = 101010100000

1000

100

10

4 CHANNELS

10

1 CHANNEL

1

0.1

1

0.01

0.1

1

10 100 1k 10k 100k 1M

CONVERSION RATE (Hz)

0.1

1

10

100

1k

CONVERSION RATE (Hz)

Figure 12. Average Supply Current vs. Conversion Rate with

External Reference

Figure 13a. MAX1246 Supply Current vs. Conversion Rate,

FULLPD

AVERAGE SUPPLY CURRENT

vs. CONVERSION RATE

(USING FASTPD)

TYPICAL REFERENCE-BUFFER POWER-UP

DELAY vs. TIME IN SHUTDOWN

10,000

2.0

R

LOAD

= ∞

CODE = 101010100000

1000

100

1.5

1.0

4 CHANNELS

1 CHANNEL

10

1

0.5

0.0

0.1

1

10 100 1k 10k 100k 1M

CONVERSION RATE (Hz)

0.001

0.01

0.1

1

10

TIME IN SHUTDOWN (sec)

Figure 13b. MAX1246 Supply Current vs. Conversion Rate,

FASTPD

Figure 13c. Typical Reference-Buffer Power-Up Delay vs. Time

in Shutdown

______________________________________________________________________________________ 17

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

COMPLETE CONVERSION SEQUENCE

9ms WAIT

(ZEROS)

CH1

CH7

(ZEROS)

DIN

1

0 0

FULLPD

1.21V

1

0 1

FASTPD

1

1 1

1

0 0

FULLPD

1

0 1

FASTPD

NOPD

REFADJ

VREF

0V

2.50V

0V

τ = RC = 20kΩ x C

REFADJ

t

≈ 200µs

BUFFEN

Figure 14. MAX1246 FULLPD/FASTPD Power-Up Sequence

Lowest Power at Higher Throughputs

Fig ure 13b s hows the p owe r c ons ump tion with

external-reference compensation in fast power-down,

with one and four channels converted. The external

4.7µF c omp e ns a tion re q uire s a 200µs wa it a fte r

p owe r-up with one d ummy c onve rs ion. This c irc uit

combines fast multi-channel conversion with the lowest

power consumption possible. Full power-down mode

may provide increased power savings in applications

where the MAX1246/MAX1247 are inactive for long

p e riod s of time , b ut whe re inte rmitte nt b urs ts of

high-speed conversions are required.

+3.3V

6/MAX1247

24k

MAX1246

REFADJ

510k

100k

9

0.047µF

Figure 15. MAX1246 Reference-Adjust Circuit

In t e rn a l a n d Ex t e rn a l Re fe re n c e s

The MAX1246 can be used with an internal or external

reference voltage, whereas an external reference is

required for the MAX1247. An external reference can

be connected directly at VREF or at the REFADJ pin.

Table 5. Software Power-Down

and Clock Mode

An inte rna l b uffe r is d e s ig ne d to p rovid e 2.5V a t

VREF for both the MAX1246 and the MAX1247. The

MAX1246’s internally trimmed 1.21V reference is buf-

fered with a 2.06 gain. The MAX1247’s REFADJ pin is

also buffered with a 2.00 gain to scale an external 1.25V

reference at REFADJ to 2.5V at VREF.

PD1

PD0

DEVICE MODE

Full Power-Down

Fast Power-Down

0

1

0

1

Internal Clock

External Clock

Internal Reference (MAX1246)

The MAX1246’s full-scale range with the internal refer-

ence is 2.5V with unipolar inputs and ±1.25V with bipo-

lar inputs. The internal reference voltage is adjustable

to ±1.5% with the circuit in Figure 15.

Table 6. Hard-Wired Power-Down

and Internal Clock Frequency

REFERENCE

BUFFER

COMPENSATION FREQUENCY

INTERNAL

CLOCK

DEVICE

MODE

SHDN

STATE

External Reference

With both the MAX1246 and MAX1247, an external ref-

erence can be placed at either the input (REFADJ) or

the output (VREF) of the internal reference-buffer ampli-

fier. The REFADJ input impedance is typically 20kΩ for

the MAX1246, and higher than 100kΩ for the MAX1247.

1

Floating

0

Enabled

Internal

External

N/A

225kHz

1.8MHz

N/A

Power-Down

18 ______________________________________________________________________________________

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

6/MAX1247

At VREF, the DC input resistance is a minimum of 18kΩ.

During conversion, an external reference at VREF must

deliver up to 350µA DC load current and have 10Ω or

less output impedance. If the reference has a higher

output impedance or is noisy, bypass it close to the

VREF pin with a 4.7µF capacitor.

OUTPUT CODE

FULL-SCALE

TRANSITION

11 . . . 111

11 . . . 110

11 . . . 101

Using the REFADJ input makes buffering the external

reference unnecessary. To use the direct VREF input,

disable the internal buffer by tying REFADJ to V . In

power-down, the input bias current to REFADJ can be

DD

FS = VREF + COM

ZS = COM

a s muc h a s 25µA with REFADJ tie d to V . Pull

DD

REFADJ to AGND to minimize the input bias current in

power-down.

VREF

4096

1LSB =

00 . . . 011

00 . . . 010

Tra n s fe r Fu n c t io n

Table 7 shows the full-scale voltage ranges for unipolar

and bipolar modes.

00 . . . 001

00 . . . 000

The external reference must have a temperature coeffi-

cient of 4ppm/°C or less to achieve accuracy to within

1LSB over the 0°C to +70°C commercial temperature

range.

0

1

2

3

FS

(COM)

FS - 3/2LSB

INPUT VOLTAGE (LSB)

Figure 16. Unipolar Transfer Function, Full Scale (FS) = VREF

+ COM, Zero Scale (ZS) = COM

Figure 16 depicts the nominal, unipolar input/output

(I/O) transfer function, and Figure 17 shows the bipolar

input/output transfer function. Code transitions occur

ha lfwa y b e twe e n s uc c e s s ive -inte g e r LSB va lue s .

Output coding is binary, with 1LSB = 610µV (2.500V /

4096) for unip ola r op e ra tion, a nd 1LSB = 610µV

[(2.500V / 2 - -2.500V / 2) / 4096] for bipolar operation.

s up p ly s hould b e low imp e d a nc e a nd a s s hort a s

possible.

High-frequency noise in the V

power supply may

DD

affect the high-speed comparator in the ADC. Bypass

the s up p ly to the s ta r g round with 0.1µF a nd 1µF

capacitors close to pin 1 of the MAX1246/MAX1247.

Minimize capacitor lead lengths for best supply-noise

rejection. If the power supply is very noisy, a 10Ω resis-

tor can be connected as a lowpass filter (Figure 18).

La yo u t , Gro u n d in g , a n d Byp a s s in g

For b e s t p e rforma nc e , us e p rinte d c irc uit b oa rd s .

Wire-wrap boards are not recommended. Board layout

should ensure that digital and analog signal lines are

separated from each other. Do not run analog and digi-

tal (especially clock) lines parallel to one another, or

digital lines underneath the ADC package.

Hig h -S p e e d Dig it a l In t e rfa c in g w it h QS P I

The MAX1246/MAX1247 can interface with QSPI using

the circuit in Figure 19 (f

= 2.0MHz, CPOL = 0,

SCLK

Figure 18 shows the recommended system ground

connections. Establish a single-point analog ground

(star ground point) at AGND, separate from the logic

ground. Connect all other analog grounds and DGND

to the star ground. No other digital system ground

should be connected to this ground. For lowest-noise

operation, the ground return to the star ground’s power

CPHA = 0). This QSPI circuit can be programmed to do a

conversion on each of the four channels. The result is

stored in memory without taxing the CPU, since QSPI

incorporates its own microsequencer.

The MAX1246/MAX1247 are QSPI compatible up to its

maximum external clock frequency of 2MHz.

Table 7. Full Scale and Zero Scale

UNIPOLAR MODE

BIPOLAR MODE

Positive

Zero

Negative

Full Scale

Zero Scale

COM

Full Scale

Scale

VREF / 2

+ COM

-VREF / 2

+ COM

VREF + COM

COM

______________________________________________________________________________________ 19

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

OUTPUT CODE

VREF

FS

=

+ COM

011 . . . 111

011 . . . 110

2

SUPPLIES

ZS = COM

+3V

GND

-VREF

2

-FS =

000 . . . 010

000 . . . 001

000 . . . 000

VREF

4096

1LSB =

R* = 10Ω

111 . . . 111

111 . . . 110

111 . . . 101

V

DD

AGND

COM DGND

+3V DGND

100 . . . 001

100 . . . 000

DIGITAL

CIRCUITRY

6/MAX1247

MAX1246

MAX1247

COM*

- FS

+FS - 1LSB

*OPTIONAL

INPUT VOLTAGE (LSB)

≤

*COM VREF / 2

Figure 18. Power-Supply Grounding Connection

Figure 17. Bipolar Transfer Function, Full Scale (FS) =

VREF / 2 + COM, Zero Scale (ZS) = COM

4) The MAX1246/MAX1247’s SSTRB output is moni-

tored via the TMS320’s FSR input. A falling edge on

the SSTRB output indicates that the conversion is in

progress and data is ready to be received from the

MAX1246/MAX1247.

TMS 3 2 0 LC3 x In t e rfa c e

Figure 20 shows an application circuit to interface the

MAX1246/MAX1247 to the TMS320 in external clock

mode. The timing diagram for this interface circuit is

shown in Figure 21.

5) The TMS320 reads in one data bit on each of the

next 16 rising edges of SCLK. These data bits rep-

resent the 12-bit conversion result followed by four

trailing bits, which should be ignored.

Use the following steps to initiate a conversion in the

MAX1246/MAX1247 and to read the results:

1) The TMS320 s hould b e c onfig ure d with CLKX

(transmit clock) as an active-high output clock and

CLKR (TMS320 receive clock) as an active-high

input clock. CLKX and CLKR on the TMS320 are

tied together with the MAX1246/MAX1247’s SCLK

input.

6) Pull CS high to disable the MAX1246/MAX1247 until

the next conversion is initiated.

2) The MAX1246/MAX1247’s CS pin is driven low by

the TMS320’s XF_ I/O port to enable data to be

clocked into the MAX1246/MAX1247’s DIN.

3) An 8-bit word (1XXXXX11) should be written to the

MAX1246/MAX1247 to initiate a conversion and

place the device into external clock mode. Refer to

Table 1 to select the proper XXXXX bit values for

your specific application.

20 ______________________________________________________________________________________

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

6/MAX1247

+3V

(POWER SUPPLIES)

1µF

16

15

14

13

12

11

10

9

SCK

1

2

3

4

5

6

7

8

V

DD

SCLK

CS

0.1µF

PCS0

CH0

MAX1246

MAX1247

CH1

DIN

MOSI

ANALOG

INPUTS

MC683XX

CH2

SSTRB

DOUT

MISO

CH3

COM

SHDN

VREF

DGND

AGND

REFADJ

+2.5V

0.1µF

(GND)

Figure 19. MAX1246/MAX1247 QSPI Connections, External Reference

XF

CLKX

CLKR

DX

CS

SCLK

TMS320LC3x

MAX1246

MAX1247

DIN

DR

DOUT

SSTRB

FSR

Figure 20. MAX1246/MAX1247-to-TMS320 Serial Interface

______________________________________________________________________________________ 21

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

CS

SCLK

DIN

START

SEL2

SEL1

SEL0

UNI/BIP SGL/DIF

PD1

PD0

HIGH

IMPEDANCE

SSTRB

HIGH

IMPEDANCE

DOUT

MSB

B10

B1

LSB

Figure 21. TMS320 Serial-Interface Timing Diagram

_Ord e rin g In fo rm a t io n (c o n t in u e d )

__________________P in Co n fig u ra t io n

INL

(LSB)

PART^†

TEMP. RANGE PIN-PACKAGE

TOP VIEW

6/MAX1247

1

2

3

4

5

6

7

8

16

15

14

13

12

V

SCLK

CS

DD

MAX1246AEPE -40°C to +85°C

MAX1246BEPE -40°C to +85°C

MAX1246AEEE -40°C to +85°C

MAX1246BEEE -40°C to +85°C

16 Plastic DIP

16 QSOP

±1/2

±1

CH0

CH1

DIN

±1/2

±1

CH2

MAX1246

MAX1247

SSTRB

DOUT

16 QSOP

MAX1246AMJE -55°C to +125°C 16 CERDIP*

MAX1246BMJE -55°C to +125°C 16 CERDIP*

±1/2

±1

CH3

COM

SHDN

VREF

11 DGND

MAX1247ACPE 0°C to +70°C

16 Plastic DIP

16 QSOP

±1/2

±1

10

9

AGND

MAX1247BCPE

MAX1247ACEE

MAX1247BCEE

0°C to +70°C

REFADJ

±1/2

±1

16 QSOP

DIP/QSOP

MAX1247AEPE -40°C to +85°C

MAX1247BEPE -40°C to +85°C

MAX1247AEEE -40°C to +85°C

MAX1247BEEE -40°C to +85°C

16 Plastic DIP

16 QSOP

±1/2

±1

±1/2

±1

16 QSOP

___________________Ch ip In fo rm a t io n

MAX1247AMJE -55°C to +125°C 16 CERDIP*

MAX1247BMJE -55°C to +125°C 16 CERDIP*

±1/2

±1

TRANSISTOR COUNT: 2554

†

Contact factory for availability of alternate surface-mount

packages.

* Contact factory for availability of CERDIP package, and for

processing to MIL-STD-883B.

22 ______________________________________________________________________________________

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

6/MAX1247

________________________________________________________P a c k a g e In fo rm a t io n

______________________________________________________________________________________ 23

+2 .7 V, Lo w -P o w e r, 4 -Ch a n n e l,

S e ria l 1 2 -Bit ADCs in QS OP -1 6

___________________________________________P a c k a g e In fo rm a t io n (c o n t in u e d )

6/MAX1247

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

24 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0

Printed USA

is a registered trademark of Maxim Integrated Products.


型号：	MAX1246BEPE
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	+2.7V, Low-Power, 4-Channel, Serial 12-Bit ADCs in QSOP-16 + 2.7V ，低功耗，四通道，串行12位ADC的QSOP -16
文件：	总24页 (文件大小：224K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX1246BEPE [MAXIM]

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