MAX1247_技术文档

19-1071; Rev 2; 10/01

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

General Description

Features

The MAX1246/MAX1247 12-bit data-acquisition systems

combine a 4-channel multiplexer, high-bandwidth

track/hold, and serial interface with high conversion

speed and low power consumption. The MAX1246 oper-

ates from a single +2.7V to +3.6V supply; the MAX1247

operates from a single +2.7V to +5.25V supply. Both

devices’ analog inputs are software configurable for

unipolar/bipolar and single-ended/differential operation.

ꢀ 4-Channel Single-Ended or 2-Channel

Differential Inputs

ꢀ Single-Supply Operation:

+2.7V to +3.6V (MAX1246)

+2.7V to +5.25V (MAX1247)

ꢀ Internal 2.5V Reference (MAX1246)

ꢀ Low Power: 1.2mA (133ksps, 3V supply)

54µA (1ksps, 3V supply)

The 4-wire serial interface connects directly to SPI™/

QSPI™ and MICROWIRE™ devices without external

logic. A serial strobe output allows direct connection to

TMS320-family digital signal processors. The MAX1246/

MAX1247 use either the internal clock or an external seri-

al-interface clock to perform successive-approximation

analog-to-digital conversions.

1µA (power-down mode)

ꢀ SPI/QSPI/MICROWIRE/TMS320-Compatible

4-Wire Serial Interface

ꢀ Software-Configurable Unipolar or Bipolar Inputs

ꢀ 16-Pin QSOP Package (same area as 8-pin SO)

The MAX1246 has an internal 2.5V reference, while the

MAX1247 requires an external reference. Both parts have

a reference-buffer amplifier with a 1.5ꢀ voltage-

adjustment range. These devices provide a hard-wired

SHDN pin and a software-selectable power-down, and

can be programmed to automatically shut down at the

end of a conversion. Accessing the serial interface auto-

matically powers up the MAX1246/MAX1247, and the

quick turn-on time allows them to be shut down between

all conversions. This technique can cut supply current to

under 60µA at reduced sampling rates. The MAX1246/

MAX1247 are available in a 16-pin DIP and a small QSOP

that occupies the same board area as an 8-pin SO.

Ordering Information

INL

(LSB)

PART

TEMP RANGE PIN-PACKAGE

MAX1246ACPE 0°C to +70°C

16 Plastic DIP

16 QSOP

1/2

1

MAX1246BCPE

MAX1246ACEE

MAX1246BCEE

0°C to +70°C

1/2

1

16 QSOP

Ordering Information continued at end of data sheet.

For 8-channel versions of these devices, see the

MAX146/MAX147 data sheet.

________________________Applications

__________Typical Operating Circuit

Portable Data Logging

Medical Instruments

Pen Digitizers

+3V

V

CH0

DD

0.1µF

Data Acquisition

0V TO

+2.5V

DGND

Battery-Powered Instruments

Process Control

ANALOG

INPUTS

MAX1246

CH3

AGND

COM

CPU

I/O

VREF

CS

4.7µF

SCLK

SCK (SK)

MOSI (SO)

MISO (SI)

DIN

Pin Configuration appears at end of data sheet.

DOUT

REFADJ

0.047µF

SSTRB

SHDN

V

SPI and QSPI are registered trademarks of Motorola, Inc.

SS

MICROWIRE is a registered trademark of National

Semiconductor Corp.

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

ABSOLUTE MAXIMUM RATINGS

DD

AGND to DGND...................................................... -0.3V to 0.3V

CH0–CH3, COM to AGND, DGND ............ -0.3V to (V + 0.3V)

V

to AGND, DGND................................................. -0.3V to 6V

QSOP (derate 8.36mW/°C above +70°C)................... 667mW

CERDIP (derate 10.00mW/°C above +70°C).............. 800mW

Operating Temperature Ranges

DD

VREF to AGND........................................... -0.3V to (V + 0.3V)

Digital Inputs to DGND .............................................. -0.3V to 6V

MAX1246_C_E/MAX1247_C_E.......................... 0°C to +70°C

MAX1246_E_E/MAX1247_E_E........................ -40°C to +85°C

MAX1246_MJE/MAX1247_MJE.................... -55°C to +125°C

Storage Temperature Range............................ -60°C to +150°C

Lead Temperature (soldering, 10s) ................................ +300°C

DD

Digital Outputs to DGND ........................... -0.3V to (V + 0.3V)

DD

Digital Output Sink Current .................................................25mA

Continuous Power Dissipation (T = +70°C)

A

Plastic DIP (derate 10.53mW/°C above +70°C) ......... 842mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V = +2.7V to +3.6V (MAX1246); V = +2.7V to +5.25V (MAX1247); COM = 0V; f = 2.0MHz; external clock (50ꢀ duty cycle);

DD

SCLK

15 clocks/conversion cycle (133ksps); MAX1246—4.7µF capacitor at VREF pin; MAX1247—external reference, VREF = 2.5V applied

to VREF pin; T = T

to T ; unless otherwise noted.)

A

MIN

MAX

PARAMETER

DC ACCURACY (Note 1)

Resolution

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Bits

12

MAX124_A

±±0.

±10±

±20±

Relative Accuracy (Note 2)

INL

MAX124_B

MAX1247C

LSB

No Missing Codes

NMC

DNL

12

Bits

MAX124_A/MAX124_B

MAX124_C

±1

Differential Nonlinearity

LSB

±±0ꢀ

±±0.

±±02.

MAX124_A

±ꢁ

±4

Offset Error

LSB

MAX124_B

Gain Error (Note ꢁ)

LSB

Gain Temperature Coefficient

ppm/°C

Channel-to-Channel Offset

Matching

±±02.

LSB

DYNAMIC SPECIFICATIONS (1±kHz sine-wave input, ±V to 20.±±Vp-p, 1ꢁꢁksps, 20±MHz external clock, bipolar input mode)

MAX124_A/MAX124_B

MAX1247C

7±

7ꢁ

Signal-to-Noise + Distortion

Ratio

SINAD

THD

dB

MAX124_A/MAX124_B

MAX1247C

-ꢀꢀ

9±

-ꢀ±

Up to the .th

harmonic

Total Harmonic Distortion

MAX124_A/MAX124_B

MAX1247C

ꢀ±

Spurious-Free Dynamic Range

SFDR

9±

Channel-to-Channel Crosstalk

Small-Signal Bandwidth

Full-Power Bandwidth

6.kHz, 20.±±V

-ꢁdB rolloff

(Note 4)

-ꢀ.

202.

10±

dB

P-P

MHz

2

_______________________________________________________________________________________

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

ELECTRICAL CHARACTERISTICS (continued)

(V = +207V to +ꢁ06V (MAX1246); V = +207V to +.02.V (MAX1247); COM = ±V; f = 20±MHz; external clock (.±% duty cycle);

DD

SCLK

1. clocks/conversion cycle (1ꢁꢁksps); MAX1246—407µF capacitor at VREF pin; MAX1247—external reference, VREF = 20.V applied

to VREF pin; T = T

to T ; unless otherwise noted0)

A

MIN

MAX

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

CONVERSION RATE

Internal clock, SHDN = FLOAT

Internal clock, SHDN = V

.0.

ꢁ.

70.

6.

DD

Conversion Time (Note .)

t

µs

CONV

External clock = 2MHz, 12 clocks/

conversion

6

Track/Hold Acquisition Time

t

10.

ACQ

Aperture Delay

Aperture Jitter

ꢁ±

<.±

10ꢀ

ns

ps

SHDN = FLOAT

Internal Clock Frequency

MHz

SHDN = V

±022.

DD

±01

±

20±

External Clock Frequency

Data transfer only

ANALOG/COM INPUTS

Unipolar, COM = ±V

± to VREF

Input Voltage Range, Single-

Ended and Differential (Note 6)

V

Bipolar, COM = VREF / 2

±VREF / 2

Multiplexer Leakage Current

Input Capacitance

On/off leakage current, V _ = ±V or V

±±0±1

±1

µA

pF

CH

DD

16

INTERNAL REFERENCE (MAX1246 only, reference buffer enabled)

VREF Output Voltage

T

A

= +2.°C

204ꢀ±

20.±±

20.2±

ꢁ±

V

VREF Short-Circuit Current

mA

MAX1246_C

±ꢁ±

±.±

±6±

±ꢀ±

VREF Temperature Coefficient

ppm/°C

MAX1246_E

MAX1246_M

±ꢁ±

Load Regulation (Note ꢀ)

Capacitive Bypass at VREF

±mA to ±02mA output load

Internal compensation mode

External compensation mode

±±0ꢁ.

mV

µF

±

407

Capacitive Bypass at REFADJ

REFADJ Adjustment Range

±0±47

µF

%

V

= V = V = 2ꢀV, V = 10.V

±10.

BST

LX

IN

FB

EXTERNAL REFERENCE AT VREF (Buffer disabled)

VREF Input Voltage Range

(Note 9)

VDD +

.±mV

10±

1ꢀ

V

VREF Input Current

VREF = 20.V

1±±

2.

1.±

V

VREF Input Resistance

Shutdown VREF Input Current

kΩ

µA

±0±1

1±±

REFADJ Buffer Disable

Threshold

VDD -

±0.

V

_______________________________________________________________________________________

3

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

ELECTRICAL CHARACTERISTICS (continued)

(V = +207V to +ꢁ06V (MAX1246); V = +207V to +.02.V (MAX1247); COM = ±V; f = 20±MHz; external clock (.±% duty cycle);

DD

SCLK

1. clocks/conversion cycle (1ꢁꢁksps); MAX1246—407µF capacitor at VREF pin; MAX1247—external reference, VREF = 20.V applied

to VREF pin; T = T

to T ; unless otherwise noted0)

A

MIN

MAX

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

EXTERNAL REFERENCE AT REFADJ

Internal compensation mode

External compensation mode

MAX1246

±

Capacitive Bypass at VREF

µF

V/V

µA

407

20±6

20±±

Reference Buffer Gain

REFADJ Input Current

MAX1247

MAX1246

±.±

±1±

MAX1247

4

_______________________________________________________________________________________

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

ELECTRICAL CHARACTERISTICS (continued)

(V = +207V to +ꢁ06V (MAX1246); V = +207V to +.02.V (MAX1247); COM = ±V; f = 20±MHz; external clock (.±% duty cycle);

DD

SCLK

1. clocks/conversion cycle (1ꢁꢁksps); MAX1246—407µF capacitor at VREF pin; MAX1247—external reference, VREF = 20.V applied

to VREF pin; T = T

to T ; unless otherwise noted0)

A

MIN

MAX

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

DIGITAL INPUTS (DIN, SCLK, CS, SHDN)

V

≤ ꢁ06V

20±

ꢁ0±

DD

V

IH

V

DIN, SCLK, CS Input High Voltage

> ꢁ06V, MAX1247 only

DD

V

±0ꢀ

V

DIN, SCLK, CS Input Low Voltage

DIN, SCLK, CS Input Hysteresis

DIN, SCLK, CS Input Leakage

DIN, SCLK, CS Input Capacitance

SHDN Input High Voltage

SHDN Input Mid Voltage

IL

V

±02

HYST

I

IN

V

= ±V or V

DD

±±0±1

±1

1.

µA

pF

V

IN

C

IN

(Note 7)

V

SH

V

- ±04

DD

V

SM

101

V

DD

- 101

±04

V

SL

V

SHDN Input Low Voltage

I

SHDN = ±V or V

SHDN = FLOAT

±40±

µA

V

SHDN Input Current

S

DD

V

DD

/ 2

SHDN Voltage, Floating

FLT

SHDN Maximum Allowed

Leakage, Mid Input

SHDN = FLOAT

±1±±

nA

DIGITAL OUTPUTS (DOUT, SSTRB)

I

= .mA

±04

±0ꢀ

SINK

Output Voltage Low

V

OL

V

= 16mA

SINK

Output Voltage High

V

OH

= ±0.mA

V - ±0.

DD

V

SOURCE

Three-State Leakage Current

Three-State Output Capacitance

POWER REQUIREMENTS

I

±±0±1

±1±

1.

µA

pF

CS = V

L

DD

C

(Note 7)

OUT

MAX1246

MAX1247

207±

ꢁ06±

.02.

20±

7±

Positive Supply Voltage

V

DD

Operating mode, full-scale input

102

ꢁ±

mA

µA

Positive Supply Current, MAX1246

I

V

DD

= ꢁ06V Fast power-down

Full power-down

DD

102

10ꢀ

±09

ꢁ±

1±

V

DD

V

DD

= .02.V

= ꢁ06V

20.

10.

7±

Operating mode,

full-scale input

mA

µA

Positive Supply Current, MAX1247

Supply Rejection (Note 1±)

Fast power-down

Full power-down

DD

V

= .02.V

= ꢁ06V

ꢁ0.

102

1.

DD

1±

DD

V

DD

= 207V to V

, full-scale input,

DD(MAX)

PSR

±±0ꢁ

mV

external reference = 20.±±V

_______________________________________________________________________________________

5

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

TIMING CHARACTERISTICS

(V = +207V to +ꢁ06V (MAX1246); V = +207V to +.02.V (MAX1247); T = T

to T

; unless otherwise noted0)

MAX

DD

A

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

10.

TYP

MAX UNITS

Acquisition Time

DIN to SCLK Setup

DIN to SCLK Hold

t

µs

ns

ACQ

t

1±±

DS

t

±

ns

DH

MAX124_ _C/E

MAX124_ _M

2±

2±±

24±

SCLK Fall to Output Data Valid

t

Figure 1

ns

DO

t

Figure 1

Figure 2

ns

CS Fall to Output Enable

CS Rise to Output Disable

CS to SCLK Rise Setup

CS to SCLK Rise Hold

DV

t

TR

t

1±±

±

CSS

CSH

t

SCLK Pulse Width High

SCLK Pulse Width Low

t

2±±

CH

t

CL

SCLK Fall to SSTRB

t

Figure 1

24±

SSTRB

t

External clock mode only, Figure 1

External clock mode only, Figure 2

Internal clock mode only (Note 7)

CS Fall to SSTRB Output Enable

CS Rise to SSTRB Output Disable

SSTRB Rise to SCLK Rise

SDV

t

STR

t

±

SCK

Note 1: Tested at V

= 207V; COM = ±V; unipolar single-ended input mode0

DD

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated0

Note 3: MAX1246—internal reference, offset nulled; MAX1247—external reference (V

Note 4: Ground “on” channel; sine wave applied to all “off” channels0

= +20.±±V), offset nulled0

REF

Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has .±% duty cycle0

Note 6: The common-mode range for the analog inputs is from AGND to V

Note 7: Guaranteed by design0 Not subject to production testing0

0

DD

Note 8: External load should not change during conversion for specified accuracy0

Note 9: ADC performance is limited by the converter’s noise floor, typically ꢁ±±µVp-p0

Note 10: Measured as V (207V) - V (V

) 0

FS

FS DD0MAX

|

__________________________________________Typical Operating Characteristics

(V

= ꢁV, VREF = 20.V, f

= 2MHz, C

= 2±pF, T = +2.°C, unless otherwise noted0)

DD

SCLK

LOAD

A

INTEGRAL NONLINEARITY

vs. CODE

INTEGRAL NONLINEARITY

vs. TEMPERATURE

INTEGRAL NONLINEARITY

vs. SUPPLY VOLTAGE

0.5

0.4

0.3

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

V

= 2.7V

DD

0.45

0.40

MAX1246

0.35

0.2

0.1

MAX1246

0.30

0.25

0.20

0

-0.1

MAX1247

-0.2

-0.3

0.15

0.10

0.05

0.00

0.10

0.05

0.00

-0.4

-0.5

-60

-20

20

60

100

140

0

1024

2048

3072

4096

2.25

2.75 3.25

3.75

(V)

4.25 4.75 5.25

CODE

V

TEMPERATURE (°C)

DD

6

_______________________________________________________________________________________

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

____________________________Typical Operating Characteristics (continued)

(V

= ꢁV, VREF = 20.V, f

= 2MHz, C

= 2±pF, T = +2.°C, unless otherwise noted0)

DD

SCLK

LOAD

A

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

SHUTDOWN SUPPLY CURRENT

vs. SUPPLY VOLTAGE

INTERNAL REFERENCE VOLTAGE

vs. SUPPLY VOLTAGE

2.00

4.0

3.5

3.0

2.5

2.0

2.5020

2.5015

2.5010

2.5005

2.5000

2.4995

2.4990

R = ∞

L

FULL POWER-DOWN

CODE = 101010100000

C

= 50pF

LOAD

1.75

1.50

1.25

1.00

0.75

0.50

MAX1246

1.5

1.0

0.5

0

C

= 20pF

LOAD

MAX1247

2.25 2.75 3.25 3.75 4.25 4.75 5.25

SUPPLY VOLTAGE (V)

V

DD

(V)

V

(V)

DD

MAX1246

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

SHUTDOWN CURRENT

vs. TEMPERATURE

SUPPLY CURRENT vs. TEMPERATURE

2.501

2.0

1.3

1.2

1.1

1.0

2.500

2.499

V

= 3.6V

MAX1246

DD

1.6

1.2

0.8

0.4

V

= 2.7V

DD

2.498

2.497

2.496

MAX1247

0.9

0.8

2.495

2.494

R

= ∞

LOAD

CODE = 101010100000

-60 -20 20

TEMPERATURE (°C)

0

-60

-20

20

60

100

140

60

100

140

-60

-20

20

60

100

140

TEMPERATURE (°C)

EFFECTIVE NUMBER OF BITS

vs. FREQUENCY

FFT PLOT

20

12.0

11.8

11.6

11.4

11.2

11.0

V

= 2.7V

DD

= 10k

V

= 2.7V

DD

f

IN

SAMPLE

0

= 133k

-20

-40

-60

-80

-100

-120

0

10

20

30

40

50

60

70

1

10

100

FREQUENCY (kHz)

_______________________________________________________________________________________

7

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

____________________________Typical Operating Characteristics (continued)

(V

= ꢁV, VREF = 20.V, f

= 2MHz, C

= 2±pF, T = +2.°C, unless otherwise noted0)

DD

SCLK

LOAD

A

GAIN ERROR

vs. SUPPLY VOLTAGE

0.50

CHANNEL-TO-CHANNEL GAIN MATCHING

vs. SUPPLY VOLTAGE

OFFSET vs. SUPPLY VOLTAGE

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

2.75 3.25 3.75

(V)

4.25 4.75 5.25

2.25

2.25 2.75

3.25 3.75 4.25 4.75 5.25

(V)

2.25

2.75 3.25

3.75 4.25 4.75 5.25

(V)

V

DD

GAIN ERROR

vs. TEMPERATURE

CHANNEL-TO-CHANNEL GAIN MATCHING

vs. TEMPERATURE

OFFSET vs. TEMPERATURE

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

-55

-30

-55 -30 -5

20 45

TEMPERATURE (˚C)

-5 20 45 70 95 120 145

TEMPERATURE (˚C)

70 95 120 145

-55 -30

TEMPERATURE (˚C)

CHANNEL-TO-CHANNEL OFFSET MATCHING

vs. TEMPERATURE

0.50

CHANNEL-TO-CHANNEL OFFSET MATCHING

vs. SUPPLY VOLTAGE

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

-30 -5

-55

20 45 70 95 120 145

TEMPERATURE (˚C)

2.25 2.75 3.25

3.75 4.25 4.75 5.25

(V)

V

DD

8

_______________________________________________________________________________________

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

______________________________________________________________Pin Description

NAME

FUNCTION

1

V

Positive Supply Voltage

Sampling Analog Inputs

DD

2–.

CH±–CHꢁ

Ground reference for analog inputs0 COM sets zero-code voltage in single-ended mode0 Must be

stable to ±±0.LSB0

6

7

COM

Three-Level Shutdown Input0 Pulling SHDN low shuts the MAX1246/MAX1247 down; otherwise, they

are fully operational0 Pulling SHDN high puts the reference-buffer amplifier in internal compensation

mode0 Letting SHDN float puts the reference-buffer amplifier in external compensation mode0

SHDN

Reference-Buffer Output/ADC Reference Input0 Reference voltage for analog-to-digital conversion0

In internal reference mode (MAX1246 only), the reference buffer provides a 20.±±V nominal output,

externally adjustable at REFADJ0 In external reference mode, disable the internal buffer by pulling

ꢀ

VREF

REFADJ to V

0

DD

9

REFADJ

AGND

DGND

DOUT

Input to the Reference-Buffer Amplifier0 To disable the reference-buffer amplifier, tie REFADJ to V

0

DD

1±

11

12

Analog Ground

Digital Ground

Serial Data Output0 Data is clocked out at SCLK’s falling edge0 High impedance when CS is high0

Serial Strobe Output0 In internal clock mode, SSTRB goes low when the MAX1246/MAX1247 begin the

A/D conversion, and goes high when the conversion is finished0 In external clock mode, SSTRB pulses

high for one clock period before the MSB decision0 High impedance when CS is high (external clock

mode)0

1ꢁ

SSTRB

14

1.

DIN

Serial Data Input0 Data is clocked in at SCLK’s rising edge0

Active-Low Chip Select0 Data will not be clocked into DIN unless CS is low0 When CS is high, DOUT is

high impedance0

CS

Serial Clock Input0 Clocks data in and out of serial interface0 In external clock mode, SCLK also sets

the conversion speed0 (Duty cycle must be 4±% to 6±%0)

16

SCLK

V

DD

6kΩ

DOUT

C

LOAD

50pF

C

LOAD

50pF

LOAD

50pF

LOAD

50pF

6kΩ

DGND

a) High-Z to V and V to V

OH

b) High-Z to V and V to V

OL

OH

OL

OH

a) V to High-Z

OH

b) V to High-Z

OL

Figure 1. Load Circuits for Enable Time

Figure 2. Load Circuits for Disable Time

_______________________________________________________________________________________

9

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

input control word has been entered0 At the end of the

acquisition interval, the T/H switch opens, retaining

charge on C as a sample of the signal at IN+0

_______________Detailed Description

The MAX1246/MAX1247 analog-to-digital converters

(ADCs) use a successive-approximation conversion

technique and input track/hold (T/H) circuitry to convert

an analog signal to a 12-bit digital output0 A flexible seri-

al interface provides easy interface to microprocessors

(µPs)0 Figure ꢁ is a block diagram of the MAX1246/

MAX12470

HOLD

The conversion interval begins with the input multiplexer

switching C from the positive input (IN+) to the

HOLD

negative input (IN-)0 In single-ended mode, IN- is simply

COM0 This unbalances node ZERO at the comparator’s

input0 The capacitive DAC adjusts during the remainder

of the conversion cycle to restore node ZERO to ±V

within the limits of 12-bit resolution0 This action is equiv-

Pseudo-Differential Input

The sampling architecture of the ADC’s analog com-

parator is illustrated in the equivalent input circuit

(Figure 4)0 In single-ended mode, IN+ is internally

switched to CH±–CHꢁ, and IN- is switched to COM0 In

differential mode, IN+ and IN- are selected from two

pairs: CH±/CH1 and CH2/CHꢁ0 Configure the channels

with Tables 2 and ꢁ0 Please note that the codes for

CH±–CHꢁ in the MAX1246/MAX1247 correspond to the

codes for CH2–CH. in the eight-channel (MAX146/

MAX147) versions0

alent to transferring a 16pF x [(V_IN+) - (V -)] charge

IN

from C

to the binary-weighted capacitive DAC,

HOLD

which in turn forms a digital representation of the analog

input signal0

Track/Hold

The T/H enters its tracking mode on the falling clock

edge after the fifth bit of the ꢀ-bit control word has been

shifted in0 It enters its hold mode on the falling clock

edge after the eighth bit of the control word has been

shifted in0 If the converter is set up for single-ended

inputs, IN- is connected to COM, and the converter

samples the “+” input0 If the converter is set up for dif-

ferential inputs, IN- connects to the “-” input, and the

difference of |IN+ - IN-| is sampled0 At the end of the

conversion, the positive input connects back to IN+,

In differential mode, IN- and IN+ are internally switched

to either of the analog inputs0 This configuration is

pseudo-differential to the effect that only the signal at IN+

is sampled0 The return side (IN-) must remain stable within

±±0.LSB (±±01LSB for best results) with respect to AGND

during a conversion0 To accomplish this, connect a ±01µF

capacitor from IN- (the selected analog input) to AGND0

and C

charges to the input signal0

HOLD

The time required for the T/H to acquire an input signal

is a function of how quickly its input capacitance is

charged0 If the input signal’s source impedance is high,

the acquisition time lengthens, and more time must be

During the acquisition interval, the channel selected

as the positive input (IN+) charges capacitor C

0

HOLD

The acquisition interval spans three SCLK cycles and

ends on the falling SCLK edge after the last bit of the

15

16

CS

SCLK

12-BIT CAPACITIVE DAC

VREF

INPUT

SHIFT

INT

14

7

DIN

CLOCK

REGISTER

CONTROL

LOGIC

COMPARATOR

INPUT

C

SHDN

HOLD

MUX

ZERO

–

+

CH0

CH1

CH2

CH3

COM

2

3

4

5

6

12

13

CH0

CH1

CH2

OUTPUT

SHIFT

DOUT

16pF

REGISTER

SSTRB

R

IN

ANALOG

INPUT

MUX

9kΩ

T/H

C

SWITCH

CLOCK

HOLD

IN

12-BIT

SAR

ADC

TRACK

CH3

AT THE SAMPLING INSTANT,

THE MUX INPUT SWITCHES

FROM THE SELECTED IN+

CHANNEL TO THE SELECTED

IN- CHANNEL.

OUT

1

T/H

SWITCH

REF

V

DD

COM

11

A ≈ 2.06*

+1.21V

DGND

AGND

20kΩ

REFERENCE

(MAX1246)

10

9

8

REFADJ

VREF

SINGLE-ENDED MODE: IN+ = CH0–CH3, IN- = COM.

DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF

CH0/CH1 AND CH2/CH3.

MAX1246

MAX1247

+2.500V

*A ≈ 2.00 (MAX1247)

Figure 4. Equivalent Input Circuit

Figure 3. Block Diagram

10 ______________________________________________________________________________________

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

Table 1. Control-Byte Format

BIT 7

(MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

(LSB)

START

SEL2

SEL1

SEL±

UNI/BIP

SGL/DIF

PD1

PD±

BIT

NAME

DESCRIPTION

7(MSB)

START

The first logic “1” bit after CS goes low defines the beginning of the control byte0

6

.

4

SEL2

SEL1

SEL±

These three bits select which of the four channels are used for the conversion (Tables 2 and ꢁ)0

ꢁ

UNI/BIP

1 = unipolar, ± = bipolar0 Selects unipolar or bipolar conversion mode0 In unipolar mode, an

analog input signal from ±V to VREF can be converted; in bipolar mode, the signal can range

from -VREF / 2 to +VREF / 20

2

SGL/DIF

1 = single ended, ± = differential0 Selects single-ended or differential conversions0 In single-

ended mode, input signal voltages are referred to COM0 In differential mode, the voltage

difference between two channels is measured (Tables 2 and ꢁ)0

1

PD1

PD±

Selects clock and power-down modes0

±(LSB)

PD1

±

PD±

±

Mode

Full power-down

Fast power-down

Internal clock mode

External clock mode

±

1

±

1

allowed between conversions0 The acquisition time,

, is the maximum time the device takes to acquire

the signal, and is also the minimum time needed for the

signal to be acquired0 It is calculated by the following

equation:

Analog Input Protection

t

Internal protection diodes, which clamp the analog input

ACQ

to V

and AGND, allow the channel input pins to swing

DD

from AGND - ±0ꢁV to V

+ ±0ꢁV without damage0

DD

However, for accurate conversions near full scale, the

inputs must not exceed V by more than .±mV or be

DD

t

= 9 x (R + R ) x 16pF

S IN

ACQ

lower than AGND by .±mV0

where R = 9kΩ, R = the source impedance of the

IN

S

ACQ

If the analog input exceeds 50mV beyond the sup-

plies, do not forward bias the protection diodes of

off channels over 4mA.

input signal, and t

is never less than 10.µs0 Note

that source impedances below 1kΩ do not significantly

affect the ADC’s AC performance0

Higher source impedances can be used if a ±0±1µF

capacitor is connected to the individual analog inputs0

Note that the input capacitor forms an RC filter with the

input source impedance, limiting the ADC’s signal

bandwidth0

How to Start a Conversion

Start a conversion by clocking a control byte into DIN0

With CS low, each rising edge on SCLK clocks a bit from

DIN into the MAX1246/MAX1247’s internal shift register0

After CS falls, the first arriving logic “1” bit defines the

control byte’s MSB0 Until this first “start” bit arrives, any

number of logic “±” bits can be clocked into DIN with no

effect0 Table 1 shows the control-byte format0

Input Bandwidth

The ADC’s input tracking circuitry has a 202.MHz

small-signal bandwidth, so it is possible to digitize

high-speed transient events and measure periodic sig-

nals with bandwidths exceeding the ADC’s sampling

rate by using undersampling techniques0 To avoid

high-frequency signals being aliased into the frequency

band of interest, anti-alias filtering is recommended0

The MAX1246/MAX1247 are compatible with SPI™/

QSPI™ and Microwire™ devices0 For SPI, select the

correct clock polarity and sampling edge in the SPI

control registers: set CPOL = ± and CPHA = ±0 Micro-

wire, SPI, and QSPI all transmit a byte and receive a

byte at the same time0 Using the Typical Operating

______________________________________________________________________________________ 11

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

Table 2. Channel Selection in Single-Ended Mode (SGL/

= 1)

SEL2

0

SEL1

0

SEL0

1

CH0

CH1

CH2

CH3

COM

+

–

1

0

1

0

1

0

+

–

+

Table 3. Channel Selection in Differential Mode (SGL/

= 0)

SEL2

SEL1

SEL0

CH0

CH1

CH2

+

CH3

0

1

0

1

0

1

0

1

0

+

–

+

–

+

Circuit, the simplest software interface requires only

three ꢀ-bit transfers to perform a conversion (one ꢀ-bit

transfer to configure the ADC, and two more ꢀ-bit trans-

fers to clock out the 12-bit conversion result)0 See Figure

19 for MAX1246/MAX1247 QSPI connections0

Digital Output

In unipolar input mode, the output is straight binary

(Figure 16)0 For bipolar inputs, the output is two’s com-

plement (Figure 17)0 Data is clocked out at the falling

edge of SCLK in MSB-first format0

Simple Software Interface

Make sure the CPU’s serial interface runs in master

mode so the CPU generates the serial clock0 Choose a

clock frequency from 1±±kHz to 2MHz0

Clock Modes

The MAX1246/MAX1247 may use either an external

serial clock or the internal clock to perform the succes-

sive-approximation conversion0 In both clock modes,

the external clock shifts data in and out of the

MAX1246/MAX12470 The T/H acquires the input signal

as the last three bits of the control byte are clocked into

DIN0 Bits PD1 and PD± of the control byte program the

clock mode0 Figures 6–9 show the timing characteristics

common to both modes0

1) Set up the control byte for external clock mode and

call it TB10 TB1 should be of the format: 1XXXXX11

binary, where the Xs denote the particular channel

and conversion mode selected0

2) Use a general-purpose I/O line on the CPU to pull

CS low0

External Clock

In external clock mode, the external clock not only shifts

data in and out, but it also drives the analog-to-digital

conversion steps0 SSTRB pulses high for one clock

period after the last bit of the control byte0 Succes-

sive-approximation bit decisions are made and appear

at DOUT on each of the next 12 SCLK falling edges

(Figure .)0 SSTRB and DOUT go into a high-impedance

state when CS goes high; after the next CS falling edge,

SSTRB outputs a logic low0 Figure 7 shows the SSTRB

timing in external clock mode0

ꢁ) Transmit TB1 and, simultaneously, receive a byte

and call it RB10 Ignore RB10

4) Transmit a byte of all zeros ($±± hex) and, simulta-

neously, receive byte RB20

.) Transmit a byte of all zeros ($±± hex) and, simulta-

neously, receive byte RBꢁ0

6) Pull CS high0

Figure . shows the timing for this sequence0 Bytes RB2

and RBꢁ contain the result of the conversion, padded

with one leading zero and three trailing zeros0 The total

conversion time is a function of the serial-clock fre-

quency and the amount of idle time between ꢀ-bit

transfers0 To avoid excessive T/H droop, make sure the

total conversion time does not exceed 12±µs0

The conversion must complete in some minimum time,

or droop on the sample-and-hold capacitors may

degrade conversion results0 Use internal clock mode if

the serial clock frequency is less than 1±±kHz, or if

serial clock interruptions could cause the conversion

interval to exceed 12±µs0

12 ______________________________________________________________________________________

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

CS

t

ACQ

SCLK

1

4

8

12

16

20

24

UNI/

BIP

SGL/

DIF

SEL2 SEL1 SEL0

PD1 PD0

DIN

SSTRB

DOUT

START

RB2

B8

RB3

RB1

FILLED WITH

ZEROS

B11

B0

B10 B9

B7

B6

B5

B4

B3

B2

B1

MSB

LSB

ACQUISITION

1.5µs

CONVERSION

A/D STATE

IDLE

(f

= 2MHz)

SCLK

Figure 5. 24-Clock External Clock Mode Conversion Timing (Microwire and SPI Compatible, QSPI Compatible with f

≤ 2MHz)

SCLK

• • •

CS

t

CSH

CSS

CH

t

CL

CSH

SCLK

t

DS

t

DH

DIN

• • •

t

TR

DV

DO

DOUT

Figure 6. Detailed Serial-Interface Timing

Internal Clock

An internal register stores data when the conversion is

in progress0 SCLK clocks the data out of this register at

any time after the conversion is complete0 After SSTRB

goes high, the next falling clock edge produces the

MSB of the conversion at DOUT, followed by the

remaining bits in MSB-first format (Figure ꢀ)0 CS does

not need to be held low once a conversion is started0

Pulling CS high prevents data from being clocked into

the MAX1246/MAX1247 and three-states DOUT, but it

does not adversely affect an internal clock mode

In internal clock mode, the MAX1246/MAX1247 generate

their own conversion clocks internally0 This frees the µP

from the burden of running the SAR conversion clock

and allows the conversion results to be read back at the

processor’s convenience, at any clock rate from ±MHz

to 2MHz0 SSTRB goes low at the start of the conversion

and then goes high when the conversion is complete0

SSTRB is low for a maximum of 70.µs (SHDN = FLOAT),

during which time SCLK should remain low for best

noise performance0

______________________________________________________________________________________ 13

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

CS

• • •

t

STR

SDV

SSTRB

• • •

t

SSTRB

SCLK

• • • •

PD0 CLOCKED IN

Figure 7. External Clock Mode SSTRB Detailed Timing

CS

SCLK

DIN

1

4

8

18

24

2

3

5

6

7

9

10

11

12

19

20

21

22

23

UNI/ SGL/

BIP

SEL2 SEL1 SEL0

PD1 PD0

DIF

START

SSTRB

t

CONV

FILLED WITH

ZEROS

B11

MSB

B0

LSB

DOUT

B10

B9

B2

B1

ACQUISITION

CONVERSION

A/D STATE

1.5µs

IDLE

7.5µs MAX

(f

= 2MHz) (SHDN = FLOAT)

SCLK

Figure 8. Internal Clock Mode Timing

conversion already in progress0 When internal clock

mode is selected, SSTRB does not go into a high-

impedance state when CS goes high0

conversion starts on SCLK’s falling edge, after the eighth

bit of the control byte (the PD± bit) is clocked into DIN0

The start bit is defined as follows:

Figure 9 shows the SSTRB timing in internal clock

mode0 In this mode, data can be shifted in and out of

the MAX1246/MAX1247 at clock rates exceeding

The first high bit clocked into DIN with CS low any

time the converter is idle; e0g0, after V

is applied0

DD

OR

20±MHz if the minimum acquisition time (t

above 10.µs0

) is kept

ACQ

The first high bit clocked into DIN after bit . of a con-

version in progress is clocked onto the DOUT pin0

Data Framing

The falling edge of CS does not start a conversion0

The first logic high clocked into DIN is interpreted as a

start bit and defines the first bit of the control byte0 A

If CS is toggled before the current conversion is com-

plete, the next high bit clocked into DIN is recognized as

a start bit; the current conversion is terminated, and a

new one is started0

14 ______________________________________________________________________________________

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

Most microcontrollers (µCs) require that conversions

occur in multiples of ꢀ SCLK clocks; 16 clocks per con-

version is typically the fastest that a µC can drive the

MAX1246/MAX12470 Figure 1±b shows the serial-

interface timing necessary to perform a conversion every

16 SCLK cycles in external clock mode0

The fastest the MAX1246/MAX1247 can run with CS held

low between conversions is 1. clocks per conversion0

Figure 1±a shows the serial-interface timing necessary to

perform a conversion every 1. SCLK cycles in external

clock mode0 If CS is tied low and SCLK is continuous,

guarantee a start bit by first clocking in 16 zeros0

CS

t

CONV

t

CSS

t

SCK

CSH

SSTRB

SCLK

t

SSTRB

t

DO

PD0 CLOCK IN

DOUT

NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.

Figure 9. Internal Clock Mode SSTRB Detailed Timing

CS

1

8

15

1

8

15

1

SCLK

DIN

S

CONTROL BYTE 2

S

CONTROL BYTE 0

S

CONTROL BYTE 1

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

CONVERSION RESULT 0

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

CONVERSION RESULT 1

DOUT

SSTRB

Figure 10a. External Clock Mode, 15 Clocks/Conversion Timing

• • •

CS

1

8

16

1

8

16

SCLK

DIN

S

CONTROL BYTE 0

S

CONTROL BYTE 1

DOUT

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

CONVERSION RESULT 0

B11 B10 B9 B8

CONVERSION RESULT 1

Figure 10b. External Clock Mode, 16 Clocks/Conversion Timing

______________________________________________________________________________________ 15

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

(Tables 1 and .)0 In both software power-down modes,

__________ Applications Information

the serial interface remains operational, but the ADC

does not convert0 Pull SHDN low at any time to shut

down the converter completely0 SHDN overrides bits 1

and ± of the control byte0

Power-On Reset

When power is first applied, and if SHDN is not pulled

low, internal power-on reset circuitry activates the

MAX1246/MAX1247 in internal clock mode, ready to

convert with SSTRB = high0 After the power supplies

stabilize, the internal reset time is 1±µs, and no conver-

sions should be performed during this phase0 SSTRB is

high on power-up and, if CS is low, the first logical 1 on

DIN is interpreted as a start bit0 Until a conversion takes

place, DOUT shifts out zeros0 (Also see Table 40)

Full power-down mode turns off all chip functions that

draw quiescent current, reducing supply current to 2µA

(typ)0 Fast power-down mode turns off all circuitry

except the bandgap reference0 With fast power-down

mode, the supply current is ꢁ±µA0 Power-up time can be

shortened to .µs in internal compensation mode0

Table 4 shows how the choice of reference-buffer com-

pensation and power-down mode affects both power-up

delay and maximum sample rate0 In external compensa-

tion mode, power-up time is 2±ms with a 407µF compen-

sation capacitor when the capacitor is initially fully

discharged0 From fast power-down, start-up time can be

eliminated by using low-leakage capacitors that do not

discharge more than 1/2LSB while shut down0 In power-

down, leakage currents at VREF cause droop on the ref-

erence bypass capacitor0 Figures 11a and 11b show

the various power-down sequences in both external and

internal clock modes0

Reference-Buffer Compensation

In addition to its shutdown function, SHDN selects inter-

nal or external compensation0 The compensation

affects both power-up time and maximum conversion

speed0 The1±±kHz minimum clock rate is limited by

droop on the sample-and-hold and is independent of

the compensation used0

Float SHDN to select external compensation0 The

Typical Operating Circuit uses a 407µF capacitor at

VREF0 A 407µF value ensures reference-buffer stability

and allows converter operation at the 2MHz full clock

speed0 External compensation increases power-up

time (see the Choosing Power-Down Mode section and

Table 4)0

Software Power-Down

Software power-down is activated using bits PD1 and PD±

of the control byte0 As shown in Table ., PD1 and PD±

also specify the clock mode0 When software shutdown is

asserted, the ADC operates in the last specified clock

mode until the conversion is complete0 Then the ADC

powers down into a low quiescent-current state0 In internal

clock mode, the interface remains active and conversion

results may be clocked out after the MAX1246/MAX1247

enter a software power-down0

Pull SHDN high to select internal compensation0

Internal compensation requires no external capacitor at

VREF and allows for the shortest power-up times0 The

maximum clock rate is 2MHz in internal clock mode

and 4±±kHz in external clock mode0

Choosing Power-Down Mode

You can save power by placing the converter in a low-

current shutdown state between conversions0 Select full

power-down mode or fast power-down mode via bits 1

and ± of the DIN control byte with SHDN high or floating

The first logical 1 on DIN is interpreted as a start bit

and powers up the MAX1246/MAX12470 Following

the start bit, the data input word or control byte also

Table 4. Typical Power-Up Delay Times

REFERENCE-

VREF

POWER-UP

DELAY

(µs)

MAXIMUM

SAMPLING RATE

(ksps)

REFERENCE

BUFFER

COMPENSATION

MODE

POWER-DOWN

MODE

CAPACITOR

(µF)

Enabled

Disabled

Internal

External

Fast

Full

.

26

ꢁ±±

407

Fast

Full

See Figure 1ꢁc

1ꢁꢁ

See Figure 1ꢁc

Fast

Full

2

16 ______________________________________________________________________________________

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

CLOCK

MODE

EXTERNAL

SHDN

SETS SOFTWARE

POWER-DOWN

SETS EXTERNAL

CLOCK MODE

SETS EXTERNAL

CLOCK MODE

DIN

S

X

X X X X

1

S X

X

X X X

0

S

X X X X X

1 1

DOUT

VALID

DATA

INVALID

DATA

12 DATA BITS

POWERED UP

12 DATA BITS

HARDWARE

POWER-

DOWN

POWERED UP

MODE

SOFTWARE

POWER-DOWN

POWERED UP

Figure 11a. Timing Diagram Power-Down Modes, External Clock

CLOCK

MODE

INTERNAL

SETS

POWER-DOWN

SETS INTERNAL

CLOCK MODE

DIN

S

X

X X X X

1

0

S X

X

X X X

0

S

DOUT

DATA VALID

SSTRB

MODE

CONVERSION

POWER-DOWN

POWERED UP

Figure 11b. Timing Diagram Power-Down Modes, Internal Clock

determines clock mode and power-down states0 For

example, if the DIN word contains PD1 = 1, then the

chip remains powered up0 If PD± = PD1 = ±, a

power-down resumes after one conversion0

controls the clock frequency in internal clock mode0

Letting SHDN float sets the internal clock frequency to

10ꢀMHz0 When returning to normal operation with SHDN

floating, there is a t delay of approximately 2MΩ x C ,

RC

L

where C is the capacitive loading on the SHDN pin0

L

Hardware Power-Down

Pulling SHDN low places the converter in hardware

power-down (Table 6)0 Unlike software power-down

mode, the conversion is not completed; it stops coin-

cidentally with SHDN being brought low0 SHDN also

Pulling SHDN high sets internal clock frequency to

22.kHz0 This feature eases the settling-time requirement

for the reference voltage0 With an external reference, the

MAX1246/MAX1247 can be considered fully powered up

within 2µs of actively pulling SHDN high0

______________________________________________________________________________________ 17

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

Figure 1ꢁa depicts the MAX1246 power consumption

Power-Down Sequencing

The MAX1246/MAX1247 auto power-down modes can

save considerable power when operating at less than

maximum sample rates0 Figures 12, 1ꢁa, and 1ꢁb show

the average supply current as a function of the sam-

pling rate0 The following discussion illustrates the vari-

ous power-down sequences0

for one or four channel conversions utilizing full power-

down mode and internal-reference compensation0 A

±0±47µF bypass capacitor at REFADJ forms an RC filter

with the internal 2±kΩ reference resistor with a ±09ms

time constant0 To achieve full 12-bit accuracy, 1± time

constants or 9ms are required after power-up0 Waiting

this 9ms in FASTPD mode instead of in full power-up

can reduce power consumption by a factor of 1± or

more0 This is achieved by using the sequence shown in

Figure 140

Lowest Power at up to 500

Conversions/Channel/Second

The following examples show two different power-down

sequences0 Other combinations of clock rates, compen-

sation modes, and power-down modes may give lowest

power consumption in other applications0

AVERAGE SUPPLY CURRENT

vs. CONVERSION RATE

WITH EXTERNAL REFERENCE

10,000

AVERAGE SUPPLY CURRENT

vs. CONVERSION RATE

(USING FULLPD)

100

VREF = V = 3.0V

DD

= ∞

R

= ∞

LOAD

R

LOAD

CODE = 101010100000

1000

100

10

4 CHANNELS

10

1 CHANNEL

1

0.1

1

0.01

0.1

1

10 100 1k 10k 100k 1M

CONVERSION RATE (Hz)

0.1

1

10

100

1k

CONVERSION RATE (Hz)

Figure 12. Average Supply Current vs. Conversion Rate with

External Reference

Figure 13a. MAX1246 Supply Current vs. Conversion Rate,

FULLPD

AVERAGE SUPPLY CURRENT

vs. CONVERSION RATE

(USING FASTPD)

TYPICAL REFERENCE-BUFFER POWER-UP

DELAY vs. TIME IN SHUTDOWN

10,000

2.0

R

= ∞

LOAD

CODE = 101010100000

1000

100

1.5

1.0

4 CHANNELS

1 CHANNEL

10

1

0.5

0.0

0.1

1

10 100 1k 10k 100k 1M

CONVERSION RATE (Hz)

0.001

0.01

0.1

1

10

TIME IN SHUTDOWN (sec)

Figure 13b. MAX1246 Supply Current vs. Conversion Rate,

FASTPD

Figure 13c. Typical Reference-Buffer Power-Up Delay vs. Time

in Shutdown

18 ______________________________________________________________________________________

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

COMPLETE CONVERSION SEQUENCE

9ms WAIT

0 1

(ZEROS)

CH1

CH7

(ZEROS)

DIN

1

0 0

1

1 1

1

0 0

1

0 1

FULLPD

1.21V

FASTPD

NOPD

FULLPD

FASTPD

REFADJ

VREF

0V

2.50V

0V

τ = RC = 20kΩ x C

REFADJ

t

≈ 200µs

BUFFEN

Figure 14. MAX1246 FULLPD/FASTPD Power-Up Sequence

Lowest Power at Higher Throughputs

Figure 1ꢁb shows the power consumption with

external-reference compensation in fast power-down,

with one and four channels converted0 The external

407µF compensation requires a 2±±µs wait after

power-up with one dummy conversion0 This circuit

combines fast multi-channel conversion with the lowest

power consumption possible0 Full power-down mode

may provide increased power savings in applications

where the MAX1246/MAX1247 are inactive for long

periods of time, but where intermittent bursts of

high-speed conversions are required0

+3.3V

24k

MAX1246

510k

100k

REFADJ

9

0.047µF

Figure 15. MAX1246 Reference-Adjust Circuit

Internal and External References

The MAX1246 can be used with an internal or external

reference voltage, whereas an external reference is

required for the MAX12470 An external reference can

be connected directly at VREF or at the REFADJ pin0

Table 5. Software Power-Down

and Clock Mode

An internal buffer is designed to provide 20.V at

VREF for both the MAX1246 and the MAX12470 The

MAX1246’s internally trimmed 1021V reference is buf-

fered with a 20±6 gain0 The MAX1247’s REFADJ pin is

also buffered with a 20±± gain to scale an external 102.V

reference at REFADJ to 20.V at VREF0

PD1

±

PD0

±

DEVICE MODE

Full Power-Down

Fast Power-Down

±

1

±

1

Internal Clock

External Clock

Internal Reference (MAX1246)

The MAX1246’s full-scale range with the internal refer-

ence is 20.V with unipolar inputs and ±102.V with bipo-

lar inputs0 The internal reference voltage is adjustable

to ±10.% with the circuit in Figure 1.0

Table 6. Hard-Wired Power-Down

and Internal Clock Frequency

REFERENCE

BUFFER

COMPENSATION FREQUENCY

INTERNAL

CLOCK

DEVICE

MODE

SHDN

STATE

External Reference

With both the MAX1246 and MAX1247, an external ref-

erence can be placed at either the input (REFADJ) or

the output (VREF) of the internal reference-buffer ampli-

fier0 The REFADJ input impedance is typically 2±kΩ for

the MAX1246, and higher than 1±±kΩ for the MAX12470

1

Floating

±

Enabled

Internal

External

N/A

22.kHz

10ꢀMHz

N/A

Power-Down

______________________________________________________________________________________ 19

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

At VREF, the DC input resistance is a minimum of 1ꢀkΩ0

During conversion, an external reference at VREF must

deliver up to ꢁ.±µA DC load current and have 1±Ω or

less output impedance0 If the reference has a higher

output impedance or is noisy, bypass it close to the

VREF pin with a 407µF capacitor0

OUTPUT CODE

FULL-SCALE

TRANSITION

11 . . . 111

11 . . . 110

11 . . . 101

Using the REFADJ input makes buffering the external

reference unnecessary0 To use the direct VREF input,

disable the internal buffer by tying REFADJ to V 0 In

DD

FS = VREF + COM

ZS = COM

power-down, the input bias current to REFADJ can be

as much as 2.µA with REFADJ tied to V 0 Pull

DD

REFADJ to AGND to minimize the input bias current in

power-down0

VREF

4096

1LSB =

00 . . . 011

00 . . . 010

Transfer Function

Table 7 shows the full-scale voltage ranges for unipolar

and bipolar modes0

00 . . . 001

00 . . . 000

The external reference must have a temperature coeffi-

cient of 4ppm/°C or less to achieve accuracy to within

1LSB over the ±°C to +7±°C commercial temperature

range0

0

1

2

3

FS

(COM)

FS - 3/2LSB

INPUT VOLTAGE (LSB)

Figure 16. Unipolar Transfer Function, Full Scale (FS) = VREF

+ COM, Zero Scale (ZS) = COM

Figure 16 depicts the nominal, unipolar input/output

(I/O) transfer function, and Figure 17 shows the bipolar

input/output transfer function0 Code transitions occur

halfway between successive-integer LSB values0

Output coding is binary, with 1LSB = 61±µV (20.V /

4±96) for unipolar operation, and 1LSB = 61±µV [(20.V /

2 - -20.V / 2) / 4±96] for bipolar operation0

supply should be low impedance and as short as

possible0

High-frequency noise in the V

power supply may

DD

affect the high-speed comparator in the ADC0 Bypass

the supply to the star ground with ±01µF and 1µF

capacitors close to pin 1 of the MAX1246/MAX12470

Minimize capacitor lead lengths for best supply-noise

rejection0 If the power supply is very noisy, a 1±Ω resis-

tor can be connected as a lowpass filter (Figure 1ꢀ)0

Layout, Grounding, and Bypassing

For best performance, use printed circuit boards0

Wire-wrap boards are not recommended0 Board layout

should ensure that digital and analog signal lines are

separated from each other0 Do not run analog and digi-

tal (especially clock) lines parallel to one another, or

digital lines underneath the ADC package0

High-Speed Digital Interfacing with QSPI

The MAX1246/MAX1247 can interface with QSPI using

the circuit in Figure 19 (f

= 20±MHz, CPOL = ±,

SCLK

Figure 1ꢀ shows the recommended system ground

connections0 Establish a single-point analog ground

(star ground point) at AGND, separate from the logic

ground0 Connect all other analog grounds and DGND

to the star ground0 No other digital system ground

should be connected to this ground0 For lowest-noise

operation, the ground return to the star ground’s power

CPHA = ±)0 This QSPI circuit can be programmed to do a

conversion on each of the four channels0 The result is

stored in memory without taxing the CPU, since QSPI

incorporates its own microsequencer0

The MAX1246/MAX1247 are QSPI compatible up to its

maximum external clock frequency of 2MHz0

Table 7. Full Scale and Zero Scale

UNIPOLAR MODE

BIPOLAR MODE

Positive

Full Scale

Zero

Scale

Negative

Full Scale

Zero Scale

COM

VREF / 2

+ COM

-VREF / 2

+ COM

VREF + COM

COM

20 ______________________________________________________________________________________

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

OUTPUT CODE

VREF

2

FS

=

+ COM

011 . . . 111

011 . . . 110

SUPPLIES

ZS = COM

+3V

GND

-VREF

2

-FS =

000 . . . 010

000 . . . 001

000 . . . 000

VREF

4096

1LSB =

R* = 10Ω

111 . . . 111

111 . . . 110

111 . . . 101

V

DD

AGND

COM DGND

+3V

DGND

100 . . . 001

100 . . . 000

DIGITAL

CIRCUITRY

MAX1246

MAX1247

COM*

- FS

+FS - 1LSB

*OPTIONAL

INPUT VOLTAGE (LSB)

≤

*COM VREF / 2

Figure 18. Power-Supply Grounding Connection

Figure 17. Bipolar Transfer Function, Full Scale (FS) =

VREF / 2 + COM, Zero Scale (ZS) = COM

4) The MAX1246/MAX1247’s SSTRB output is moni-

tored via the TMSꢁ2±’s FSR input0 A falling edge on

the SSTRB output indicates that the conversion is in

progress and data is ready to be received from the

MAX1246/MAX12470

TMS320LC3x Interface

Figure 2± shows an application circuit to interface the

MAX1246/MAX1247 to the TMSꢁ2± in external clock

mode0 The timing diagram for this interface circuit is

shown in Figure 210

.) The TMSꢁ2± reads in one data bit on each of the

next 16 rising edges of SCLK0 These data bits rep-

resent the 12-bit conversion result followed by four

trailing bits, which should be ignored0

Use the following steps to initiate a conversion in the

MAX1246/MAX1247 and to read the results:

1) The TMSꢁ2± should be configured with CLKX

(transmit clock) as an active-high output clock and

CLKR (TMSꢁ2± receive clock) as an active-high

input clock0 CLKX and CLKR on the TMSꢁ2± are

tied together with the MAX1246/MAX1247’s SCLK

input0

6) Pull CS high to disable the MAX1246/MAX1247 until

the next conversion is initiated0

2) The MAX1246/MAX1247’s CS pin is driven low by

the TMSꢁ2±’s XF_ I/O port to enable data to be

clocked into the MAX1246/MAX1247’s DIN0

ꢁ) An ꢀ-bit word (1XXXXX11) should be written to the

MAX1246/MAX1247 to initiate a conversion and

place the device into external clock mode0 Refer to

Table 1 to select the proper XXXXX bit values for

your specific application0

______________________________________________________________________________________ 21

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

+3V

(POWER SUPPLIES)

1µF

16

15

14

13

12

11

10

9

SCK

1

2

3

4

5

6

7

8

V

DD

SCLK

CS

0.1µF

PCS0

CH0

MAX1246

MAX1247

CH1

DIN

MOSI

ANALOG

INPUTS

MC683XX

CH2

SSTRB

DOUT

MISO

CH3

COM

SHDN

VREF

DGND

AGND

+2.5V

REFADJ

0.1µF

(GND)

Figure 19. MAX1246/MAX1247 QSPI Connections, External Reference

XF

CLKX

CLKR

DX

CS

SCLK

TMS320LC3x

MAX1246

MAX1247

DIN

DR

DOUT

SSTRB

FSR

Figure 20. MAX1246/MAX1247-to-TMS320 Serial Interface

22 ______________________________________________________________________________________

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

CS

SCLK

DIN

START

SEL2

SEL1

SEL0

UNI/BIP SGL/DIF

PD1

PD0

HIGH

IMPEDANCE

SSTRB

HIGH

IMPEDANCE

DOUT

MSB

B10

B1

LSB

Figure 21. TMS320 Serial-Interface Timing Diagram

_Ordering Information (continued)

__________________Pin Configuration

INL

(LSB)

PART^†

TEMP RANGE PIN-PACKAGE

TOP VIEW

1

2

3

4

5

6

7

8

16

15

14

13

12

V

SCLK

CS

DD

MAX1246AEPE -4±°C to +ꢀ.°C

MAX1246BEPE -4±°C to +ꢀ.°C

MAX1246AEEE -4±°C to +ꢀ.°C

MAX1246BEEE -4±°C to +ꢀ.°C

16 Plastic DIP

16 QSOP

±1/2

±1

CH0

CH1

DIN

±1/2

±1

CH2

MAX1246

MAX1247

SSTRB

DOUT

16 QSOP

MAX1246AMJE -..°C to +12.°C 16 CERDIP*

MAX1246BMJE -..°C to +12.°C 16 CERDIP*

±1/2

±1

CH3

COM

SHDN

VREF

11 DGND

MAX1247ACPE ±°C to +7±°C

16 Plastic DIP

16 QSOP

±1/2

±1

10

9

AGND

MAX1247BCPE

MAX1247ACEE

MAX1247BCEE

±°C to +7±°C

REFADJ

±1/2

±1

16 QSOP

DIP/QSOP

MAX1247CCEE -±°C to +7±°C

MAX1247AEPE -4±°C to +ꢀ.°C

MAX1247BEPE -4±°C to +ꢀ.°C

MAX1247AEEE -4±°C to +ꢀ.°C

MAX1247BEEE -4±°C to +ꢀ.°C

MAX1247CEEE -4±°C to +ꢀ.°C

16 QSOP

±2

16 Plastic DIP

16 QSOP

±1/2

±1

±1/2

±1

___________________Chip Information

16 QSOP

±2

TRANSISTOR COUNT: 2..4

MAX1247AMJE -..°C to +12.°C 16 CERDIP*

MAX1247BMJE -..°C to +12.°C 16 CERDIP*

±1/2

±1

* Contact factory for availability of CERDIP package, and for

processing to MIL-STD-883B.

______________________________________________________________________________________ 23

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

________________________________________________________Package Information

24 ______________________________________________________________________________________

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

___________________________________________Package Information (continued)

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25

Printed USA

is a registered trademark of Maxim Integrated Products0


型号：	MAX1247
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	+2.7V.Low-Power.4-Channel.Serial 12-Bit ADCs in QSOP-16 + 2.7V.Low - Power.4 - Channel.Serial 12位ADC的QSOP -16\n
文件：	总25页 (文件大小：343K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX1247 [MAXIM]

相关型号：

MAX1247ACEE

MAX1247ACPE

MAX1247ACPE+

MAX1247AEEE

MAX1247AEEE+

MAX1247AEEE+T

MAX1247AEEE-T

MAX1247AEPE

MAX1247AMJE

MAX1247BCEE

MAX1247BCEE+

MAX1247BCEE-T