MAX1220BETX-T [MAXIM]
Analog Circuit, 1 Func, BICMOS, 6 X 6 MM, 0.80 MM HEIGHT, TQFN-36;
| 型号： | MAX1220BETX-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Analog Circuit, 1 Func, BICMOS, 6 X 6 MM, 0.80 MM HEIGHT, TQFN-36 信息通信管理 |
| 文件： | 总47页 (文件大小：983K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3295; Rev 3; 11/04
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
General Description
Features
The MAX1220–MAX1223/MAX1257/MAX1258 integrate a
12-bit, multichannel, analog-to-digital converter (ADC),
and a 12-bit, octal, digital-to-analog converter (DAC) in a
single IC. These devices also include a temperature sen-
sor and configurable general-purpose I/O ports (GPIOs)
with a 25MHz SPI™-/QSPI™-/MICROWIRE™-compatible
serial interface. The ADC is available in 8/12/16 input-
channel versions. The octal DAC outputs settle within
2.0µs and the ADC has a 300ksps conversion rate.
♦ 12-Bit, 300ksps ADC
Analog Multiplexer with True-Differential
Track/Hold (T/H)
16 Single-Ended Channels or 8 Differential
Channels (Unipolar or Bipolar)
12 Single-Ended Channels or 6 Differential
Channels (Unipolar or Bipolar)
8 Single-Ended Channels or 4 Differential
Channels (Unipolar or Bipolar)
Excellent Accuracy: 0ꢀ. ꢁSB ꢂIꢁ, 0ꢀ. ꢁSB DIꢁ
All devices include an internal reference (2.5V or
4.096V) for both the ADC and DAC. Programmable ref-
erence modes allow the use of an internal reference, an
external reference, or a combination of both. Features
such as an internal 1°C accurate temperature sensor,
FIFO, scan modes, programmable internal or external
clock modes, data averaging, and AutoShutdown™
allow users to minimize power consumption and proces-
sor requirements. The low glitch energy (4nV•s) and low
digital feedthrough (0.5nV•s) of the integrated octal
DACs make these devices ideal for digital control of
fast-response closed-loop systems.
♦ 12-Bit, Octal, 2µs Settling DAC
Ultra-ꢁow Glitch Energy (4nV•s)
Power-Up Options from Zero Scale or Full Scale
Excellent Accuracy: 0ꢀ. ꢁSB ꢂIꢁ
♦ ꢂnternal Reference or External Single-Ended/
Differential Reference
ꢂnternal Reference Voltage 2ꢀ.V or 4ꢀ096V
♦ ꢂnternal 1ꢃC Accurate Temperature Sensor
♦ On-Chip FꢂFO Capable of Storing 16 ADC
Conversion Results and One Temperature Result
♦ On-Chip Channel-Scan Mode and ꢂnternal
The devices are guaranteed to operate with a supply volt-
age from +2.7V to +3.6V (MAX1221/MAX1223/MAX1257)
and from +4.75V to +5.25V (MAX1220/MAX1222/
MAX1258). These devices consume 2.5mA at 300ksps
throughput, only 22µA at 1ksp throughput, and under
0.2µA in the shutdown mode. The MAX1257/MAX1258
feature 12 GPIOs, while the MAX1220/MAX1221 offer 4
GPIOs that can be configured as inputs or outputs.
The MAX1220–MAX1223 are available in 36-pin thin
QFN packages. The MAX1257/MAX1258 are available
in 48-pin thin QFN packages. All devices are specified
over the -40°C to +85°C temperature range.
Data-Averaging Features
♦ Analog Single-Supply Operation
+2ꢀ7V to +3ꢀ6V or +4ꢀ7.V to +.ꢀ2.V
♦ 2.MHz, SPꢂ/QSPꢂ/MꢂCROWꢂRE Serial ꢂnterface
♦ AutoShutdown Between Conversions
♦ ꢁow-Power ADC
2ꢀ.mA at 300ksps
22µA at 1ksps
0ꢀ2µA at Shutdown
♦ ꢁow-Power DAC: 1ꢀ.µA
♦ Evaluation Kit Available (Order MAX12.8EVKꢂT)
Applications
Controls for Optical Components
Base-Station Control Loops
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
System Supervision and Control
Data-Acquisition Systems
Ordering Information/Selector Guide
REF
VOꢁTAGE
(V)
AIAꢁOG
SUPPꢁY
VOꢁTAGE (V)
RESOꢁUTꢂOI
BꢂTS***
ADC
DAC
PART
TEMP RAIGE PꢂI-PACKAGE
GPꢂOs
CHAIIEꢁS CHAIIEꢁS
MAX1220BETX -40°C to +85°C 36 Thin QFN-EP**
MAX1221BETX -40°C to +85°C 36 Thin QFN-EP**
MAX1222BETX* -40°C to +85°C 36 Thin QFN-EP**
MAX1223BETX* -40°C to +85°C 36 Thin QFN-EP**
MAX12.7BETM -40°C to +85°C 48 Thin QFN-EP**
MAX12.8BETM -40°C to +85°C 48 Thin QFN-EP**
4.096
2.5
4.75 to 5.25
2.7 to 3.6
12
12
12
12
12
12
8
8
8
8
8
8
8
4
4
8
4.096
2.5
4.75 to 5.25
2.7 to 3.6
12
12
16
16
0
0
2.5
2.7 to 3.6
12
12
4.096
4.75 to 5.25
*Future product—contact factory for availability.
**EP = Exposed pad.
***Number of resolution bits refers to both DAC and ADC.
Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ABSOꢁUTE MAXꢂMUM RATꢂIGS
AV
to AGND .........................................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
DD
DGND to AGND.....................................................-0.3V to +0.3V
DV to AV .......................................................-3.0V to +0.3V
Digital Inputs to DGND.............................................-0.3V to +6V
36-Pin Thin QFN (6mm x 6mm)
(derate 26.3mW/°C above +70°C)......................2105.3mW
40-Pin Thin QFN (6mm x 6mm)
DD
DD
Digital Outputs to DGND .........................-0.3V to (DV + 0.3V)
Analog Inputs, Analog Outputs and REF_
(derate 26.3mW/°C above +70°C)......................2105.3mW
48-Pin Thin QFN (7mm x 7mm)
DD
to AGND...............................................-0.3V to (AV + 0.3V)
(derate 26.3mW/°C above +70°C)......................2105.3mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
DD
Maximum Current into Any Pin (except AGND, DGND, AV
,
DD
DV , and OUT_) ...........................................................50mA
DD
Maximum Current into OUT_.............................................100mA
Iote: If the package power dissipation is not exceeded, one output at a time may be shorted to AV , DV , AGND, or DGND
DD
DD
indefinitely.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS
(AV
= DV
= 2.7V to 3.6V (MAX1221/MAX1223/MAX1257), external reference V
= 2.5V (MAX1221/MAX1223/MAX1257), AV
=
DD
DD
REF
DD
DV = 4.75V to 5.25V (MAX1220/MAX1222/MAX1258), external reference V
= 4.096V (MAX1220/MAX1222/MAX1258), f
= 4.8MHz
DD
REF
SCLK
(50% duty cycle), T = -40°C to +85°C, unless otherwise noted. Typical values are at AV = DV = 3V (MAX1221/MAX1223/MAX1257),
A
DD
DD
AV = DV = 5V (MAX1220/MAX1222/MAX1258), T = +25°C. Outputs are unloaded, unless otherwise noted.)
DD
DD
A
PARAMETER
SYMBOꢁ
COIDꢂTꢂOIS
ADC
MꢂI
TYP
MAX
UIꢂTS
DC ACCURACY (Note 1)
Resolution
12
Bits
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
0.5
0.5
1
1.0
1.0
4.0
4.0
DNL
LSB
LSB
Gain Error
(Note 2)
0.1
0.8
0.1
LSB
Gain Temperature Coefficient
Channel-to-Channel Offset
ppm/°C
LSB
DYIAMꢂC SPECꢂFꢂCATꢂOIS (10kHz sine wave input, V = 2ꢀ.V
(MAX1221/MAX1223/MAX12.7), V = 4ꢀ096V
ꢂI P-P
ꢂI
P-P
(MAX1220/MAX1222/MAX12.8), 300ksps, f
= 4ꢀ8MHz)
SCꢁK
Signal-to-Noise Plus Distortion
SINAD
70
-76
72
dB
Total Harmonic Distortion
(Up to the Fifth Harmonic)
THD
dBc
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Linear Bandwidth
SFDR
IMD
dBc
dBc
kHz
f
= 9.9kHz, f = 10.2kHz
76
100
1
in1
in2
SINAD > 70dB
-3dB point
Full-Power Bandwidth
MHz
COIVERSꢂOI RATE (Note 3)
External reference
0.8
µs
Conversion
clock
Power-Up Time
t
PU
Internal reference (Note 4)
218
cycles
2
_______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS (continued)
(AV
= DV
= 2.7V to 3.6V (MAX1221/MAX1223/MAX1257), external reference V
= 2.5V (MAX1221/MAX1223/MAX1257), AV
=
DD
DD
REF
DD
DV = 4.75V to 5.25V (MAX1220/MAX1222/MAX1258), external reference V
= 4.096V (MAX1220/MAX1222/MAX1258), f
= 4.8MHz
DD
REF
SCLK
(50% duty cycle), T = -40°C to +85°C, unless otherwise noted. Typical values are at AV = DV = 3V (MAX1221/MAX1223/MAX1257),
A
DD
DD
AV = DV = 5V (MAX1220/MAX1222/MAX1258), T = +25°C. Outputs are unloaded, unless otherwise noted.)
DD
DD
A
PARAMETER
SYMBOꢁ
COIDꢂTꢂOIS
MꢂI
TYP
3.5
MAX
UIꢂTS
Acquisition Time
t
(Note 5)
0.6
µs
ACQ
Internally clocked
Conversion Time
t
µs
CONV
Externally clocked
2.7
Internal Clock Frequency
External Clock Frequency
Duty Cycle
Internally clocked conversion
Externally clocked conversion (Note 5)
4.3
MHz
MHz
%
f
0.1
40
4.8
60
CLK
Aperture Delay
30
ns
Aperture Jitter
<50
ps
AIAꢁOG ꢂIPUTS
Unipolar
Bipolar
0
V
REF
Input Voltage Range (Note 6)
V
-V
/2
V
/2
REF
REF
Input Leakage Current
Input Capacitance
0.01
24
1
µA
pF
ꢂITERIAꢁ TEMPERATURE SEISOR
T
T
= +25°C
0.7
1.0
1/8
A
A
Measurement Error (Notes 5, 7)
°C
= T
to T
3.0
MIN
MAX
Temperature Resolution
°C/LSB
ꢂITERIAꢁ REFEREICE
MAX1221/MAX1223/MAX1257
MAX1220/MAX1222/MAX1258
2.482
4.066
2.50
2.518
4.126
REF1 Output Voltage (Note 8)
V
4.096
REF1 Voltage Temperature
Coefficient
TC
30
ppm/°C
kΩ
REF
REF1 Output Impedance
REF1 Short-Circuit Current
EXTERIAꢁ REFEREICE
6.5
V
V
= 2.5V
0.39
0.63
REF
REF
mA
= 4.096V
AV
0.05
+
DD
REF1 Input Voltage Range
V
V
REF mode 11 (Note 4)
1
V
V
REF1
REF2
AV
0.05
+
DD
REF mode 01
REF mode 11
1
0
REF2 Input Voltage Range
(Note 4)
1
_______________________________________________________________________________________
3
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS (continued)
(AV
= DV
= 2.7V to 3.6V (MAX1221/MAX1223/MAX1257), external reference V
= 2.5V (MAX1221/MAX1223/MAX1257), AV
=
DD
DD
REF
DD
DV = 4.75V to 5.25V (MAX1220/MAX1222/MAX1258), external reference V
= 4.096V (MAX1220/MAX1222/MAX1258), f
= 4.8MHz
DD
REF
SCLK
(50% duty cycle), T = -40°C to +85°C, unless otherwise noted. Typical values are at AV = DV = 3V (MAX1221/MAX1223/MAX1257),
A
DD
DD
AV = DV = 5V (MAX1220/MAX1222/MAX1258), T = +25°C. Outputs are unloaded, unless otherwise noted.)
DD
DD
A
PARAMETER
SYMBOꢁ
COIDꢂTꢂOIS
MꢂI
TYP
MAX
UIꢂTS
V
= 2.5V
REF
(MAX1221/MAX1223/MAX1257),
= 300ksps
25
80
f
SAMPLE
REF1 Input Current (Note 9)
I
µA
REF1
V
= 4.096V
REF
(MAX1220/MAX1222/MAX1258),
= 300ksps
40
80
1
f
SAMPLE
Acquisition between conversions
0.01
25
V
= 2.5V
REF
(MAX1221/MAX1223/MAX1257),
= 300ksps
80
f
SAMPLE
REF2 Input Current
I
µA
REF2
V
= 4.096V
REF
(MAX1220/MAX1222/MAX1258),
= 300ksps
40
80
1
f
SAMPLE
Acquisition between conversions
0.01
DAC
DC ACCURACY (Note 10)
Resolution
12
Bits
LSB
LSB
mV
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
DNL
0.5
4
Guaranteed monotonic
(Note 8)
1.0
10
V
3
10
5
OS
ppm of
FS/°C
Offset-Error Drift
Gain Error
GE
(Note 8)
10
LSB
ppm of
FS/°C
Gain Temperature Coefficient
DAC OUTPUT
8
AV
0.02
-
-
DD
No load
0.02
0.1
Output-Voltage Range
V
AV
0.1
DD
10kΩ load to either rail
DC Output Impedance
Capacitive Load
0.5
Ω
(Note 11)
1
nF
AV
= 2.7V, V
= 2.5V
DD
REF
(MAX1221/MAX1223/MAX1257),
gain error < 1%
2000
500
Resistive Load to AGND
R
L
Ω
AV
= 4.75V, V
= 4.096V
DD
REF
(MAX1220/MAX1222/MAX1258),
gain error < 2%
4
_______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS (continued)
(AV
= DV
= 2.7V to 3.6V (MAX1221/MAX1223/MAX1257), external reference V
= 2.5V (MAX1221/MAX1223/MAX1257), AV
=
DD
DD
REF
DD
DV = 4.75V to 5.25V (MAX1220/MAX1222/MAX1258), external reference V
= 4.096V (MAX1220/MAX1222/MAX1258), f
= 4.8MHz
DD
REF
SCLK
(50% duty cycle), T = -40°C to +85°C, unless otherwise noted. Typical values are at AV = DV = 3V (MAX1221/MAX1223/MAX1257),
A
DD
DD
AV = DV = 5V (MAX1220/MAX1222/MAX1258), T = +25°C. Outputs are unloaded, unless otherwise noted.)
DD
DD
A
PARAMETER
SYMBOꢁ
COIDꢂTꢂOIS
MꢂI
TYP
25
21
1
MAX
UIꢂTS
µs
From power-down mode, AV
From power-down mode, AV
= 5V
DD
Wake-Up Time (Note 12)
1kΩ Output Termination
100kΩ Output Termination
= 2.7V
DD
Programmed in power-down mode
kΩ
At wake-up or programmed in
power-down mode
100
kΩ
DYIAMꢂC PERFORMAICE (Notes 5, 13)
Output-Voltage Slew Rate
Output-Voltage Settling Time
Digital Feedthrough
SR
Positive and negative
3
V/µs
µs
t
To 1 LSB, 400 - C00 hex (Note 7)
Code 0, all digital inputs from 0 to DV
2
5
S
0.5
nV•s
DD
Major Code Transition Glitch
Impulse
Between codes 2047 and 2048
4
nV•s
From V
660
720
260
320
REF
Output Noise (0.1Hz to 50MHz)
Output Noise (0.1Hz to 500kHz)
µV
µV
P-P
P-P
Using internal reference
From V
REF
Using internal reference
DAC-to-DAC Transition
Crosstalk
0.5
nV•s
ꢂITERIAꢁ REFEREICE
REF1 Output Voltage (Note 8)
REF1 Temperature Coefficient
REF1 Short-Circuit Current
MAX1221/MAX1223/MAX1257
MAX1220/MAX1222/MAX1258
2.482
4.066
2.5
4.096
30
2.518
4.126
V
TC
ppm/°C
mA
REF
V
V
= 2.5V
0.39
0.63
REF
REF
= 4.096V
EXTERIAꢁ-REFEREICE ꢂIPUT
REF1 Input Voltage Range
REF1 Input Impedance
V
R
REF modes 01, 10, and 11 (Note 4)
0.7
70
AV
V
REF1
DD
100
130
kΩ
REF1
DꢂGꢂTAꢁ ꢂITERFACE
DꢂGꢂTAꢁ ꢂIPUTS (SCꢁK, DꢂI, CS, CNVST, LDAC)
Input-Voltage High
V
DV = 2.7V to 5.25V
2.4
V
V
IH
DD
DV = 3.6V to 5.25V
0.8
0.6
10
DD
Input-Voltage Low
V
IL
DV = 2.7V to 3.6V
DD
Input Leakage Current
Input Capacitance
I
0.01
15
µA
pF
L
C
IN
DꢂGꢂTAꢁ OUTPUT (DOUT) (Note 14)
Output-Voltage Low
V
I
= 2mA
SINK
0.4
V
OL
_______________________________________________________________________________________
.
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS (continued)
(AV
= DV
= 2.7V to 3.6V (MAX1221/MAX1223/MAX1257), external reference V
= 2.5V (MAX1221/MAX1223/MAX1257), AV
=
DD
DD
REF
DD
DV = 4.75V to 5.25V (MAX1220/MAX1222/MAX1258), external reference V
= 4.096V (MAX1220/MAX1222/MAX1258), f
= 4.8MHz
DD
REF
SCLK
(50% duty cycle), T = -40°C to +85°C, unless otherwise noted. Typical values are at AV = DV = 3V (MAX1221/MAX1223/MAX1257),
A
DD
DD
AV = DV = 5V (MAX1220/MAX1222/MAX1258), T = +25°C. Outputs are unloaded, unless otherwise noted.)
DD
DD
A
PARAMETER
SYMBOꢁ
COIDꢂTꢂOIS
= 2mA
MꢂI
TYP
MAX
10
UIꢂTS
DV
-
-
DD
Output-Voltage High
V
I
V
OH
SOURCE
0.5
Tri-State Leakage Current
Tri-State Output Capacitance
DꢂGꢂTAꢁ OUTPUT (EOC) (Note 14)
Output-Voltage Low
µA
pF
C
15
OUT
V
I
I
= 2mA
0.4
10
V
V
OL
SINK
DV
DD
Output-Voltage High
V
= 2mA
SOURCE
OH
0.5
Tri-State Leakage Current
µA
pF
Tri-State Output Capacitance
C
15
OUT
DꢂGꢂTAꢁ OUTPUTS (GPꢂO_) (Note 14)
I
I
= 2mA
0.4
0.8
SINK
GPIOB_, GPIOC_ Output-
Voltage Low
V
= 4mA
SINK
GPIOB_, GPIOC_ Output-
Voltage High
DV
0.5
-
-
DD
I
I
I
= 2mA
V
V
V
SOURCE
GPIOA_ Output-Voltage Low
GPIOA_ Output-Voltage High
Tri-State Leakage Current
= 15mA
0.8
10
SINK
DV
0.8
DD
= 15mA
SOURCE
µA
pF
Tri-State Output Capacitance
C
15
OUT
POWER REQUꢂREMEITS (Note 15)
Digital Positive-Supply Voltage
DV
2.70
AV
V
DD
DD
Idle, all blocks shut down
0.2
1
4
µA
mA
Digital Positive-Supply Current
DI
AV
DD
Only ADC on, external reference
MAX1221/MAX1223/MAX1257
MAX1220/MAX1222/MAX1258
Idle, all blocks shut down
2.7
3.6
5.25
2
Analog Positive-Supply Voltage
Analog Positive-Supply Current
V
DD
4.75
0.2
2.8
2.6
1.5
µA
f
f
= 300ksps
= 100ksps
4.2
SAMPLE
SAMPLE
Only ADC on,
external reference
A
IDD
mA
All DACs on, no load, internal reference
4
AV = 2.7V (MAX1221/MAX1223/
MAX1257)
DD
-77
-80
0.1
0.1
REF1 Positive-Supply Rejection
DAC Positive-Supply Rejection
PSRR
PSRD
dB
AV = 4.75V (MAX1220/MAX1222/
DD
MAX1258)
MAX1221/MAX1223/MAX1257
0.5
0.5
Output
code =
FFFhex
AV
= 2.7V to 3.6V
DD
mV
MAX1220/MAX1222/MAX1258
AV = 4.75V to 5.25V
DD
6
_______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS (continued)
(AV
= DV
= 2.7V to 3.6V (MAX1221/MAX1223/MAX1257), external reference V
= 2.5V (MAX1221/MAX1223/MAX1257), AV
=
DD
DD
REF
DD
DV = 4.75V to 5.25V (MAX1220/MAX1222/MAX1258), external reference V
= 4.096V (MAX1220/MAX1222/MAX1258), f
= 4.8MHz
DD
REF
SCLK
(50% duty cycle), T = -40°C to +85°C, unless otherwise noted. Typical values are at AV = DV = 3V (MAX1221/MAX1223/MAX1257),
A
DD
DD
AV = DV = 5V (MAX1220/MAX1222/MAX1258), T = +25°C. Outputs are unloaded, unless otherwise noted.)
DD
DD
A
PARAMETER
SYMBOꢁ
COIDꢂTꢂOIS
MꢂI
TYP
MAX
UIꢂTS
MAX1221/MAX1223/MAX1257
0.06
0.5
Full-
scale
input
AV
= 2.7V to 3.6V
DD
ADC Positive-Supply Rejection
PSRA
mV
MAX1220/MAX1222/MAX1258
AV = 4.75V to 5.25V
0.06
0.5
DD
TꢂMꢂIG CHARACTERꢂSTꢂCS (Figures 6–13)
SCLK Clock Period
t
40
16
16
ns
ns
ns
CP
CH
SCLK Pulse-Width High
SCLK Pulse-Width Low
t
40/60 duty cycle
60/40 duty cycle
t
CL
GPIO Output Rise/Fall After
CS Rise
t
C
= 20pF
100
ns
GOD
LOAD
GPIO Input Setup Before CS Fall
LDAC Pulse Width
t
0
20
1.8
10
1.8
10
10
0
ns
ns
GSU
t
LDACPWL
C
C
C
C
= 20pF, SLOW = 0
= 20pF, SLOW = 1
= 20pF, SLOW = 0
= 20pF, SLOW = 1
12.0
40
LOAD
LOAD
LOAD
LOAD
SCLK Fall to DOUT Transition
(Note 16)
t
t
ns
ns
DOT
DOT
12.0
40
SCLK Rise to DOUT Transition
(Notes 16, 17)
CS Fall to SCLK Fall Setup Time
SCLK Fall to CS Rise Setup Time
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
CS Pulse-Width High
t
ns
ns
ns
ns
ns
ns
ns
ns
CSS
t
CSH
t
10
0
DS
t
DH
t
50
CSPWH
CS Rise to DOUT Disable
CS Fall to DOUT Enable
EOC Fall to CS Fall
t
C
C
= 20pF
= 20pF
25
DOD
LOAD
LOAD
t
1.5
30
25.0
DOE
t
RDS
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference on
55
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference
initially off
120
CS or CNVST Rise to EOC Fall
t
µs
DOV
CKSEL = 01 (voltage conversion)
8
8
CKSEL = 10 (voltage conversion),
internal reference on
CKSEL = 10 (voltage conversion),
internal reference initially off
80
CKSEL = 00, CKSEL = 01 (temp sense)
CKSEL = 01 (voltage conversion)
40
ns
µs
CNVST Pulse Width
t
CSW
1.4
_______________________________________________________________________________________
7
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS (continued)
(AV
= DV
= 2.7V to 3.6V (MAX1221/MAX1223/MAX1257), external reference V
= 2.5V (MAX1221/MAX1223/MAX1257), AV
=
DD
DD
REF
DD
DV = 4.75V to 5.25V (MAX1220/MAX1222/MAX1258), external reference V
= 4.096V (MAX1220/MAX1222/MAX1258), f
= 4.8MHz
DD
REF
SCLK
(50% duty cycle), T = -40°C to +85°C, unless otherwise noted. Typical values are at AV = DV = 3V (MAX1221/MAX1223/MAX1257),
A
DD
DD
AV = DV = 5V (MAX1220/MAX1222/MAX1258), T = +25°C. Outputs are unloaded, unless otherwise noted.)
DD
DD
A
Iote 1: Tested at DV = AV = +3.6V (MAX1221/MAX1223/MAX1257), DV = AV = +5.25V (MAX1220/MAX1222/MAX1258).
DD
DD
DD
DD
Iote 2: Offset nulled.
Iote 3: No bus activity during conversion. Conversion time is defined as the number of conversion clock cycles multiplied by the
clock period.
Iote 4: See Table 5 for reference-mode details.
Iote .: Not production tested. Guaranteed by design.
Iote 6: See the ADC/DAC References section.
Iote 7: Fast automated test, excludes self-heating effects.
Iote 8: Specified over the -40°C to +85°C temperature range.
Iote 9: REFSEL[1:0] = 00 or when DACs are not powered up.
Iote 10: DAC linearity, gain, and offset measurements are made between codes 115 and 3981.
Iote 11: The DAC buffers are guaranteed by design to be stable with a 1nF load.
Iote 12: Time required by the DAC output to power up and settle within 1 LSB in the external reference mode.
Iote 13: All DAC dynamic specifications are valid for a load of 100pF and 10kΩ.
Iote 14: Only one digital output (either DOUT, EOC, or the GPIOs) can be indefinitely shorted to either supply at one time.
Iote 1.: All digital inputs at either DV
or DGND. DV
should not exceed AV
.
DD
DD
DD
Iote 16: See the Reset Register section and Table 9 for details on programming the SLOW bit.
Iote 17: Clock mode 11 only.
Typical Operating Characteristics
(AV
= DV
= 3V (MAX1221/MAX1223/MAX1257), external V
= 2.5V (MAX1221/MAX1223/MAX1257), AV
= DV = 5V
DD
DD
DD
REF
DD
(MAX1220/MAX1222/MAX1258), external V
= 4.096V (MAX1220/MAX1222/MAX1258), f
= 4.8MHz (50% duty cycle), f
REF
CLK
SAMPLE
= 300ksps, C
= 50pF, 0.1µF capacitor at REF, T = +25°C, unless otherwise noted.)
LOAD
A
SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
SHUTDOWN CURRENT
vs. TEMPERATURE
SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
0.20
0.18
0.16
0.14
0.12
0.10
0.6
0.30
0.25
0.20
0.15
0.10
0.05
0
0.5
0.4
0.3
0.2
0.1
0
MAX1221/MAX1223/MAX1257
MAX1220/MAX1222/MAX1258
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
5.15
5.25
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
8
_______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics (continued)
(AV
= DV
= 3V (MAX1221/MAX1223/MAX1257), external V
= 2.5V (MAX1221/MAX1223/MAX1257), AV
= DV = 5V
DD
DD
DD
REF
DD
(MAX1220/MAX1222/MAX1258), external V
= 4.096V (MAX1220/MAX1222/MAX1258), f = 4.8MHz (50% duty cycle), f
CLK SAMPLE
REF
= 300ksps, C
= 50pF, 0.1µF capacitor at REF, T = +25°C, unless otherwise noted.)
LOAD
A
INTERNAL OSCILLATOR FREQUENCY
vs. ANALOG SUPPLY VOLTAGE
INTERNAL OSCILLATOR FREQUENCY
vs. ANALOG SUPPLY VOLTAGE
INTERNAL OSCILLATOR FREQUENCY
vs. TEMPERATURE
4.5
4.4
4.3
4.2
4.1
4.0
4.90
4.85
4.80
4.75
4.70
4.65
4.60
5.0
4.8
4.6
4.4
4.2
4.0
3.8
MAX1221/MAX1223/MAX1257
MAX1220/MAX1222/MAX1258
MAX1220/MAX1222/MAX1258
MAX1221/MAX1223/MAX1257
4.75
4.85
4.95
5.05
5.15
5.25
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
4096
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
MAX1220/MAX1222/MAX1258
MAX1221/MAX1223/MAX1257
MAX1221/MAX1223/MAX1257
0
1024
2048
3072
4096
0
1024
2048
3072
4096
0
1024
2048
3072
OUTPUT CODE
OUTPUT CODE
OUTPUT CODE
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
0
-1
-2
-3
-4
1.00
0.75
0.50
0.25
0
-0.50
-0.75
-1.00
-1.25
-1.50
-0.25
-0.50
-0.75
-1.00
MAX1221/MAX1223/MAX1257
MAX1221/MAX1223/MAX1257
MAX1220/MAX1222/MAX1258
2.7
3.0
3.3
0
1024
2048
3072
4096
4.75
4.85
4.95
5.05
5.15
5.25
SUPPLY VOLTAGE (V)
OUTPUT CODE
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
9
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics (continued)
(AV
= DV
= 3V (MAX1221/MAX1223/MAX1257), external V
= 2.5V (MAX1221/MAX1223/MAX1257), AV
= DV = 5V
DD
DD
DD
REF
DD
(MAX1220/MAX1222/MAX1258), external V
= 4.096V (MAX1220/MAX1222/MAX1258), f
= 4.8MHz (50% duty cycle), f
REF
CLK
SAMPLE
= 300ksps, C
= 50pF, 0.1µF capacitor at REF, T = +25°C, unless otherwise noted.)
LOAD
A
ADC GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
ADC GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
ADC OFFSET ERROR
vs. TEMPERATURE
0.2
0.1
1.7
1
1.6
1.5
1.4
1.3
1.2
1.1
1.0
MAX1220/MAX1222/MAX1258
0
-1
-2
-3
-4
0
-0.1
-0.2
-0.3
MAX1220/MAX1222/MAX1258
MAX1221/MAX1223/MAX1257
10 35 60 85
MAX1221/MAX1223/MAX1257
4.75
4.85
4.95
5.05
5.15
5.25
2.7
3.0
3.3
3.6
-40
-15
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
ADC EXTERNAL REFERENCE
INPUT CURRENT vs. SAMPLING RATE
ADC GAIN ERROR
vs. TEMPERATURE
ANALOG SUPPLY CURRENT
vs. SAMPLING RATE
60
50
40
30
20
10
0
2.0
1.5
1.0
0.5
0
3.0
2.5
2.0
1.5
1.0
0.5
0
MAX1220/MAX1222/MAX1258
MAX1220/MAX1222/MAX1258
MAX1221/MAX1223/MAX1257
MAX1220/MAX1222/MAX1258
-0.5
-1.0
MAX1221/MAX1223/MAX1257
MAX1221/MAX1223/MAX1257
0
50
100
150
200
250
300
-40
-15
10
35
60
85
0
50
100
150
200
250
300
SAMPLING RATE (ksps)
TEMPERATURE (°C)
SAMPLING RATE (ksps)
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
2.7
2.6
2.5
2.4
2.3
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
MAX1221/MAX1223/MAX1257
MAX1220/MAX1222/MAX1258
MAX1220/MAX1222/MAX1258
-40
-15
10
35
60
85
2.7
3.0
3.3
3.6
4.75
4.85
4.95
5.05
5.15
5.25
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
10 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics (continued)
(AV
= DV
= 3V (MAX1221/MAX1223/MAX1257), external V
= 2.5V (MAX1221/MAX1223/MAX1257), AV
= DV = 5V
DD
DD
DD
REF
DD
(MAX1220/MAX1222/MAX1258), external V
= 4.096V (MAX1220/MAX1222/MAX1258), f = 4.8MHz (50% duty cycle), f
CLK SAMPLE
REF
= 300ksps, C
= 50pF, 0.1µF capacitor at REF, T = +25°C, unless otherwise noted.)
LOAD
A
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
DAC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
DAC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
2.16
2.15
2.14
2.13
2.12
2.11
2.10
1.5
1.0
0.5
0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-0.5
-1.0
-1.5
MAX1221/MAX1223/MAX1257
MAX1220/MAX1222/MAX1258
MAX1221/MAX1223/MAX1257
-40
-15
10
35
60
85
0
1024
2048
3072
4096
0
1024
2048
3072
4096
TEMPERATURE (°C)
OUTPUT CODE
OUTPUT CODE
DAC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
DAC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
DAC FULL-SCALE ERROR
vs. ANALOG SUPPLY VOLTAGE
0.4
0.2
0
0.4
0.2
0
0.20
0.16
0.12
0.08
0.04
0
-0.2
-0.4
-0.2
-0.4
MAX1220/MAX1222/MAX1258
MAX1221/MAX1223/MAX1257
MAX1220/MAX1222/MAX1258
2047
2050
2053
2056
2059
2062
2047
2050
2053
2056
2059
2062
4.75
4.85
4.95
5.05
5.15
5.25
OUTPUT CODE
OUTPUT CODE
SUPPLY VOLTAGE (V)
DAC FULL-SCALE ERROR
vs. ANALOG SUPPLY VOLTAGE
DAC FULL-SCALE ERROR
vs. TEMPERATURE
DAC FULL-SCALE ERROR
vs. TEMPERATURE
-2.1
-2.2
-2.3
-2.4
-2.5
5
4
0
-1
-2
-3
-4
-5
-6
-7
-8
3
EXTERNAL REFERENCE = 2.500V
INTERNAL REFERENCE
INTERNAL REFERENCE
2
EXTERNAL REFERENCE = 4.096V
1
0
-1
-2
MAX1221/MAX1223/MAX1257
MAX1220/MAX1222/MAX1258
MAX1221/MAX1223/MAX1257
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
______________________________________________________________________________________ 11
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics (continued)
(AV
= DV
= 3V (MAX1221/MAX1223/MAX1257), external V
= 2.5V (MAX1221/MAX1223/MAX1257), AV
= DV = 5V
DD
DD
DD
REF
DD
(MAX1220/MAX1222/MAX1258), external V
= 4.096V (MAX1220/MAX1222/MAX1258), f
= 4.8MHz (50% duty cycle), f
REF
CLK
SAMPLE
= 300ksps, C
= 50pF, 0.1µF capacitor at REF, T = +25°C, unless otherwise noted.)
LOAD
A
DAC FULL-SCALE ERROR
vs. LOAD CURRENT
DAC FULL-SCALE ERROR
vs. REFERENCE VOLTAGE
DAC FULL-SCALE ERROR
vs. REFERENCE VOLTAGE
5
1.00
0.75
0.50
0.25
0
0
-1
-2
-3
-4
-5
-6
-7
0
-5
-0.25
-0.50
-0.75
-1.00
-10
-15
MAX1220/MAX1222/MAX1258
MAX1220/MAX1222/MAX1258
MAX1221/MAX1223/MAX1257
0
5
10
15
20
25
30
0
1
2
3
4
5
0
0.5
1.0
1.5
2.0
2.5
3.0
LOAD CURRENT (mA)
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
DAC FULL-SCALE ERROR
vs. LOAD CURRENT
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
5
0
4.12
4.11
4.10
4.09
4.08
2.52
2.51
2.50
2.49
2.48
-5
-10
-15
MAX1221/MAX1223/MAX1257
MAX1220/MAX1222/MAX1258
MAX1221/MAX1223/MAX1257
0
0.5
1.0
1.5
2.0
2.5
3.0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
LOAD CURRENT (mA)
TEMPERATURE (°C)
TEMPERATURE (°C)
ADC REFERENCE SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
ADC REFERENCE SUPPLY CURRENT
vs. TEMPERATURE
ADC REFERENCE SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
43.0
42.8
42.6
42.4
42.2
42.0
50
48
46
44
42
40
25.8
25.7
25.6
25.5
25.4
MAX1220/MAX1222/MAX1258
MAX1221/MAX1223/MAX1257
MAX1220/MAX1222/MAX1258
4.75
4.85
4.95
5.05
5.15
5.25
-40
-15
10
35
60
85
2.7
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
12 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics (continued)
(AV
= DV
= 3V (MAX1221/MAX1223/MAX1257), external V
= 2.5V (MAX1221/MAX1223/MAX1257), AV
= DV
= 5V
DD
DD
REF
DD
DD
(MAX1220/MAX1222/MAX1258), external V
= 4.096V (MAX1220/MAX1222/MAX1258), f
= 4.8MHz (50% duty cycle), f
REF
CLK
SAMPLE
= 300ksps, C
= 50pF, 0.1µF capacitor at REF, T = +25°C, unless otherwise noted.)
LOAD
A
ADC REFERENCE SUPPLY CURRENT
vs. TEMPERATURE
ADC FFT PLOT
ADC IMD PLOT
0
-20
0
27.00
26.75
26.50
26.25
26.00
25.75
25.50
25.25
25.00
f
f
f
= 32.768kHz
= 10.080kHz
= 5.24288MHz
f
f
f
= 5.24288MHz
SAMPLE
ANALOG_)N
CLK
CLK
IN1
IN2
= 9.0kHz
= 11.0kHz
= -6dBFS
-20
SINAD = 71.27dBc
SNR = 71.45dBc
THD = 85.32dBc
SFDR = 87.25dBc
A
-40
-40
-60
IN
IMD = 82.99dBc
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
MAX1221/MAX1223/MAX1257
0
50
100
150
200
0
50
100
150
200
-40
-15
10
35
60
85
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
TEMPERATURE (°C)
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
ADC CROSSTALK PLOT
0
-20
2.08
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
f = 5.24288MHz
CLK
f = 10.080kHz
IN1
f = 8.0801kHz
IN2
2.07
2.06
2.05
2.04
2.03
2.02
2.01
2.00
SNR = 72.00dBc
THD = 85.24dBc
ENOB = 11.65 BITS
-40
-60
-80
-100
-120
-140
-160
SINKING
SINKING
SOURCING
SOURCING
DAC OUTPUT = MIDSCALE
MAX1220/MAX1222/MAX1258
DAC OUTPUT = MIDSCALE
MAX1221/MAX1223/MAX1257
0
50
100
150
200
-30
0
30
60
90
-30
-20
0
10
20
30
-10
ANALOG INPUT FREQUENCY (kHz)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
GPIO OUTPUT VOLTAGE
vs. SOURCE CURRENT
GPIO OUTPUT VOLTAGE
vs. SOURCE CURRENT
GPIO OUTPUT VOLTAGE
vs. SINK CURRENT
5
4
3
2
1
0
3.0
2.5
2.0
1.5
1.0
0.5
0
1500
1200
900
600
300
0
MAX1220/MAX1222/MAX1258
MAX1221/MAX1223/MAX1257
GPIOA0–A3 OUTPUTS
GPIOB0–B3, C0–C3
OUTPUTS
GPIOA0–A3 OUTPUTS
GPIOB0–B3, C0–C3
OUTPUTS
GPIOA0–A3 OUTPUTS
GPIOB0–B3,
C0–C3 OUTPUTS
MAX1220/MAX1222/MAX1258
0
20
40
60
80
100
0
20
40
60
80
100
0
20
40
60
80
100
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
SINK CURRENT (mA)
______________________________________________________________________________________ 13
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics (continued)
(AV
= DV
= 3V (MAX1221/MAX1223/MAX1257), external V
= 2.5V (MAX1221/MAX1223/MAX1257), AV
= DV = 5V
DD
DD
DD
REF
DD
(MAX1220/MAX1222/MAX1258), external V
= 4.096V (MAX1220/MAX1222/MAX1258), f
= 4.8MHz (50% duty cycle), f
REF
CLK
SAMPLE
= 300ksps, C
= 50pF, 0.1µF capacitor at REF, T = +25°C, unless otherwise noted.)
LOAD
A
GPIO OUTPUT VOLTAGE
vs. SINK CURRENT
TEMPERATURE SENSOR ERROR
vs. TEMPERATURE
DAC-TO-DAC CROSSTALK
R
= 10kΩ, C
= 100pF
LOAD
MAX1220 toc51
LOAD
1.00
0.75
0.50
0.25
0
1500
1200
900
600
300
0
GPIOB0–B3, C0–C3
OUTPUTS
V
OUTA
1V/div
-0.25
-0.50
-0.75
-1.00
V
OUTB
GPIOA0–A3 OUTPUTS
10mV/div
AC-COUPLED
MAX1221/MAX1223/MAX1257
MAX1221/MAX1223/MAX1257
-40
-15
10
35
60
85
0
10
20
30
40
50
60
100µs
TEMPERATURE (°C)
SINK CURRENT (mA)
DYNAMIC RESPONSE RISE TIME
= 10kΩ, C = 100pF
DYNAMIC RESPONSE RISE TIME
= 10kΩ, C = 100pF
DAC-TO-DAC CROSSTALK
= 10kΩ, C = 100pF
R
R
LOAD
R
LOAD
LOAD
LOAD
LOAD
LOAD
MAX1220 toc53
MAX1220 toc54
MAX1220 toc52
MAX1221/MAX1223/MAX1257
CS
2V/div
V
OUTA
2V/div
V
OUT
1V/div
V
OUTB
V
10mV/div
AC-COUPLED
OUT
CS
1V/div
2V/div
MAX1220/MAX1222/MAX1258
MAX1220/MAX1222/MAX1258
1µs
1µs
100µs
DYNAMIC RESPONSE FALL TIME
= 10kΩ, C = 100pF
DYNAMIC RESPONSE FALL TIME
= 10kΩ, C = 100pF
MAJOR CARRY TRANSITION
= 10kΩ, C = 100pF
R
R
LOAD
R
LOAD
LOAD
LOAD
LOAD
LOAD
MAX1220 toc55
MAX1220 toc56
MAX1220 toc57
MAX1221/MAX1223/MAX1257
CS
2V/div
CS
1V/div
V
OUT
1V/div
V
OUT
V
OUT
10mV/div
AC-COUPLED
CS
1V/div
2V/div
MAX1220/MAX1222/MAX1258
MAX1220/MAX1222/MAX1258
1µs
1µs
1µs
14 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics (continued)
(AV
= DV
= 3V (MAX1221/MAX1223/MAX1257), external V
= 2.5V (MAX1221/MAX1223/MAX1257), AV
= DV = 5V
DD
DD
DD
REF
DD
(MAX1220/MAX1222/MAX1258), external V
= 4.096V (MAX1220/MAX1222/MAX1258), f = 4.8MHz (50% duty cycle), f
CLK SAMPLE
REF
= 300ksps, C
= 50pF, 0.1µF capacitor at REF, T = +25°C, unless otherwise noted.)
LOAD
A
DAC DIGITAL FEEDTHROUGH R
= 10kΩ,
DAC DIGITAL FEEDTHROUGH R
= 10kΩ,
LOAD
MAJOR CARRY TRANSITION
= 10kΩ, C = 100pF
LOAD
C
LOAD
= 100pF, CS = HIGH, DIN = LOW
C
LOAD
= 100pF, CS = HIGH, DIN = LOW
R
LOAD
LOAD
MAX1220 toc60
MAX1220 toc59
MAX1220 toc58
SCLK
2V/div
CS
2V/div
SCLK
1V/div
V
V
OUT
V
OUT
OUT
100mV/div
AC-COUPLED
100mV/div
AC-COUPLED
20mV/div
AC-COUPLED
MAX1220/MAX1222/MAX1258
200ns
MAX1221/MAX1223/MAX1257
200ns
MAX1220/MAX1222/MAX1258
1µs
NEGATIVE FULL-SCALE SETTLING TIME
= 10kΩ, C = 100pF
NEGATIVE FULL-SCALE SETTLING TIME
POSITIVE FULL-SCALE SETTLING TIME
R
R
LOAD
= 10kΩ, C
= 100pF
R
LOAD
= 10kΩ, C
= 100pF
LOAD
MAX1220 toc63
LOAD
LOAD
LOAD
MAX1220 toc61
MAX1220 toc62
MAX1221/MAX1223/MAX1257
MAX1221/MAX1223/MAX1257
V
LDAC
V
OUT
2V/div
V
OUT_
1V/div
1V/div
V
OUT_
2V/div
V
LDAC
V
LDAC
1V/div
1V/div
MAX1220/MAX1222/MAX1258
1µs
2µs
1µs
ADC REFERENCE FEEDTHROUGH
= 10kΩ, C = 100pF
ADC REFERENCE FEEDTHROUGH
= 10kΩ, C = 100pF
POSITIVE FULL-SCALE SETTLING TIME
= 10kΩ, C = 100pF
R
R
LOAD
R
LOAD
LOAD
LOAD
LOAD
LOAD
MAX1220 toc65
MAX1220 toc66
MAX1220 toc64
V
REF2
V
REF2
1V/div
V
LDAC
2V/div
2V/div
V
OUT_
V
DAC-OUT
2V/div
V
DAC-OUT
10mV/div
2mV/div
AC-COUPLED
AC-COUPLED
MAX1221/MAX1223/MAX1257
MAX1220/MAX1222/MAX1258
MAX1220/MAX1222/MAX1258
ADC REFERENCE SWITCHING
ADC REFERENCE SWITCHING
200µs
200µs
1µs
______________________________________________________________________________________ 1.
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Pin Description
PꢂI
IAME
FUICTꢂOI
MAX1220/ MAX1222/ MAX12.7/
MAX1221 MAX1223 MAX12.8
1, 2
—
—
GPIOA0, GPIOA1 General-Purpose I/O A0, A1. GPIOA0, A1 can sink and source 15mA.
Active-Low End-of-Conversion Output. Data is valid after the falling edge of
EOC.
3
3
4
EOC
Digital Positive-Power Input. Bypass DV
to DGND with a 0.1µF
4
5
4
5
7
8
DV
DD
DD
DGND
Digital Ground. Connect DGND to AGND.
Serial-Data Output. Data is clocked out on the falling edge of the SCLK
clock in modes 00, 01, and 10. Data is clocked out on the rising edge of
the SCLK clock in mode 11. It is high impedance when CS is high.
6
6
9
DOUT
Serial-Clock Input. Clocks data in and out of the serial interface. (Duty
cycle must be 40% to 60%.) See Table 5 for details on programming the
clock mode.
7
8
7
8
10
11
SCLK
Serial-Data Input. DIN data is latched into the serial interface on the falling
edge of SCLK.
DIN
9–12,
16–19
9–12,
16–19
12–15,
22–25
OUT0–OUT7
DAC Outputs
Positive Analog Power Input. Bypass AV
Analog Ground
to AGND with a 0.1µF
13
14
13
14
18
19
AV
DD
DD
AGND
15, 23, 32,
33
2, 15, 24, 32
—
26
27
N.C.
No Connection. Not internally connected.
Active-Low Load DAC. LDAC is an asynchronous active-low input that
updates the DAC outputs. Drive LDAC low to make the DAC registers
transparent.
20
21
20
21
LDAC
CS
Active-Low Chip-Select Input. When CS is low, the serial interface is
enabled. When CS is high, DOUT is high impedance.
Reset Select. Select DAC wake-up mode. Set RES_SEL low to wake up the
DAC outputs with a 100kΩ resistor to GND or set RES_SEL high to wake
22
22
—
28
—
RES_SEL
up the DAC outputs with a 100kΩ resistor to V
power up the DAC input register to FFFh. Set RES_SEL low to power up the
DAC input register to 000h.
. Set RES_SEL high to
REF
24, 25
GPIOC0, GPIOC1 General-Purpose I/O C0, C1. GPIOC0, C1 can sink 4mA and source 2mA.
16 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Pin Description (continued)
PꢂI
IAME
FUICTꢂOI
MAX1220/ MAX1222/ MAX12.7/
MAX1221 MAX1223 MAX12.8
Reference 1 Input. Reference voltage; leave unconnected to use the
internal reference (2.5V for the MAX1221/MAX1223/MAX1257 or 4.096V for
the MAX1220/MAX1222/MAX1258). REF1 is the positive reference in ADC
external differential reference mode. Bypass REF1 to AGND with a 0.1µF
capacitor in external reference mode only. See the ADC/DAC References
section.
26
26
35
REF1
27–31, 34
35
—
—
—
—
AIN0–AIN5
REF2/AIN6
Analog Inputs
Reference 2 Input/Analog-Input Channel 6. See Table 5 for details on
programming the setup register.
Active-Low Conversion-Start Input/Analog Input 7. See Table 5 for details
on programming the setup register. REF2 is the negative reference in the
ADC external differential reference mode.
36
—
—
1
—
—
CNVST/AIN7
CNVST/AIN11
Active-Low Conversion-Start Input/Analog Input 11. See Table 5 for details
on programming the setup register.
23, 25,
27–31,
33, 34, 35
—
—
—
AIN0–AIN9
Analog Inputs
Reference 2 Input/Analog-Input Channel 10. See Table 5 for details on
programming the setup register. REF2 is the negative reference in the ADC
external differential reference mode.
36
—
1
REF2/AIN10
Active-Low Conversion-Start Input/Analog Input 15. See Table 5 for details
on programming the setup register.
—
—
—
—
—
—
CNVST/AIN15
2, 3, 5, 6 GPIOA0–GPIOA3 General-Purpose I/O A0–A3. GPIOA0–GPIOA3 can sink and source 15mA.
16, 17,
20, 21
General-Purpose I/O B0–B3. GPIOB0–GPIOB3 can sink 4mA and
source 2mA.
GPIOB0–GPIOB3
GPIOC0–GPIOC3
AIN0–AIN13
General-Purpose I/O C0–C3. GPIOC0–GPIOC3 can sink 4mA and
source 2mA.
—
—
—
—
29–32
33, 34,
36–47
Analog Inputs
Reference 2 Input/Analog-Input Channel 14. See Table 5 for details on
programming the setup register. REF2 is the negative reference in the ADC
external differential reference mode.
—
—
—
—
48
—
REF2/AIN14
EP
Exposed Paddle. Must be externally connected to AGND. Do not use as a
ground connect.
______________________________________________________________________________________ 17
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
the SCLK frequency of 25MHz or less, and set the
Detailed Description
clock polarity (CPOL) and phase (CPHA) in the µC con-
The MAX1220–MAX1223/MAX1257/MAX1258 integrate
trol registers to the same value. The MAX1220–
a 12-bit, multichannel, analog-to-digital converter
MAX1223/MAX1257/MAX1258 operate with SCLK idling
(ADC), and a 12-bit, octal, digital-to-analog converter
high or low, and thus operate with CPOL = CPHA = 0 or
(DAC) in a single IC. These devices also include a tem-
CPOL = CPHA = 1. Set CS low to latch any input data
perature sensor and configurable GPIOs with a 25MHz
at DIN on the falling edge of SCLK. Output data at
SPI-/QSPI-/MICROWIRE-compatible serial interface.
DOUT is updated on the falling edge of SCLK in clock
The ADC is available in 8/12/16 input-channel
modes 00, 01, and 10. Output data at DOUT is updated
versions. The octal DAC outputs settle within 2.0µs, and
on the rising edge of SCLK in clock mode 11. See
the ADC has a 300ksps conversion rate.
Figures 6–11. Bipolar true-differential results and tem-
All devices include an internal reference (2.5V or
4.096V) providing a well-regulated, low-noise reference
for both the ADC and DAC. Programmable reference
modes for the ADC and DAC allow the use of an inter-
nal reference, an external reference, or a combination
of both. Features such as an internal 1°C accurate
temperature sensor, FIFO, scan modes, programmable
internal or external clock modes, data averaging, and
AutoShutdown allow users to minimize both power con-
sumption and processor requirements. The low glitch
energy (4nV•s) and low digital feedthrough (0.5nV•s) of
the integrated octal DACs make these devices ideal for
digital control of fast-response closed-loop systems.
perature-sensor results are available in two’s comple-
ment format, while all other results are in binary.
A high-to-low transition on CS initiates the data-input
operation. Serial communications to the ADC always
begin with an 8-bit command byte (MSB first) loaded
from DIN. The command byte and the subsequent data
bytes are clocked from DIN into the serial interface on
the falling edge of SCLK. The serial-interface and fast-
interface circuitry is common to the ADC, DAC, and
GPIO sections. The content of the command byte
determines whether the SPI port should expect 8, 16, or
24 bits and whether the data is intended for the ADC,
DAC, or GPIOs (if applicable). See Table 1. Driving CS
high resets the serial interface.
These devices are guaranteed to operate with a supply
voltage from +2.7V to +3.6V (MAX1221/MAX1223/
MAX1257) and from +4.75V to +5.25V (MAX1220/
MAX1222/MAX1258). These devices consume 2.5mA
at 300ksps throughput, only 22µA at 1ksps throughput,
and under 0.2µA in the shutdown mode. The MAX1257/
MAX1258 feature 12 GPIOs while the MAX1220/
MAX1221 offer 4 GPIOs that can be configured as
inputs or outputs.
The conversion register controls ADC channel selec-
tion, ADC scan mode, and temperature-measurement
requests. See Table 4 for information on writing to the
conversion register. The setup register controls the
clock mode, reference, and unipolar/bipolar ADC con-
figuration. Use a second byte, following the first, to
write to the unipolar-mode or bipolar-mode registers.
See Table 5 for details of the setup register and see
Tables 6, 7, and 8 for setting the unipolar- and bipolar-
mode registers. Hold CS low between the command
byte and the second and third byte. The ADC averag-
ing register is specific to the ADC. See Table 9 to
address that register. Table 11 shows the details of the
reset register.
Figure 1 shows the MAX1257/MAX1258 functional dia-
gram. The MAX1220/MAX1221 only include the GPIO
A0, A1, GPIO C0, C1 block. The MAX1222/MAX1223
exclude the GPIOs. The output-conditioning circuitry
takes the internal parallel data bus and converts it to a
serial data format at DOUT, with the appropriate wake-
up timing. The arithmetic logic unit (ALU) performs the
averaging function.
Begin a write to the DAC by writing 0001XXXX as a
command byte. The last 4 bits of this command byte
are don’t-care bits. Write another 2 bytes (holding CS
low) to the DAC interface register following the com-
mand byte to select the appropriate DAC and the data
to be written to it. See the DAC Serial Interface section
and Tables 10, 20, and 21.
SPI-Compatible Serial Interface
The MAX1220–MAX1223/MAX1257/MAX1258 feature a
serial interface that is compatible with SPI and
MICROWIRE devices. For SPI, ensure the SPI bus mas-
ter (typically a microcontroller (µC)) runs in master
mode so that it generates the serial clock signal. Select
18 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
DV
AV
DD
DD
GPIOB0– GPIOC0–
GPIOB3 GPIOC3
GPIOA0–
GPIOA3
MAX1257
MAX1258
GPIO
CONTROL
USER-PROGRAMMABLE
I/O
OUTPUT
CONDITIONING
12-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
OSCILLATOR
SCLK
CS
OUTPUT
CONDITIONING
12-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
DIN
SPI
PORT
OUTPUT
CONDITIONING
12-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
DOUT
OUTPUT
CONDITIONING
12-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
TEMPERATURE
SENSOR
OUTPUT
CONDITIONING
12-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
EOC
LOGIC
CONTROL
OUTPUT
CONDITIONING
12-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
CNVST
AIN0
12-BIT
SAR
ADC
OUTPUT
CONDITIONING
12-BIT
DAC
FIFO AND
ALU
INPUT
REGISTER
DAC
REGISTER
T/H
AIN13
REF2/
AIN14
CNVST/
AIN15
OUTPUT
CONDITIONING
12-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
REF2
INTERNAL
REFERENCE
REF1
RES_SEL
LDAC
AGND
DGND
Figure 1. MAX1257/MAX1258 Functional Diagram
______________________________________________________________________________________ 19
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 1ꢀ Command Byte (MSB First)
REGꢂSTER IAME
Conversion
Setup
BꢂT 7
BꢂT 6
BꢂT .
BꢂT 4
BꢂT 3
BꢂT 2
BꢂT 1
BꢂT 0
1
0
0
0
0
0
0
0
0
CHSEL3
CHSEL2
CHSEL1
CHSEL0
SCAN1
SCAN0
TEMP
1
0
0
0
0
0
0
0
CKSEL1
CKSEL0
REFSEL1
REFSEL0
DIFFSEL1
DIFFSEL0
ADC Averaging
DAC Select
Reset
1
0
0
0
0
0
0
AVGON
NAVG1
NAVG0
NSCAN1
NSCAN0
1
0
0
0
0
0
X
1
0
0
0
0
X
X
X
RESET
SLOW
FBGON
GPIO Configure*
GPIO Write*
GPIO Read*
No Operation
0
0
0
0
1
1
0
0
1
0
1
0
X = Don’t care.
*Only applicable on the MAX1220/MAX1221/MAX1257/MAX1258.
Write to the GPIOs (if applicable) by issuing a com-
mand byte to the appropriate register. Writing to the
MAX1220/MAX1221 GPIOs requires 1 additional byte
following the command byte. Writing to the MAX1257/
MAX1258 requires 2 additional bytes following the
command byte. See Tables 12–19 for details on GPIO
configuration, writes, and reads. See the GPIO
Command section. Command bytes written to the
GPIOs on devices without GPIOs are ignored.
between four different clock modes for various ways to
start a conversion and determine whether the acquisi-
tions are internally or externally timed. Select clock
mode 00 to configure CNVST/AIN_ to act as a conver-
sion start and use it to request internally timed conver-
sions, without tying up the serial bus. In clock mode 01,
use CNVST to request conversions one channel at a
time, thereby controlling the sampling speed without
tying up the serial bus. Request and start internally
timed conversions through the serial interface by writ-
ing to the conversion register in the default clock mode,
10. Use clock mode 11 with SCLK up to 4.8MHz for
externally timed acquisitions to achieve sampling rates
up to 300ksps. Clock mode 11 disables scanning and
averaging. See Figures 6–9 for timing specifications on
how to begin a conversion.
Power-Up Default State
The MAX1220–MAX1223/MAX1257/MAX1258 power up
with all blocks in shutdown (including the reference). All
registers power up in state 00000000, except for the
setup register and the DAC input register. The setup
register powers up at 0010 1000 with CKSEL1 = 1 and
REFSEL1 = 1. The DAC input register powers up to
FFFh when RES_SEL is high and powers up to 000h
when RES_SEL is low.
These devices feature an active-low, end-of-conversion
output. EOC goes low when the ADC completes the
last requested operation and is waiting for the next
command byte. EOC goes high when CS or CNVST go
low. EOC is always high in clock mode 11.
12-Bit ADC
The MAX1220–MAX1223/MAX1257/MAX1258 ADCs
use a fully differential successive-approximation regis-
ter (SAR) conversion technique and on-chip track-and-
hold (T/H) circuitry to convert temperature and voltage
signals into 12-bit digital results. The analog inputs
accept both single-ended and differential input signals.
Single-ended signals are converted using a unipolar
transfer function, and differential signals are converted
using a selectable bipolar or unipolar transfer function.
See the ADC Transfer Functions section for more data.
Single-Ended or Differential Conversions
The MAX1220–MAX1223/MAX1257/MAX1258 use a
fully differential ADC for all conversions. When a pair of
inputs are connected as a differential pair, each input is
connected to the ADC. When configured in single-
ended mode, the positive input is the single-ended
channel and the negative input is referred to AGND.
See Figure 2.
In differential mode, the T/H samples the difference
between two analog inputs, eliminating common-mode
DC offsets and noise. IN+ and IN- are selected from
the following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5,
AIN6/AIN7, AIN8/AIN9, AIN10/AIN11, AIN12/AIN13,
ADC Clock Modes
When addressing the setup, register bits 5 and 4 of the
command byte (CKSEL1 and CKSEL0, respectively)
control the ADC clock modes. See Table 5. Choose
20 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
AIN14/AIN15. AIN0–AIN7 are available on all devices.
AIN0–AIN11 are available on the MAX1222/MAX1223.
AIN0–AIN15 are available on the MAX1257/MAX1258.
See Tables 5–8 for more details on configuring the
inputs. For the inputs that are configurable as CNVST,
REF2, and an analog input, only one function can be
used at a time.
connected to AIN0–AIN15 in single-ended mode and
AIN0, AIN2, and AIN4–AIN14 (only positive inputs) in
differential mode. A negative input capacitor is con-
nected to AGND in single-ended mode or AIN1, AIN3,
and AIN5–AIN15 (only negative inputs) in differential
mode. For external T/H timing, use clock mode 01.
After the T/H enters hold mode, the difference between
the sampled positive and negative input voltages is
converted. The input capacitance charging rate deter-
mines the time required for the T/H to acquire an input
signal. If the input signal’s source impedance is high,
the required acquisition time lengthens.
Unipolar or Bipolar Conversions
Address the unipolar- and bipolar-mode registers
through the setup register (bits 1 and 0). See Table 5 for
the setup register. See Figures 3 and 4 for the transfer-
function graphs. Program a pair of analog inputs for dif-
ferential operation by writing a one to the appropriate bit
of the bipolar- or unipolar-mode register. Unipolar mode
Any source impedance below 300Ω does not signifi-
cantly affect the ADC’s AC performance. A high-imped-
ance source can be accommodated either by
sets the differential input range from 0 to V
A nega-
REF1.
lengthening t
(only in clock mode 01) or by placing
ACQ
tive differential analog input in unipolar mode causes
the digital output code to be zero. Selecting bipolar
a 1µF capacitor between the positive and negative ana-
log inputs. The combination of the analog-input source
impedance and the capacitance at the analog input cre-
ates an RC filter that limits the analog input bandwidth.
mode sets the differential input range to V
/ 2. The
REF1
digital output code is binary in unipolar mode and two’s
complement in bipolar mode.
In single-ended mode, the MAX1220–MAX1223/
MAX1257/MAX1258 always operate in unipolar mode.
The analog inputs are internally referenced to AGND
with a full-scale input range from 0 to the selected ref-
erence voltage.
Input Bandwidth
The ADC’s input-tracking circuitry has a 1MHz small-
signal bandwidth, making it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias prefiltering
of the input signals is necessary to avoid high-frequen-
cy signals aliasing into the frequency band
of interest.
Analog Input (T/H)
The equivalent circuit of Figure 2 shows the ADC input
architecture of the MAX1220–MAX1223/MAX1257/
MAX1258. In track mode, a positive input capacitor is
Analog-Input Protection
Internal electrostatic-discharge (ESD) protection diodes
clamp all analog inputs to AV
and AGND, allowing
DD
AIN0–AIN15
(SINGLE-ENDED),
AIN0, AIN2,
REF1
DAC
the inputs to swing from (AGND - 0.3V) to (AV
+
DD
ACQ
AGND
0.3V) without damage. However, for accurate conver-
sions near full scale, the inputs must not exceed AV
AIN4–AIN14
DD
(DIFFERENTIAL)
CIN+
by more than 50mV or be lower than AGND by 50mV. If
an analog input voltage exceeds the supplies, limit the
input current to 2mA.
COMPARATOR
HOLD
Internal FIFO
The MAX1220–MAX1223/MAX1257/MAX1258 contain a
first-in/first-out (FIFO) buffer that holds up to 16 ADC
results plus one temperature result. The internal FIFO
allows the ADC to process and store multiple internally
clocked conversions and a temperature measurement
without being serviced by the serial bus.
CIN-
AGND
(SINGLE-ENDED),
AIN1, AIN3,
AIN5–AIN15
(DIFFERENTIAL)
ACQ
ACQ
HOLD
HOLD
If the FIFO is filled and further conversions are request-
ed without reading from the FIFO, the oldest ADC
results are overwritten by the new ADC results. Each
result contains 2 bytes, with the MSB preceded by four
leading zeros. After each falling edge of CS, the oldest
AV / 2
DD
Figure 2. Equivalent Input Circuit
______________________________________________________________________________________ 21
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
available pair of bytes of data is available at DOUT,
MSB first. When the FIFO is empty, DOUT is zero.
Table 5) to program the reference. If using an external
voltage reference, bypass REF1 with a 0.1µF capacitor
to AGND. The MAX1221/MAX1223/MAX1257 internal
reference is 2.5V. The MAX1220/MAX1222/MAX1258
internal reference is 4.096V. When using an external
reference on any of these devices, the voltage range is
The first 2 bytes of data read out after a temperature
measurement always contain the 12-bit temperature
result, preceded by four leading zeros, MSB first. If
another temperature measurement is performed before
the first temperature result is read out, the old measure-
ment is overwritten by the new result. Temperature
results are in degrees Celsius (two’s complement), at a
resolution of 8 LSB per degree. See the Temperature
Measurements section for details on converting the dig-
ital code to a temperature.
0.7V to AV
.
DD
DAC Transfer Function
See Table 2 for various analog outputs from the DAC.
DAC Power-On Wake-Up Modes
The state of the RES_SEL input determines the wake-up
state of the DAC outputs. Connect RES_SEL to AV
or
DD
12-Bit DAC
In addition to the 12-bit ADC, the MAX1220–MAX1223/
MAX1257/MAX1258 also include eight voltage-output,
12-bit, monotonic DACs with less than 4 LSB integral
nonlinearity error and less than 1 LSB differential non-
linearity error. Each DAC has a 2µs settling time and
ultra-low glitch energy (4nV•s). The 12-bit DAC code is
AGND upon power-up to be sure the DAC outputs
wake up to a known state. Connect RES_SEL to AGND
to wake up all DAC outputs at 000h. While RES_SEL is
low, the 100kΩ internal resistor pulls the DAC outputs to
AGND and the output buffers are powered down.
Connect RES_SEL to AV
to wake up all DAC outputs
DD
at FFFh. While RES_SEL is high, the 100kΩ pullup
unipolar binary with 1 LSB = V
/ 4096.
REF
resistor pulls the DAC outputs to V
buffers are powered down.
and the output
REF1
DAC Digital Interface
Figure 1 shows the functional diagram of the MAX1257/
MAX1258. The shift register converts a serial 16-bit
word to parallel data for each input register operating
with a clock rate up to 25MHz. The SPI-compatible digi-
tal interface to the shift register consists of CS, SCLK,
DIN, and DOUT. Serial data at DIN is loaded on the
falling edge of SCLK. Pull CS low to begin a write
sequence. Begin a write to the DAC by writing
0001XXXX as a command byte. The last 4 bits of the
DAC select register are don’t-care bits. See Table 10.
Write another 2 bytes to the DAC interface register fol-
lowing the command byte to select the appropriate DAC
and the data to be written to it. See Tables 20 and 21.
DAC Power-Up Modes
See Table 21 for a description of the DAC power-up
and power-down modes.
Table 2ꢀ DAC Output Code Table
DAC COITEITS
AIAꢁOG OUTPUT
MSB
ꢁSB
4095
4096
1111
1111
0000
0000
0111
1111
+V
REF
The eight double-buffered DACs include an input and a
DAC register. The input registers are directly connect-
ed to the shift register and hold the result of the most
recent write operation. The eight 12-bit DAC registers
hold the current output code for the respective DAC.
Data can be transferred from the input registers to the
DAC registers by pulling LDAC low or by writing the
appropriate DAC command sequence at DIN. See
Table 20. The outputs of the DACs are buffered through
eight rail-to-rail op amps.
2049
4096
1000
1000
0111
0001
0000
0111
+V
REF
2048
4096
+V
REF
+V
=
REF
2
2047
4096
+V
REF
The MAX1220–MAX1223/MAX1257/MAX1258 DAC out-
put-voltage range is based on the internal reference or
an external reference. Write to the setup register (see
1
0000
0000
0000
0000
0001
0000
+V
REF
4096
0
22 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
REFSEL[1:0] = 00 to program both the ADC and DAC
for internal reference use. Set REFSEL[1:0] = 10 to pro-
gram the ADC for internal reference. Set REFSEL[1:0] =
10 to program the DAC for external reference, REF1.
When using REF1 or REF2/AIN_ in external-reference
mode, connect a 0.1µF capacitor to AGND. Set
REFSEL[1:0] = 01 to program the ADC and DAC for
external-reference mode. The DAC uses REF1 as its
external reference, while the ADC uses REF2 as its
external reference. Set REFSEL[1:0] = 11 to program
the ADC for external differential reference mode. REF1
is the positive reference and REF2 is the negative refer-
ence in the ADC external differential mode.
GPIOs
In addition to the internal ADC and DAC, the
MAX1257/MAX1258 also provide 12 general-purpose
input/output channels, GPIOA0–GPIOA3, GPIOB0–
GPIOB3, and GPIOC0–GPIOC3. The MAX1220/MAX1221
include four GPIO channels (GPIOA0, GPIOA1, GPIOC0,
GPIOC1). Read and write to the GPIOs as detailed in
Table 1 and Tables 12–19. Also, see the GPIO Command
section. See Figures 11 and 12 for GPIO timing.
Write to the GPIOs by writing a command byte to the
GPIO command register. Write a single data byte to the
MAX1220/MAX1221 following the command byte. Write
2 bytes to the MAX1257/MAX1258 following the com-
mand byte.
When REFSEL[1:0] = 00 or 10, REF2/AIN_ functions as
an analog input channel. When REFSEL[1:0] = 01 or 11,
REF2/AIN_ functions as the device’s negative reference.
The GPIOs can sink and source current. The
MAX1257/MAX1258 GPIOA0–GPIOA3 can sink and
source up to 15mA. GPIOB0–GPIOB3 and GPIOC0–
GPIOC3 can sink 4mA and source 2mA. The MAX1220/
MAX1221 GPIOA0 and GPIOA1 can sink and source up
to 15mA. The MAX1220/MAX1221 GPIOC0 and GPIOC1
can sink 4mA and source 2mA. See Table 3.
Temperature Measurements
Issue a command byte setting bit 0 of the conversion
register to one to take a temperature measurement.
See Table 4. The MAX1220–MAX1223/MAX1257/
MAX1258 perform temperature measurements with an
internal diode-connected transistor. The diode bias cur-
rent changes from 68µA to 4µA to produce a tempera-
ture-dependent bias voltage difference. The second
conversion result at 4µA is subtracted from the first at
68µA to calculate a digital value that is proportional to
absolute temperature. The output data appearing at
DOUT is the digital code above, minus an offset to
adjust from Kelvin to Celsius.
Clock Modes
Internal Clock
The MAX1220–MAX1223/MAX1257/MAX1258 can
operate from an internal oscillator. The internal oscilla-
tor is active in clock modes 00, 01, and 10. Figures 6,
7, and 8 show how to start an ADC conversion in the
three internally timed conversion modes.
Read out the data at clock speeds up to 25MHz
through the SPI interface.
The reference voltage used for the temperature mea-
surements is always derived from the internal reference
source to ensure that 1 LSB corresponds to 1/8 of a
degree Celsius. On every scan where a temperature
measurement is requested, the temperature conversion
is carried out first. The first 2 bytes of data read from
the FIFO contain the result of the temperature measure-
ment. If another temperature measurement is per-
formed before the first temperature result is read out,
the old measurement is overwritten by the new result.
Temperature results are in degrees Celsius (two’s com-
plement). See the Applications Information section for
information on how to perform temperature measure-
ments in each clock mode.
External Clock
Set CKSEL1 and CKSEL0 in the setup register to 11 to
set up the interface for external clock mode 11. See
Table 5. Pulse SCLK at speeds from 0.1MHz to
4.8MHz. Write to SCLK with a 40% to 60% duty cycle.
The SCLK frequency controls the conversion timing.
See Figure 9 for clock mode 11 timing. See the ADC
Conversions in Clock Mode 11 section.
ADC/DAC References
Address the reference through the setup register, bits 3
and 2. See Table 5. Following a wake-up delay, set
Table 3ꢀ GPꢂO Maximum Sink/Source Current
MAX12.7/MAX12.8
CURREIT
MAX1220/MAX1221
GPꢂOA0–GPꢂOA3
15mA
GPꢂOB0–GPꢂOB3
GPꢂOC0–GPꢂOC3
GPꢂOA0, GPꢂOA1
15mA
GPꢂOC0, GPꢂOC1
4mA
2mA
4mA
2mA
4mA
2mA
SꢂIK CURREIT
15mA
15mA
SOURCE CURREIT
______________________________________________________________________________________ 23
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Register Descriptions
The MAX1220–MAX1223/MAX1257/MAX1258 commu-
nicate between the internal registers and the external
circuitry through the SPI-compatible serial interface.
Table 1 details the command byte, the registers, and
the bit names. Tables 4–12 show the various functions
within the conversion register, setup register, unipolar-
mode register, bipolar-mode register, ADC averaging
register, DAC select register, reset register, and GPIO
command register, respectively.
Table 4ꢀ Conversion Register*
BꢂT
IAME
BꢂT
FUICTꢂOI
—
7 (MSB)
Set to one to select conversion register.
Analog-input channel select.
Analog-input channel select.
Analog-input channel select.
Analog-input channel select.
Scan-mode select.
CHSEL3
CHSEL2
CHSEL1
CHSEL0
SCAN1
SCAN0
6
5
4
3
2
1
Conversion Register
Select active analog input channels, scan modes, and
a single temperature measurement per scan by issuing
a command byte to the conversion register. Table 4
details channel selection, the four scan modes, and
how to request a temperature measurement. Start a
scan by writing to the conversion register when in clock
mode 10 or 11, or by applying a low pulse to the
CNVST pin when in clock mode 00 or 01. See Figures 6
and 7 for timing specifications for starting a scan with
CNVST.
Scan-mode select.
Set to one to take a single temp-
erature measurement. The first
conversion result of a scan contains
temperature information.
TEMP
0 (LSB)
*See below for bit details.
SEꢁECTED
CHAIIEꢁ
(I)
CHSEꢁ3
CHSEꢁ2
CHSEꢁ1
CHSEꢁ0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN0
AIN1
A conversion is not performed if it is requested on a
channel or one of the channel pairs that has been con-
figured as CNVST or REF2. For channels configured as
differential pairs, the CHSEL0 bit is ignored and the two
pins are treated as a single differential channel.
AIN2
AIN3
AIN4
Select scan mode 00 or 01 to return one result per sin-
gle-ended channel and one result per differential pair
within the selected scanning range (set by bits 2 and 1,
SCAN1 and SCAN0), plus one temperature result, if
selected. Select scan mode 10 to scan a single input
channel numerous times, depending on NSCAN1 and
NSCAN0 in the ADC averaging register (Table 9).
Select scan mode 11 to return only one result from a
single channel.
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
Setup Register
Issue a command byte to the setup register to config-
ure the clock, reference, power-down modes, and ADC
single-ended/differential modes. Table 5 details the bits
in the setup-register command byte. Bits 5 and 4
(CKSEL1 and CKSEL0) control the clock mode, acqui-
sition and sampling, and the conversion start. Bits 3
and 2 (REFSEL1 and REFSEL0) set the device for either
internal or external reference. Bits 1 and 0 (DIFFSEL1
and DIFFSEL0) address the ADC unipolar-mode and
bipolar-mode registers and configure the analog-input
channels for differential operation.
SCAI MODE
SCAI1 SCAI0
(CHAIIEꢁ I ꢂS SEꢁECTED BY
BꢂTS CHSEꢁ3–CHSEꢁ0)
0
0
0
1
Scans channels 0 through N.
Scans channels N through the highest
numbered channel.
Scans channel N repeatedly. The ADC
averaging register sets the number of
results.
1
1
0
1
No scan. Converts channel N once only.
24 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table .ꢀ Setup Register*
BꢂT IAME
—
BꢂT
FUICTꢂOI
7 (MSB)
Set to zero to select setup register.
Set to one to select setup register.
—
6
CKSEL1
CKSEL0
REFSEL1
REFSEL0
DIFFSEL1
DIFFSEL0
5
Clock mode and CNVST configuration; resets to one at power-up.
Clock mode and CNVST configuration.
4
3
Reference-mode configuration.
2
1
Reference-mode configuration.
Unipolar-/bipolar-mode register configuration for differential mode.
Unipolar-/bipolar-mode register configuration for differential mode.
0 (LSB)
*See below for bit details.
Table .aꢀ Clock Modes*
CKSEꢁ1
CKSEꢁ0
COIVERSꢂOI CꢁOCK
ACQUꢂSꢂTꢂOI/SAMPꢁꢂIG
Internally timed.
CNVST COIFꢂGURATꢂOI
0
0
1
1
0
1
0
1
Internal
Internal
CNVST
Externally timed by CNVST.
Internally timed.
CNVST
Internal
AIN15/AIN11/AIN7
AIN15/AIN11/AIN7
External (4.8MHz max)
Externally timed by SCLK.
*See the Clock Modes section.
Table .bꢀ Clock Modes 00, 01, and 10
VOꢁTAGE
REFEREICE COIDꢂTꢂOIS
OVERRꢂDE
REF2
COIFꢂGURATꢂOI
REFSEꢁ1 REFSEꢁ0
AUTOSHUTDOWI
Internal reference turns off after scan is complete. If
internal reference is turned off, there is a programmed
delay of 218 internal-conversion clock cycles.
AIN
Internal (DAC
and ADC)
0
0
0
1
AIN14/AIN10/AIN6
Internal reference required. There is a programmed
Temperature delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
AIN
Internal reference not used.
External single-
ended (REF1
for DAC and
Internal reference required. There is a programmed
Temperature delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
REF2
REF2 for ADC)
Default reference mode. Internal reference turns off
after scan is complete. If internal reference is turned
off, there is a programmed delay of 218 internal-
AIN
Internal (ADC)
and external
REF1 (DAC)
conversion clock cycles.
1
1
0
1
AIN14/AIN10/AIN6
Internal reference required. There is a programmed
Temperature delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
AIN
Internal reference not used.
External
differential
(ADC), external
REF1 (DAC)
Internal reference required. There is a programmed
Temperature delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
REF2
______________________________________________________________________________________ 2.
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
The ADC reference is always on if any of the following
conditions are true:
3)At least one DAC is powered down through the
100kΩ to V and REFSEL[1:0] = 00.
REF
1)The FBGON bit is set to one in the reset register.
If any of the above conditions exist, the ADC reference
is always on, but there is a 188 clock-cycle delay
before temperature-sensor measurements begin, if
requested.
2)At least one DAC output is powered up and
REFSEL[1:0] (in the setup register) = 00.
Table .cꢀ Clock Mode 11
VOꢁTAGE
REFEREICE COIDꢂTꢂOIS
OVERRꢂDE
REF2
AUTOSHUTDOWI
REFSEꢁ1 REFSEꢁ0
COIFꢂGURATꢂOI
Internal reference turns off after scan is complete. If
internal reference is turned off, there is a programmed
delay of 218 external conversion clock cycles.
AIN
Internal (DAC
and ADC)
0
0
0
1
AIN14/AIN10/AIN6
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
Temperature
AIN
External single-
Internal reference not used.
Internal reference required. There is a programmed
ended (REF1
for DAC and
REF2 for ADC)
REF2
AIN14/AIN10/AIN6
REF2
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
Temperature
Default reference mode. Internal reference turns off
after scan is complete. If internal reference is turned
off, there is a programmed delay of 218 external
conversion clock cycles.
AIN
Internal (ADC)
and external
REF1 (DAC)
1
1
0
1
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
Temperature
AIN
Internal reference not used.
External
differential
(ADC), external
REF1 (DAC)
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
Temperature
Table .dꢀ Differential Select Modes
DꢂFFSEꢁ1 DꢂFFSEꢁ0
FUICTꢂOI
0
0
1
1
0
1
0
1
No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged.
No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged.
1 byte of data follows the command setup byte and is written to the unipolar-mode register.
1 byte of data follows the command setup byte and is written to the bipolar-mode register.
26 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 6ꢀ Unipolar-Mode Register (Addressed Through the Setup Register)
BꢂT IAME
UCH0/1
BꢂT
FUICTꢂOI
Configure AIN0 and AIN1 for unipolar differential conversion.
Configure AIN2 and AIN3 for unipolar differential conversion.
Configure AIN4 and AIN5 for unipolar differential conversion.
Configure AIN6 and AIN7 for unipolar differential conversion.
Configure AIN8 and AIN9 for unipolar differential conversion.
Configure AIN10 and AIN11 for unipolar differential conversion.
Configure AIN12 and AIN13 for unipolar differential conversion.
Configure AIN14 and AIN15 for unipolar differential conversion.
7 (MSB)
UCH2/3
6
UCH4/5
5
UCH6/7
4
UCH8/9
3
UCH10/11
UCH12/13
UCH14/15
2
1
0 (LSB)
Table 7ꢀ Bipolar-Mode Register (Addressed Through the Setup Register)
BꢂT IAME
BꢂT
FUICTꢂOI
Set to one to configure AIN0 and AIN1 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN0 and AIN1 for unipolar
single-ended conversion.
BCH0/1
7 (MSB)
Set to one to configure AIN2 and AIN3 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN2 and AIN3 for unipolar
single-ended conversion.
BCH2/3
BCH4/5
6
Set to one to configure AIN4 and AIN5 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN4 and AIN5 for unipolar
single-ended conversion.
5
Set to one to configure AIN6 and AIN7 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN6 and AIN7 for unipolar
single-ended conversion.
BCH6/7
4
Set to one to configure AIN8 and AIN9 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN8 and AIN9 for unipolar
single-ended conversion.
BCH8/9
3
Set to one to configure AIN10 and AIN11 for bipolar differential conversion. Set the corresponding
bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN10 and AIN11 for
unipolar single-ended conversion.
BCH10/11
BCH12/13
BCH14/15
2
1
Set to one to configure AIN12 and AIN13 for bipolar differential conversion. Set the corresponding
bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN12 and AIN13 for
unipolar single-ended conversion.
Set to one to configure AIN14 and AIN15 for bipolar differential conversion. Set the corresponding
bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN14 and AIN15 for
unipolar single-ended conversion.
0 (LSB)
______________________________________________________________________________________ 27
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Unipolar/Bipolar Registers
The final 2 bits (LSBs) of the setup register control the
unipolar-/bipolar-mode address registers. Set
DIFFSEL[1:0] = 10 to write to the unipolar-mode regis-
ter. Set bits DIFFSEL[1:0] = 11 to write to the bipolar-
mode register. In both cases, the setup command byte
must be followed by 1 byte of data that is written to the
unipolar-mode register or bipolar-mode register. Hold
CS low and run 16 SCLK cycles before pulling CS high.
If the last 2 bits of the setup register are 00 or 01, nei-
ther the unipolar-mode register nor the bipolar-mode
register is written. Any subsequent byte is recognized
as a new command byte. See Tables 6, 7, and 8 to pro-
gram the unipolar- and bipolar-mode registers.
Both registers power up at all zeros to set the inputs as
16 unipolar single-ended channels. To configure a
channel pair as single-ended unipolar, bipolar differen-
tial, or unipolar differential, see Table 8.
In unipolar mode, AIN+ can exceed AIN- by up to
REF
bipolar mode, either input can exceed the other by up
Table 8ꢀ Unipolar/Bipolar Channel Function
V
. The output format in unipolar mode is binary. In
UIꢂPOꢁAR-
to V
/ 2. The output format in bipolar mode is two’s
REF
BꢂPOꢁAR-MODE
REGꢂSTER BꢂT
CHAIIEꢁ PAꢂR
FUICTꢂOI
MODE
complement (see the ADC Transfer Functions section).
REGꢂSTER BꢂT
ADC Averaging Register
Write a command byte to the ADC averaging register to
configure the ADC to average up to 32 samples for
each requested result, and to independently control the
number of results requested for single-channel scans.
0
0
1
1
0
1
0
1
Unipolar single-ended
Bipolar differential
Unipolar differential
Unipolar differential
Table 9ꢀ ADC Averaging Register*
BꢂT IAME
BꢂT
FUICTꢂOI
—
7 (MSB)
Set to zero to select ADC averaging register.
—
—
6
Set to zero to select ADC averaging register.
5
Set to one to select ADC averaging register.
AVGON
4
Set to one to turn averaging on. Set to zero to turn averaging off.
Configures the number of conversions for single-channel scans.
Configures the number of conversions for single-channel scans.
Single-channel scan count. (Scan mode 10 only.)
Single-channel scan count. (Scan mode 10 only.)
NAVG1
3
NAVG0
2
1
NSCAN1
NSCAN0
0 (LSB)
*See below for bit details.
FUICTꢂOI
AVGOI
IAVG1
IAVG0
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Performs one conversion for each requested result.
Performs four conversions and returns the average for each requested result.
Performs eight conversions and returns the average for each requested result.
Performs 16 conversions and returns the average for each requested result.
Performs 32 conversions and returns the average for each requested result.
ISCAI1
ISCAI0
FUICTꢂOI (APPꢁꢂES OIꢁY ꢂF SCAI MODE 10 ꢂS SEꢁECTED)
Scans channel N and returns four results.
0
0
1
1
0
1
0
1
Scans channel N and returns eight results.
Scans channel N and returns 12 results.
Scans channel N and returns 16 results.
28 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 9 details the four scan modes available in the
ADC conversion register. All four scan modes allow
averaging as long as the AVGON bit, bit 4 in the
averaging register, is set to 1. Select scan mode 10 to
scan the same channel multiple times. Clock mode 11
disables averaging. For example, if AVGON = 1,
NAVG[1:0] = 00, NSCAN[1:0] = 11 and SCAN[1:0] =
10, 16 results are written to the FIFO, with each result
being the average of four conversions of channel N.
Reset Register
Write to the reset register (as shown in Table 11) to
clear the FIFO or to reset all registers to their default
states. Set the RESET bit to one to reset the FIFO. Set
the RESET bit to zero to return the MAX1220–MAX1223/
MAX1257/MAX1258 to their default power-up state. All
registers power up in state 00000000, except for the
setup register that powers up in clock mode 10
(CKSEL1 = 1). Set the SLOW bit to one to add a 15ns
delay in the DOUT signal path to provide a longer hold
time. Writing a one to the SLOW bit also clears the con-
tents of the FIFO. Set the FBGON bit to one to force the
bias block and bandgap reference to power up regard-
less of the state of the DAC and activity of the ADC
block. Setting the FBGON bit high also removes the
programmed wake-up delay between conversions in
clock modes 01 and 11. Setting the FBGON bit high
also clears the FIFO.
DAC Select Register
Write a command byte 0001XXXX to the DAC select
register (as shown in Table 9) to set up the DAC inter-
face and indicate that another word will follow. The last
4 bits of the DAC select register are don’t-care bits. The
word that follows the DAC select-register command
byte controls the DAC serial interface. See Table 20
and the DAC Serial Interface section.
GPIO Command
Write a command byte to the GPIO command register
to configure, write, or read the GPIOs, as detailed in
Table 12.
Table 10ꢀ DAC Select Register
BꢂT
BꢂT
FUICTꢂOI
IAME
—
—
—
—
X
7 (MSB) Set to zero to select DAC select register.
Write the command byte 00000011 to configure the
GPIOs. The eight SCLK cycles following the command
byte load data from DIN to the GPIO configuration reg-
ister in the MAX1220/MAX1221. The 16 SCLK cycles
6
5
4
3
2
1
0
Set to zero to select DAC select register.
Set to zero to select DAC select register.
Set to one to select DAC select register.
Don’t care.
Table 12ꢀ GPꢂO Command Register
X
Don’t care.
BꢂT IAME
BꢂT
FUICTꢂOI
X
Don’t care.
—
7 (MSB)
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
GPIO configuration bit.
X
Don’t care.
—
6
—
5
Table 11ꢀ Reset Register
—
—
4
3
BꢂT
BꢂT
FUICTꢂOI
—
2
1
IAME
GPIOSEL1
GPIOSEL2
—
—
—
—
—
7 (MSB) Set to zero to select ADC reset register.
0 (LSB)
GPIO write bit.
6
5
4
3
Set to zero to select ADC reset register.
Set to zero to select ADC reset register.
Set to zero to select ADC reset register.
Set to one to select ADC reset register.
GPꢂOSEꢁ1 GPꢂOSEꢁ2
FUICTꢂOI
GPIO configuration; written data is
entered in the GPIO configuration
register.
1
1
0
1
0
1
Set to zero to clear the FIFO only. Set to
one to set the device in its power-on
condition.
RESET
SLOW
2
1
GPIO write; written data is entered
in the GPIO write register.
Set to one to turn on slow mode.
GPIO read; the next 8/16 SCLK
cycles transfer the state of all GPIO
drivers into DOUT.
Set to one to force internal bias block and
bandgap reference to be always powered
up.
FBGON 0 (LSB)
______________________________________________________________________________________ 29
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
following the command byte load data from DIN to the
GPIO Write
Write the command byte 00000010 to indicate a GPIO
GPIO configuration register in the MAX1257/MAX1258.
See Tables 13 and 14. The register bits are updated
after the last CS rising edge. All GPIOs default to inputs
upon power-up.
write operation. The eight SCLK cycles following the
command byte load data from DIN into the GPIO write
register in the MAX1220/MAX1221. The 16 SCLK
cycles following the command byte load data from DIN
into the GPIO write register in the MAX1257/MAX1258.
See Tables 15 and 16. The register bits are updated
after the last CS rising edge.
The data in the register controls the function of each
GPIO, as shown in Tables 13–19.
Table 13ꢀ MAX1220/MAX1221 GPꢂO Configuration
DATA PꢂI
DꢂI
DOUT
GPꢂO COMMAID BYTE
DATA BYTE
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
GPIOC1
0
GPIOC0
0
GPIOA1
0
GPIOA0
0
X
0
X
0
X
0
X
0
Table 14ꢀ MAX12.7/MAX12.8 GPꢂO Configuration
DATA PꢂI
GPꢂO COMMAID BYTE
DATA BYTE 1
DATA BYTE 2
DꢂI
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
X
0
X
X
0
X
0
DOUT
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 1.ꢀ MAX1220/MAX1221 GPꢂO Write
DATA PꢂI
DꢂI
GPꢂO COMMAID BYTE
DATA BYTE
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
GPIOC1
0
GPIOC0
0
GPIOA1
0
GPIOA0
0
X
0
X
0
X
X
0
DOUT
0
Table 16ꢀ MAX12.7/MAX12.8 GPꢂO Write
DATA PꢂI
GPꢂO COMMAID BYTE
DATA BYTE 1
DATA BYTE 2
DꢂI
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
X
0
X
X
X
0
DOUT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
30 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
GPIO Read
Write the command byte 00000001 to indicate a GPIO
read operation. The eight SCLK cycles following the
command byte transfer the state of the GPIOs to DOUT
in the MAX1220/MAX1221. The 16 SCLK cycles follow-
ing the command byte transfer the state of the GPIOs to
DOUT in the MAX1257/MAX1258. See Tables 18 and 19.
DAC Serial Interface
Write a command byte 0001XXXX to the DAC select
register to indicate the word to follow is written to the
DAC serial interface, as detailed in Tables 1, 10, 20, and
21. Write the next 16 bits to the DAC interface register,
as shown in Tables 20 and 21. Following the high-to-low
transition of CS, the data is shifted synchronously and
latched into the input register on each falling edge of
SCLK. Each word is 16 bits. The first 4 bits are the con-
trol bits followed by 12 data bits (MSB first) and 2 don’t-
care sub-bits. See Figures 9–12 for DAC timing
specifications.
Table 17ꢀ GPꢂO-Mode Control
COIFꢂGURATꢂOI
BꢂT
WRꢂTE
BꢂT
OUTPUT
STATE
GPꢂO
FUICTꢂOI
If CS goes high prior to completing 16 SCLK cycles,
the command is discarded. To initiate a new transfer,
drive CS low again.
1
1
0
1
0
1
1
0
Output
Output
Input
For example, writing the DAC serial interface word
1111 0000 and 1111 0100 disconnects DAC outputs 4
through 7 and forces them to a high-impedance state.
DAC outputs 0 through 3 remain in their previous state.
Tri-state
Pulldown
(open drain)
0
0
0
Table 18ꢀ MAX1220/MAX1221 GPꢂO Read
DATA PꢂI
DꢂI
GPꢂO COMMAID BYTE
DATA BYTE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
X
0
X
0
X
0
X
0
X
X
X
X
DOUT
GPIOC1
GPIOC0
GPIOA1
GPIOA0
Table 19ꢀ MAX12.7/MAX12.8 GPꢂO Read
DATA PꢂI
DꢂI
GPꢂO COMMAID BYTE
DATA BYTE 1
DATA BYTE 2
0
0
0
0
0
0
0
0
1
0
X
0
X
0
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
DOUT
0
0
0
0
0
0
0
______________________________________________________________________________________ 31
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 20ꢀ DAC Serial-ꢂnterface Configuration
16-BꢂT SERꢂAꢁ WORD
MSB
COITROꢁ
BꢂTS
C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D. D4 D3 D2 D1 D0
ꢁSB
DESCRꢂPTꢂOI
FUICTꢂOI
DATA BꢂTS
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
NOP
No operation.
Reset all internal registers to 000h and
leave output buffers in their present state.
0
0
0
1
0
X
0
X
X
X
X
X
X
X
X
X
RESET
Preset all internal registers to FFFh and
leave output buffers in their present state.
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
1
X
1
X
X
X
X
X
X
X
X
X
Pull-High
DAC0
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
DAC7
D11–D0 to input register 0,
DAC output unchanged.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D11–D0 to input register 1,
DAC output unchanged.
D11–D0 to input register 2,
DAC output unchanged.
D11–D0 to input register 3,
DAC output unchanged.
D11–D0 to input register 4,
DAC output unchanged.
D11–D0 to input register 5,
DAC output unchanged.
D11–D0 to input register 6,
DAC output unchanged.
D11–D0 to input register 7,
DAC output unchanged.
D11–D0 to input registers 0–3 and DAC
registers 0–3. DAC outputs updated
(write-through).
1
1
0
0
1
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DAC0–DAC3
D11–D0 to input registers 4–7 and DAC
DAC4–DAC7 registers 4–7. DAC outputs updated
(write-through).
D11–D0 to input registers 0–7 and DAC
registers 0–7. DAC outputs updated
(write-through).
1
1
1
1
0
0
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DAC0–DAC7
DAC0–DAC7
D11–D0 to input registers 0–7.
DAC outputs unchanged.
Input registers to DAC registers indicated
by ones, DAC outputs updated,
equivalent to software LDAC.
1
1
1
0
X
X
X
X
DAC0–DAC7
(No effect on DACs indicated by zeros.)
32 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 21ꢀ DAC Power-Up and Power-Down Commands
COITROꢁ
DATA BꢂTS
BꢂTS
DESCRꢂPTꢂOI
FUICTꢂOI
C3 C2 C1 C0
D3 D2 D1 D0
Power up individual DAC buffers indicated by data
in DAC0 through DAC7. A one indicates the DAC
output is connected and active. A zero does not
affect the DAC’s present state.
1
1
1
1
1
1
1
1
— — — — — — — —
0
0
0
1
1
0
X
X
Power-Up
Power down individual DAC buffers indicated by
data in DAC0 through DAC7. A one indicates the
DAC output is disconnected and high impedance.
A zero does not affect the DAC’s present state.
— — — — — — — —
Power-Down 1
Power down individual DAC buffers indicated by
data in DAC0 through DAC7. A one indicates the
DAC output is disconnected and pulled to AGND
with a 1kΩ resistor. A zero does not affect the DAC’s
present state.
1
1
1
1
1
1
1
1
1
1
1
1
— — — — — — — —
— — — — — — — —
— — — — — — — —
1
0
1
0
0
1
0
0
1
X
X
X
Power-Down 2
Power down individual DAC buffers indicated by
data in DAC0 through DAC7. A one indicates the
Power-Down 3 DAC output is disconnected and pulled to AGND
with a 100kΩ resistor. A zero does not affect the
DAC’s present state.
Power down individual DAC buffers indicated by
data in DAC0 through DAC7. A one indicates the
Power-Down 4 DAC output is disconnected and pulled to REF1 with
a 100kΩ resistor. A zero does not affect the DAC’s
present state.
occur halfway between successive-integer LSB values.
Output-Data Format
Output coding is binary, with 1 LSB = V
/ 4096
Figures 6–9 illustrate the conversion timing for the
MAX1220–MAX1223/MAX1257/MAX1258. All 12-bit
conversion results are output in 2-byte format, MSB
first, with four leading zeros. Data appears on DOUT on
the falling edges of SCLK. Data is binary for unipolar
mode and two’s complement for bipolar mode and tem-
perature results. See Figures 3, 4, and 5 for input/out-
put and temperature-transfer functions.
REF1
(MAX1221/MAX1223/MAX1257) and 1 LSB = V
/
REF1
4096 (MAX1220/MAX1222/MAX1258) for unipolar and
bipolar operation, and 1 LSB = +0.125°C for tempera-
ture measurements. Bipolar true-differential results and
temperature-sensor results are available in two’s com-
plement format, while all others are in binary. See
Tables 6, 7, and 8 for details on which setting (unipolar
or bipolar) takes precedence.
ADC Transfer Functions
Figure 3 shows the unipolar transfer function for single-
ended or differential inputs. Figure 4 shows the bipolar
transfer function for differential inputs. Code transitions
In unipolar mode, AIN+ can exceed AIN- by up to
V
. In bipolar mode, either input can exceed the
REF1
other by up to V
/ 2.
REF1
______________________________________________________________________________________ 33
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
MAX1257/MAX1258 then wake up, scan all requested
channels, store the results in the FIFO, and shut down.
After the scan is complete, EOC is pulled low and the
results are available in the FIFO. Wait until EOC goes
low before pulling CS low to communicate with the seri-
al interface. EOC stays low until CS or CNVST is pulled
low again. A temperature-conversion result, if request-
ed, precedes all other FIFO results.
Partial Reads and Partial Writes
If the 1st byte of an entry in the FIFO is partially read
(CS is pulled high after fewer than eight SCLK cycles),
the remaining bits are lost for that byte. The next byte of
data that is read out contains the next 8 bits. If the first
byte of an entry in the FIFO is read out fully, but the
second byte is read out partially, the rest of that byte is
lost. The remaining data in the FIFO is unaffected and
can be read out normally after taking CS low again, as
long as the 4 leading bits (normally zeros) are ignored.
If CS is pulled low before EOC goes low, a conversion
may not be completed and the FIFO data may not be
correct. Incorrect writes (pulling CS high before com-
pleting eight SCLK cycles) are ignored and the register
remains unchanged.
V
REF
= V - V
REF+ REF-
V
REF
V
REF
011....111
011....110
011....101
FS = V / 2 + V
REF
COM
ZS = COM
-FS = -V / 2
REF
V
REF
Applications Information
1 LSB = V / 4096
REF
000....001
000....000
111....111
Internally Timed Acquisitions and
(COM)
Conversions Using CNVST
ADC Conversions in Clock Mode 00
In clock mode 00, the wake-up, acquisition, conversion,
and shutdown sequence is initiated through CNVST
and performed automatically using the internal oscilla-
tor. Results are added to the internal FIFO to be read
out later. See Figure 6 for clock mode 00 timing after a
command byte is issued. See Table 5 for details on
programming the clock mode in the setup register.
V
REF
100....011
100....010
100....001
100....000
-FS
-1 0 +1
(COM)
+FS - 1 LSB
INPUT VOLTAGE (LSB)
Initiate a scan by setting CNVST low for at least 40ns
before pulling it high again. The MAX1220–MAX1223/
Figure 4. Bipolar Transfer Function—Full Scale ( FS) =
V
REF
/ 2
OUTPUT CODE
FULL-SCALE
TRANSITION
111....111
011....111
011....110
FS = V
REF
111....110
111....101
1 LSB = V / 4096
REF
000....010
000....001
000....000
111....111
111....110
111....101
000....011
000....010
000....001
000....000
100....001
100....000
0
1
2
3
FS
INPUT VOLTAGE (LSB)
0
-256
+255.5
FS - 3/2 LSB
TEMPERATURE (°C)
Figure 5. Temperature Transfer Function
Figure 3. Unipolar Transfer Function—Full Scale (FS) = V
REF
34 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
CNVST
CS
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
SCLK
DOUT
LSB1
MSB2
MSB1
t
RDS
EOC
Figure 6. Clock Mode 00—After writing a command byte, set CNVST low for at least 40ns to begin a conversion.
t
CSW
CNVST
(CONVERSION 2)
(ACQUISITION 1)
(ACQUISITION 2)
CS
t
DOV
SCLK
(CONVERSION 1)
DOUT
EOC
LSB1
MSB2
MSB1
Figure 7. Clock Mode 01—After writing a command byte, request multiple conversions by setting CNVST low for each conversion.
at least 1.4µs to complete the acquisition. If reference
mode 00 or 10 is selected, an additional 45µs is
required for the internal reference to power up. If a tem-
perature measurement is being requested, reference
power-up and temperature measurement is internally
timed. In this case, hold CNVST low for at least 40ns.
Do not issue a second CNVST signal before EOC goes
low; otherwise, the FIFO can be corrupted. Wait until all
conversions are complete before reading the FIFO. SPI
communications to the DAC and GPIO registers are per-
mitted during conversion. However, coupled noise may
result in degraded ADC signal-to-noise ratio (SNR).
Set CNVST high to begin a conversion. Sampling is
completed approximately 500ns after CNVST goes
high. After the conversion is complete, the ADC shuts
down and pulls EOC low. EOC stays low until CS or
CNVST is pulled low again. Wait until EOC goes low
before pulling CS or CNVST low. The number of CNVST
signals must equal the number of conversions request-
ed by the scan and averaging registers to correctly
update the FIFO. Wait until all conversions are com-
plete before reading the FIFO. SPI communications to
the DAC and GPIO registers are permitted during
Externally Timed Acquisitions and
Internally Timed Conversions with CNVST
ADC Conversions in Clock Mode 01
In clock mode 01, conversions are requested one at a
time using CNVST and performed automatically using
the internal oscillator. See Figure 7 for clock mode 01
timing after a command byte is issued.
Setting CNVST low begins an acquisition, wakes up the
ADC, and places it in track mode. Hold CNVST low for
______________________________________________________________________________________ 3.
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
(CONVERSION BYTE)
DIN
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
CS
SCLK
DOUT
MSB1
LSB1
MSB2
t
DOV
EOC
Figure 8. Clock Mode 10—The command byte to the conversion register begins the acquisition (CNVST is not required).
conversion. However, coupled noise may result in
degraded ADC SNR.
Internally Timed Acquisitions and
Conversions Using the Serial Interface
If averaging is turned on, multiple CNVST pulses need to
be performed before a result is written to the FIFO. Once
the proper number of conversions has been performed
to generate an averaged FIFO result (as specified to the
averaging register), the scan logic automatically switch-
es the analog-input multiplexer to the next requested
channel. If a temperature measurement is programmed,
it is performed after the first rising edge of CNVST follow-
ing the command byte written to the conversion register.
The temperature-conversion result is available on DOUT
once EOC has been pulled low.
ADC Conversions in Clock Mode 10
In clock mode 10, the wake-up, acquisition, conversion,
and shutdown sequence is initiated by writing a com-
mand byte to the conversion register, and is performed
automatically using the internal oscillator. This is the
default clock mode upon power-up. See Figure 8 for
clock mode 10 timing.
Initiate a scan by writing a command byte to the conver-
sion register. The MAX1220–MAX1223/MAX1257/
MAX1258 then power up, scan all requested channels,
store the results in the FIFO, and shut down. After the
scan is complete, EOC is pulled low and the results are
available in the FIFO. If a temperature measurement is
requested, the temperature result precedes all other
FIFO results. EOC stays low until CS is pulled low again.
Wait until all conversions are complete before reading
the FIFO. SPI communications to the DAC and GPIO
registers are permitted during conversion. However,
coupled noise may result in degraded ADC SNR.
36 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
(CONVERSION BYTE)
DIN
(ACQUISITION1)
(CONVERSION1)
(ACQUISITION2)
CS
SCLK
DOUT
EOC
MSB1
LSB1
MSB2
Figure 9. Clock Mode 11—Externally Timed Acquisition, Sampling, and Conversion without CNVST
Conversion-Time Calculations
The conversion time for each scan is based on a num-
ber of different factors: conversion time per sample,
samples per result, results per scan, if a temperature
measurement is requested, and if the external refer-
ence is in use. Use the following formula to calculate
the total conversion time for an internally timed conver-
sion in clock mode 00 and 10 (see the Electrical
Characteristics, as applicable):
Externally Clocked Acquisitions and
Conversions Using the Serial Interface
ADC Conversions in Clock Mode 11
In clock mode 11, acquisitions and conversions are ini-
tiated by writing a command byte to the conversion
register and are performed one at a time using the
SCLK as the conversion clock. Scanning, averaging
and the FIFO are disabled, and the conversion result is
available at DOUT during the conversion. Output data
is updated on the rising edge of SCLK in clock mode
11. See Figure 9 for clock mode 11 timing.
Total conversion time =
t
x n
x n + t + t
SCAN TS INT-REF,SU
CNV
AVG
where:
= t
Initiate a conversion by writing a command byte to the
conversion register followed by 16 SCLK cycles. If CS
is pulsed high between the eighth and ninth cycles, the
pulse width must be less than 100µs. To continuously
convert at 16 cycles per conversion, alternate 1 byte of
zeros (NOP byte) between each conversion byte. If 2
NOP bytes follow a conversion byte, the analog cells
power down at the end of the second NOP. Set the
FBGON bit to one in the reset register to keep the inter-
nal bias block powered.
t
, where t
is dependent on the clock
DOV
CNV
DOV
mode and the reference mode selected
n
= samples per result (amount of averaging)
AVG
n
= number of times each channel is scanned; set
SCAN
to one unless [SCAN1, SCAN0] = 10
t
= time required for temperature measurement
TS
(53.1µs); set to zero if temperature measurement is not
requested
If reference mode 00 is requested, or if an external refer-
ence is selected but a temperature measurement is being
requested, wait 45µs with CS high after writing the con-
version byte to extend the acquisition and allow the inter-
nal reference to power up. To perform a temperature
measurement, write 24 bytes (192 cycles) of zeros after
the conversion byte. The temperature result appears on
DOUT during the last 2 bytes of the 192 cycles.
t
= t
(external-reference wake-up); if a
WU
INT-REF,SU
conversion using the external reference is requested
In clock mode 01, the total conversion time depends on
how long CNVST is held low or high. Conversion time in
externally clocked mode (CKSEL1, CKSEL0 = 11)
depends on the SCLK period and how long CS is held
high between each set of eight SCLK cycles. In clock
mode 01, the total conversion time does not include the
time required to turn on the internal reference.
______________________________________________________________________________________ 37
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
t
CH
t
CL
32
16
8
SCLK
DIN
5
1
2
3
4
t
DH
t
DS
D13
D12
D11
D15
D14
D1
D0
t
DOT
t
DOD
t
DOE
D15
D7
D14
D6
D12
D4
D13
D5
DOUT
D1
D0
t
CSS
t
CSPWH
t
CSH
CS
Figure 10. DAC/GPIO Serial-Interface Timing (Clock Modes 00, 01, and 10)
DAC/GPIO Timing
Figures 10–13 detail the timing diagrams for writing to
the DAC and GPIOs. Figure 10 shows the timing speci-
fications for clock modes 00, 01, and 10. Figure 11
shows the timing specifications for clock mode 11.
Figure 12 details the timing specifications for the DAC
input select register and 2 bytes to follow. Output data
is updated on the rising edge of SCLK in clock mode
11. Figure 13 shows the GPIO timing. Figure 14 shows
the timing details of a hardware LDAC command DAC-
register update. For a software-command DAC-register
update, t is valid from the rising edge of CS, which fol-
S
lows the last data bit in the software command word.
38 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
t
CH
t
CL
32
16
8
SCLK
5
1
2
3
4
t
DH
t
DS
D15
D14
D13
D12
D11
D1
D0
DIN
DOUT
CS
t
t
DOT
DOE
t
DOD
D15
D7
D14
D6
D13
D5
D12
D4
D1
D0
t
CSS
t
CSPWH
t
CSH
Figure 11. DAC/GPIO Serial-Interface Timing (Clock Mode 11)
SCLK
10
24
1
2
8
9
DIN
BIT 7 (MSB)
BIT 6
BIT 0 (LSB)
BIT 15
BIT 14
BIT 1
BIT 0
DOUT
CS
THE COMMAND BYTE
INITIALIZES THE DAC SELECT
REGISTER
THE NEXT 16 BITS SELECT THE DAC
AND THE DATA WRITTEN TO IT
Figure 12. DAC-Select Register Byte and DAC Serial-Interface Word
______________________________________________________________________________________ 39
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
CS
t
GOD
t
GSU
GPIO INPUT/OUTPUT
Figure 13. GPIO Timing
t
LDACPWL
LDAC
t
S
1 LSB
OUT_
Figure 14. LDAC Functionality
The MAX1220–MAX1223/MAX1257/MAX1258 thin QFN
packages contain an exposed pad on the underside of
the device. Connect this exposed pad to AGND. Refer to
the MAX1258EVKIT for an example of proper layout.
LDAC Functionality
Drive LDAC low to transfer the content of the input reg-
isters to the DAC registers. Drive LDAC permanently
low to make the DAC register transparent. The DAC
output typically settles from zero to full scale within
LSB after 2µs. See Figure 14.
1
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. INL for
the MAX1220–MAX1223/MAX1257/MAX1258 is mea-
sured using the end-point method.
Layout, Grounding, and Bypassing
For best performance, use PC boards. Ensure that digi-
tal and analog signal lines are separated from each
other. Do not run analog and digital signals parallel to
one another (especially clock signals) or do not run
digital lines underneath the MAX1220–MAX1223/
MAX1257/MAX1258 package. High-frequency noise in
the AV
power supply may affect performance.
DD
Bypass the AV
AGND, close to the AV
with a 0.1µF capacitor to DGND, close to the DV
supply with a 0.1µF capacitor to
DD
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
pin. Bypass the DV
supply
DD
DD
pin.
DD
Minimize capacitor lead lengths for best supply-noise
rejection. If the power supply is very noisy, connect a
10Ω resistor in series with the supply to improve power-
supply filtering.
40 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Unipolar ADC Offset Error
For an ideal converter, the first transition occurs at 0.5
LSB, above zero. Offset error is the amount of deviation
between the measured first transition point and the
ideal first transition point.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
SINAD(dB) = 20 x log (Signal
/ Noise
)
RMS
RMS
Bipolar ADC Offset Error
While in bipolar mode, the ADC’s ideal midscale transi-
tion occurs at AGND -0.5 LSB. Bipolar offset error is the
measured deviation from this ideal value.
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the ENOB as follows:
ADC Gain Error
Gain error is defined as the amount of deviation
between the ideal transfer function and the measured
transfer function, with the offset error removed and with
a full-scale analog input voltage applied to the ADC,
resulting in all ones at DOUT.
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
DAC Offset Error
DAC offset error is determined by loading a code of all
zeros into the DAC and measuring the analog output
voltage.
2
2
2
2
2
THD = 20 x log
V
+ V3 + V4 + V5 + V6 /V
(
)
2
1
DAC Gain Error
DAC gain error is defined as the amount of deviation
between the ideal transfer function and the measured
transfer function, with the offset error removed, when
loading a code of all ones into the DAC.
where V is the fundamental amplitude, and V through
6
1
2
V are the amplitudes of the first five harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest distortion
component.
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples.
ADC Channel-to-Channel Crosstalk
Bias the ON channel to midscale. Apply a full-scale sine
wave test tone to all OFF channels. Perform an FFT on
the ON channel. ADC channel-to-channel crosstalk is
expressed in dB as the amplitude of the FFT spur at the
frequency associated with the OFF channel test tone.
Aperture Delay
Aperture delay (t ) is the time between the rising
AD
edge of the sampling clock and the instant when an
actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analog-
to-digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N bits):
Intermodulation Distortion (IMD)
IMD is the total power of the intermodulation products
relative to the total input power when two tones, f1 and
f2, are present at the inputs. The intermodulation prod-
ucts are (f1 f2), (2 x f1), (2 x f2), (2 x f1 f2), (2 x f2
f1). The individual input tone levels are at -7dB FS.
SNR = (6.02 x N + 1.76)dB
Small-Signal Bandwidth
A small -20dB FS analog input signal is applied to an
ADC so the signal’s slew rate does not limit the ADC’s
performance. The input frequency is then swept up to
the point where the amplitude of the digitized conver-
sion result has decreased by -3dB. Note that the T/H
performance is usually the limiting factor for the small-
signal input bandwidth.
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise. RMS noise
includes all spectral components to the Nyquist fre-
quency excluding the fundamental, the first five har-
monics, and the DC offset.
______________________________________________________________________________________ 41
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Full-Power Bandwidth
A large -0.5dB FS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full-
power input bandwidth frequency.
DAC Power-Supply Rejection
DAC PSR is the amount of change in the converter’s
value at full-scale as the power-supply voltage changes
from its nominal value. PSR assumes the converter’s
linearity is unaffected by changes in the power-supply
voltage.
DAC Digital Feedthrough
DAC digital feedthrough is the amount of noise that
appears on the DAC output when the DAC digital con-
trol lines are toggled.
Chip Information
TRANSISTOR COUNT: 58,141
PROCESS: BiCMOS
ADC Power-Supply Rejection
ADC power-supply rejection (PSR) is defined as the
shift in offset error when the power-supply is moved
from the minimum operating voltage to the maximum
operating voltage.
42 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Pin Configurations
TOP VIEW
1
2
3
4
5
6
7
8
9
27 AIN2
26 REF1
25 AIN1
24 N.C.
23 AIN0
22 RES_SEL
21 CS
GPIOA0
GPIOA1
EOC
1
2
3
4
5
6
7
8
9
27 AIN0
CNVST/AIN11
N.C.
26 REF1
25 GPIOC1
24 GPIOC0
23 N.C.
EOC
DV
DD
DV
DD
DGND
DOUT
SCLK
DIN
DGND
DOUT
SCLK
DIN
MAX1222
MAX1223
MAX1220
MAX1221
22 RES_SEL
21 CS
LDAC
20
LDAC
20
OUT0
19 OUT7
OUT0
19 OUT7
THꢂI QFI
THꢂI QFI
36
35
34
33
32
31
30
29
28
27
26
25
CNVST/AIN15
1
2
3
4
5
6
7
8
9
AIN2
REF1
AIN1
AIN0
GPIOA0
GPIOA1
EOC
GPIOA2
GPIOA3
GPIOC3
GPIOC2
GPIOC1
GPIOC0
RES_SEL
CS
MAX1257
MAX1258
DV
DD
DGND
DOUT
SCLK 10
DIN 11
LDAC
OUT7
OUT0 12
THꢂI QFI
______________________________________________________________________________________ 43
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to wwwꢀmaxim-icꢀcom/packages.)
D2
D
C
L
b
D2/2
D/2
k
E/2
E2/2
C
(NE-1) X
e
E
E2
L
k
L
DETAIL A
e
(ND-1) X
e
DETAIL B
e
C
C
L
L
L
L1
L
L
e
e
DALLAS
SEMICONDUCTOR
A
A1
A2
PROPRIETARYINFORMATION
TITLE:
PACKAGE OUTLINE
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0144
D
2
44 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to wwwꢀmaxim-icꢀcom/packages.)
DALLAS
SEMICONDUCTOR
PROPRIETARYINFORMATION
TITLE:
PACKAGE OUTLINE
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
2
21-0144
D
2
______________________________________________________________________________________ 4.
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to wwwꢀmaxim-icꢀcom/packages.)
D2
D
C
L
b
D/2
D2/2
k
E/2
E2/2
(NE-1) X
e
C
L
E
E2
k
L
e
(ND-1) X
e
e
L
C
C
L
L
L1
L
L
e
e
A
A1
A2
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
1
E
21-0141
2
46 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to wwwꢀmaxim-icꢀcom/packages.)
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
2
E
21-0141
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 47
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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