MAX1221 [MAXIM]
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports; 12位，多通道ADC / DAC，带有FIFO ，温度传感器和GPIO端口
| 型号： | MAX1221 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports |
| 文件： | 总44页 (文件大小：553K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4010; Rev 1; 12/07
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2/MAX143
General Description
Features
♦ 12-Bit, 225ksps ADC
The MAX1221/MAX1223/MAX1343 integrate a multichan-
nel, 12-bit, analog-to-digital converter (ADC) and a 12-bit,
digital-to-analog converter (DAC) in a single IC. The
devices also include a temperature sensor and config-
urable general-purpose I/O ports (GPIOs) with a 25MHz
SPI™-/QSPI™-/MICROWIRE™-compatible serial inter-
face. The ADC is available in a 12 or an eight input-chan-
nel version. The DAC outputs settle within 2.0µs, and the
ADC has a 225ksps conversion rate.
Analog Multiplexer with True-Differential
Track/Hold (T/H)
12 Single-Ended Channels or Six Differential
Channels (Unipolar or Bipolar) (MAX1223)
Eight Single-Ended Channels or Four Differential
Channels (Unipolar or Bipolar)
(MAX1221/MAX1343)
Excellent Accuracy: ±±05 ꢀSB ꢁIꢀ, ±±05 ꢀSB DIꢀ
♦ 12-Bit, Octal, 2µs Settling DAC
(MAX1221/MAX1223)
All devices include an internal reference (2.5V) providing
a well-regulated, low-noise reference for both the ADC
and DAC. Programmable reference modes for the ADC
and DAC allow the use of an internal reference, an exter-
nal reference, or a combination of both. Features such as
an internal 1ꢀC accurate temperature sensor, FIFO,
scan modes, programmable internal or external clock
modes, data averaging, and AutoShutdown™ allow users
to minimize both power consumption and processor
requirements. The low glitch energy (4nV•s) and low digi-
tal feedthrough (0.5nV•s) of the integrated DACs make
these devices ideal for digital control of fast-response
closed-loop systems.
Ultra-ꢀow Glitch Energy (4nV•s)
Power-Up Options from Zero Scale or Full Scale
Excellent Accuracy: ±±05 ꢀSB ꢁIꢀ
♦ ꢁnternal Reference or External Single-Ended/
Differential Reference
ꢁnternal Reference Voltage 205V
♦ ꢁnternal ±1ꢂC Accurate Temperature Sensor
♦ On-Chip FꢁFO Capable of Storing 16 ADC
Conversion Results and One Temperature Result
♦ On-Chip Channel-Scan Mode and ꢁnternal
Data-Averaging Features
The devices are guaranteed to operate with a supply volt-
age from +2.7V to +5.25V. The devices consume 2.5mA
at 225ksps throughput, only 22µA at 1ksps throughput,
and under 0.2µA in the shutdown mode. The MAX1221/
MAX1343 offer four GPIOs that can be configured as
inputs or outputs.
♦ Analog Single-Supply Operation
+207V to +5025V
♦ 207V to AV
Digital Supply
DD
♦ 25MHz, SPꢁ/QSPꢁ/MꢁCROWꢁRE Serial ꢁnterface
♦ AutoShutdown Between Conversions
♦ ꢀow-Power ADC
205mA at 225ksps
22µA at 1ksps
The MAX1221/MAX1223/MAX1343 are available in 36-pin
thin QFN packages. All devices are specified over the
-40ꢀC to +85ꢀC temperature range.
±02µA at Shutdown
Applications
Closed-Loop Controls for Optical Components
and Base Stations
♦ ꢀow-Power DAC: 105mA
♦ Evaluation Kit Available (Order MAX1258EVKꢁT)
System Supervision and Control
Data-Acquisition Systems
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
Pin Configurations appear at end of data sheet0
Ordering Information/Selector Guide
REF
VOꢀTAGE
(V)
AIAꢀOG
SUPPꢀY
VOꢀTAGE (V)
RESOꢀUTꢁOI
BꢁTS**
ADC
DAC
PKG
CODE
PART
PꢁI-PACKAGE
GPꢁOs
CHAIIEꢀS CHAIIEꢀS
MAX1221BETX
MAX1223BETX
MAX1343BETX
36 Thin QFN-EP*
36 Thin QFN-EP*
36 Thin QFN-EP*
2.5
2.5
2.5
2.7 to 5.25
2.7 to 5.25
2.7 to 5.25
12
12
12
8
12
8
8
8
4
4
0
4
T3666-3
T3666-3
T3666-3
Iote: All devices are specified over the -40ꢀC to +85ꢀC operating temperature range.
*EP = Exposed pad.
**Number of resolution bits refers to both DAC and ADC.
________________________________________________________________ Maxim ꢁntegrated Products
1
For pricing delivery, and ordering information please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www0maxim-ic0com0
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ABSOꢀUTE MAXꢁMUM RATꢁIGS
AV
to AGND .........................................................-0.3V to +6V
Maximum Current into OUT_.............................................100mA
DD
DGND to AGND.....................................................-0.3V to +0.3V
DV to AV .......................................................-3.0V to +0.3V
Digital Inputs to DGND.............................................-0.3V to +6V
Continuous Power Dissipation (T = +70ꢀC)
36-Pin Thin QFN (6mm x 6mm)
(derate 26.3mW/ꢀC above +70ꢀC)......................2105.3mW
Operating Temperature Range ...........................-40ꢀC to +85ꢀC
Storage Temperature Range.............................-60ꢀC to +150ꢀC
Junction Temperature......................................................+150ꢀC
Lead Temperature (soldering, 10s) .................................+300ꢀC
A
DD
DD
Digital Outputs to DGND.........................-0.3V to (DV + 0.3V)
DD
Analog Inputs, Analog Outputs and REF_
to AGND...............................................-0.3V to (AV + 0.3V)
DD
Maximum Current into Any Pin (except AGND, DGND, AV
,
DD
DV , and OUT_)...........................................................50mA
DD
Iote: If the package power dissipation is not exceeded, one output at a time may be shorted to AV , DV , AGND, or DGND
DD
DD
indefinitely.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
EꢀECTRꢁCAꢀ CHARACTERꢁSTꢁCS
(AV
= DV
= 2.7V to 5.25V, external reference V
= 2.5V, f
= 3.6MHz (50% duty cycle), T = -40ꢀC to +85ꢀC, unless other-
CLK A
DD
DD
REF
wise noted. Typical values are at AV
= DV
= 3V. T = +25ꢀC. Outputs are unloaded, unless otherwise noted.)
DD A
DD
PARAMETER
SYMBOꢀ
COIDꢁTꢁOIS
ADC
MꢁI
TYP
MAX
UIꢁTS
DC ACCURACY (Iote 1)
Resolution
12
Bits
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
0.5
0.5
0.5
0.5
0.8
0.1
1.0
1.0
4.0
4.0
DNL
LSB
LSB
2/MAX143
Gain Error
(Note 2)
LSB
Gain Temperature Coefficient
Channel-to-Channel Offset
ppm/ꢀC
LSB
DYIAMꢁC SPECꢁFꢁCATꢁOIS (1±kHz sine-wave input, V = 205V , 225ksps, f
= 306MHz)
ꢁI
P-P
CꢀK
Signal-to-Noise Plus Distortion
SINAD
70
dB
Total Harmonic Distortion
(Up to the Fifth Harmonic)
THD
-76
dBc
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Linear Bandwidth
SFDR
IMD
72
76
100
1
dBc
dBc
kHz
f
= 9.9kHz, f
= 10.2kHz
IN1
IN2
SINAD > 70dB
-3dB point
Full-Power Bandwidth
MHz
COIVERSꢁOI RATE (Iote 3)
External reference
0.8
µs
Conversion
clock
Power-Up Time
t
PU
Internal reference (Note 4)
218
cycles
2
_______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2/MAX143
EꢀECTRꢁCAꢀ CHARACTERꢁSTꢁCS (continued)
(AV
= DV
= 2.7V to 5.25V, external reference V
= 2.5V, f
= 3.6MHz (50% duty cycle), T = -40ꢀC to +85ꢀC, unless other-
DD
DD
REF
CLK A
wise noted. Typical values are at AV
= DV
= 3V. T = +25ꢀC. Outputs are unloaded, unless otherwise noted.)
DD A
DD
PARAMETER
Acquisition Time
SYMBOꢀ
COIDꢁTꢁOIS
MꢁI
TYP
MAX
UIꢁTS
t
(Note 5)
0.6
µs
ACQ
Internally clocked
5.5
Conversion Time
t
µs
CONV
Externally clocked
3.6
0.1
40
External-Clock Frequency
Duty Cycle
f
Externally clocked conversion (Note 5)
3.6
60
MHz
%
CLK
Aperture Delay
30
ns
Aperture Jitter
< 50
ps
AIAꢀOG ꢁIPUTS
Unipolar
Bipolar
0
V
REF
Input Voltage Range (Note 6)
V
-V
/ 2
V
/ 2
REF
REF
Input Leakage Current
Input Capacitance
0.01
24
1
µA
pF
ꢁITERIAꢀ TEMPERATURE SEISOR
T
T
= +25ꢀC
0.7
1.0
1/8
A
A
Measurement Error (Notes 5, 7)
ꢀC
= T
to T
2.0
MIN
MAX
Temperature Resolution
ꢁITERIAꢀ REFEREICE
REF1 Output Voltage
ꢀC/LSB
(Note 8)
2.482
2.50
30
2.518
V
REF1 Voltage Temperature
Coefficient
TC
ppm/ꢀC
REF
REF1 Output Impedance
REF1 Short-Circuit Current
EXTERIAꢀ REFEREICE
6.5
kΩ
V
= 2.5V
0.39
mA
REF
AV
0.05
+
DD
REF1 Input Voltage Range
V
V
REF mode 11 (Note 4)
1
V
V
REF1
REF2
AV
0.05
+
DD
REF mode 01
REF mode 11
1
0
REF2 Input Voltage Range
(Note 4)
1
_______________________________________________________________________________________
3
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
EꢀECTRꢁCAꢀ CHARACTERꢁSTꢁCS (continued)
(AV
= DV
= 2.7V to 5.25V, external reference V
= 2.5V, f
= 3.6MHz (50% duty cycle), T = -40ꢀC to +85ꢀC, unless other-
DD
DD
REF
CLK A
wise noted. Typical values are at AV
= DV
= 3V. T = +25ꢀC. Outputs are unloaded, unless otherwise noted.)
DD A
DD
PARAMETER
SYMBOꢀ
COIDꢁTꢁOIS
= 2.5V, f = 225ksps
MꢁI
TYP
25
MAX
80
1
UIꢁTS
V
REF
SAMPLE
REF1 Input Current (Note 9)
I
I
µA
REF1
REF2
Acquisition between conversions
= 2.5V, f = 225ksps
0.01
25
V
80
1
REF
SAMPLE
REF2 Input Current
µA
Acquisition between conversions
0.01
DAC
DC ACCURACY (Iote 1±)
Resolution
12
Bits
LSB
LSB
mV
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
0.5
4
DNL
Guaranteed monotonic
(Note 8)
1.0
10
V
3
10
5
OS
ppm of
FS/ꢀC
Offset-Error Drift
Gain Error
GE
(Note 8)
10
LSB
ppm of
FS/ꢀC
Gain Temperature Coefficient
DAC OUTPUT
8
AV
0.02
-
-
DD
No load
0.02
0.1
Output Voltage Range
V
AV
0.1
DD
2/MAX143
10kΩ load to either rail
DC Output Impedance
Capacitive Load
0.5
Ω
(Note 11)
1
nF
AV
= 2.7V, V
= 2.5V,
DD
REF
Resistive Load to AGND
R
L
2000
Ω
gain error < 1%
4
_______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2/MAX143
EꢀECTRꢁCAꢀ CHARACTERꢁSTꢁCS (continued)
(AV
= DV
= 2.7V to 5.25V, external reference V
= 2.5V, f
= 3.6MHz (50% duty cycle), T = -40ꢀC to +85ꢀC, unless other-
DD
DD
REF
CLK A
wise noted. Typical values are at AV
= DV
= 3V. T = +25ꢀC. Outputs are unloaded, unless otherwise noted.)
DD A
DD
PARAMETER
Wake-Up Time (Note 12)
1kΩ Output Termination
100kΩ Output Termination
SYMBOꢀ
COIDꢁTꢁOIS
From power-down mode, AV
From power-down mode, AV
MꢁI
TYP
25
21
1
MAX
UIꢁTS
µs
= 5V
DD
DD
= 2.7V
Programmed in power-down mode
kΩ
At wake-up or programmed in
power-down mode
100
kΩ
DYIAMꢁC PERFORMAICE (Iotes 5, 13)
Output-Voltage Slew Rate
Output-Voltage Settling Time
Digital Feedthrough
SR
Positive and negative
3
V/µs
µs
t
To 1 LSB, 400 - C00 hex (Note 7)
Code 0, all digital inputs from 0 to DV
2
5
S
0.5
nV•s
DD
Major Code Transition Glitch
Impulse
Between codes 2047 and 2048
4
nV•s
From V
660
720
260
320
REF
Output Noise (0.1Hz to 50MHz)
Output Noise (0.1Hz to 500kHz)
µV
µV
P-P
P-P
Using internal reference
From V
REF
Using internal reference
DAC-to-DAC Transition
Crosstalk
0.5
nV•s
ꢁITERIAꢀ REFEREICE
REF1 Output Voltage
2.482
2.50
30
2.518
V
REF1 Temperature Coefficient
REF1 Short-Circuit Current
EXTERIAꢀ-REFEREICE ꢁIPUT
REF1 Input Voltage Range
REF1 Input Impedance
TC
ppm/ꢀC
mA
REF
V
= 2.5V
0.39
REF
V
R
REF modes 01, 10, and 11 (Note 4)
0.7
70
AV
V
REF1
DD
100
130
kΩ
REF1
DꢁGꢁTAꢀ ꢁITERFACE
DꢁGꢁTAꢀ ꢁIPUTS (SCꢀK, DꢁI, CS, CNVST, LDAC)
Input-Voltage High
V
DV = 2.7V to 5.25V
2.4
V
V
IH
DD
DV = 3.6V to 5.25V
0.8
0.6
10
DD
Input-Voltage Low
V
IL
DV = 2.7V to 3.6V
DD
Input Leakage Current
Input Capacitance
I
0.01
15
µA
pF
L
C
IN
DꢁGꢁTAꢀ OUTPUT (DOUT) (Iote 14)
Output-Voltage Low
V
I
= 2mA
SINK
0.4
V
OL
_______________________________________________________________________________________
5
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
EꢀECTRꢁCAꢀ CHARACTERꢁSTꢁCS (continued)
(AV
= DV
= 2.7V to 5.25V, external reference V
= 2.5V, f
= 3.6MHz (50% duty cycle), T = -40ꢀC to +85ꢀC, unless other-
DD
DD
REF
CLK A
wise noted. Typical values are at AV
= DV
= 3V. T = +25ꢀC. Outputs are unloaded, unless otherwise noted.)
DD A
DD
PARAMETER
SYMBOꢀ
COIDꢁTꢁOIS
= 2mA
SOURCE
MꢁI
TYP
MAX
UIꢁTS
DV
-
-
DD
Output-Voltage High
V
I
V
OH
0.5
Tri-State Leakage Current
Tri-State Output Capacitance
DꢁGꢁTAꢀ OUTPUT (EOC) (Iote 14)
Output-Voltage Low
10
µA
pF
C
15
OUT
V
I
I
= 2mA
0.4
10
V
V
OL
SINK
DV
DD
Output-Voltage High
V
= 2mA
SOURCE
OH
0.5
Tri-State Leakage Current
µA
pF
Tri-State Output Capacitance
C
15
OUT
DꢁGꢁTAꢀ OUTPUTS (GPꢁO_) (Iote 14)
I
I
= 2mA
0.4
0.8
SINK
GPIOC_ Output-Voltage Low
V
= 4mA
SINK
DV
0.5
-
-
DD
GPIOC_ Output-Voltage High
GPIOA_ Output-Voltage Low
GPIOA_ Output-Voltage High
Tri-State Leakage Current
I
I
I
= 2mA
V
V
V
SOURCE
= 15mA
0.8
10
SINK
DV
0.8
DD
= 15mA
SOURCE
µA
pF
Tri-State Output Capacitance
C
15
OUT
DD
2/MAX143
POWER REQUꢁREMEITS (Iote 15)
Digital Positive-Supply Voltage
Digital Positive-Supply Current
Analog Positive-Supply Voltage
DV
2.7
AV
V
µA
mA
V
DD
Idle, all blocks shut down
0.2
1
4
DI
DD
Only ADC on, external reference
AV
2.70
5.25
2
DD
Idle, all blocks shut down
0.2
2.8
2.6
1.5
-77
µA
f
f
= 225ksps
= 100ksps
4.2
SAMPLE
SAMPLE
Only ADC on,
external reference
Analog Positive-Supply Current
A
IDD
mA
All DACs on, no load, internal reference
AV = 2.7V
4.0
0.5
REF1 Positive-Supply Rejection
DAC Positive-Supply Rejection
PSRR
PSRD
dB
DD
Output code = FFFhex,
AV = 2.7V to 5.25V
0.1
mV
DD
6
_______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2/MAX143
EꢀECTRꢁCAꢀ CHARACTERꢁSTꢁCS (continued)
(AV
= DV
= 2.7V to 5.25V, external reference V
= 2.5V, f
= 3.6MHz (50% duty cycle), T = -40ꢀC to +85ꢀC, unless other-
DD
DD
REF
CLK A
wise noted. Typical values are at AV
= DV
= 3V. T = +25ꢀC. Outputs are unloaded, unless otherwise noted.)
DD A
DD
PARAMETER
SYMBOꢀ
COIDꢁTꢁOIS
Full-scale input, AV = 2.7V to 5.25V
MꢁI
TYP
MAX
UIꢁTS
ADC Positive-Supply Rejection
PSRA
0.06
0.5
mV
DD
TꢁMꢁIG CHARACTERꢁSTꢁCS (Figures 6–13)
SCLK Clock Period
t
40
16
16
ns
ns
ns
CP
CH
SCLK Pulse-Width High
SCLK Pulse-Width Low
t
40/60 duty cycle
60/40 duty cycle
t
CL
GPIO Output Rise/Fall After
CS Rise
t
C
= 20pF
100
ns
GOD
LOAD
GPIO Input Setup Before CS Fall
LDAC Pulse Width
t
0
20
1.8
10
1.8
10
10
0
ns
ns
GSU
t
LDACPWL
C
C
C
C
= 20pF, SLOW = 0
= 20pF, SLOW = 1
= 20pF, SLOW = 0
= 20pF, SLOW = 1
12.0
40
LOAD
LOAD
LOAD
LOAD
SCLK Fall to DOUT Transition
(Note 16)
t
t
ns
ns
DOT
DOT
12.0
40
SCLK Rise to DOUT Transition
(Notes 16, 17)
CS Fall to SCLK Fall Setup Time
SCLK Fall to CS Rise Setup Time
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
CS Pulse-Width High
t
ns
ns
ns
ns
ns
ns
ns
ns
CSS
t
2000
CSH
t
10
0
DS
t
DH
t
50
CSPWH
CS Rise to DOUT Disable
CS Fall to DOUT Enable
EOC Fall to CS Fall
t
C
C
= 20pF
= 20pF
25
DOD
LOAD
LOAD
t
1.5
30
25.0
DOE
t
RDS
CKSEL = 01 (temp sense) or CKSEL = 10
(temp sense), internal reference on
65
CKSEL = 01 (temp sense) or CKSEL = 10
(temp sense), internal reference initially off
140
CS or CNVST Rise to EOC
Fall—Internally Clocked
Conversion Time
t
µs
DOV
CKSEL = 01 (voltage conversion)
9
9
CKSEL = 10 (voltage conversion), internal
reference on
CKSEL = 10 (voltage conversion), internal
reference initially off
80
CKSEL = 00, CKSEL = 01 (temp sense)
CKSEL = 01 (voltage conversion)
40
ns
µs
CNVST Pulse Width
t
CSW
1.4
_______________________________________________________________________________________
7
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
EꢀECTRꢁCAꢀ CHARACTERꢁSTꢁCS (continued)
(AV
= DV
= 2.7V to 5.25V, external reference V
= 2.5V, f
= 3.6MHz (50% duty cycle), T = -40ꢀC to +85ꢀC, unless other-
DD
DD
REF
CLK A
wise noted. Typical values are at AV
= DV
= 3V. T = +25ꢀC. Outputs are unloaded, unless otherwise noted.)
DD A
DD
Iote 1: Tested at DV
= AV
= +2.7V.
DD
DD
Iote 2: Offset nulled.
Iote 3: No bus activity during conversion. Conversion time is defined as the number of conversion clock cycles, multiplied by the
clock period.
Iote 4: See Table 5 for reference-mode details.
Iote 5: Not production tested. Guaranteed by design.
Iote 6: See the ADC/DAC References section.
Iote 7: Fast automated test, excludes self-heating effects.
Iote 8: Specified over the -40ꢀC to +85ꢀC temperature range.
Iote 9: REFSEL[1:0] = 00 or when DACs are not powered up.
Iote 1±: DAC linearity, gain, and offset measurements are made between codes 115 and 3981.
Iote 11: The DAC buffers are guaranteed by design to be stable with a 1nF load.
Iote 12: Time required by the DAC output to power up and settle within 1 LSB in the external reference mode.
Iote 13: All DAC dynamic specifications are valid for a load of 100pF and 10kΩ.
Iote 14: Only one digital output (either DOUT, EOC, or the GPIOs) can be indefinitely shorted to either supply at one time.
Iote 15: All digital inputs at either DV
or DGND. DV
should not exceed AV
.
DD
DD
DD
Iote 16: See the Reset Register section and Table 9 for details on programming the SLOW bit.
Iote 17: Clock mode 11 only.
Typical Operating Characteristics
(AV
= DV
= 3V external V
= 2.5V, f
= 3.6MHz (50% duty cycle), f
= 225ksps, C
= 50pF, 0.1µF capacitor at
DD
DD
REF
CLK
SAMPLE
LOAD
REF, T = +25ꢀC, unless otherwise noted.)
A
2/MAX143
ANALOG SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
ANALOG SHUTDOWN CURRENT
vs. TEMPERATURE
0.5
1.00
0.4
0.3
0.2
0.1
0
AV = DV = 5V
DD
DD
EXTERNAL REFERENCE = 4.096V
0.75
0.50
0.25
0
0.4
0.3
0.2
0.1
0
-0.25
-0.50
-0.75
-1.00
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
1024
2048
3072
4096
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
OUTPUT CODE
TEMPERATURE (°C)
8
_______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2/MAX143
Typical Operating Characteristics (continued)
(AV
= DV
= 3V external V
= 2.5V, f
= 3.6MHz (50% duty cycle), f
= 225ksps, C
= 50pF, 0.1µF capacitor at
DD
DD
REF
CLK
SAMPLE
LOAD
REF, T = +25ꢀC, unless otherwise noted.)
A
ADC INTEGRAL NONLINEARITY
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
vs. OUTPUT CODE
1.00
1.00
1.00
0.75
0.50
0.25
0
AV = DV = 5V
EXTERNAL REFERENCE = 4.096V
DD
DD
0.75
0.50
0.25
0
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
0
1024
2048
3072
4096
0
1024
2048
3072
4096
0
1024
2048
3072
4096
OUTPUT CODE
OUTPUT CODE
OUTPUT CODE
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
ADC GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
ADC OFFSET ERROR vs. TEMPERATURE
2
1
1.0
0.8
0.6
0.4
0.2
0
1.0
0.5
0
0
-1
-2
-0.5
-1.0
-40
-15
10
35
60
85
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
ADC EXTERNAL REFERENCE
INPUT CURRENT vs. SAMPLING RATE
ANALOG SUPPLY CURRENT
vs. SAMPLING RATE
ADC GAIN ERROR vs. TEMPERATURE
2
1
60
50
40
30
20
10
0
3.0
2.5
2.0
1.5
1.0
0.5
0
0
-1
-2
-40
-15
10
35
60
85
0
50
100
150
200
250
300
0
50
100
150
200
250
300
TEMPERATURE (°C)
SAMPLING RATE (ksps)
SAMPLING RATE (ksps)
_______________________________________________________________________________________
9
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics (continued)
(AV
= DV
= 3V external V
= 2.5V, f
= 3.6MHz (50% duty cycle), f
= 225ksps, C
= 50pF, 0.1µF capacitor at
DD
DD
REF
CLK
SAMPLE
LOAD
REF, T = +25ꢀC, unless otherwise noted.)
A
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
2.04
DAC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
1.5
2.02
2.00
1.98
1.96
1.94
1.92
1.90
1.88
AV = DV = 5V
DD
DD
EXTERNAL REFERENCE = 4.096V
AV = DV = 5V
2.02
2.00
1.98
1.96
1.94
1.92
1.90
DD
DD
1.0
0.5
0
AV = DV = 3V
DD
DD
-0.5
-1.0
-1.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40
-15
10
35
60
85
0
1024
2048
3072
4096
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
OUTPUT CODE
DAC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
DAC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
DAC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
0.4
0.2
0
0.4
0.2
0
1.5
1.0
0.5
0
AV = DV = 5V
DD
DD
EXTERNAL REFERENCE = 4.096V
2/MAX143
-0.5
-1.0
-1.5
-0.2
-0.4
-0.2
-0.4
2047
2050
2053
2056
2059
2062
2047
2050
2053
2056
2059
2062
0
1024
2048
3072
4096
OUTPUT CODE
OUTPUT CODE
OUTPUT CODE
DAC FULL-SCALE ERROR
vs. ANALOG SUPPLY VOLTAGE
DAC FULL-SCALE ERROR
vs. TEMPERATURE
DAC FULL-SCALE ERROR
vs. TEMPERATURE
10
8
10
8
1.2
1.0
0.8
0.6
0.4
0.2
INTERNAL
REFERENCE
6
6
4
4
2
2
0
0
EXTERNAL
REFERENCE = 4.096V
EXTERNAL
-2
-4
-6
-2
-4
-6
REFERENCE = 2.5V
AV = DV = 5V
AV = DV = 3V
DD
DD
DD
DD
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40
-15
10
35
60
85
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
1± ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2/MAX143
Typical Operating Characteristics (continued)
(AV
= DV
= 3V external V
= 2.5V, f
= 3.6MHz (50% duty cycle), f
= 225ksps, C
= 50pF, 0.1µF capacitor at
DD
DD
REF
CLK
SAMPLE
LOAD
REF, T = +25ꢀC, unless otherwise noted.)
A
DAC FULL-SCALE ERROR
vs. REFERENCE VOLTAGE
DAC FULL-SCALE ERROR
vs. REFERENCE VOLTAGE
DAC FULL-SCALE ERROR
vs. LOAD CURRENT
1.00
0
-1
-2
-3
-4
-5
-6
-7
5
AV = DV = 5V
AV = DV = 5V
EXTERNAL REFERENCE = 4.096V
DD
DD
DD
DD
0.75
0.50
0.25
0
0
-5
-0.25
-0.50
-0.75
-1.00
-10
-15
0
1
2
3
4
5
0
0.5
1.0
1.5
2.0
2.5
3.0
85
85
0
2.5
0
5
10
15
20
25
30
5.5
200
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
LOAD CURRENT (mA)
DAC FULL-SCALE ERROR
vs. LOAD CURRENT
INTERNAL REFERENCE
ADC REFERENCE SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
VOLTAGE vs. TEMPERATURE
5
0
2.52
2.51
2.50
2.49
2.48
25.1
25.0
24.9
24.8
24.7
-5
-10
-15
0
0.5
1.0
1.5
2.0
2.5
3.0
-40
-15
10
35
60
3.0
3.5
4.0
4.5
5.0
LOAD CURRENT (mA)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
ADC REFERENCE SUPPLY
CURRENT vs. TEMPERATURE
ADC REFERENCE SUPPLY
CURRENT vs. TEMPERATURE
ADC FFT PLOT
0
-20
25.1
25.0
24.9
24.8
24.7
41.0
40.9
40.8
40.7
40.6
40.5
f
f
f
= 32.768kHz
= 10.080kHz
= 5.24288MHz
SAMPLE
ANALOG_)N
CLK
SINAD = 71.27dBc
SNR = 71.45dBc
THD = 85.32dBc
SFDR = 87.25dBc
-40
-60
-80
-100
-120
-140
-160
AV = DV = 5V
EXTERNAL REFERENCE = 4.096V
AV = DV = 3V
EXTERNAL REFERENCE = 2.5V
DD
DD
DD
DD
50
100
150
-40
-15
10
35
60
85
-40
-15
10
35
60
ANALOG INPUT FREQUENCY (kHz)
TEMPERATURE (°C)
TEMPERATURE (°C)
______________________________________________________________________________________ 11
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics (continued)
(AV
= DV
= 3V external V
= 2.5V, f
= 3.6MHz (50% duty cycle), f
= 225ksps, C
= 50pF, 0.1µF capacitor at
DD
DD
REF
CLK
SAMPLE
LOAD
REF, T = +25ꢀC, unless otherwise noted.)
A
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
ADC IMD PLOT
ADC CROSSTALK PLOT
0
0
2.08
2.07
2.06
2.05
2.04
2.03
2.02
f
f
f
= 5.24288MHz
= 9.0kHz
= 11.0kHz
= -6dBFS
f = 5.24288MHz
CLK
f = 10.080kHz
IN1
f = 8.0801kHz
IN2
AV = DV = 5V
CLK
IN1
IN2
DD
DD
EXTERNAL REFERENCE = 4.096V
-20
-40
-20
-40
-60
-80
A
SNR = 72.00dBc
THD = 85.24dBc
ENOB = 11.65 BITS
IN
IMD = 82.99dBc
-60
-80
-100
-120
-140
-160
-100
-120
-140
-160
SINKING
SOURCING
DAC OUTPUT = MIDSCALE
2.01
2.00
0
50
100
150
200
0
50
100
150
200
-30
0
30
60
90
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
OUTPUT CURRENT (mA)
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
GPIO OUTPUT VOLTAGE
vs. SOURCE CURRENT
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
5
4
3
2
1
0
DAC OUTPUT = MIDSCALE
GPIOA0, AGPIOA1 OUTPUTS
GPIOC0, GPIOC1 OUTPUTS
2/MAX143
SINKING
SOURCING
AV = DV = 5V
DD
DD
EXTERNAL REFERENCE = 4.096V
-30
-20
0
10
20
30
0
20
40
60
80
100
-10
OUTPUT CURRENT (mA)
SOURCE CURRENT (mA)
GPIO OUTPUT VOLTAGE
vs. SOURCE CURRENT
GPIO OUTPUT VOLTAGE
vs. SINK CURRENT
3.0
2.5
2.0
1.5
1.0
0.5
0
1500
1200
900
600
300
0
GPIOC0, GPIOC1
OUTPUTS
GPIOA0, GPIOA1 OUTPUTS
GPIOC0, GPIOC1
OUTPUTS
GPIOA0, GPIOA1 OUTPUTS
AV = DV = 5V
DD
DD
EXTERNAL REFERENCE = 4.096V
40 60 80 100
SINK CURRENT (mA)
0
20
40
60
80
100
0
20
SOURCE CURRENT (mA)
12 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2/MAX143
Typical Operating Characteristics (continued)
(AV
= DV
= 3V external V
= 2.5V, f
= 3.6MHz (50% duty cycle), f
= 225ksps, C = 50pF, 0.1µF capacitor at
LOAD
DD
DD
REF
CLK
SAMPLE
REF, T = +25ꢀC, unless otherwise noted.)
A
GPIO OUTPUT VOLTAGE
vs. SINK CURRENT
TEMPERATURE SENSOR ERROR
vs. TEMPERATURE
1.00
0.75
0.50
0.25
0
1500
1200
900
600
300
0
GPIOC0, GPIOC1
OUTPUTS
-0.25
-0.50
GPIOA0, GPIOA1 OUTPUTS
-0.75
-1.00
-40
-15
10
35
60
85
0
10
20
30
40
50
60
TEMPERATURE (°C)
SINK CURRENT (mA)
DAC-TO-DAC CROSSTALK
= 10kΩ, C = 100pF)
DAC-TO-DAC CROSSTALK
(R = 10kΩ, C = 100pF)
LOAD
(R
LOAD
LOAD
LOAD
MAX1221 toc40
MAX1221 toc41
V
OUTA
V
OUTA
1V/div
2V/div
V
OUTB
V
OUTB
10mV/div
AC-COUPLED
10mV/div
AC-COUPLED
AV = DV = 5V
DD
DD
EXTERNAL REFERENCE = 4.096V
100μs/div
100μs/div
DYNAMIC RESPONSE RISE TIME
DYNAMIC RESPONSE RISE TIME
(R = 10kΩ, C = 100pF)
(R
LOAD
= 10kΩ, C
= 100pF)
LOAD
MAX1221 toc43
LOAD
LOAD
MAX1221 toc42
CS
2V/div
V
OUT
1V/div
V
OUT
CS
1V/div
2V/div
AV = DV = 5V
DD
DD
EXTERNAL REFERENCE = 4.096V
1μs/div
1μs/div
______________________________________________________________________________________ 13
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics (continued)
(AV
= DV
= 3V external V
= 2.5V, f
= 3.6MHz (50% duty cycle), f
= 225ksps, C
= 50pF, 0.1µF capacitor at
DD
DD
REF
CLK
SAMPLE
LOAD
REF, T = +25ꢀC, unless otherwise noted.)
A
DYNAMIC RESPONSE FALL TIME
(R = 10kΩ, C = 100pF)
DYNAMIC RESPONSE FALL TIME
(R = 10kΩ, C = 100pF)
LOAD
LOAD
LOAD
LOAD
MAX1221 toc44
MAX1221 toc45
CS
2V/div
V
OUT
1V/div
V
OUT
CS
1V/div
2V/div
AV = DV = 5V
DD
DD
EXTERNAL REFERENCE = 4.096V
1μs/div
1μs/div
MAJOR CARRY TRANSITION
(R = 10kΩ, C = 100pF)
MAJOR CARRY TRANSITION
(R
LOAD
= 10kΩ, C
= 100pF)
LOAD
MAX1221 toc47
LOAD
LOAD
MAX1221 toc46
CS
2V/div
CS
1V/div
2/MAX143
V
V
OUT
OUT
10mV/div
20mV/div
AC-COUPLED
AC-COUPLED
AV = DV = 5V
DD
DD
EXTERNAL REFERENCE = 4.096V
1μs/div
1μs/div
DAC DIGITAL FEEDTHROUGH (R
= 10kΩ,
DAC DIGITAL FEEDTHROUGH (R
= 10kΩ,
LOAD
LOAD
C
LOAD
= 100pF, CS = HIGH, DIN = LOW)
C
LOAD
= 100pF, CS = HIGH, DIN = LOW)
MAX1221 toc48
MAX1221 toc49
SCLK
2V/div
SCLK
1V/div
V
OUT
V
OUT
100mV/div
100mV/div
AC-COUPLED
AC-COUPLED
AV = DV = 5V
DD
DD
EXTERNAL REFERENCE = 4.096V
200ns/div
200ns/div
14 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2/MAX143
Typical Operating Characteristics (continued)
(AV
= DV
= 3V external V
= 2.5V, f
= 3.6MHz (50% duty cycle), f
= 225ksps, C
= 50pF, 0.1µF capacitor at
DD
DD
REF
CLK
SAMPLE
LOAD
REF, T = +25ꢀC, unless otherwise noted.)
A
NEGATIVE FULL-SCALE SETTLING TIME
(R = 10kΩ, C = 100pF)
NEGATIVE FULL-SCALE SETTLING TIME
(R = 10kΩ, C = 100pF)
LOAD
LOAD
LOAD
LOAD
MAX1340 toc50
MAX1221 toc51
V
LDAC
V
OUT
2V/div
1V/div
V
OUT_
2V/div
V
LDAC
AV = DV = 5V
EXTERNAL REFERENCE = 4.096V
DD
DD
1V/div
1μs/div
2μs/div
POSITIVE FULL-SCALE SETTLING TIME
(R = 10kΩ, C = 100pF)
POSITIVE FULL-SCALE SETTLING TIME
(R = 10kΩ, C = 100pF)
LOAD
LOAD
LOAD
LOAD
MAX1221 toc53
MAX1221 toc52
V
LDAC
2V/div
V
OUT_
1V/div
V
OUT_
2V/div
V
LDAC
AV = DV = 5V
EXTERNAL REFERENCE = 4.096V
DD
DD
1V/div
1μs/div
1μs/div
ADC REFERENCE FEEDTHROUGH
(R = 10kΩ, C = 100pF)
ADC REFERENCE FEEDTHROUGH
(R = 10kΩ, C = 100pF)
LOAD
LOAD
LOAD
LOAD
MAX1221 toc54
MAX1221 toc55
V
REF2
V
REF2
1V/div
2V/div
V
DAC-OUT
V
DAC-OUT
10mV/div
AC-COUPLED
2mV/div
AC-COUPLED
AV = DV = 5V
EXTERNAL REFERENCE = 4.096V
ADC REFERENCE SWITCHING
DD
DD
ADC REFERENCE SWITCHING
200μs/div
200μs/div
______________________________________________________________________________________ 15
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Pin Description
PꢁI
IAME
FUICTꢁOI
MAX1221 MAX1223 MAX1343
1, 2
—
1, 2
GPIOA0, GPIOA1 General-Purpose I/O A0, A1. GPIOA0, A1 can sink and source 15mA.
Active-Low Conversion-Start Input/Analog Input 11. See Table 5 for details
on programming the setup register.
—
1
—
CNVST/AIN11
Active-Low End-of-Conversion Output. Data is valid after the falling edge
of EOC.
3
3
3
EOC
Digital Positive-Power Input. Bypass DV
capacitor.
to DGND with a 0.1µF
DD
4
5
4
5
4
5
DV
DD
DGND
DOUT
Digital Ground. Connect DGND to AGND.
Serial-Data Output. Data is clocked out on the falling edge of the SCLK
clock in modes 00, 01, and 10. Data is clocked out on the rising edge of
the SCLK clock in mode 11. It is high impedance when CS is high.
6
7
6
7
6
7
Serial-Clock Input. Clocks data in and out of the serial interface. (Duty
cycle must be 40% to 60%). See Table 5 for details on programming the
clock mode.
SCLK
Serial-Data Input. DIN data is latched into the serial interface on the falling
edge of SCLK.
8
8
8
9–12
—
DIN
—
—
OUT0–OUT3
OUT0–OUT7
DAC Outputs
9–12,
16–19
9–12,
16–19
DAC Outputs
2/MAX143
Positive Analog Power Input. Bypass AV
capacitor.
to AGND with a 0.1µF
DD
13
14
13
14
13
14
AV
DD
AGND
N.C.
Analog Ground
15, 23,
32, 33
2, 15, 24,
32
15, 23,
32, 33
No Connection. Not internally connected.
Do Not Connect. Do not connect to this pin.
—
—
16–19
D.C.
Active-Low Load DAC. LDAC is an asynchronous active-low input that
updates the DAC outputs. Drive LDAC low to make the DAC registers
transparent.
20
20
20
LDAC
CS
Active-Low Chip-Select Input. When CS is low, the serial interface is
enabled. When CS is high, DOUT is high impedance.
21
21
21
Reset Select. Select DAC wake-up mode. Set RES_SEL low to wake up
the DAC outputs with a 100kΩ resistor to GND or set RES_SEL high to
22
22
—
22
RES_SEL
wake up the DAC outputs with a 100kΩ resistor to V
. The default is the
REF
external V
.
REF
24, 25
24, 25
GPIOC0, GPIOC1 General-Purpose I/O C0, C1. GPIOC0, C1 can sink 4mA and source 2mA.
16 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2/MAX143
Pin Description (continued)
PꢁI
IAME
FUICTꢁOI
MAX1221 MAX1223 MAX1343
23, 25,
27–31,
—
—
AIN0–AIN9
Analog Inputs
33, 34, 35
Reference 1 Input. Reference voltage; leave unconnected to use the
internal reference (2.5V). REF1 is the positive reference in ADC differential
mode. Bypass REF1 to AGND with a 0.1µF capacitor in external reference
mode only. See the ADC/DAC References section.
26
26
26
REF1
27–31, 34
35
—
—
27–31, 34
35
AIN0–AIN5
REF2/AIN6
Analog Inputs
Reference 2 Input/Analog Input Channel 6. See Table 5 for details on
programming the setup register.
Active-Low Conversion-Start Input/Analog Input 7. See Table 5 for details
on programming the setup register.
36
—
—
—
36
—
36
—
—
CNVST/AIN7
REF2/AIN10
EP
Reference 2 Input/Analog Input Channel 10. See Table 5 for details on
programming the setup register.
Exposed Pad. Must be externally connected to AGND. Do not use as a
ground connect.
______________________________________________________________________________________ 17
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
low to latch any input data at DIN on the falling edge of
Detailed Description
SCLK. Output data at DOUT is updated on the falling
The MAX1221/MAX1223/MAX1343 integrate a multi-
edge of SCLK in clock modes 00, 01, and 10. Output
channel 12-bit ADC, and an octal/quad 12-bit DAC in a
data at DOUT is updated on the rising edge of SCLK in
single IC. The devices also include a temperature sen-
clock mode 11. See Figures 6–11. Bipolar true-differen-
sor and configurable GPIOs with a 25MHz SPI-/QSPI-/
tial results and temperature-sensor results are available
MICROWIRE-compatible serial interface. The ADC is
in two’s complement format, while all other results are in
available in a 12 or an eight input-channel version. The
binary.
DAC outputs settle within 2.0µs, and the ADC has a
225ksps conversion rate.
A high-to-low transition on CS initiates the data-input
operation. Serial communications to the ADC always
begin with an 8-bit command byte (MSB first) loaded
from DIN. The command byte and the subsequent data
bytes are clocked from DIN into the serial interface on
the falling edge of SCLK. The serial-interface and fast-
interface circuitry is common to the ADC, DAC, and
GPIO sections. The content of the command byte
determines whether the SPI port should expect 8, 16, or
24 bits and whether the data is intended for the ADC,
DAC, or GPIOs (if applicable). See Table 1. Driving CS
high resets the serial interface.
All devices include an internal reference (2.5V) provid-
ing a well-regulated, low-noise reference for both the
ADC and DAC. Programmable reference modes for the
ADC and DAC allow the use of an internal reference, an
external reference, or a combination of both. Features
such as an internal 1ꢀC accurate temperature sensor,
FIFO, scan modes, programmable internal or external
clock modes, data averaging, and AutoShutdown allow
users to minimize both power consumption and proces-
sor requirements. The low glitch energy (4nV•s) and
low digital feedthrough (0.5nV•s) of the integrated
DACs make these devices ideal for digital control of
fast-response closed-loop systems.
The conversion register controls ADC channel selec-
tion, ADC scan mode, and temperature-measurement
requests. See Table 4 for information on writing to the
conversion register. The setup register controls the
clock mode, reference, and unipolar/bipolar ADC con-
figuration. Use a second byte, following the first, to
write to the unipolar-mode or bipolar-mode registers.
See Table 5 for details of the setup register and see
Tables 6, 7, and 8 for setting the unipolar- and bipolar-
mode registers. Hold CS low between the command
byte and the second and third byte. The ADC averag-
ing register is specific to the ADC. See Table 9 to
address that register. Table 11 shows the details of the
reset register.
The devices are guaranteed to operate with a supply
voltage from +2.7V to +5.25V. The devices consume
2.5mA at 225ksps throughput, only 22µA at 1ksps
throughput, and under 0.2µA in the shutdown mode.
The MAX1221/MAX1343 offer four GPIOs that can be
configured as inputs or outputs.
2/MAX143
Figure 1 shows the MAX1221 functional diagram. The
MAX1221/MAX1343 only include the GPIOA0, GPIOA1
and GPIOC0, GPIOC1 blocks. The MAX1223 excludes
the GPIOs. The output-conditioning circuitry takes the
internal parallel data bus and converts it to a serial
data format at DOUT, with the appropriate wake-up
timing. The arithmetic logic unit (ALU) performs the
averaging function.
Begin a write to the DAC by writing 0001XXXX as a
command byte. The last 4 bits of this command byte
are don’t-care bits. Write another 2 bytes (holding CS
low) to the DAC interface register following the com-
mand byte to select the appropriate DAC and the data
to be written to it. See the DAC Serial Interface section
and Tables 10, 17, and 18.
SPI-Compatible Serial Interface
The MAX1221/MAX1223/MAX1343 feature a serial inter-
face that is compatible with SPI and MICROWIRE
devices. For SPI, ensure the SPI bus master (typically a
microcontroller (µC)) runs in master mode so that it
generates the serial clock signal. Select the SCLK fre-
quency of 25MHz or less, and set the clock polarity
(CPOL) and phase (CPHA) in the µC control registers to
the same value. The MAX1221/MAX1223/MAX1343
operate with SCLK idling high or low, and thus operate
with CPOL = CPHA = 0 or CPOL = CPHA = 1. Set CS
Write to the GPIOs (if applicable) by issuing a command
byte to the appropriate register. Writing to the
MAX1221/MAX1343 GPIOs requires 1 additional byte fol-
lowing the command byte. See Tables 12–16 for details
on GPIO configuration, writes, and reads. See the GPIO
Command section. Command bytes written to the
GPIOs on devices without GPIOs are ignored.
18 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2/MAX143
DV
AV
DD
DD
GPIOC0,
GPIOC1
GPIOA0,
GPIOA1
MAX1221
GPIO
USER-PROGRAMMABLE
CONTROL
I/O
OUTPUT
CONDITIONING
12-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
OSCILLATOR
SCLK
CS
OUTPUT
CONDITIONING
12-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
DIN
SPI
PORT
OUTPUT
CONDITIONING
12-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
DOUT
OUTPUT
CONDITIONING
12-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
TEMPERATURE
SENSOR
OUTPUT
CONDITIONING
12-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
EOC
LOGIC
CONTROL
OUTPUT
CONDITIONING
12-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
CNVST
T/H
AIN0
AIN5
REF2/
AIN6
12-BIT
SAR
ADC
OUTPUT
CONDITIONING
12-BIT
DAC
FIFO AND
ALU
INPUT
REGISTER
DAC
REGISTER
CNVST/
AIN7
OUTPUT
CONDITIONING
12-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
REF2
INTERNAL
REFERENCE
REF1
RES_SEL
LDAC
AGND
DGND
Figure 1. MAX1221 Functional Diagram
______________________________________________________________________________________ 19
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 10 Command Byte (MSB First)
REGꢁSTER IAME
Conversion
BꢁT 7
BꢁT 6
BꢁT 5
BꢁT 4
BꢁT 3
BꢁT 2
BꢁT 1
BꢁT ±
1
0
0
0
0
0
0
0
0
CHSEL3
CHSEL2
CHSEL1
CHSEL0
SCAN1
SCAN0
TEMP
Setup
1
0
0
0
0
0
0
0
CKSEL1
CKSEL0
REFSEL1
REFSEL0
DIFFSEL1
DIFFSEL0
ADC Averaging
DAC Select
Reset
1
0
0
0
0
0
0
AVGON
NAVG1
NAVG0
NSCAN1
NSCAN0
1
0
0
0
0
0
X
1
0
0
0
0
X
X
X
RESET
SLOW
FBGON
GPIO Configure*
GPIO Write*
GPIO Read*
No Operation
0
0
0
0
1
1
0
0
1
0
1
0
X = Don’t care.
*Only applicable on the MAX1221/MAX1343.
Power-Up Default State
The MAX1221/MAX1223/MAX1343 power up with all
blocks in shutdown (including the reference). All regis-
ters power up in state 00000000, except for the setup
register and the DAC input register. The setup register
powers up at 0010 1000 with CKSEL1 = 1 and REF-
SEL1 = 1. The DAC input register powers up to FFFh
when RES_SEL is high and powers up to 000h when
RES_SEL is low.
timed conversions through the serial interface by writ-
ing to the conversion register in the default clock mode,
10. Use clock mode 11 with SCLK up to 3.6MHz for
externally timed acquisitions to achieve sampling rates
up to 225ksps. Clock mode 11 disables scanning and
averaging. See Figures 6–9 for timing specifications on
how to begin a conversion.
These devices feature an active-low, end-of-conversion
output. EOC goes low when the ADC completes the last
requested operation and is waiting for the next com-
mand byte. EOC goes high when CS or CNVST go low.
EOC is always high in clock mode 11.
2/MAX143
12-Bit ADC
The MAX1221/MAX1223/MAX1343 ADCs use a fully dif-
ferential successive-approximation register (SAR) con-
version technique and on-chip track-and-hold (T/H)
circuitry to convert temperature and voltage signals into
12-bit digital results. The analog inputs accept both sin-
gle-ended and differential input signals. Single-ended
signals are converted using a unipolar transfer function,
and differential signals are converted using a selec-
table bipolar or unipolar transfer function. See the ADC
Transfer Functions section for more data.
Single-Ended or Differential Conversions
The MAX1221/MAX1223/MAX1343 use a fully differen-
tial ADC for all conversions. When a pair of inputs are
connected as a differential pair, each input is connect-
ed to the ADC. When configured in single-ended mode,
the positive input is the single-ended channel and the
negative input is referred to AGND. See Figure 2.
In differential mode, the T/H samples the difference
between two analog inputs, eliminating common-mode
DC offsets and noise. IN+ and IN- are selected from the
following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5,
AIN6/AIN7, AIN8/AIN9, AIN10/AIN11. AIN0–AIN7 are
available on all devices. AIN0–AIN11 are available on
the MAX1223. See Tables 5–8 for more details on con-
figuring the inputs. For the inputs that are configurable
as CNVST, REF2, and an analog input, only one func-
tion can be used at a time.
ADC Clock Modes
When addressing the setup, register bits 5 and 4 of the
command byte (CKSEL1 and CKSEL0, respectively)
control the ADC clock modes. See Table 5. Choose
between four different clock modes for various ways to
start a conversion and determine whether the acquisi-
tions are internally or externally timed. Select clock
mode 00 to configure CNVST/AIN_ to act as a conver-
sion start and use it to request internally timed conver-
sions, without tying up the serial bus. In clock mode 01,
use CNVST to request conversions one channel at a
time, thereby controlling the sampling speed without
tying up the serial bus. Request and start internally
Unipolar or Bipolar Conversions
Address the unipolar- and bipolar-mode registers
through the setup register (bits 1 and 0). See Table 5 for
2± ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2/MAX143
the setup register. See Figures 3 and 4 for the transfer-
function graphs. Program a pair of analog inputs for dif-
ferential operation by writing a one to the appropriate bit
of the bipolar- or unipolar-mode register. Unipolar mode
voltages is converted. The input capacitance charging
rate determines the time required for the T/H to acquire
an input signal. If the input signal’s source impedance is
high, the required acquisition time lengthens.
sets the differential input range from 0 to V
A nega-
REF1.
Any source impedance below 300Ω does not signifi-
cantly affect the ADC’s AC performance. A high-imped-
ance source can be accommodated either by
tive differential analog input in unipolar mode causes the
digital output code to be zero. Selecting bipolar mode
sets the differential input range to
V
REF1
/ 2. The digital
lengthening t
(only in clock mode 01) or by placing
ACQ
output code is binary in unipolar mode and two’s com-
plement in bipolar mode.
a 1µF capacitor between the positive and negative ana-
log inputs. The combination of the analog-input source
impedance and the capacitance at the analog input cre-
ates an RC filter that limits the analog input bandwidth.
In single-ended mode, the MAX1221/MAX1223/
MAX1343 always operate in unipolar mode. The analog
inputs are internally referenced to AGND with a full-scale
input range from 0 to the selected reference voltage.
ꢁnput Bandwidth
The ADC’s input-tracking circuitry has a 1MHz small-sig-
nal bandwidth, making it possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias prefiltering
of the input signals is necessary to avoid high-frequency
signals aliasing into the frequency band of interest.
Analog ꢁnput (T/H)
The equivalent circuit of Figure 2 shows the ADC input
architecture of the MAX1223. In track mode, a positive
input capacitor is connected to AIN0–AIN11 in single-
ended mode and AIN0, AIN2, AIN4–AIN10 in differential
mode. A negative input capacitor is connected to AGND
in single-ended mode or AIN1, AIN3, AIN5–AIN11 in dif-
ferential mode. The MAX1221/MAX1343 feature eight
analog input channels (AIN0–AIN7). In track mode, a pos-
itive input capacitor is connected to AIN0–AIN7 in single-
ended mode and to AIN0, AIN2, AIN4, and AIN6 in
differential mode. A negative input capacitor is connected
to AGND in single-ended mode or to AIN1, AIN3, AIN5,
and AIN7 in differential mode. For external T/H timing, use
clock mode 01. After the T/H enters hold mode, the differ-
ence between the sampled positive and negative input
Analog ꢁnput Protection
Internal electrostatic-discharge (ESD) protection diodes
clamp all analog inputs to AV
and AGND, allowing
DD
the inputs to swing from (AGND - 0.3V) to (AV
+
DD
0.3V) without damage. However, for accurate conver-
sions near full scale, the inputs must not exceed AV
DD
by more than 50mV or be lower than AGND by 50mV. If
an analog input voltage exceeds the supplies, limit the
input current to 2mA.
ꢁnternal FꢁFO
The MAX1221/MAX1223/MAX1343 contain a first-
in/first-out (FIFO) buffer that holds up to 16 ADC results
plus one temperature result. The internal FIFO allows
the ADC to process and store multiple internally
clocked conversions and a temperature measurement
without being serviced by the serial bus.
AIN0–AIN11
(SINGLE-ENDED),
AIN0, AIN2,
AIN4–AIN10
(DIFFERENTIAL)
REF1
DAC
ACQ
AGND
CIN+
COMPARATOR
If the FIFO is filled and further conversions are request-
ed without reading from the FIFO, the oldest ADC
results are overwritten by the new ADC results. Each
result contains 2 bytes, with the MSB preceded by four
leading zeros. After each falling edge of CS, the oldest
available pair of bytes of data is available at DOUT,
MSB first. When the FIFO is empty, DOUT is zero.
HOLD
CIN-
AGND
(SINGLE-ENDED),
AIN1, AIN3,
ACQ
The first 2 bytes of data read out after a temperature
measurement always contain the 12-bit temperature
result, preceded by four leading zeros, MSB first. If anoth-
er temperature measurement is performed before the first
temperature result is read out, the old measurement is
overwritten by the new result. Temperature results are in
degrees Celsius (two’s complement), at a resolution of 8
AIN5–AIN11
(DIFFERENTIAL)
ACQ
HOLD
HOLD
AV / 2
DD
Figure 2. MAX1223 Equivalent Input Circuit
______________________________________________________________________________________ 21
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
LSB per degree. See the Temperature Measurements
section for details on converting the digital code to a tem-
perature.
AGND upon power-up to be sure the DAC outputs
wake up to a known state. Connect RES_SEL to AGND
to wake up all DAC outputs at 000h. While RES_SEL is
low, the 100kΩ internal resistor pulls the DAC outputs to
AGND and the output buffers are powered down.
12-Bit DAC
In addition to the 12-bit ADC, the MAX1221/MAX1223/
MAX1343 also include eight (MAX1221/MAX1223) or
four (MAX1343) voltage-output, 12-bit, monotonic DACs
with less than 4 LSB integral nonlinearity error and less
than 1 LSB differential nonlinearity error. Each DAC has
a 2µs settling time and ultra-low glitch energy (4nV•s).
The 12-bit DAC code is unipolar binary with 1 LSB =
Connect RES_SEL to AV
to wake up all DAC outputs
DD
at FFFh. While RES_SEL is high, the 100kΩ pullup
resistor pulls the DAC outputs to V
buffers are powered down.
and the output
REF1
DAC Power-Up Modes
See Table 18 for a description of the DAC power-up
and power-down modes.
V
REF
/ 4096.
DAC Digital ꢁnterface
GPIOs
In addition to the internal ADC and DAC, the
MAX1221/MAX1343 also provide four GPIO channels,
GPIOA0, GPIOA1, GPIOC0, GPIOC1. Read and write to
the GPIOs as detailed in Table 1 and Tables 12–16. Also,
see the GPIO Command section. See Figures 11 and 12
for GPIO timing.
Figure 1 shows the functional diagram of the MAX1221.
The shift register converts a serial 16-bit word to parallel
data for each input register operating with a clock rate
up to 25MHz. The SPI-compatible digital interface to the
shift register consists of CS, SCLK, DIN, and DOUT.
Serial data at DIN is loaded on the falling edge of SCLK.
Pull CS low to begin a write sequence. Begin a write to
the DAC by writing 0001XXXX as a command byte. The
last 4 bits of the DAC select register are don’t-care bits.
See Table 10. Write another 2 bytes to the DAC inter-
face register following the command byte to select the
appropriate DAC and the data to be written to it. See
Tables 17 and 18.
Write to the GPIOs by writing a command byte to the
GPIO command register. Write a single data byte to the
MAX1221/MAX1343 following the command byte.
The GPIOs can sink and source current. GPIOA0 and
GPIOA1 can sink and source up to 15mA. GPIOC0 and
GPIOC1 can sink 4mA and source 2mA. See Table 3.
The double-buffered DACs include an input and a DAC
register. The input registers are directly connected to the
shift register and hold the result of the most recent write
operation. The 12-bit DAC registers hold the current out-
put code for the respective DAC. Data can be transferred
from the input registers to the DAC registers by pulling
LDAC low or by writing the appropriate DAC command
sequence at DIN. See Table 17. The outputs of the DACs
are buffered through eight (MAX1221/MAX1223) or four
(MAX1343) rail-to-rail op amps.
2/MAX143
Table 20 DAC Output Code Table
DAC COITEITS
AIAꢀOG OUTPUT
MSB
ꢀSB
4095
4096
⎛
⎞
+V
+V
1111
1111
0000
0000
0111
1111
⎜
⎝
⎟
⎠
REF
2049
4096
⎛
⎞
The MAX1221/MAX1223/MAX1343 DAC output-voltage
range is based on the internal reference or an external
reference. Write to the setup register (see Table 5) to
program the reference. If using an external voltage
reference, bypass REF1 with a 0.1µF capacitor to
AGND. The internal reference is 2.5V. When using an
external reference on any of these devices, the voltage
1000
1000
0111
0001
0000
0111
⎜
⎝
⎟
⎠
REF
2048
4096
+V
REF
⎛
⎞
⎛
⎞
+V
=
⎜
⎝
⎟
⎠
⎜
⎝
⎟
⎠
REF
2
range is 0.7V to AV
.
DD
2047
4096
⎛
⎞
+V
⎜
⎝
⎟
⎠
REF
DAC Transfer Function
See Table 2 for various analog outputs from the DAC.
1
⎛
⎞
DAC Power-On Wake-Up Modes
0000
0000
0000
0000
0001
0000
+V
⎜
⎝
⎟
⎠
REF
4096
The state of the RES_SEL input determines the wake-up
state of the DAC outputs. Connect RES_SEL to AV
or
DD
0
22 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2/MAX143
See Table 4. The MAX1221/MAX1223/MAX1343 perform
temperature measurements with an internal diode-con-
nected transistor. The diode bias current changes from
68µA to 4µA to produce a temperature-dependent bias
voltage difference. The second conversion result at 4µA
is subtracted from the first at 68µA to calculate a digital
value that is proportional to absolute temperature. The
output data appearing at DOUT is the digital code
above, minus an offset to adjust from Kelvin to Celsius.
Clock Modes
ꢁnternal Clock
The MAX1221/MAX1223/MAX1343 can operate from an
internal oscillator. The internal oscillator is active in
clock modes 00, 01, and 10. Figures 6, 7, and 8 show
how to start an ADC conversion in the three internally
timed conversion modes.
Read out the data at clock speeds up to 25MHz
through the SPI interface.
The reference voltage used for the temperature mea-
surements is always derived from the internal reference
source to ensure that 1 LSB corresponds to 1/8 of a
degree Celsius. On every scan where a temperature
measurement is requested, the temperature conversion
is carried out first. The first 2 bytes of data read from
the FIFO contain the result of the temperature measure-
ment. If another temperature measurement is per-
formed before the first temperature result is read out,
the old measurement is overwritten by the new result.
Temperature results are in degrees Celsius (two’s com-
plement). See the Applications Information section for
information on how to perform temperature measure-
ments in each clock mode.
External Clock
Set CKSEL1 and CKSEL0 in the setup register to 11 to
set up the interface for external clock mode 11. See
Table 5. Pulse SCLK at speeds from 0.1MHz to
3.6MHz. Write to SCLK with a 40% to 60% duty cycle.
The SCLK frequency controls the conversion timing.
See Figure 9 for clock mode 11 timing. See the ADC
Conversions in Clock Mode 11 section.
ADC/DAC References
Address the reference through the setup register, bits 3
and 2. See Table 5. Following a wake-up delay, set
REFSEL[1:0] = 00 to program both the ADC and DAC
for internal reference use. Set REFSEL[1:0] = 10 to pro-
gram the ADC for internal reference use without a
wake-up delay. Set REFSEL[1:0] = 10 to program the
DAC for external reference, REF1. When using REF1 or
REF2/AIN_ in external-reference mode, connect a 0.1µF
capacitor to AGND. Set REFSEL[1:0] = 01 to program
the ADC and DAC for external-reference mode. The
DAC uses REF1 as its external reference, while the
ADC uses REF2 as its external reference. Set
REFSEL[1:0] = 11 to program the ADC for external dif-
ferential reference mode. REF1 is the positive reference
and REF2 is the negative reference in the ADC external
differential mode.
Register Descriptions
The MAX1221/MAX1223/MAX1343 communicate
between the internal registers and the external circuitry
through the SPI-compatible serial interface. Table 1
details the command byte, the registers, and the bit
names. Tables 4–12 show the various functions within
the conversion register, setup register, unipolar-mode
register, bipolar-mode register, ADC averaging regis-
ter, DAC select register, reset register, and GPIO com-
mand register, respectively.
Conversion Register
Select active analog input channels, scan modes, and
a single temperature measurement per scan by issuing
a command byte to the conversion register. Table 4
details channel selection, the four scan modes, and
how to request a temperature measurement. Start a
scan by writing to the conversion register when in clock
mode 10 or 11, or by applying a low pulse to the
CNVST pin when in clock mode 00 or 01. See Figures 6
and 7 for timing specifications for starting a scan with
CNVST.
When REFSEL[1:0] = 00 or 10, REF2/AIN_ functions as
an analog input channel. When REFSEL[1:0] = 01 or 11,
REF2/AIN_ functions as the device’s negative reference.
Temperature Measurements
Issue a command byte setting bit 0 of the conversion
register to one to take a temperature measurement.
Table 30 GPꢁO Maximum Sink/Source
Current
A conversion is not performed if it is requested on a
channel or one of the channel pairs that has been con-
figured as CNVST or REF2. For channels configured as
differential pairs, the CHSEL0 bit is ignored and the two
pins are treated as a single differential channel. For the
MAX1221/MAX1343, the CHSEL3 bit must be zero.
MAX1221/MAX1343
CURREIT
GPꢁOA±, GPꢁOA1 GPꢁOC±, GPꢁOC1
(mA)
(mA)
Sink
15
4
2
Source
15
______________________________________________________________________________________ 23
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Channels 8–11 are invalid. Any scans or averages on
Table 40 Conversion Register*
these channles can cause corrupt data.
BꢁT
IAME
BꢁT
FUICTꢁOI
Select scan mode 00 or 01 to return one result per sin-
gle-ended channel and one result per differential pair
within the selected scanning range (set by bits 2 and 1,
SCAN1 and SCAN0), plus one temperature result if
selected. Select scan mode 10 to scan a single input
channel numerous times, depending on NSCAN1 and
NSCAN0 in the ADC averaging register (Table 9).
Select scan mode 11 to return only one result from a
single channel.
—
7 (MSB) Set to one to select conversion register.
Analog input channel select
CHSEL3
6
(MAX1223). Set to 0 on the
MAX1221/MAX1343.
CHSEL2
CHSEL1
CHSEL0
SCAN1
SCAN0
5
4
3
2
1
Analog input channel select.
Analog input channel select.
Analog input channel select.
Scan mode select.
Setup Register
Issue a command byte to the setup register to config-
ure the clock, reference, power-down modes, and ADC
single-ended/differential modes. Table 5 details the bits
in the setup-register command byte. Bits 5 and 4
(CKSEL1 and CKSEL0) control the clock mode, acqui-
sition and sampling, and the conversion start. Bits 3
and 2 (REFSEL1 and REFSEL0) set the device for either
internal or external reference. Bits 1 and 0 (DIFFSEL1
and DIFFSEL0) address the ADC unipolar-mode and
bipolar-mode registers and configure the analog input
channels for differential operation.
Scan mode select.
Set to one to take a single temperature
measurement. The first conversion
result of a scan contains temperature
information.
TEMP
0 (LSB)
*See below for bit details.
SEꢀECTED
CHAIIEꢀ (I)
CHSEꢀ3 CHSEꢀ2 CHSEꢀ1 CHSEꢀ±
The ADC reference is always on if any of the following
conditions are true:
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
1) The FBGON bit is set to one in the reset register.
2/MAX143
2) At least one DAC output is powered up and
REFSEL[1:0] (in the setup register) = 00.
3) At least one DAC is powered down through the
100kΩ to V
and REFSEL[1:0] = 00.
REF
If any of the above conditions exist, the ADC reference is
always on, but there is a 188 clock-cycle delay before
temperature-sensor measurements begin, if requested.
SCAI MODE
(CHAIIEꢀ I ꢁS SEꢀECTED BY
BꢁTS CHSEꢀ3–CHSEꢀ±)
SCAI1 SCAI±
0
0
0
1
Scans channels 0 through N.
Scans channels N through the highest
numbered channel.
Scans channel N repeatedly. The ADC
averaging register sets the number of
results.
1
1
0
1
No scan. Converts channel N once only.
24 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2/MAX143
Table 50 Setup Register*
BꢁT IAME
—
BꢁT
FUICTꢁOI
7 (MSB)
Set to zero to select setup register.
Set to one to select setup register.
—
6
CKSEL1
CKSEL0
REFSEL1
REFSEL0
DIFFSEL1
DIFFSEL0
5
Clock mode and CNVST configuration; resets to one at power-up.
Clock mode and CNVST configuration.
4
3
Reference-mode configuration.
2
1
Reference-mode configuration.
Unipolar-/bipolar-mode register configuration for differential mode.
Unipolar-/bipolar-mode register configuration for differential mode.
0 (LSB)
*See below for bit details.
Table 5a0 Clock Modes (see Clock Modes section)
CKSEꢀ1
CKSEꢀ±
COIVERSꢁOI CꢀOCK
Internal
ACQUꢁSꢁTꢁOI/SAMPꢀꢁIG
Internally timed.
CNVST COIFꢁGURATꢁOI
CNVST
0
0
1
1
0
1
0
1
Internal
Externally timed by CNVST.
Internally timed.
CNVST
Internal
AIN11/AIN7
External (3.6MHz max)
Externally timed by SCLK.
AIN11/AIN7
Table 5b0 Clock Modes ±±, ±1, and 1±
VOꢀTAGE
REFEREICE COIDꢁTꢁOIS
OVERRꢁDE
REF2
COIFꢁGURATꢁOI
REFSEꢀ1 REFSEꢀ±
AUTOSHUTDOWI
Internal reference turns off after scan is complete. If
internal reference is turned off, there is a programmed
delay of 218 internal-conversion clock cycles.
AIN
Internal (DAC
and ADC)
0
0
0
1
AIN10/AIN6
Internal reference required. There is a programmed
Temperature delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
AIN
Internal reference not used.
External single-
ended (REF1
for DAC and
Internal reference required. There is a programmed
Temperature delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
REF2
REF2 for ADC)
Default reference mode. Internal reference turns off
after scan is complete. If internal reference is turned
off, there is a programmed delay of 218 internal-
AIN
Internal (ADC)
and external
REF1 (DAC)
conversion clock cycles.
1
1
0
1
AIN10/AIN6
Internal reference required. There is a programmed
Temperature delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
AIN
Internal reference not used.
External
differential
(ADC), external
REF1 (DAC)
Internal reference required. There is a programmed
Temperature delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
REF2
______________________________________________________________________________________ 25
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 5c0 Clock Mode 11
VOꢀTAGE
REFEREICE COIDꢁTꢁOIS
OVERRꢁDE
REF2
COIFꢁGURATꢁOI
REFSEꢀ1 REFSEꢀ±
AUTOSHUTDOWI
Internal reference turns off after scan is complete. If
internal reference is turned off, there is a programmed
delay of 218 external-conversion clock cycles.
AIN
Internal (DAC
and ADC)
0
0
0
1
AIN10/AIN6
Internal reference required. There is a programmed
delay of 244 external-conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
Temperature
AIN
External single-
ended (REF1
Internal reference not used.
Internal reference required. There is a programmed
delay of 244 external-conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
REF2
for DAC and
Temperature
REF2 for ADC)
Default reference mode. Internal reference turns off
after scan is complete. If internal reference is turned
off, there is a programmed delay of 218 external-
conversion clock cycles.
AIN
Internal (ADC)
and external
REF1 (DAC)
1
1
0
1
AIN10/AIN6
Internal reference required. There is a programmed
delay of 244 external-conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
Temperature
AIN
2/MAX143
Internal reference not used.
External
differential
(ADC), external
REF1 (DAC)
Internal reference required. There is a programmed
delay of 244 external-conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
REF2
Temperature
Table 5d0 Differential Select Modes
DꢁFFSEꢀ1 DꢁFFSEꢀ±
FUICTꢁOI
0
0
1
1
0
1
0
1
No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged.
No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged.
1 byte of data follows the command setup byte and is written to the unipolar-mode register.
1 byte of data follows the command setup byte and is written to the bipolar-mode register.
26 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2/MAX143
Table 60 Unipolar-Mode Register (Addressed Through the Setup Register)
BꢁT IAME
UCH0/1
UCH2/3
UCH4/5
UCH6/7
BꢁT
FUICTꢁOI
Configure AIN0 and AIN1 for unipolar differential conversion.
Configure AIN2 and AIN3 for unipolar differential conversion.
Configure AIN4 and AIN5 for unipolar differential conversion.
Configure AIN6 and AIN7 for unipolar differential conversion.
7 (MSB)
6
5
4
Configure AIN8 and AIN9 for unipolar differential conversion (MAX1223). Set UCH8/9 to zero on the
MAX1221/MAX1343.
UCH8/9
3
2
Configure AIN10 and AIN11 for unipolar differential conversion (MAX1223). Set UCH8/9 to zero on
the MAX1221/MAX1343.
UCH10/11
X
X
1
Don’t care.
Don’t care.
0 (LSB)
Table 70 Bipolar-Mode Register (Addressed Through the Setup Register)
BꢁT IAME
BꢁT
FUICTꢁOI
Set to one to configure AIN0 and AIN1 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN0 and AIN1 for unipolar
single-ended conversion.
BCH0/1
7 (MSB)
Set to one to configure AIN2 and AIN3 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN2 and AIN3 for unipolar
single-ended conversion.
BCH2/3
BCH4/5
BCH6/7
BCH8/9
BCH10/11
6
5
4
3
2
Set to one to configure AIN4 and AIN5 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN4 and AIN5 for unipolar
single-ended conversion.
Set to one to configure AIN6 and AIN7 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN6 and AIN7 for unipolar
single-ended conversion.
Set to one to configure AIN8 and AIN9 for bipolar differential conversion (MAX1223). Set the
corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN8 and
AIN9 for unipolar single-ended conversion. Set BCH8/9 to zero on the MAX1221 and MAX1343.
Set to one to configure AIN10 and AIN11 for bipolar differential conversion (MAX1223). Set the
corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN10 and
AIN11 for unipolar single-ended conversion. Set BCH8/9 to zero on the MAX1221 and MAX1343.
X
X
1
Don’t care.
Don’t care.
0 (LSB)
______________________________________________________________________________________ 27
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Unipolar/Bipolar Registers
The final 2 bits (LSBs) of the setup register control the
unipolar-/bipolar-mode address registers. Set
DIFFSEL[1:0] = 10 to write to the unipolar-mode regis-
ter. Set bits DIFFSEL[1:0] = 11 to write to the bipolar-
mode register. In both cases, the setup command byte
must be followed by 1 byte of data that is written to the
unipolar-mode register or bipolar-mode register. Hold
CS low and run 16 SCLK cycles before pulling CS high.
If the last 2 bits of the setup register are 00 or 01, nei-
ther the unipolar-mode register nor the bipolar-mode
register is written. Any subsequent byte is recognized
as a new command byte. See Tables 6, 7, and 8 to pro-
gram the unipolar- and bipolar-mode registers.
Both registers power up at all zeros to set the inputs as
eight unipolar single-ended channels. To configure a
channel pair as single-ended unipolar, bipolar differen-
tial, or unipolar differential, see Table 8.
In unipolar mode, AIN+ can exceed AIN- by up to
REF
bipolar mode, either input can exceed the other by up
Table 80 Unipolar/Bipolar Channel Function
V
. The output format in unipolar mode is binary. In
UIꢁPOꢀAR-
to V
/ 2. The output format in bipolar mode is two’s
REF
BꢁPOꢀAR-MODE
REGꢁSTER BꢁT
CHAIIEꢀ PAꢁR
FUICTꢁOI
MODE
complement (see the ADC Transfer Functions section).
REGꢁSTER BꢁT
ADC Averaging Register
Write a command byte to the ADC averaging register to
configure the ADC to average up to 32 samples for
each requested result, and to independently control the
number of results requested for single-channel scans.
0
0
1
1
0
1
0
1
Unipolar single-ended
Bipolar differential
Unipolar differential
Unipolar differential
Table 90 ADC Averaging Register*
BꢁT IAME
—
BꢁT
FUICTꢁOI
7 (MSB)
Set to zero to select ADC averaging register.
—
6
Set to zero to select ADC averaging register.
—
5
Set to one to select ADC averaging register.
2/MAX143
AVGON
NAVG1
NAVG0
NSCAN1
NSCAN0
4
Set to one to turn averaging on. Set to zero to turn averaging off.
Configures the number of conversions for single-channel scans.
Configures the number of conversions for single-channel scans.
Single-channel scan count. (Scan mode 10 only.)
Single-channel scan count. (Scan mode 10 only.)
3
2
1
0 (LSB)
*See below for bit details.
FUICTꢁOI
AVGOI
IAVG1
IAVG±
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Performs one conversion for each requested result.
Performs four conversions and returns the average for each requested result.
Performs eight conversions and returns the average for each requested result.
Performs 16 conversions and returns the average for each requested result.
Performs 32 conversions and returns the average for each requested result.
ISCAI1
ISCAI±
FUICTꢁOI (APPꢀꢁES OIꢀY ꢁF SCAI MODE 1± ꢁS SEꢀECTED)
Scans channel N and returns four results.
0
0
1
1
0
1
0
1
Scans channel N and returns eight results.
Scans channel N and returns 12 results.
Scans channel N and returns 16 results.
28 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2/MAX143
Table 9 details the four scan modes available in the
ADC conversion register. All four scan modes allow
averaging as long as the AVGON bit, bit 4 in the
averaging register, is set to 1. Select scan mode 10 to
scan the same channel multiple times. Clock mode 11
disables averaging. For example, if AVGON = 1,
NAVG[1:0] = 00, NSCAN[1:0] = 11 and SCAN[1:0] =
10, 16 results are written to the FIFO, with each result
being the average of four conversions of channel N.
byte controls the DAC serial interface. See Table 17
and the DAC Serial Interface section.
Reset Register
Write to the reset register (as shown in Table 11) to
clear the FIFO or reset all registers (excluding the DAC
and GPIO registers) to their default states. When the
RESET bit in the reset register is set to 0, the FIFO is
cleared. Set the RESET bit to one to return all the
device registers to their default power-up state. All reg-
isters power up in state 00000000, except for the setup
register that powers up in clock mode 10 (CKSEL1 = 1
and REFSEL1 = 1). The DAC and GPIO registers are
not reset by writing to the reset register. Set the SLOW
bit to one to add a 15ns delay in the DOUT signal path
to provide a longer hold time. Writing a one to the
SLOW bit also clears the contents of the FIFO. Set the
FBGON bit to one to force the bias block and bandgap
reference to power up regardless of the state of the
DAC and activity of the ADC block. Setting the FBGON
bit high also removes the programmed wake-up delay
between conversions in clock modes 01 and 11.
Setting the FBGON bit high also clears the FIFO.
DAC Select Register
Write a command byte 0001XXXX to the DAC select
register (as shown in Table 9) to set up the DAC inter-
face and indicate that another word will follow. The last
4 bits of the DAC select register are don’t-care bits. The
word that follows the DAC select-register command
Table 1±0 DAC Select Register
BꢁT
IAME
BꢁT
FUICTꢁOI
—
—
—
—
X
7 (MSB) Set to zero to select DAC select register.
6
5
4
3
2
1
0
Set to zero to select DAC select register.
Set to zero to select DAC select register.
Set to one to select DAC select register.
Don’t care.
Table 120 GPꢁO Command Register
X
Don’t care.
X
Don’t care.
BꢁT IAME
BꢁT
FUICTꢁOI
X
Don’t care.
—
7 (MSB)
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
GPIO configuration bit.
—
6
—
5
Table 110 Reset Register
—
—
4
BꢁT
BꢁT
3
FUICTꢁOI
IAME
—
2
1
—
—
—
—
—
7 (MSB) Set to zero to select ADC reset register.
GPIOSEL1
GPIOSEL2
6
5
4
3
Set to zero to select ADC reset register.
Set to zero to select ADC reset register.
Set to zero to select ADC reset register.
Set to one to select ADC reset register.
0 (LSB)
GPIO write bit.
GPꢁOSEꢀ1 GPꢁOSEꢀ2
FUICTꢁOI
GPIO configuration; written data is
entered in the GPIO configuration
register.
Set to zero to clear the FIFO only. Set to
one to set the device in its power-on
condition.
1
1
RESET
SLOW
2
1
GPIO write; written data is entered
in the GPIO write register.
1
0
0
1
Set to one to turn on slow mode.
Set to one to force internal bias block and
bandgap reference to be always powered
up.
GPIO read; the next 8 SCLK cycles
transfer the state of all GPIO
drivers into DOUT.
FBGON 0 (LSB)
______________________________________________________________________________________ 29
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
GPꢁO Command
GPꢁO Read
Write the command byte 00000001 to indicate a GPIO
read operation. The eight SCLK cycles following the
command byte transfer the state of the GPIOs to DOUT
in the MAX1221/MAX1343. See Table 16.
Write a command byte to the GPIO command register
to configure, write, or read the GPIOs, as detailed in
Table 12.
Write the command byte 00000011 to configure the
GPIOs. The eight SCLK cycles following the command
byte load data from DIN to the GPIO configuration reg-
ister in the MAX1221/MAX1343. See Tables 13 and 14.
The register bits are updated after the last CS rising
edge. All GPIOs default to inputs upon power-up.
DAC Serial ꢁnterface
Write a command byte 0001XXXX to the DAC select
register to indicate the word to follow is written to the
DAC serial interface, as detailed in Tables 1, 10, 17, and
18. Write the next 16 bits to the DAC interface register,
as shown in Tables 17 and 18. Following the high-to-low
transition of CS, the data is shifted synchronously and
latched into the input register on each falling edge of
SCLK. Each word is 16 bits. The first 4 bits are the con-
trol bits followed by 12 data bits (MSB first). See Figures
9–12 for DAC timing specifications.
The data in the register controls the function of each
GPIO, as shown in Tables 13, 14, and 16.
GPꢁO Write
Write the command byte 00000010 to indicate a GPIO
write operation. The eight SCLK cycles following the com-
mand byte load data from DIN into the GPIO write register
in the MAX1221/MAX1343. See Tables 14 and 15. The
register bits are updated after the last CS rising edge.
If CS goes high prior to completing 16 SCLK cycles, the
command is discarded. To initiate a new transfer, drive
CS low again.
For example, writing the DAC serial interface word 1111
0000 and 0011 0100 disconnects DAC outputs 2 and 3
Table 130 MAX1221/MAX1343 GPꢁO Configuration
DATA PꢁI
DꢁI
DOUT
GPꢁO COMMAID BYTE
DATA BYTE
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
GPIOC1
0
GPIOC0
0
GPIOA1
0
GPIOA0
0
X
0
X
0
X
0
X
0
2/MAX143
Table 140 MAX1221/MAX1343 GPꢁO Write
DATA PꢁI
DꢁI
GPꢁO COMMAID BYTE
DATA BYTE
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
GPIOC1
0
GPIOC0
0
GPIOA1
0
GPIOA0
0
X
0
X
X
X
0
DOUT
0
0
Table 150 GPꢁO-Mode Control
COIFꢁGURATꢁOI
BꢁT
WRꢁTE
BꢁT
OUTPUT
STATE
GPꢁO
FUICTꢁOI
1
1
0
1
0
1
1
0
Output
Output
Input
Tri-state
Pulldown
(open drain)
0
0
0
Table 160 MAX1221/MAX1343 GPꢁO Read
DATA PꢁI
DꢁI
GPꢁO COMMAID BYTE
DATA BYTE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
X
0
X
0
X
0
X
0
X
X
X
X
DOUT
GPIOC1
GPIOC0
GPIOA1
GPIOA0
3± ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2/MAX143
Table 170 DAC Serial-ꢁnterface Configuration
16-BꢁT SERꢁAꢀ WORD
MSB
ꢀSB
DESCRꢁPTꢁOI
FUICTꢁOI
COITROꢀ BꢁTS
DATA BꢁTS
C3 C2 C1 C± D11 D1± D9 D8 D7 D6 D5 D4 D3 D2 D1 D±
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
NOP
No operation.
Reset all internal registers to
000h and leave output buffers in
their present state.
0
0
0
1
0
X
X
X
X
X
X
X
X
X
X
X
RESET
Preset all internal registers to
FFFh and leave output buffers in
their present state.
0
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
Pull-High
D11–D0 to input register 0, DAC
output unchanged.
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DAC0
DAC1
DAC2
DAC3
D11–D0 to input register 1, DAC
output unchanged.
D11–D0 to input register 2, DAC
output unchanged.
D11–D0 to input register 3, DAC
output unchanged.
D11–D0 to input register 4, DAC
output unchanged
(MAX1221/MAX1223). NOP
command (MAX1343).
D11–D0 to input register 5, DAC
output unchanged
(MAX1221/MAX1223). NOP
command (MAX1343).
D11–D0 to input register 6, DAC
output unchanged
(MAX1221/MAX1223). NOP
command (MAX1343).
0
0
1
1
1
0
1
1
0
0
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DAC4
DAC5
DAC6
D11–D0 to input register 7, DAC
output unchanged
(MAX1221/MAX1223). NOP
command (MAX1343).
1
1
0
0
0
1
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DAC7
D11–D0 to input registers 0–3
and DAC register 0–3. DAC
outputs updated (write-through).
DAC0–3
D11–D0 to input registers 4–7
and DAC register 4–7. DAC
outputs updated (write-through)
(MAX1221/MAX1223). NOP
command (MAX1343).
D11–D0 to input registers 0–7
and DAC register 0–7
(MAX1221/MAX1223). D11–D0 to
input registers 0–3 and DAC
registers 0–3 (MAX1343). DAC
outputs updated (write-through).
1
1
0
1
1
0
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DAC4–7
DAC0–7
______________________________________________________________________________________ 31
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 170 DAC Serial-ꢁnterface Configuration (continued)
16-BꢁT SERꢁAꢀ WORD
MSB
ꢀSB
DESCRꢁPTꢁOI
FUICTꢁOI
COITROꢀ BꢁTS
DATA BꢁTS
C3 C2 C1 C± D11 D1± D9 D8 D7 D6 D5 D4 D3 D2 D1 D±
D11–D0 to input registers 0–7
(MAX1221/MAX1223). D11–D0 to
input registers 0–3 (MAX1343).
DAC outputs unchanged.
1
1
1
1
0
1
—
—
—
—
—
—
—
—
—
X
—
X
—
X
—
X
DAC0–7
Input registers to DAC registers
indicated by ones, DAC outputs
updated, equivalent to software
LDAC. (No effect on DACs
indicated by zeros.) DAC7–DAC4
are only valid on the MAX1221/
MAX1223. These are don’t-care
bits for the MAX1343.
DAC DACDAC DACDAC DACDAC DAC
7
1
0
DAC0–7
6
5
4
3
2
1
0
Table 180 DAC Power-Up and Power-Down Commands
COITROꢀ
DATA BꢁTS
BꢁTS
DESCRꢁPTꢁOI
FUICTꢁOI
C3 C2 C1 C±
D3 D2 D1 D±
2/MAX143
Power up individual DAC buffers indicated by data
in DAC0 through DAC3. A one indicates the DAC
output is connected and active. A zero does not
affect the DAC’s present state.
1
1
1
1
1
1
1
1
— — — — — — — —
— — — — — — — —
0
0
0
1
1
0
X
X
Power-Up
Power down individual DAC buffers indicated by
data in DAC0 through DAC3. A one indicates the
DAC output is disconnected and high impedance.
A zero does not affect the DAC’s present state.
Power-Down 1
Power down individual DAC buffers indicated by
data in DAC0 through DAC3. A one indicates the
DAC output is disconnected and pulled to AGND
with a 1kΩ resistor. A zero does not affect the DAC’s
present state.
1
1
1
1
1
1
1
1
1
1
1
1
— — — — — — — —
— — — — — — — —
— — — — — — — —
1
0
1
0
0
1
0
0
1
X
X
X
Power-Down 2
Power down individual DAC buffers indicated by
data in DAC0 through DAC3. A one indicates the
Power-Down 3 DAC output is disconnected and pulled to AGND
with a 100kΩ resistor. A zero does not affect the
DAC’s present state.
Power down individual DAC buffers indicated by
data in DAC0 through DAC3. A one indicates the
Power-Down 4 DAC output is disconnected and pulled to REF1 with
a 100kΩ resistor. A zero does not affect the DAC’s
present state.
32 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2/MAX143
and forces them to a high-impedance state. DAC out-
puts 0 and 1 remain in their previous state.
second byte is read out partially, the rest of that byte is
lost. The remaining data in the FIFO is unaffected and
can be read out normally after taking CS low again, as
long as the 4 leading bits (normally zeros) are ignored.
If CS is pulled low before EOC goes low, a conversion
may not be completed and the FIFO data may not be
correct. Incorrect writes (pulling CS high before com-
pleting eight SCLK cycles) are ignored and the register
remains unchanged.
Output-Data Format
Figures 6–9 illustrate the conversion timing for the
MAX1221/MAX1223/MAX1343. All 12-bit conversion
results are output in 2-byte format, MSB first, with four
leading zeros. Data appears on DOUT on the falling
edges of SCLK. Data is binary for unipolar mode and
two’s complement for bipolar mode and temperature
results. See Figures 3, 4, and 5 for input/output and
temperature-transfer functions.
V
REF
= V
- V
REF+ REF-
ADC Transfer Functions
Figure 3 shows the unipolar transfer function for single-
ended or differential inputs. Figure 4 shows the bipolar
transfer function for differential inputs. Code transitions
occur halfway between successive-integer LSB values.
V
V
REF
REF
011....111
011....110
011....101
FS = V / 2 + V
REF
COM
ZS = COM
-FS = -V / 2
REF
V
REF
Output coding is binary, with 1 LSB = V
/ 4096 for
1 LSB = V / 4096
REF1
REF
000....001
000....000
111....111
unipolar and bipolar operation, and 1 LSB = +0.125ꢀC
for temperature measurements. Bipolar true-differential
results and temperature-sensor results are available in
two’s complement format, while all others are in binary.
See Tables 6, 7, and 8 for details on which setting
(unipolar or bipolar) takes precedence.
(COM)
V
REF
100....011
100....010
100....001
100....000
In unipolar mode, AIN+ can exceed AIN- by up to
V
. In bipolar mode, either input can exceed the
REF1
other by up to V
-FS
-1
(COM)
INPUT VOLTAGE (LSB)
0
+1
+FS - 1 LSB
/ 2.
REF1
Partial Reads and Partial Writes
If the first byte of an entry in the FIFO is partially read
(CS is pulled high after fewer than eight SCLK cycles),
the remaining bits are lost for that byte. The next byte of
data that is read out contains the next 8 bits. If the first
byte of an entry in the FIFO is read out fully, but the
Figure 4. Bipolar Transfer Function—Full Scale ( FS) =
V
/ 2
REF
OUTPUT CODE
FULL-SCALE
TRANSITION
011....111
011....110
111....111
111....110
111....101
FS = V
REF
1 LSB = V / 4096
REF
000....010
000....001
000....000
111....111
111....110
111....101
000....011
000....010
000....001
000....000
100....001
100....000
0
1
2
3
FS
INPUT VOLTAGE (LSB)
0
-256
+255.5
FS - 3/2 LSB
TEMPERATURE (°C)
Figure 5. Temperature Transfer Function
______________________________________________________________________________________ 33
Figure 3. Unipolar Transfer Function—Full Scale (FS) = V
REF
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
CNVST
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
CS
SCLK
DOUT
MSB1
LSB1
MSB2
t
RDS
EOC
Figure 6. Clock Mode 00—After writing a command byte, set CNVST low for at least 40ns to begin a conversion.
t
CSW
CNVST
(CONVERSION 2)
(ACQUISITION 1)
(ACQUISITION 2)
CS
t
DOV
(CONVERSION 1)
SCLK
DOUT
2/MAX143
MSB1
LSB1
MSB2
EOC
Figure 7. Clock Mode 01—After writing a command byte, request multiple conversions by setting CNVST low for each conversion.
store the results in the FIFO, and shut down. After the
Applications Information
scan is complete, EOC is pulled low and the results are
Internally Timed Acquisitions and
available in the FIFO. Wait until EOC goes low before
pulling CS low to communicate with the serial interface.
EOC stays low until CS or CNVST is pulled low again. A
temperature-conversion result, if requested, precedes
all other FIFO results.
Conversions Using CNVST
ADC Conversions in Clock Mode ±±
In clock mode 00, the wake-up, acquisition, conversion,
and shutdown sequence is initiated through CNVST
and performed automatically using the internal oscilla-
tor. Results are added to the internal FIFO to be read
out later. See Figure 6 for clock mode 00 timing after a
command byte is issued. See Table 5 for details on
programming the clock mode in the setup register.
Do not issue a second CNVST signal before EOC goes
low; otherwise, the FIFO can be corrupted. Wait until all
conversions are complete before reading the FIFO. SPI
communications to the DAC and GPIO registers are per-
mitted during conversion. However, coupled noise may
result in degraded ADC signal-to-noise ratio (SNR).
Initiate a scan by setting CNVST low for at least 40ns
before pulling it high again. The MAX1221/MAX1223/
MAX1343 then wake up, scan all requested channels,
34 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2/MAX143
(CONVERSION BYTE)
DIN
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
CS
SCLK
DOUT
EOC
MSB1
LSB1
MSB2
t
DOV
Figure 8. Clock Mode 10—The command byte to the conversion register begins the acquisition (CNVST is not required).
Externally Timed Acquisitions and
pulled low again. Wait until EOC goes low before pulling
CS or CNVST low. The number of CNVST signals must
equal the number of conversions requested by the scan
and averaging registers to correctly update the FIFO.
Wait until all conversions are complete before reading
the FIFO. SPI communications to the DAC and GPIO
registers are permitted during conversion. However,
coupled noise may result in degraded ADC SNR.
Internally Timed Conversions with CNVST
ADC Conversions in Clock Mode ±1
In clock mode 01, conversions are requested one at a
time using CNVST and performed automatically using
the internal oscillator. See Figure 7 for clock mode 01
timing after a command byte is issued.
Setting CNVST low begins an acquisition, wakes up the
ADC, and places it in track mode. Hold CNVST low for
at least 1.4µs to complete the acquisition. If reference
mode 00 or 10 is selected, an additional 45µs is
required for the internal reference to power up. If a tem-
perature measurement is being requested, reference
power-up and temperature measurement is internally
timed. In this case, hold CNVST low for at least 40ns.
If averaging is turned on, multiple CNVST pulses need to
be performed before a result is written to the FIFO. Once
the proper number of conversions has been performed
to generate an averaged FIFO result (as specified to the
averaging register), the scan logic automatically switch-
es the analog input multiplexer to the next requested
channel. If a temperature measurement is programmed,
it is performed after the first rising edge of CNVST follow-
ing the command byte written to the conversion register.
The temperature-conversion result is available on DOUT
once EOC has been pulled low.
Set CNVST high to begin a conversion. Sampling is
completed approximately 500ns after CNVST goes high.
After the conversion is complete, the ADC shuts down
and pulls EOC low. EOC stays low until CS or CNVST is
______________________________________________________________________________________ 35
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
(CONVERSION BYTE)
DIN
(ACQUISITION1)
(CONVERSION1)
(ACQUISITION2)
CS
SCLK
DOUT
EOC
MSB1
LSB1
MSB2
Figure 9. Clock Mode 11—Externally Timed Acquisition, Sampling, and Conversion without CNVST
Initiate a conversion by writing a command byte to the
conversion register followed by 16 SCLK cycles. If CS
is pulsed high between the eighth and ninth cycles, the
pulse width must be less than 100µs. To continuously
convert at 16 cycles per conversion, alternate 1 byte of
zeros (NOP byte) between each conversion byte. If 2
NOP bytes follow a conversion byte, the analog cells
power down at the end of the second NOP. Set the
FBGON bit to one in the reset register to keep the inter-
nal bias block powered.
Internally Timed Acquisitions and
Conversions Using the Serial Interface
ADC Conversions in Clock Mode 1±
In clock mode 10, the wake-up, acquisition, conversion,
and shutdown sequence is initiated by writing a com-
mand byte to the conversion register, and is performed
automatically using the internal oscillator. This is the
default clock mode upon power-up. See Figure 8 for
clock mode 10 timing.
Initiate a scan by writing a command byte to the conver-
sion register. The MAX1221/MAX1223/MAX1343 then
power up, scan all requested channels, store the results
in the FIFO, and shut down. After the scan is complete,
EOC is pulled low and the results are available in the
FIFO. If a temperature measurement is requested, the
temperature result precedes all other FIFO results. EOC
stays low until CS is pulled low again. Wait until all con-
versions are complete before reading the FIFO. SPI
communications to the DAC and GPIO registers are per-
mitted during conversion. However, coupled noise may
result in degraded ADC SNR.
2/MAX143
If reference mode 00 is requested, or if an external refer-
ence is selected but a temperature measurement is being
requested, wait 45µs with CS high after writing the con-
version byte to extend the acquisition and allow the inter-
nal reference to power up. To perform a temperature
measurement, write 24 bytes (192 cycles) of zeros after
the conversion byte. The temperature result appears on
DOUT during the last 2 bytes of the 192 cycles.
Conversion-Time Calculations
The conversion time for each scan is based on a num-
ber of different factors: conversion time per sample,
samples per result, results per scan, if a temperature
measurement is requested, and if the external refer-
ence is in use. Use the following formula to calculate
the total conversion time for an internally timed conver-
sion in clock mode 00 and 10 (see the Electrical
Characteristics, as applicable):
Externally Clocked Acquisitions and
Conversions Using the Serial Interface
ADC Conversions in Clock Mode 11
In clock mode 11, acquisitions and conversions are ini-
tiated by writing a command byte to the conversion
register and are performed one at a time using the
SCLK as the conversion clock. Scanning, averaging
and the FIFO are disabled, and the conversion result is
available at DOUT during the conversion. Output data
is updated on the rising edge of SCLK in clock mode
11. See Figure 9 for clock mode 11 timing.
Total conversion time =
t
x n
x n
+ t + t
CNV
AVG
SCAN TS INT-REF,SU
where:
t
= t
(where t
is dependent from the clock
DOV
CNV
DOV
and reference mode selected.)
36 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2/MAX143
t
CH
t
CL
32
16
8
SCLK
DIN
5
1
2
3
4
t
DH
t
DS
D13
D12
D11
D15
D14
D1
D0
t
DOT
t
DOD
t
DOE
D15
D7
D14
D6
D12
D4
D13
D5
DOUT
D1
D0
t
CSS
t
CSPWH
t
CSH
CS
Figure 10. DAC/GPIO Serial-Interface Timing (Clock Modes 00, 01, and 10)
n
n
= samples per result (amount of averaging)
fications for clock modes 00, 01, and 10. Figure 11
shows the timing specifications for clock mode 11.
Figure 12 details the timing specifications for the DAC
input select register and 2 bytes to follow. Output data
is updated on the rising edge of SCLK in clock mode
11. Figure 13 shows the GPIO timing. Figure 14 shows
the timing details of a hardware LDAC command DAC-
register update. For a software-command DAC-register
AVG
= number of times each channel is scanned; set
SCAN
to one unless [SCAN1, SCAN0] = 10
t
= time required for temperature measurement
TS
(58.1µs); set to zero if temperature measurement is not
requested
t
= t
(external-reference wake-up); if a
WU
INT-REF,SU
conversion using the external reference is requested
update, t is valid from the rising edge of CS, which fol-
S
lows the last data bit in the software command word.
In clock mode 01, the total conversion time depends on
how long CNVST is held low or high. Conversion time in
externally clocked mode (CKSEL1, CKSEL0 = 11)
depends on the SCLK period and how long CS is held
high between each set of eight SCLK cycles. In clock
mode 01, the total conversion time does not include the
time required to turn on the internal reference.
LDAC Functionality
Drive LDAC low to transfer the content of the input reg-
isters to the DAC registers. Drive LDAC permanently
low to make the DAC register transparent. The DAC
output typically settles from zero to full scale within
LSB after 2µs. See Figure 14.
1
DAC/GPꢁO Timing
Figures 10–13 detail the timing diagrams for writing to
the DAC and GPIOs. Figure 10 shows the timing speci-
______________________________________________________________________________________ 37
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
t
CH
t
CL
32
16
8
SCLK
5
1
2
3
4
t
DH
t
DS
D15
D14
D13
D12
D11
D1
D0
DIN
DOUT
CS
t
t
DOT
DOE
t
DOD
D15
D7
D14
D6
D13
D5
D12
D4
D1
D0
t
CSS
t
CSPWH
t
CSH
Figure 11. DAC/GPIO Serial-Interface Timing (Clock Mode 11)
2/MAX143
SCLK
10
24
1
2
8
9
DIN
BIT 7 (MSB)
BIT 6
BIT 0 (LSB)
BIT 15
BIT 14
BIT 1
BIT 0
DOUT
CS
THE COMMAND BYTE
INITIALIZES THE DAC SELECT
REGISTER
THE NEXT 16 BITS SELECT THE DAC
AND THE DATA WRITTEN TO IT
Figure 12. DAC-Select Register Byte and DAC Serial-Interface Word
38 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2/MAX143
CS
t
GOD
t
GSU
GPIO INPUT/OUTPUT
Figure 13. GPIO Timing
t
LDACPWL
LDAC
t
S
1 LSB
OUT_
Figure 14. LDAC Functionality
Layout, Grounding, and Bypassing
For best performance, use PC boards. Ensure that digital
and analog signal lines are separated from each other.
Do not run analog and digital signals parallel to one
another (especially clock signals) or do not run digital
lines underneath the MAX1221/MAX1223/MAX1343
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. INL for
the MAX1221/MAX1223/MAX1343 is measured using
the end-point method.
package. High-frequency noise in the AV
power sup-
DD
ply may affect performance. Bypass the AV
with a 0.1µF capacitor to AGND, close to the AV
supply
DD
DD
pin.
Bypass the DV
supply with a 0.1µF capacitor to
DD
DGND, close to the DV
pin. Minimize capacitor lead
DD
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
lengths for best supply-noise rejection. If the power sup-
ply is very noisy, connect a 10Ω resistor in series with the
supply to improve power-supply filtering.
The MAX1221/MAX1223/MAX1343 thin QFN packages
contain an exposed pad on the underside of the device.
Connect this exposed pad to AGND. Refer to the
MAX1258EVKIT for an example of proper layout.
Unipolar ADC Offset Error
For an ideal converter, the first transition occurs at 0.5
LSB, above zero. Offset error is the amount of deviation
between the measured first transition point and the
ideal first transition point.
______________________________________________________________________________________ 39
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Bipolar ADC Offset Error
While in bipolar mode, the ADC’s ideal midscale transi-
tion occurs at AGND -0.5 LSB. Bipolar offset error is the
measured deviation from this ideal value.
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the ENOB as follows:
ADC Gain Error
Gain error is defined as the amount of deviation
between the ideal transfer function and the measured
transfer function, with the offset error removed and with
a full-scale analog input voltage applied to the ADC,
resulting in all ones at DOUT.
ENOB = (SINAD - 1.76)/6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
DAC Offset Error
DAC offset error is determined by loading a code of
all zeros into the DAC and measuring the analog
output voltage.
⎡
⎣
⎤
2
2
2
2
2
THD = 20 x log
V
+ V + V + V + V
/V
1
(
)
2
3
4
5
6
⎢
⎥
⎦
DAC Gain Error
DAC gain error is defined as the amount of deviation
between the ideal transfer function and the measured
transfer function, with the offset error removed, when
loading a code of all ones into the DAC.
where V is the fundamental amplitude, and V through
6
1
2
V are the amplitudes of the first five harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest distortion
component.
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples.
ADC Channel-to-Channel Crosstalk
Bias the ON channel to midscale. Apply a full-scale sine
wave test tone to all OFF channels. Perform an FFT on
the ON channel. ADC channel-to-channel crosstalk is
expressed in dB as the amplitude of the FFT spur at the
frequency associated with the OFF channel test tone.
Aperture Delay
Aperture delay (t ) is the time between the rising
AD
edge of the sampling clock and the instant when an
actual sample is taken.
2/MAX143
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analog-
to-digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N bits):
Intermodulation Distortion (IMD)
IMD is the total power of the intermodulation products
relative to the total input power when two tones, f1 and
f2, are present at the inputs. The intermodulation prod-
ucts are (f1 f2), (2 x f1), (2 x f2), (2 x f1 f2), (2 x f2
f1). The individual input tone levels are at -7dBFS.
SNR = (6.02 x N + 1.76)dB
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC so the signal’s slew rate does not limit the ADC’s
performance. The input frequency is then swept up to
the point where the amplitude of the digitized conver-
sion result has decreased by -3dB. Note that the T/H
performance is usually the limiting factor for the small-
signal input bandwidth.
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise. RMS noise
includes all spectral components to the Nyquist fre-
quency excluding the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full-
power input bandwidth frequency.
SINAD(dB) = 20 x log (Signal /Noise
RMS
)
RMS
4± ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2/MAX143
DAC Digital Feedthrough
Chip Information
DAC digital feedthrough is the amount of noise that
TRANSISTOR COUNT: 58,141
appears on the DAC output when the DAC digital con-
PROCESS: BiCMOS
trol lines are toggled.
ADC Power-Supply Rejection
ADC power-supply rejection (PSR) is defined as the
shift in offset error when the power supply is moved
from the minimum operating voltage to the maximum
operating voltage.
DAC Power-Supply Rejection
DAC PSR is the amount of change in the converter’s
value at full-scale as the power-supply voltage changes
from its nominal value. PSR assumes the converter’s lin-
earity is unaffected by changes in the power-supply
voltage.
______________________________________________________________________________________ 41
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Pin Configurations
TOP VIEW
GPIOA0
GPIOA1
EOC
1
2
3
4
5
6
7
8
9
27 AIN0
CNVST/AIN11
N.C.
1
2
3
4
5
6
7
8
9
27 AIN2
26 REF1
25 AIN1
24 N.C.
23 AIN0
22 RES_SEL
21 CS
26 REF1
25 GPIOC1
24 GPIOC0
23 N.C.
EOC
DV
DD
DV
DD
DGND
DOUT
SCLK
DIN
DGND
DOUT
SCLK
DIN
MAX1221
MAX1223
22 RES_SEL
21 CS
LDAC
20
LDAC
20
OUT0
19 OUT7
OUT0
19 OUT7
THꢁI QFI
THꢁI QFI
TOP VIEW
2/MAX143
36 35 34 33 32 31 30 29 28
GPIOA0
1
2
3
4
5
6
7
8
9
27 AIN0
GPIOA1
EOC
26 REF1
25 GPIOC1
24 GPIOC0
23 N.C.
DV
DD
DGND
DOUT
SCLK
DIN
MAX1343
22 RES_SEL
21 CS
20 LDAC
19 D.C.
OUT0
10 11 12 13 14 15 16 17 18
THꢁI QFI
(6mm x 6mm x ±08mm)
42 ______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2/MAX143
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www0maxim-ic0com/packages.)
______________________________________________________________________________________ 43
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Revision History
REVꢁSꢁOI
IUMBER
REVꢁSꢁOI
DATE
PAGES
CHAIGED
DESCRꢁPTꢁOI
1
12/07
Changed timing characteristic specification
7
2/MAX143
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
44 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
MAX1224ETC+
A/D Converter, 12-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, ROHS COMPLIANT, TQFN-12
MAXIM
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