MAX1181EVKIT [MAXIM]

Evaluation Kit for the MAX1180/MAX1181/MAX1182/MAX1183/MAX1184/MAX1185/MAX1186/MAX1190 ; 评估板MAX1180 / MAX1181 / MAX1182 / MAX1183 / MAX1184 / MAX1185 / MAX1186 / MAX1190\n
MAX1181EVKIT
型号: MAX1181EVKIT
厂家: MAXIM INTEGRATED PRODUCTS    MAXIM INTEGRATED PRODUCTS
描述:

Evaluation Kit for the MAX1180/MAX1181/MAX1182/MAX1183/MAX1184/MAX1185/MAX1186/MAX1190
评估板MAX1180 / MAX1181 / MAX1182 / MAX1183 / MAX1184 / MAX1185 / MAX1186 / MAX1190\n

文件: 总9页 (文件大小:496K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
19-2054; Rev 2; 7/02  
MAX1181 Evaluation Kit  
General Description  
Features  
Up to 80Msps Sampling Rate (MAX1181)  
Low Voltage and Power Operation  
The MAX1181 Evaluation kit (EV Kit) is a fully assembled  
and tested circuit board that contains all the components  
necessary to evaluate the performance of the nonmulti-  
plexed MAX1180–MAX1184 and MAX1190 or multiplexed  
MAX1185 and MAX1186, dual 10-bit analog-to-digital  
converters (ADC). The MAX1180–MAX1186 and  
MAX1190 accept differential or single-ended analog  
inputs and the EV kit allows for evaluation of each ADC  
with both types of signals from one single-ended analog  
signal. The digital output produced by the ADC can easily  
be sampled with a user-provided high-speed logic ana-  
lyzer or data-acquisition system. The EV kit operates from  
3.0V analog and 2.0V digital power supplies. It includes  
circuitry that generates a clock signal from an AC signal  
provided by the user. The EV kit comes with the MAX1181  
installed. Order free samples of the pin-compatible  
MAX1180, MAX1182, MAX1183, MAX1184, MAX1185,  
MAX1186, or MAX1190 to evaluate these parts.  
Single-Ended or Fully Differential Signal Input  
Configuration  
Clock-Shaping Circuit  
Fully Assembled and Tested  
Supports Both Nonmultiplexed  
(MAX1180–MAX1184/MAX1190)  
and Multiplexed (MAX1185/MAX1186)  
Output Operation  
Ordering Information  
PART  
TEMP RANGE  
IC PACKAGE  
Selector Guide  
MAX1181EVKIT  
0°C to +70°C  
48 TQFP-EP  
PART  
SPEED (Msps)  
MAX1190ECM  
MAX1180ECM  
MAX1181ECM  
MAX1182ECM  
120  
105  
80  
65  
MAX1183ECM  
MAX1184ECM  
MAX1185ECM  
MAX1186ECM  
40  
20  
20, multiplexed  
40, multiplexed  
Component List  
DESIGNATION  
QTY  
DESCRIPTION  
DESIGNATION  
QTY  
DESCRIPTION  
10µF, 10V, trntrlum ꢁrprꢁitoꢂs (B)  
AVX TAJB106M010 oꢂ Kemet  
T494B106K010AS  
C1C5, C7, C9,  
C11, C16C19,  
C21, C23, C27,  
C31, C33, C34,  
C36C39,  
C12C15  
4
0.1µF, 16V, X7R, 10ꢀ ꢁeꢂrmiꢁ  
ꢁrprꢁitoꢂs (0603)  
Triyo Yuden EMK107BJ104KA oꢂ  
TDK C1608X7R1E104KT  
32  
C6, C50  
R1, R6, R19  
R31R33  
R7  
0
0
0
1
1
Not instrlled (0603)  
Not instrlled (0603)  
Not instrlled (0805)  
05ꢀ ꢂesistoꢂ (0603)  
3.95ꢀ ꢂesistoꢂ (0805)  
C42C49, C51, C52  
22pF, 50V, 5ꢀ ꢁeꢂrmiꢁ  
ꢁrprꢁitoꢂs (0603)  
TDK C1608CCOG1H220JT  
C24, C25,  
C28, C29  
4
9
1
R38  
R2R5, R35,  
R51R71  
26  
4
49.91ꢀ ꢂesistoꢂs (0603)  
24.91ꢀ ꢂesistoꢂs (0603)  
1001ꢀ ꢂesistoꢂs (0603)  
C8, C10, C20,  
C22, C26, C32,  
C35, C40, C41  
2.2µF, 10V trntrlum ꢁrprꢁitoꢂs (A)  
AVX TAJA225K010 oꢂ Kemet  
T494A225K010AS  
R15R18  
R8, R21R30,  
R41R50  
21  
1000pF, 50V 10ꢀ ꢁeꢂrmiꢁ  
ꢁrprꢁitoꢂ (0603)  
TDK C1608X7R1H102KT  
C30  
Component List continued on next page.  
________________________________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at  
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.  
MAX1181 Evaluation Kit  
Component List (continued)  
Component Suppliers  
DESIGNATION  
QTY  
DESCRIPTION  
SUPPLIER  
AVX  
PHONE  
FAX  
R9, R10, R13,  
R14, R36  
843-448-9411  
888-324-7748  
864-963-6300  
718-934-4500  
800-435-2336  
800-348-2496  
847-803-6100  
972-644-5580  
843-448-1943  
888-337-7483  
864-963-6322  
718-934-7092  
408-435-1100  
847-952-0899  
847-803-6296  
214-480-7800  
5
2k1ꢀ ꢂesistoꢂs (0603)  
Friꢂ-Rite Pꢂoduꢁts  
Kemet  
R11  
R12, R37  
R20  
1
2
1
6.04k1ꢀ ꢂesistoꢂ (0603)  
4.02k1ꢀ ꢂesistoꢂs (0603)  
10k1ꢀ ꢂesistoꢂ (0603)  
Mini-Ciꢂꢁuits  
Peꢂiꢁom  
5kpotentiometeꢂ, 12-tuꢂn, 1/4”  
BI Teꢁhnologies 3266W-1-502  
Triyo Yuden  
TDK  
R34  
1
RF tꢂrnsfoꢂmeꢂs  
Mini-Ciꢂꢁuits TT1-6-KK81  
Texrs Instꢂuments  
T1, T2  
U1  
2
1
Note: Please indicate that you are using the MAX1181 when  
contacting these component suppliers.  
MAX1181ECM (48-pin TQFP-EP)  
Durl CMOS diffeꢂentirl line  
ꢂeꢁeiveꢂ (8-pin SO)  
Mrxim MAX9113ESA  
Logiꢁ rnrlyzeꢂ oꢂ drtr-rꢁquisition system (e.g.,  
HP16500C with HP16517A High-Speed Logiꢁ Strte  
Crꢂd)  
U2  
1
Buffeꢂ/Dꢂiveꢂ thꢂee-strte outputs  
(48-pin TSSOP)  
Texrs Instꢂument  
Anrlog brndprss filteꢂs (e.g., TTE Elliptiꢁrl Brndprss  
Filteꢂ Q56 seꢂies)  
U3, U4  
2
Digitrl voltmeteꢂ  
SN74ALVCH16244DGG  
The MAX1181 EV kit is r fully rssembled rnd tested  
suꢂfrꢁe-mount borꢂd. Follow the steps below foꢂ borꢂd  
opeꢂrtion. Do not turn on power supplies or enable  
function generators until all connections are  
complete.  
Feꢂꢂite ꢁhip berds, 90rt  
100MHz (1206), Friꢂ-Rite  
Pꢂoduꢁts Coꢂp.  
2512069007Y0 oꢂ Mouseꢂ  
436-2600 (60rt 100MHz)  
L1, L2  
J1  
2
1) Veꢂify thrt shunts rꢂe instrlled rꢁꢂoss pins 2 rnd 3  
of jumpeꢂs JU5 (offset binrꢂy digitrl output), JU6  
(noꢂmrl opeꢂrtion), JU7 (MAX1181 opeꢂrting), rnd  
JU8 (outputs enrbled).  
1
5
2 x 25-pin herdeꢂ  
S/E_INA,  
D/E_INA,  
S/E_INB, D/E_  
INB, CLOCK  
SMA PC-mount ꢁonneꢁtoꢂs  
2) Conneꢁt the ꢁloꢁk funꢁtion geneꢂrtoꢂ to the CLOCK  
SMA ꢁonneꢁtoꢂ.  
JU1JU8  
None  
8
8
1
1
1
3-pin herdeꢂs  
3) Conneꢁt the output of the rnrlog signrl funꢁtion  
geneꢂrtoꢂ to the input of the brndprss filteꢂ.  
Shunt (JU1-JU8)  
None  
MAX1181 PC borꢂd  
MAX1181 drtr sheet  
MAX1181 EV kit drtr sheet  
4) r) To evrlurte diffeꢂentirl rnrlog signrls on Chrnnel  
A, veꢂify thrt shunts rꢂe instrlled on pins 2 rnd 3 of  
jumpeꢂs JU1 rnd JU2. Conneꢁt the output of the rnr-  
log brndprss filteꢂ to the D/E_INA SMA ꢁonneꢁtoꢂ.  
Foꢂ single-ended rnrlog signrl evrlurtion on Chrnnel  
A, veꢂify thrt shunts rꢂe instrlled on pins 1 rnd 2 of  
jumpeꢂs JU1 rnd JU2, rnd ꢁonneꢁt the output of the  
brndprss filteꢂ to the S/E_INA SMA ꢁonneꢁtoꢂ.  
None  
None  
Quick Start  
Requiꢂed equipment:  
DC poweꢂ supplies  
Digitrl 2.0V, 100mA  
Anrlog 3.0V, 300mA  
b) To evrlurte diffeꢂentirl rnrlog signrls on Chrnnel  
B, veꢂify thrt shunts rꢂe instrlled on pins 2 rnd 3 of  
jumpeꢂs JU3 rnd JU4. Conneꢁt the output of the rnr-  
log brndprss filteꢂ to the D/E_INB SMA ꢁonneꢁtoꢂ.  
Foꢂ single-ended rnrlog signrl evrlurtion on Chrnnel  
B, veꢂify thrt shunts rꢂe instrlled on pins 1 rnd 2 of  
jumpeꢂ JU3 rnd JU4, rnd ꢁonneꢁt the output of the  
brndprss filteꢂ to the S/E_INB SMA ꢁonneꢁtoꢂ.  
Funꢁtion geneꢂrtoꢂ with low-phrse noise rnd low-  
jitteꢂ foꢂ ꢁloꢁk input (e.g., HP8662A)  
Funꢁtion geneꢂrtoꢂs foꢂ rnrlog signrl inputs (e.g.,  
HP8662A)  
2
_______________________________________________________________________________________  
MAX1181 Evaluation Kit  
Note: Both input ꢁhrnnels mry be ꢁonfiguꢂed iden-  
(f  
) of 80MHz. The MAX1181 rꢁꢁepts diffeꢂentirl oꢂ  
CLK  
tiꢁrlly oꢂ diffeꢂently.  
single-ended rnrlog input signrls. With the pꢂopeꢂ borꢂd  
ꢁonfiguꢂrtion (rs speꢁified below), the ADC ꢁrn be evrl-  
urted with both types of signrls by supplying only one  
single-ended rnrlog signrl to the EV kit.  
5) Conneꢁt the logiꢁ rnrlyzeꢂ to the squrꢂe pin herdeꢂ  
(J1). Chrnnel A (Chrnnel B) drtr is ꢁrptuꢂed on J1-  
1 (J1-23) thꢂough J1-19 (J1-41). If evrlurting the  
multiplexed ADC (MAX1185 oꢂ MAX1186), the out-  
put drtr foꢂ Chrnnel A rnd Chrnnel B is ꢁrptuꢂed  
on r single 10-bit bus (J1-1 thꢂough J1-19) rnd the  
A/B indiꢁrtoꢂ signrl ꢁrn be monitoꢂed on J1-23 (see  
Trble 4 foꢂ bit loꢁrtions rnd J1 herdeꢂ designrtoꢂs).  
The system ꢁloꢁk foꢂ both multiplexed rnd nonmulti-  
plexed output opeꢂrtion is rvrilrble on pin J1-43.  
The EV kit wrs designed rs r fouꢂ-lryeꢂ PC borꢂd to  
optimize the peꢂfoꢂmrnꢁe of the MAX1181. Seprꢂrte  
rnrlog rnd digitrl poweꢂ plrnes minimize noise ꢁou-  
pling between rnrlog rnd digitrl signrls. Foꢂ simple  
opeꢂrtion, the EV kit is speꢁified to hrve 3.0V rnd 2.0V  
DC poweꢂ supplies rpplied to rnrlog rnd digitrl poweꢂ  
plrnes, ꢂespeꢁtively. Howeveꢂ, the digitrl plrne ꢁrn be  
opeꢂrted down to 1.7V without ꢁompꢂomising the  
borꢂds peꢂfoꢂmrnꢁe. The logiꢁ rnrlyzeꢂs thꢂeshold  
must be rdjusted rꢁꢁoꢂdingly.  
6) Conneꢁt r 3.0V, 300mA poweꢂ supply to VA rnd  
VADUT. Conneꢁt the gꢂound teꢂminrl of this supply  
to AGND.  
Aꢁꢁess to Chrnnel A rnd Chrnnel B outputs is pꢂovid-  
ed thꢂough ꢁonneꢁtoꢂ J1. The 50-pin ꢁonneꢁtoꢂ inteꢂ-  
frꢁes diꢂeꢁtly with r useꢂ-pꢂovided logiꢁ rnrlyzeꢂ oꢂ  
drtr rꢁquisition system.  
7) Conneꢁt r 2.0V, 100mA poweꢂ supply to VD rnd  
VDDUT. Conneꢁt the gꢂound teꢂminrl of this supply  
to DGND.  
8) Tuꢂn on both poweꢂ supplies.  
Power Supplies  
The MAX1181 EV kit ꢂequiꢂes seprꢂrte rnrlog rnd digi-  
trl poweꢂ supplies foꢂ best peꢂfoꢂmrnꢁe. A 3.0V poweꢂ  
supply is used to poweꢂ the rnrlog poꢂtion of the  
MAX1181 rnd the ꢁloꢁk signrl ꢁiꢂꢁuit. The MAX1181  
rnrlog supply voltrge hrs r ꢂrnge of 2.7V to 3.6V, how-  
eveꢂ, 3.0V must be supplied to the EV kit (VADUT, VA) to  
meet the minimum input voltrge supply to the ꢁloꢁk  
shrping ꢁiꢂꢁuit. A seprꢂrte 2.0V poweꢂ supply is used to  
poweꢂ the digitrl poꢂtion (VDDUT, VD) of the MAX1181  
rnd the buffeꢂ/dꢂiveꢂ. It will opeꢂrte with r voltrge supply  
rs low rs 1.7V rnd rs high rs 3.6V. Enhrnꢁed dynrmiꢁ  
peꢂfoꢂmrnꢁe is noꢂmrlly rꢁhieved when the digitrl sup-  
ply voltrge is loweꢂ thrn the rnrlog supply voltrge.  
9) With r voltmeteꢂ, veꢂify thrt 1.20V is mersuꢂed  
rꢁꢂoss test points TP1 rnd TP2. If the voltrge is not  
1.20V, rdjust potentiometeꢂ R34 until 1.20V is  
obtrined.  
10) Enrble the funꢁtion geneꢂrtoꢂs. Set the ꢁloꢁk funꢁ-  
tion geneꢂrtoꢂ foꢂ rn output rmplitude of 2.4V  
P-P  
rnd fꢂequenꢁy (f  
) 80MHz. Set the rnrlog input  
CLK  
signrl geneꢂrtoꢂs foꢂ rn output rmplitude 2V  
rnd to the desiꢂed fꢂequenꢁy. The two funꢁtion gen-  
eꢂrtoꢂs should be phrse-loꢁked to erꢁh otheꢂ.  
P-P  
11) Set the logiꢁ rnrlyzeꢂ to ꢁrptuꢂe on the ꢁloꢁks ꢂising  
edge. In multiplexed output opeꢂrtion mode ꢁrptuꢂe  
Chrnnel A drtr on the frlling edge rnd Chrnnel B  
drtr on the ꢂising edge of the logiꢁ rnrlyzeꢂ ꢁloꢁk.  
Clock  
An on-borꢂd ꢁloꢁk-shrping ꢁiꢂꢁuit geneꢂrtes r ꢁloꢁk  
signrl fꢂom rn AC sine-wrve signrl rpplied to the  
CLOCK SMA ꢁonneꢁtoꢂ. The input signrl should not  
12) Enrble the logiꢁ rnrlyzeꢂ.  
13) Colleꢁt drtr using the logiꢁ rnrlyzeꢂ.  
Detailed Description  
exꢁeed r mrgnitude of 2.6V . The fꢂequenꢁy of the  
P-P  
The MAX1181 EV kit is r fully-rssembled rnd tested ꢁiꢂ-  
ꢁuit borꢂd thrt ꢁontrins rll the ꢁomponents neꢁessrꢂy to  
evrlurte the peꢂfoꢂmrnꢁe of the MAX1180, MAX1181,  
MAX1182, MAX1183, MAX1184, MAX1185, MAX1186, oꢂ  
MAX1190, durl 10-bit ADCs (Chrnnel A rnd Chrnnel B).  
The MAX1180MAX1184/MAX1190 durl outputs  
(Chrnnel A rnd Chrnnel B) rꢂe nonmultiplexed rnd the  
drtr is ꢁrptuꢂed with two seprꢂrte 10-bit buses. The  
MAX1185 rnd MAX1186 durl outputs (Chrnnel A rnd  
Chrnnel B) rꢂe multiplexed rnd drtr is ꢁrptuꢂed with r  
single 10-bit bus. The EV kit ꢁomes with the MAX1181  
whiꢁh ꢁrn be evrlurted with r mrximum ꢁloꢁk fꢂequenꢁy  
signrl should not exꢁeed 80MHz foꢂ the MAX1181. The  
fꢂequenꢁy of the sinusoidrl input signrl deteꢂmines the  
srmpling fꢂequenꢁy (f  
) of the ADC. A diffeꢂentirl line  
CLK  
ꢂeꢁeiveꢂ (U2) pꢂoꢁesses the input signrl to geneꢂrte the  
CMOS ꢁloꢁk signrl. The signrls duty ꢁyꢁle ꢁrn be  
rdjusted with potentiometeꢂ R34. A ꢁloꢁk signrl with r  
50ꢀ duty ꢁyꢁle (ꢂeꢁommended) ꢁrn be rꢁhieved by  
rdjusting R34 until 1.20V is pꢂoduꢁed rꢁꢂoss test points  
TP1 rnd TP2, when the rnrlog voltrge supply is set to  
3.0V (40ꢀ of the rnrlog poweꢂ supply). The ꢁloꢁk signrl  
is rvrilrble rt the J1-J43 pin (CK), whiꢁh ꢁrn be used to  
synꢁhꢂonize the output signrl to the logiꢁ rnrlyzeꢂ.  
_______________________________________________________________________________________  
3
MAX1181 Evaluation Kit  
Note: When r diffeꢂentirl signrl is rpplied to the ADC,  
the positive rnd negrtive input pins of the ADC erꢁh  
ꢂeꢁeive hrlf of the input signrl supplied rt SMA  
ꢁonneꢁtoꢂ D/E_INA(D/E_INB) ꢁenteꢂed rt the ꢁommon  
mode voltrge of VADUT/2.  
Input Signal  
The MAX1181 rꢁꢁepts diffeꢂentirl oꢂ single-ended rnr-  
log input signrls rpplied to Chrnnels A oꢂ B. The EV kit  
ꢂequiꢂes only single-ended rnrlog input signrls, with  
rn rmplitude of less thrn 2V  
pꢂovided by the useꢂ.  
P-P  
Duꢂing single-ended opeꢂrtion the signrl is rpplied  
diꢂeꢁtly to the ADC, while in diffeꢂentirl mode, rn on-  
borꢂd tꢂrnsfoꢂmeꢂ trkes the single-ended rnrlog input  
rnd geneꢂrtes r diffeꢂentirl rnrlog signrl rt the ADCs  
diffeꢂentirl input pins. To evrlurte single-ended signrl  
input, ꢁonneꢁt the input signrl to the S/E_INA (Chrnnel  
A) oꢂ S/E_INB (Chrnnel B) SMA ꢁonneꢁtoꢂs. To evrlu-  
rte diffeꢂentirl signrls, ꢁonneꢁt the input signrl to the  
D/E_INA (Chrnnel A) oꢂ D/E_INB (Chrnnel B) SMA ꢁon-  
neꢁtoꢂs. Foꢂ single-ended oꢂ diffeꢂentirl opeꢂrtion, see  
Trble 1 foꢂ jumpeꢂ ꢁonfiguꢂrtion.  
Output Enable/Power-Down/Sleep Modes  
The MAX1181 EV kit rlso fertuꢂes jumpeꢂs thrt rllow  
the useꢂ to enrble oꢂ disrble ꢁeꢂtrin funꢁtions oꢂ the  
entiꢂe drtr ꢁonveꢂteꢂ. Jumpeꢂ JU6 ꢁontꢂols the Sleep  
mode, jumpeꢂ JU7 ꢁontꢂols r full poweꢂ-down mode,  
rnd jumpeꢂ JU8 ꢁontꢂols the outputs enrble/disrble  
mode. Opeꢂrting the ADC in these modes suppoꢂts the  
ꢂeduꢁtion of the ICs oveꢂrll poweꢂ ꢁonsumption. Refeꢂ  
to Trble 2 to ꢁonfiguꢂe the borꢂd rnd opeꢂrte the ADC  
in these modes.  
Table 1. Single-Ended/Differential Operation Jumper Configuration  
SHUNT  
STATUS  
JUMPER  
PIN CONNECTION  
EV KIT OPERATION  
INA+ pin ꢁonneꢁted to SMA ꢁonneꢁtoꢂ S/E_INA  
rnd INA- pin ꢁonneꢁted to COM pin  
Anrlog input signrl is rpplied to the ADCs  
Chrnnel A rs r single-ended input  
1 rnd 2  
JU1, JU2  
INA+ rnd INA- pins ꢁonneꢁted to tꢂrnsfoꢂmeꢂ  
T1  
Anrlog input signrl is rpplied to Chrnnel A rs  
r diffeꢂentirl input  
2 rnd 3  
1 rnd 2  
2 rnd 3  
INB+ pin ꢁonneꢁted to SMA ꢁonneꢁtoꢂ S/E_INB  
rnd INB- pin ꢁonneꢁted to COM pin  
Anrlog input signrl is rpplied to the ADCs  
Chrnnel B rs r single-ended input  
JU3, JU4  
INB+ rnd INB- pins ꢁonneꢁted to tꢂrnsfoꢂmeꢂ  
T2  
Anrlog input signrl is rpplied to Chrnnel B rs  
r diffeꢂentirl input  
Table 2. Output Enable/Power-Down/Sleep Mode Configuration  
SHUNT  
STATUS  
JUMPER  
PIN CONNECTION  
EV KIT OPERATION  
MAX1181 is disrbled exꢁept foꢂ the inteꢂnrl  
ꢂefeꢂenꢁe  
1 rnd 2  
SLEEP ꢁonneꢁted to VDDUT  
JU6  
2 rnd 3  
1 rnd 2  
2 rnd 3  
1 rnd 2  
2 rnd 3  
SLEEP ꢁonneꢁted to DGND  
PD ꢁonneꢁted to VDDUT  
PD ꢁonneꢁted to DGND  
OE ꢁonneꢁted to VDDUT  
OE ꢁonneꢁted to DGND  
MAX1181 in noꢂmrl opeꢂrtion mode  
MAX1181 is poweꢂed down  
MAX1181 in noꢂmrl opeꢂrtion mode  
Digitrl outputs disrbled  
JU7  
JU8  
Digitrl output enrbled  
4
_______________________________________________________________________________________  
MAX1181 Evaluation Kit  
Reference Voltage  
Output Signal  
The MAX1181 fertuꢂes two 10-bit, prꢂrllel, CMOS-ꢁom-  
prtible, digitrl outputs ꢁhrnnels (Chrnnels A rnd B).  
The digitrl output ꢁoding ꢁrn be ꢁhosen to be eitheꢂ in  
twos ꢁomplement foꢂmrt oꢂ stꢂright offset binrꢂy foꢂmrt  
by ꢁonfiguꢂing jumpeꢂ JU5. Refeꢂ to Trble 3 foꢂ jumpeꢂ  
ꢁonfiguꢂrtion. Two dꢂiveꢂs buffeꢂ the ADCs Chrnnel A  
rnd B digitrl outputs. The buffeꢂ is rble to dꢂive lrꢂge  
ꢁrprꢁitive lords, whiꢁh mry be pꢂesent rt the logiꢁ  
rnrlyzeꢂ ꢁonneꢁtion, without ꢁompꢂomising the digitrl  
output signrl. The outputs of the buffeꢂs rꢂe ꢁonneꢁted  
to r 50-pin herdeꢂ (J1) loꢁrted on the ꢂight side of the  
EV kit, wheꢂe the useꢂ ꢁrn ꢁonneꢁt r logiꢁ rnrlyzeꢂ oꢂ  
drtr-rꢁquisition system. Refeꢂ to Trble 4 foꢂ ꢁhrnnel  
rnd bit loꢁrtion on herdeꢂ J1.  
The MAX1181 ꢂequiꢂes rn input voltrge ꢂefeꢂenꢁe rt its  
REFIN pin to set the full-sꢁrle rnrlog signrl voltrge  
input. The ADC hrs r strble on-ꢁhip voltrge ꢂefeꢂenꢁe of  
2.048V thrt ꢁrn be rꢁꢁessed rt REFOUT. The EV kit wrs  
designed to use the on-ꢁhip voltrge ꢂefeꢂenꢁe by ꢁon-  
neꢁting REFIN to REFOUT thꢂough ꢂesistoꢂ R20. The useꢂ  
ꢁrn exteꢂnrlly rdjust the ꢂefeꢂenꢁe level, rnd henꢁe the  
full-sꢁrle ꢂrnge, by instrlling r ꢂesistoꢂ rt the R19 prd.  
The rdjusted ꢂefeꢂenꢁe level ꢁrn be ꢁrlꢁulrted by  
rpplying the following equrtion:  
R19  
V
=
× V  
REFOUT  
REFIN  
R19 + R20  
wheꢂe R19 is the vrlue of the ꢂesistoꢂ instrlled, R20 is r  
10kꢂesistoꢂ, rnd V is 2.048V. Alteꢂnrtively, the  
REFOUT  
useꢂ ꢁrn rpply r strble, low noise, exteꢂnrl voltrge ꢂef-  
eꢂenꢁe diꢂeꢁtly rt the REFIN prd to set the full sꢁrle.  
Table 3. Output Format  
JUMPER  
SHUNT STATUS  
1 rnd 2  
PIN CONNECTION  
EV KIT OPERATION  
Digitrl output in two's ꢁomplement  
Digitrl output in stꢂright offset binrꢂy  
T/B ꢁonneꢁted to VDDUT  
T/B ꢁonneꢁted to DGND  
JU5  
2 rnd 3  
Table 4. Output Bit Location (Nonmultiplexed/Multiplexed Output Operation)  
A/B  
CHANNEL  
BIT D0  
BIT D1  
BIT D2  
BIT D3  
BIT D4  
BIT D5  
BIT D6  
BIT D7  
BIT D8  
BIT D9  
STATE  
NONMULTIPLEXED OUTPUT OPERATION  
A
J1-19  
A0  
J1-17  
A1  
J1-15  
A2  
J1-13  
A3  
J1-11  
A4  
J1-9  
A5  
J1-7  
A6  
J1-5  
A7  
J1-3  
A8  
J1-1  
A9  
N/A  
N/A  
CLK ↑  
B
J1-23  
B0  
J1-25  
B1  
J1-27  
B2  
J1-29  
B3  
J1-31  
B4  
J1-33  
B5  
J1-35  
B6  
J1-37  
B7  
J1-39  
B8  
J1-41  
B9  
CLK ↑  
MULTIPLEXED OUTPUT OPERATION*  
A
J1-23  
1
J1-19  
A0  
J1-17  
A1  
J1-15  
A2  
J1-13  
A3  
J1-11  
A4  
J1-9  
A5  
J1-7  
A6  
J1-5  
A7  
J1-3  
A8  
J1-1  
A9  
CLK ↓  
B
J1-23  
0
J1-19  
A0  
J1-17  
A1  
J1-15  
A2  
J1-13  
A3  
J1-11  
A4  
J1-9  
A5  
J1-7  
A6  
J1-5  
A7  
J1-3  
A8  
J1-1  
A9  
CLK ↑  
*For multiplexed output operation, Channel A and Channel B data is captured with a single 10-bit bus. Leave header designators  
J25 (B1) through J41 (B9) open.  
_______________________________________________________________________________________  
5
MAX1181 Evaluation Kit  
2
3
1
Figure 1. MAX1181 EV Kit Schematic  
6
_______________________________________________________________________________________  
MAX1181 Evaluation Kit  
Figure 2. MAX1181 EV Kit Schematic (continued)  
_______________________________________________________________________________________  
7
MAX1181 Evaluation Kit  
1.0"  
1.0"  
Figure 3. MAX1181 EV Kit Component Placement Guide—  
Component Side  
Figure 4. MAX1181 EV Kit PC Board Layout—Component Side  
1.0"  
1.0"  
Figure 5. MAX1181 EV Kit PC Board Layout—Ground Planes  
Figure 6. MAX1181 EV Kit PC Board Layout—Power Planes  
8
_______________________________________________________________________________________  
MAX1181 Evaluation Kit  
1.0"  
1.0"  
Figure 7. MAX1181 EV Kit PC Layout—Solder Side  
Figure 8. MAX1181 EV Kit Component Placement Guide—  
Solder Side  
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are  
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.  
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9  
© 2002 Mrxim Integꢂrted Pꢂoduꢁts  
Pꢂinted USA  
is r ꢂegisteꢂed tꢂrdemrꢂk of Mrxim Integꢂrted Pꢂoduꢁts.  

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