MAX1182 [MAXIM]
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs; 双路10位，支持65Msps ， + 3V ，低功耗ADC ，内置电压基准及并行输出
| 型号： | MAX1182 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs |
| 文件： | 总22页 (文件大小：686K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2094; Rev 0; 7/01
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
General Description
Features
The MAX1182 is a +3V, dual 10-bit analog-to-digital
converter (ADC) featuring fully-differential wideband
track-and-hold (T/H) inputs, driving two pipelined, 9-
stage ADCs. The MAX1182 is optimized for low-power,
high-dynamic performance applications in imaging,
instrumentation and digital communication applications.
This ADC operates from a single +2.7V to +3.6V sup-
ply, consuming only 195mW while delivering a typical
signal-to-noise ratio (SNR) of 59dB at an input frequen-
cy of 20MHz and a sampling rate of 65Msps. The T/H
driven input stages incorporate 400MHz (-3dB) input
amplifiers. The converters may also be operated with
single-ended inputs. In addition to low operating power,
the MAX1182 features a 2.8mA sleep mode as well as a
1µA power-down mode to conserve power during idle
periods.
o Single +3V Operation
o Excellent Dynamic Performance:
59dB SNR at f = 20MHz
IN
77dB SFDR at f = 20MHz
IN
o Low Power:
65mA (Normal Operation)
2.8mA (Sleep Mode)
1µA (Shutdown Mode)
o 0.02dB Gain and 0.25° Phase Matching (typ)
o Wide 1V
Differential Analog Input Voltage
P-P
Range
o 400MHz -3dB Input Bandwidth
o On-Chip +2.048V Precision Bandgap Reference
o User-Selectable Output Format—Two’s
Complement or Offset Binary
o 48-Pin TQFP Package with Exposed Pad for
Improved Thermal Dissipation
o Evaluation Kit Available
An internal +2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of the internal or an externally
derived reference, if desired for applications requiring
increased accuracy or a different input voltage range.
The MAX1182 features parallel, CMOS-compatible
three-state outputs. The digital output format is set to
two’s complement or straight offset binary through a
single control pin. The device provides for a separate
output power supply of +1.7V to +3.6V for flexible inter-
facing. The MAX1182 is available in a 7mm x 7mm, 48-
pin TQFP package, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Ordering Information
PART
TEMP. RANGE
PIN-PACKAGE
MAX1182ECM
-40°C to +85°C
48 TQFP-EP
Pin Configuration
Pin-compatible higher and lower speed versions of the
MAX1182 are also available. Please refer to the
MAX1180 datasheet for 105Msps, the MAX1181
datasheet for 80Msps, the MAX1183 datasheet for
40Msps, and the MAX1184 datasheet for 20Msps. In
addition to these speed grades, this family includes a
20Msps multiplexed output version (MAX1185), for
which digital data is presented time-interleaved on a
single, parallel 10-bit output port.
COM
1
2
36 D1A
35 D0A
34 OGND
V
DD
GND
INA+
INA-
3
4
33 OV
32 OV
DD
DD
5
Applications
V
6
31 OGND
30 D0B
29 D1B
DD
MAX1182
GND
INB-
INB+
GND
7
High Resolution Imaging
I/Q Channel Digitization
Multchannel IF Undersampling
Instrumentation
8
D2B
D3B
D4B
D5B
9
28
27
26
25
10
11
12
V
DD
CLK
Video Application
48 TQFP-EP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
ABSOLUTE MAXIMUM RATINGS
DD
V
, OVDD to GND...............................................-0.3V to +3.6V
Continuous Power Dissipation (T = +70°C)
A
OGND to GND.......................................................-0.3V to +0.3V
48-Pin TQFP (derate 12.5mW/°C above +70°C).......1000mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead temperature (soldering, 10s) ..................................+300°C
INA+, INA-, INB+, INB- to GND ...............................-0.3V to V
REFIN, REFOUT, REFP, REFN, CLK,
DD
COM to GND ..........................................-0.3V to (V + 0.3V)
DD
OE, PD, SLEEP, T/B, D9A–D0A,
D9B–D0B to OGND .............................-0.3V to (OV + 0.3V)
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +3V, OV
= +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through
DD
DD
a 10kΩ resistor, V = 2Vp-p (differential w.r.t. COM), C = 10pF at digital outputs (Note 5), f
= 65MHz (50% duty cycle),
IN
L
CLK
T
A
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MIN
MAX A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
10
Bits
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
f
f
= 7.47MHz
0.6
0.4
1.9
1.0
1.7
2
IN
IN
DNL
= 7.47MHz, no missing codes guaranteed
LSB
<
1
% FS
% FS
Gain Error
0
ANALOG INPUT
Differential Input Voltage
Range
V
Differential or single-ended inputs
Switched capacitor load
1.0
/2
V
V
DIFF
Common-Mode Input Voltage
Range
V
DD
V
CM
0.5
Input Resistance
R
33
5
kΩ
IN
IN
Input Capacitance
C
pF
CONVERSION RATE
Maximum Clock Frequency
f
65
MHz
CLK
Clock
Cycles
Data Latency
5
DYNAMIC CHARACTERISTICS (f
= 65MHz, 4096-point FFT)
CLK
f
f
f
f
f
f
f
f
f
= 7.47MHz, T = +25°C
56.8
56.5
59.5
59
INA or B
INA or B
INA or B
INA or B
INA or B
INA or B
INA or B
INA or B
INA or B
A
Signal-to-Noise Ratio
SNR
dB
dB
= 20MHz, T = +25°C
A
= 39.9MHz (Note 1)
59
= 7.47MHz, T = +25°C
56.5
56
59
A
Signal-to-Noise and Distortion
(up to 5th harmonic)
SINAD
SFDR
= 20MHz, T = +25°C
58.5
58.5
76
A
= 39.9MHz (Note 1)
= 7.47MHz, T = +25°C
65
65
A
Spurious-Free Dynamic Range
dBc
= 20MHz, T = +25°C
77
A
= 39.9MHz, (Note 1)
75
2
_______________________________________________________________________________________
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
= +3V, OV
= +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through
DD
DD
a 10kΩ resistor, V = 2Vp-p (differential w.r.t. COM), C = 10pF at digital outputs (Note 5), f
= 65MHz (50% duty cycle),
IN
L
CLK
T
A
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MIN
MAX A
PARAMETER
SYMBOL
CONDITIONS
= 7.47MHz
MIN
TYP
-83
-82
-77
MAX
UNITS
f
f
f
f
f
f
f
f
INA or B
INA or B
INA or B
INA or B
INA or B
INA or B
INA or B
INA or B
Third-Harmonic Distortion
HD3
= 20MHz
dBc
= 39.9MHz (Note 1)
= 19.13042MHz at -6.5dB FS
= 21.2886MHz at -6.5dB FS (Note 2)
Intermodulation Distortion
(first 5 odd-order IMDs)
IMD
THD
-75
dBc
dBc
= 7.47MHz, T = +25°C
-75.5
-76
-74
500
400
1
-64
-63
A
Total Harmonic Distortion
(first 5 harmonics)
= 20MHz, T = +25°C
A
= 39.9MHz, (Note 1)
Small-Signal Bandwidth
Full-Power Bandwidth
Aperture Delay
Input at -20dB FS, differential inputs
Input at -0.5dB FS, differential inputs
MHz
MHz
ns
FPBW
t
AD
Aperture Jitter
t
2
ps
RMS
AJ
Overdrive Recovery Time
Differential Gain
For 1.5 x full-scale input
2
ns
%
1
Differential Phase
Output Noise
0.25
0.2
degrees
INA+ = INA- = INB+ = INB- = COM
LSB
RMS
INTERNAL REFERENCE
2.048
3%
Reference Output Voltage
REFOUT
V
Reference Temperature
Coefficient
TC
60
ppm/°C
REF
Load Regulation
1.25
mV/mA
BUFFERED EXTERNAL REFERENCE (V
= +2.048V)
REFIN
REFIN Input Voltage
V
2.048
2.012
V
V
REFIN
Positive Reference Output
Voltage
V
REFP
Negative Reference Output
Voltage
V
0.988
V
REFN
Differential Reference Output
Voltage Range
∆V
∆V
= V
- V
REFN
0.98
1.024
>50
1.07
V
REF
REF
REFP
REFIN Resistance
R
MΩ
REFIN
_______________________________________________________________________________________
3
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
= +3V, OV
= +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through
DD
DD
a 10kΩ resistor, V = 2Vp-p (differential w.r.t. COM), C = 10pF at digital outputs (Note 5), f
= 65MHz (50% duty cycle),
IN
L
CLK
T
A
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MIN
MAX A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Maximum REFP, COM Source
Current
I
>5
mA
SOURCE
Maximum REFP, COM Sink
Current
I
250
µA
SINK
Maximum REFN Source Current
Maximum REFN Sink Current
I
250
>5
µA
SOURCE
I
mA
SINK
(V
REFIN
= AGND, reference voltage applied to REFP, REFN, and COM)
UNBUFFERED EXTERNAL REFERENCE
R
R
,
Measured between REFP and COM, and
REFN and COM
REFP
REFP, REFN Input Resistance
4
kΩ
V
REFN
Differential Reference Input
Voltage
1.024
10%
∆V
∆V
= V
– V
REFP REFN
REF
REF
VDD/2
10%
COM Input Voltage
REFP Input Voltage
REFN Input Voltage
V
V
COM
REFP
REFN
V
+
COM
V
V
∆V
/2
REF
V
-
COM
V
V
∆V
/2
REF
OE
DIGITAL INPUTS (CLK, PD,
, SLEEP, T/B)
CLK
0.8 x V
DD
Input High Threshold
V
V
IH
PD, OE, SLEEP, T/B
CLK
0.8xOV
DD
0.2 x V
DD
Input Low Threshold
Input Hysteresis
Input Leakage
V
V
V
IL
PD, OE, SLEEP, T/B
0.2xOV
DD
V
0.1
5
HYST
I
IH
V
V
= OV or V (CLK)
5
5
IH
IL
DD
DD
µA
pF
I
= 0
IL
Input Capacitance
C
IN
DIGITAL OUTPUTS (D9A–D0A, D9B–D0B)
Output Voltage Low
V
I
I
= 200µA
0.2
10
V
V
OL
SINK
Output Voltage High
V
= 200µA
OV - 0.2
DD
OH
SOURCE
Three-State Leakage Current
Three-State Output Capacitance
I
OE = OV
OE = OV
µA
pF
LEAK
DD
DD
C
5
OUT
4
_______________________________________________________________________________________
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
= +3V, OV
= +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through
DD
DD
a 10kΩ resistor, V = 2Vp-p (differential w.r.t. COM), C = 10pF at digital outputs (Note 5), f
= 65MHz (50% duty cycle),
IN
L
CLK
T
A
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MIN
MAX A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
V
2.7
1.7
3.0
2.5
65
2.8
1
3.6
3.6
80
V
V
DD
OV
DD
Operating, f
Sleep mode
= 20MHz at -0.5dB FS
INA or B
mA
µA
Analog Supply Current
I
VDD
Shutdown, clock idle, PD = OE = OV
15
DD
Operating, C = 15pF, f
L
-0.5dB FS
= 20MHz at
INA or B
11
mA
Output Supply Current
I
OVDD
Sleep mode
100
2
µA
Shutdown, clock idle, PD = OE = OV
10
DD
Operating, f
Sleep mode
= 20MHz at -0.5dB FS
195
8.4
3
240
INA or B
mW
Power Dissipation
PDISS
PSRR
Shutdown, clock idle, PD = OE = OV
45
8
µW
mV/V
%/V
DD
Offset
Gain
0.2
0.1
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Output Enable Time
t
Figure 3 (Note 3)
5
ns
ns
ns
ns
ns
DO
t
Figure 4
10
ENABLE
Output Disable Time
t
Figure 4
1.5
DISABLE
7.7 1.5
7.7 1.5
CLK Pulse Width High
CLK Pulse Width Low
t
Figure 3, clock period: 15.4ns
Figure 3, clock period: 15.4ns
Wakeup from Sleep mode (Note 4)
Wakeup from Shutdown (Note 4)
CH
t
CL
0.42
1.5
Wake-Up Time
t
µs
WAKE
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
f
f
f
= 20MHz at -0.5dB FS
= 20MHz at -0.5dB FS
= 20MHz at -0.5dB FS
-70
dB
dB
INA or B
INA or B
INA or B
Gain Matching
0.02
0.25
0.2
Phase Matching
degrees
Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS referenced to a +1.024V full-scale
input voltage range.
Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB or better, if referenced to the two-tone envelope.
Note 3: Digital outputs settle to V , V . Parameter guaranteed by design.
IH IL
Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Note 5: Equivalent dynamic performance is obtainable over full OV
range with reduced C .
DD
L
_______________________________________________________________________________________
5
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Typical Operating Characteristics
(V = +3V, OV = +2.5V, internal reference, differential input at -0.5dB FS, f
noted.)
= 65MHz, C ≈ 10pF, T = +25°C, unless otherwise
DD
DD
CLK
L
A
FFT PLOT CHA (8192-POINT RECORD,
DIFFERENTIAL INPUT)
FFT PLOT CHB (8192-POINT RECORD,
DIFFERENTIAL INPUT)
FFT PLOT CHA (8192-POINT RECORD,
DIFFERENTIAL INPUT)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f
f
f
= 6.0065MHz
= 7.51410MHz
= 65.00057MHz
f
f
f
= 6.0065MHz
= 7.51410MHz
= 65.00057MHz
CHB
CHA
INA
INB
CLK
INA
INB
CLK
f
f
f
= 20.08257MHz
= 25.09727MHz
= 65.00057MHz
CHA
INA
INB
CLK
AINA = -0.55dB FS
AINB = -0.56dB FS
AINB = -0.52dB FS
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT CHB (8192-POINT RECORD,
DIFFERENTIAL INPUT)
FFT PLOT CHA (8192-POINT RECORD,
DIFFERENTIAL INPUT)
FFT PLOT CHB (8192-POINT RECORD,
DIFFERENTIAL INPUT)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f
f
f
= 37.31661MHz
= 46.99687MHz
= 65.00057MHz
f
f
f
= 20.08257MHz
= 25.09727MHz
= 65.00057MHz
INA
INB
CLK
f
f
f
= 37.31661MHz
= 46.99687MHz
= 65.00057MHz
INA
INB
CLK
CHB
INA
INB
CLK
CHA
CHB
AINB = -0.49dB FS
AINB = -0.52dB FS
AINB = -0.52dB FS
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
TWO-TONE IMD PLOT (8192-POINT RECORD,
DIFFERENTIAL INPUT)
SIGNAL-TO-NOISE + DISTORTION
vs. ANALOG INPUT FREQUENCY
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
62
60
58
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
61
60
59
58
57
56
55
DIFFERENTIAL INPUT CONFIGURATION
CHB
DIFFERENTIAL INPUT CONFIGURATION
f
f
f
= 19.13042MHz
= 21.28864MHz
= 65.00057MHz
IN1
IN2
CLK
CHB
f
IN1
AIN = -6.5dB FS
TWO-TONE ENVELOPE
= -0.47dB FS
CHA
f
IN2
CHA
3rd ORDER IMD
2nd ORDER IMD
56
54
1
10
100
1
10
100
0
5
10
15
20
25
30
35
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
6
_______________________________________________________________________________________
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Typical Operating Characteristics (continued)
(V = +3V, OV = +2.5V, internal reference, differential input at -0.5dB FS, f
noted.)
= 65MHz, C ≈ 10pF, T = +25°C, unless otherwise
DD
DD
CLK
L
A
FULL-POWER INPUT BANDWIDTH
vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
-65
6
87
83
79
75
71
67
63
DIFFERENTIAL INPUT
CONFIGURATION
DIFFERENTIAL INPUT
CHA
CONFIGURATION
4
2
-68
-71
-74
-77
CHB
0
-2
-4
-6
-8
CHA
CHB
-80
1
10
100
1
10
100
1
10
100
1000
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
SMALL-SIGNAL INPUT BANDWIDTH
vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED
SIGNAL-TO-NOISE RATIO
SIGNAL-TO-NOISE + DISTORTION
vs. INPUT POWER (f = 20.085279MHz)
vs. INPUT POWER (f = 20.085279MHz)
IN
IN
6
65
65
60
55
50
45
40
35
A
IN
= 100mV
P-P
4
2
60
55
50
45
40
35
0
-2
-4
-6
-8
1
10
100
1000
-20
-16
-12
-8
-4
0
-20
-16
-12
-8
-4
0
ANALOG INPUT FREQUENCY (MHz)
INPUT POWER (dB FS)
INPUT POWER (dB FS)
TOTAL HARMONIC DISTORTION
vs. INPUT POWER (f = 20.085279MHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. INPUT POWER (f = 20.085279MHz)
INTEGRAL NONLINEARITY
(BEST-ENDPOINT FIT)
IN
IN
1.0
-55
-60
-65
-70
-75
-80
80
76
72
68
64
60
0.5
0
-0.5
-1.0
-20
-16
-12
-8
-4
0
-20
-16
-12
-8
-4
0
0
128 256 384 512 640 768 896 1024
DIGITAL OUTPUT CODE
INPUT POWER (dB FS)
INPUT POWER (dB FS)
_______________________________________________________________________________________
7
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Typical Operating Characteristics (continued)
(V = +3V, OV = +2.5V, internal reference, differential input at -0.5dB FS, f
noted.)
= 65MHz, C ≈ 10pF, T = +25°C, unless otherwise
DD
DD
CLK
L
A
OFFSET ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE
GAIN ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE (V
= +2.048V)
DIFFERENTIAL NONLINEARITY
REFIN
(V
= +2.048V)
REFIN
0.5
0.4
1.0
0.5
0.15
0.10
0.05
0
CHB
0.3
0
CHB
0.2
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
CHA
-0.05
-0.10
-0.15
CHA
0
128 256 384 512 640 768 896 1024
DIGITAL OUTPUT CODE
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
ANALOG POWER-DOWN CURRENT
vs. ANALOG POWER SUPPLY
80
70
60
50
40
85
0.30
0.24
0.18
0.12
0.06
0
OE = PD = OV
DD
75
65
55
45
2.70 2.85 3.00 3.15 3.30 3.45 3.60
(V)
-40
-15
10
35
60
85
2.70 2.85 3.00 3.15 3.30 3.45 3.60
(V)
V
DD
TEMPERATURE (°C)
V
DD
INTERNAL REFERENCE VOLTAGE
vs. ANALOG POWER VOLTAGE
SFDR, SNR, THD, SINAD
vs. CLOCK DUTY CYCLE
2.045
2.040
2.035
2.030
2.025
2.020
90
80
70
60
50
40
f
= 25.097265MHz
IN
SFDR
THD
SNR
SINAD
2.70 2.85 3.00 3.15 3.30 3.45 3.60
30 35 40 45 50 55 60 65 70
CLOCK DUTY CYCLE (%)
V
DD
(V)
8
_______________________________________________________________________________________
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Typical Operating Characteristics (continued)
(V = +3V, OV = +2.5V, internal reference, differential input at -0.5dB FS, f
noted.)
= 65MHz, C ≈ 10pF, T = +25°C, unless otherwise
L A
DD
DD
CLK
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
OUTPUT NOISE HISTOGRAM (DC INPUT)
160000
140000
120000
100000
80000
60000
40000
20000
0
2.06
2.05
2.04
2.03
2.02
2.01
2.00
129421
926
N-1
725
N+1
0
0
N-2
N
N+2
-40
-15
10
35
60
85
DIGITAL OUTPUT CODE
TEMPERATURE (°C)
Pin Description
PIN
NAME
FUNCTION
1
COM
Common-Mode Voltage Input/Output. Bypass to GND with a ≥0.1µF capacitor.
Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with
0.1µF.
2, 6, 11, 14, 15
V
DD
3, 7, 10, 13, 16
GND
INA+
INA-
INB-
INB+
CLK
Analog Ground
4
5
Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+.
Channel A Negative Analog Input. For single-ended operation, connect INA- to COM.
Channel B Negative Analog Input. For single-ended operation, connect INB- to COM.
Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+.
Converter Clock Input
8
9
12
T/B selects the ADC digital output format.
High: Two’s complement.
Low: Straight offset binary.
17
18
19
20
T/B
SLEEP
PD
Sleep Mode Input.
High: Deactivates the two ADCs, but leaves the reference bias circuit active.
Low: Normal operation.
Power-Down Input.
High: Power-down mode
Low: Normal operation
Output Enable Input.
High: Digital outputs disabled
Low: Digital outputs enabled
OE
_______________________________________________________________________________________
9
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Pin Description (continued)
PIN
21
NAME
D9B
D8B
D7B
D6B
D5B
D4B
D3B
D2B
D1B
D0B
OGND
FUNCTION
Three-State Digital Output, Bit 9 (MSB), Channel B
22
Three-State Digital Output, Bit 8, Channel B
Three-State Digital Output, Bit 7, Channel B
Three-State Digital Output, Bit 6, Channel B
Three-State Digital Output, Bit 5, Channel B
Three-State Digital Output, Bit 4, Channel B
Three-State Digital Output, Bit 3, Channel B
Three-State Digital Output, Bit 2, Channel B
Three-State Digital Output, Bit 1, Channel B
Three-State Digital Output, Bit 0 (LSB), Channel B
Output Driver Ground
23
24
25
26
27
28
29
30
31, 34
Output Driver Supply Voltage. Bypass to OGND with a capacitor combination of 2.2µF in
parallel with 0.1µF.
32, 33
OV
DD
35
36
37
38
39
40
41
42
43
44
D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
D9A
Three-State Digital Output, Bit 0 (LSB), Channel A
Three-State Digital Output, Bit 1, Channel A
Three-State Digital Output, Bit 2, Channel A
Three-State Digital Output, Bit 3, Channel A
Three-State Digital Output, Bit 4, Channel A
Three-State Digital Output, Bit 5, Channel A
Three-State Digital Output, Bit 6, Channel A
Three-State Digital Output, Bit 7, Channel A
Three-State Digital Output, Bit 8, Channel A
Three-State Digital Output, Bit 9 (MSB), Channel A
Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor
divider.
45
46
47
48
REFOUT
REFIN
REFP
Reference Input. V
= 2 ✕ (V
REFP
- V
REFN
). Bypass to GND with a >1nF capacitor.
REFIN
Positive Reference Input/Output. Conversion range is (V
> 0.1µF capacitor.
- V
REFN
). Bypass to GND with a
REFP
REFN
Negative Reference Input/Output. Conversion range is (V
a > 0.1µF capacitor.
- V
REFN
). Bypass to GND with
REFP
10 ______________________________________________________________________________________
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
hold mode. In track mode, switches S1, S2a, S2b, S4a,
Detailed Description
S4b, S5a and S5b are closed. The fully-differential cir-
The MAX1182 uses a 9-stage, fully-differential
cuits sample the input signals onto the two capacitors
pipelined architecture (Figure 1) that allows for high-
(C2a and C2b) through switches S4a and S4b. S2a and
speed conversion while minimizing power consump-
S2b set the common mode for the amplifier input, and
tion. Samples taken at the inputs move progressively
open simultaneously with S1, sampling the input wave-
through the pipeline stages every half clock cycle.
form. Switches S4a and S4b are then opened before
Counting the delay through the output latch, the clock-
switches S3a and S3b, connect capacitors C1a and
cycle latency is five clock cycles.
C1b to the output of the amplifier, and switch S4c is
1.5-bit (2-comparator) flash ADCs convert the held-
input voltages into a digital code. The digital-to-analog
converters (DACs) convert the digitized results back
into analog voltages, which are then subtracted from
the original held input signals. The resulting error sig-
nals are then multiplied by two and the residues are
passed along to the next pipeline stages where the
process is repeated until the signals have been
processed by all nine stages. Digital error correction
compensates for ADC comparator offsets in each of
these pipeline stages and ensures no missing codes.
closed. The resulting differential voltages are held on
capacitors C2a and C2b. The amplifiers are used to
charge capacitors C1a and C1b to the same values
originally held on C2a and C2b. These values are then
presented to the first-stage quantizers and isolate the
pipelines from the fast-changing inputs. The wide input
bandwidth T/H amplifiers allow the MAX1182 to track-
and-sample/hold analog inputs of high frequencies (>
Nyquist). The ADC inputs (INA+, INB+, INA-, and INB-)
can be driven either differentially or single-ended.
Match the impedance of INA+ and INA- as well as
INB+ and INB- and set the common-mode voltage to
Input Track-and-Hold (T/H) Circuits
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuits in both track and
mid-supply (V /2) for optimum performance.
DD
V
IN
V
IN
V
OUT
V
OUT
x2
x2
Σ
Σ
T/H
T/H
FLASH
ADC
FLASH
ADC
DAC
DAC
1.5 BITS
1.5 BITS
2-BIT FLASH
ADC
2-BIT FLASH
ADC
STAGE 1
STAGE 2
STAGE 8
STAGE 9
STAGE 1
STAGE 2
STAGE 8
STAGE 9
DIGITAL CORRECTION LOGIC
10
DIGITAL CORRECTION LOGIC
10
T/H
T/H
D9A–D0A
D9B–D0B
V
INA
V
INB
V
INA
V
INB
= INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE-ENDED)
= INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE-ENDED)
Figure 1. Pipelined Architecture—Stage Blocks
______________________________________________________________________________________ 11
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
INTERNAL
COM
S5a
BIAS
S2a
C1a
S3a
S4a
S4b
INA+
INA-
OUT
OUT
C2a
C2b
S4c
S1
C1b
S3b
S5b
COM
S2b
INTERNAL
BIAS
CLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
HOLD
HOLD
INTERNAL
BIAS
TRACK
TRACK
COM
S5a
S2a
C1a
S3a
S4a
S4b
INB+
INB-
OUT
OUT
C2a
C2b
S4c
S1
MAX1182
C1b
S3b
S5b
COM
S2b
INTERNAL
BIAS
Figure 2. MAX1182 T/H Amplifiers
12 ______________________________________________________________________________________
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
ered as an analog input and routed away from any ana-
log input or other digital signal lines.
Analog Inputs and Reference
Configurations
The full-scale range of the MAX1182 is determined by the
internally generated voltage difference between REFP
The MAX1182 clock input operates with a voltage thresh-
old set to V /2. Clock inputs with a duty cycle other than
DD
(V /2 + V
/4) and REFN (V /2 - V
/4). The
REFIN
DD
REFIN
DD
50%, must meet the specifications for high and low peri-
full-scale range for both on-chip ADCs is adjustable
ods as stated in the Electrical Characteristics.
through the REFIN pin, which is provided for this purpose.
System Timing Requirements
Figure 3 depicts the relationship between the clock
input, analog input, and data output. The MAX1182
samples at the rising edge of the input clock. Output
data for channels A and B is valid on the next rising
edge of the input clock. The output data has an internal
latency of five clock cycles. Figure 4 also determines
the relationship between the input clock parameters
and the valid output data on channels A and B.
REFOUT, REFP, COM (VDD/2), and REFN are internally
buffered low-impedance outputs.
The MAX1182 provides three modes of reference oper-
ation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
In internal reference mode, connect the internal refer-
ence output REFOUT to REFIN through a resistor (e.g.,
10kΩ) or resistor divider, if an application requires a
reduced full-scale range. For stability and noise filtering
purposes bypass REFIN with a >10nF capacitor to
GND. In internal reference mode, REFOUT, COM,
REFP, and REFN become low-impedance outputs.
Digital Output Data, Output Data Format
Selection (T/B), Output Enable (/OE)
All digital outputs, D0A–D9A (Channel A) and D0B–D9B
(Channel B), are TTL/CMOS logic-compatible. There is
a 5-clock-cycle latency between any particular sample
and its corresponding output data. The output coding
can be chosen to be either straight offset binary or
two’s complement (Table 1) controlled by a single pin
(T/B). Pull T/B low to select offset binary and high to
activate two’s complement output coding. The capaci-
tive load on the digital outputs D0A–D9A and D0B–D9B
should be kept as low as possible (<15pF), to avoid
large digital currents that could feed back into the ana-
log portion of the MAX1182, thereby degrading its
dynamic performance. Using buffers on the digital out-
puts of the ADCs can further isolate the digital outputs
from heavy capacitive loads. To further improve the
dynamic performance of the MAX1182 small-series
resistors (e.g., 100Ω) maybe added to the digital output
paths, close to the MAX1182.
In buffered external reference mode, adjust the refer-
ence voltage levels externally by applying a stable and
accurate voltage at REFIN. In this mode, COM, REFP,
and REFN become outputs. REFOUT may be left open
or connected to REFIN through a >10kΩ resistor.
In unbuffered external reference mode, connect REFIN
to GND. This deactivates the on-chip reference buffers
for REFP, COM, and REFN. With their buffers shut
down, these nodes become high impedance and may
be driven through separate external reference sources.
Clock Input (CLK)
The MAX1182’s CLK input accepts CMOS-compatible
clock signals. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (< 2ns). In particular,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide lowest possible jitter. Any
significant aperture jitter would limit the SNR perfor-
mance of the on-chip ADCs as follows:
Figure 4 displays the timing relationship between out-
put enable and data output valid as well as power
down/wake-up and data output valid.
Power-Down (PD) and
Sleep (SLEEP) Modes
The MAX1182 offers two power-save modes—sleep and
full power-down mode. In sleep mode (SLEEP = 1), only
the reference bias circuit is active (both ADCs are dis-
abled), and current consumption is reduced to 2.8mA.
✕
SNR = 20 log (1 / [2π x fIN x tAJ]),
dB
10
To enter full power-down mode, pull PD high. With OE
simultaneously low, all outputs are latched at the last
value prior to the power down. Pulling OE high forces
the digital outputs into a high impedance state.
where fIN represents the analog input frequency and t
is the time of the aperture jitter.
AJ
Clock jitter is especially critical for undersampling
applications. The clock input should always be consid-
______________________________________________________________________________________ 13
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
5 CLOCK-CYCLE LATENCY
N
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
ANALOG INPUT
CLOCK INPUT
t
D0
t
CH
t
CL
DATA OUTPUT
N - 6
N - 6
N - 5
N - 5
N - 4
N - 4
N - 3
N - 3
N - 2
N - 1
N - 1
N
N
N + 1
D9A–D0A
DATA OUTPUT
N - 2
N + 1
D9B–D0B
Figure 3. System Timing Diagram
amplifiers. The user may select the R
and C val-
IN
ISO
ues to optimize the filter performance, to suit a particu-
lar application. For the application in Figure 5, a R of
OE
ISO
50Ω is placed before the capacitive load to prevent
ringing and oscillation. The 22pF C capacitor acts as
IN
a small bypassing capacitor.
t
t
DISABLE
ENABLE
OUTPUT
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
Using Transformer Coupling
A RF transformer (Figure 6) provides an excellent solu-
tion to convert a single-ended source signal to a fully
differential signal, required by the MAX1182 for opti-
mum performance. Connecting the center tap of the
VALID DATA
VALID DATA
D9A–D0A
OUTPUT
D9B–D0B
transformer to COM provides a V /2 DC level shift to
DD
the input. Although a 1:1 transformer is shown, a step-
up transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the over-
all distortion.
Figure 4. Output Timing Diagram
Applications Information
Figure 5 depicts a typical application circuit containing
two single-ended to differential converters. The internal
In general, the MAX1182 provides better SFDR and
THD with fully-differential input signals than single-
ended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower as both inputs (INA+, INA- and/or INB+, INB-) are
balanced, and each of the ADC inputs only requires
half the signal swing compared to single-ended mode.
reference provides a V /2 output voltage for level
DD
shifting purposes. The input is buffered and then split to
a voltage follower and inverter. One lowpass filter per
ADC suppresses some of the wideband noise associat-
ed with high-speed operational amplifiers, follows the
14 ______________________________________________________________________________________
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Table 1. MAX1182 Output Codes For Differential Inputs
STRAIGHT OFFSET
DIFFERENTIAL INPUT
VOLTAGE*
DIFFERENTIAL
INPUT
TWO’S COMPLEMENT
BINARY
T/B = 0
T/B = 1
V
x 511/512
+FULL SCALE - 1LSB
+ 1 LSB
11 1111 1111
10 0000 0001
10 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
11 1111 1111
10 0000 0001
10 0000 0000
REF
V
x 1/512
0
REF
Bipolar Zero
- V
x 1/512
- 1 LSB
REF
-V
x 511/512
x 512/512
- FULL SCALE + 1 LSB
- FULL SCALE
REF
REF
-V
= V
*V
REF
- V
REFN
REFP
Single-Ended AC-Coupled Input Signal
Grounding, Bypassing, and
Board Layout
Figure 7 shows an AC-coupled, single-ended applica-
tion. Amplifiers like the MAX4108 provide high-speed,
high-bandwidth, low noise, and low distortion to main-
tain the integrity of the input signal.
The MAX1182 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side as
the ADC, using surface-mount devices for minimum
Typical QAM Demodulation Application
The most frequently used modulation technique for dig-
ital communications applications is probably the
Quadrature Amplitude Modulation (QAM). Typically
found in spread-spectrum based systems, a QAM sig-
nal represents a carrier frequency modulated in both
amplitude and phase. At the transmitter, modulating the
baseband signal with quadrature outputs, a local oscil-
lator followed by subsequent up-conversion can gener-
ate the QAM signal. The result is an in-phase (I) and a
quadrature (Q) carrier component, where the Q compo-
nent is 90 degree phase-shifted with respect to the in-
phase component. At the receiver, the QAM signal is
divided down into it’s I and Q components, essentially
representing the modulation process reversed. Figure 8
displays the demodulation process performed in the
analog domain, using the dual matched +3V, 10-bit
ADC MAX1182 and the MAX2451 quadrature demodu-
lator to recover and digitize the I and Q baseband sig-
nals. Before being digitized by the MAX1182, the
mixed-down signal components may be filtered by
matched analog filters, such as Nyquist or pulse-shap-
ing filters which remove any unwanted images from the
mixing process, thereby enhancing the overall signal-
to-noise (SNR) performance and minimizing inter-sym-
bol interference.
inductance. Bypass V , REFP, REFN, and COM with
DD
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OV ) to OGND. Multilayer
DD
boards with separated ground and power planes pro-
duce the highest level of signal integrity. Consider the
use of a split ground plane arranged to match the
physical location of the analog ground (GND) and the
digital output driver ground (OGND) on the ADCs pack-
age. The two ground planes should be joined at a sin-
gle point such that the noisy digital ground currents do
not interfere with the analog ground plane. The ideal
location of this connection can be determined experi-
mentally at a point along the gap between the two
ground planes, which produces optimum results. Make
this connection with a low-value, surface-mount resistor
(1Ω to 5Ω), a ferrite bead or a direct short. Alternatively,
all ground pins could share the same ground plane, if
the ground plane is sufficiently isolated from any noisy,
digital systems ground plane (e.g., downstream output
buffer or DSP ground plane). Route high-speed digital
signal traces away from the sensitive analog traces of
either channel. Make sure to isolate the analog input
lines to each respective converter to minimize channel-
to-channel crosstalk. Keep all signal lines short and
free of 90 degree turns.
______________________________________________________________________________________ 15
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
+5V
0.1µF
LOWPASS FILTER
INA+
MAX4108
R
IS0
50Ω
0.1µF
300Ω
C
IN
22pF
0.1µF
-5V
600Ω
600Ω
300Ω
COM
0.1µF
+5V
+5V
0.1µF
0.1µF
600Ω
INPUT
0.1µF
0.1µF
LOWPASS FILTER
MAX4108
300Ω
300Ω
INA-
MAX4108
R
IS0
C
IN
22pF
50Ω
-5V
-5V
+5V
300Ω
300Ω
600Ω
MAX1182
0.1µF
0.1µF
LOWPASS FILTER
INB+
MAX4108
R
IS0
0.1µF
300Ω
C
IN
22pF
50Ω
-5V
600Ω
600Ω
300Ω
0.1µF
+5V
+5V
0.1µF
0.1µF
600Ω
INPUT
0.1µF
0.1µF
LOWPASS FILTER
MAX4108
300Ω
300Ω
INB-
MAX4108
R
IS0
50Ω
C
IN
22pF
-5V
-5V
300Ω
300Ω
600Ω
Figure 5. Typical Application for Single-Ended to Differential Conversion
16 ______________________________________________________________________________________
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
25Ω
INA+
22pF
0.1µF
6
5
4
1
2
T1
V
IN
N.C.
COM
2.2µF
0.1µF
3
MINICIRCUITS
TT1–6
25Ω
INA-
INB+
22pF
22pF
MAX1182
25Ω
0.1µF
6
5
4
1
2
3
T1
V
IN
N.C.
2.2µF
0.1µF
MINICIRCUITS
TT1–6
25Ω
INB-
22pF
Figure 6. Transformer-Coupled Input Drive
error specification of less than 1LSB guarantees no
missing codes and a monotonic transfer function.
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the endpoints of the transfer function, once
offset and gain errors have been nullified. The static lin-
earity parameters for the MAX1182 are measured using
the best straight-line fit method.
Dynamic Parameter Definitions
Aperture Jitter
Figure 9 depicts the aperture jitter (t ), which is the
AJ
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (t ) is the time defined between the
AD
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 9).
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step-width and the ideal value of 1LSB. A DNL
______________________________________________________________________________________ 17
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
REFP
1kΩ
1kΩ
R
V
IN
ISO
50Ω
0.1µF
INA+
COM
INA-
MAX4108
C
IN
22pF
100Ω
100Ω
REFN
0.1µF
R
50Ω
ISO
C
IN
22pF
REFP
MAX1182
R
1kΩ
ISO
50Ω
V
IN
0.1µF
INB+
MAX4108
C
IN
22pF
100Ω
100Ω
1kΩ
REFN
0.1µF
R
ISO
50Ω
INB-
C
IN
22pF
Figure 7: Using an Op Amp for Single-Ended, AC-Coupled Input Drive
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of the
full-scale analog input (RMS value) to the RMS quantiza-
tion error (residual error). The ideal, theoretical minimum
analog-to-digital noise is caused by quantization error
only and results directly from the ADC’s resolution
(N-Bits):
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to all spectral components minus the fundamental
and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB
is computed from:
SNR
= 6.02 x N + 1.76
dB dB
dB[max]
In reality, there are other noise sources besides quanti-
zation noise e.g. thermal noise, reference noise, clock
jitter, etc. SNR is computed by taking the ratio of the
RMS signal to the RMS noise, which includes all spec-
tral components minus the fundamental, the first five
harmonics, and the DC offset.
SINAD
−1.76
dB
dB
ENOB =
6.02
dB
18 ______________________________________________________________________________________
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
MAX2451
INA+
INA-
0°
DSP
90°
POST
MAX1182
PROCESSING
INB+
INB-
DOWNCONVERTER
÷
8
Figure 8. Typical QAM Application, Using the MAX1182
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first four
harmonics of the input signal to the fundamental itself.
This is expressed as:
CLK
2
2
2
2
V
+ V + V + V
3 4 5
2
THD = 20 ×log
10
ANALOG
INPUT
V
1
t
AD
where V is the fundamental amplitude, and V through
5
harmonics.
1
2
t
AJ
V
are the amplitudes of the 2nd- through 5th-order
SAMPLED
DATA (T/H)
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest spurious
component, excluding DC offset.
HOLD
TRACK
TRACK
T/H
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) inter-
modulation products. The individual input tone levels
are at -6.5dB full scale and their envelope is at -0.5dB
full scale.
Figure 9. T/H Aperture Timing
Chip Information
TRANSISTOR COUNT: 10,811
PROCESS: CMOS
______________________________________________________________________________________ 19
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Functional Diagram
V
OGND
OV
DD
GND
DD
INA+
10
10
OUTPUT
DRIVERS
PIPELINE
ADC
D9A–D0A
DEC
T/H
INA-
CLK
CONTROL
OE
INB+
INB-
10
10
PIPELINE
ADC
OUTPUT
DRIVERS
DEC
T/H
D9B–D0B
T/B
PD
SLEEP
REFERENCE
MAX1182
REFOUT
REFN COM REFP
REFIN
20 ______________________________________________________________________________________
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.
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