MAX1121EGK-TD [MAXIM]
ADC, Proprietary Method, 8-Bit, 1 Func, 1 Channel, Parallel, 8 Bits Access, 10 X 10 MM, 0.9 MM HEIGHT, MO-220, QFN-68;
| 型号： | MAX1121EGK-TD |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Proprietary Method, 8-Bit, 1 Func, 1 Channel, Parallel, 8 Bits Access, 10 X 10 MM, 0.9 MM HEIGHT, MO-220, QFN-68 转换器 |
| 文件： | 总17页 (文件大小：425K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3077; Rev 1; 2/04
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
General Description
Features
The MAX1121 is a monolithic 8-bit, 250Msps analog-to-
digital converter (ADC) optimized for outstanding
dynamic performance at high IF frequencies up to
500MHz. The product operates with conversion rates of
up to 250Msps while consuming only 477mW.
♦ 250Msps Conversion Rate
♦ SNR = 48.8dB/48.7dB at f = 100MHz/500MHz
IN
♦ SFDR = 68dBc/63.8dBc at f = 100MHz/500MHz
♦ Single 1.8V Supply
IN
At 250Msps and an input frequency of 100MHz, the
MAX1121 achieves a spurious-free dynamic range
(SFDR) of 68dBc. Its excellent signal-to-noise ratio
(SNR) of 48.9dB at 10MHz remains flat (within 0.5dB)
for input tones up to 500MHz. This makes the MAX1121
ideal for wideband applications such as digital predis-
tortion in cellular base-station transceiver systems.
♦ 477mW Power Dissipation at 250Msps
♦ On-Chip Track-and-Hold and Internal Reference
♦ On-Chip Selectable Divide-by-2 Clock Input
♦ LVDS Digital Outputs with Data Clock Output
♦ Evaluation Kit Available (Order MAX1124EVKIT)
The MAX1121 requires a single 1.8V supply. The ana-
log input is designed for either differential or single-
ended operation and can be AC- or DC-coupled. The
ADC also features a selectable on-chip divide-by-2
clock circuit, which allows the user to apply clock fre-
quencies as high as 500MHz. This helps to reduce the
phase noise of the input clock source. A differential
LVDS sampling clock is recommended for best perfor-
mance. The converter’s digital outputs are LVDS com-
patible, and the data format can be selected to be
either two’s complement or offset binary.
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX1121EGK
-40°C to +85°C
68 QFN-EP*
*EP = Exposed paddle.
The MAX1121 is available in a 68-pin QFN with
exposed paddle (EP) and is specified over the industri-
al (-40°C to +85°C) temperature range.
Pin Configuration
For pin-compatible, higher resolution versions of the
MAX1121, refer to the MAX1122 (170Msps), the
MAX1123 (210Msps), and the MAX1124 (250Msps)
data sheets.
TOP VIEW
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
Applications
Wireless and Wired Broadband Communication
AV
1
2
3
4
5
6
7
8
9
51 D4P
50 D4N
49 D3P
48 D3N
47 D2P
46 D2N
45 OGND
CC
EP
AGND
REFIO
Digital Oscilloscopes
REFADJ
AGND
Digital Predistortion Receivers
Communications Test Equipment
AV
CC
AGND
INP
44 OV
CC
Radar and Satellite Subsystems Antenna Array
Processing
INN
43 DCLKP
42 DCLKN
MAX1121
AGND 10
AV
AV
AV
AV
11
12
13
14
41 OV
CC
CC
CC
CC
CC
Instrumentation
40 D1P
39 D1N
38 D0P
37 D0N
36 N.C.
35 N.C.
AGND 15
AGND 16
CLKDIV 17
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
ABSOLUTE MAXIMUM RATINGS
AV
to AGND ......................................................-0.3V to +2.1V
to OGND .....................................................-0.3V to +2.1V
Continuous Power Dissipation (T = +70°C)
A
CC
OV
68-Pin QFN (derate 41.7mW/°C above +70°C) .........3333mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Maximum Current into Any Pin............................................50mA
CC
AV
to OV .......................................................-0.3V to +2.1V
CC
CC
AGND to OGND ....................................................-0.3V to +0.3V
Analog Inputs to AGND ...........................-0.3V to (AV
Digital Inputs to AGND.............................-0.3V to (AV
REF, REFADJ to AGND............................-0.3V to (AV
Digital Outputs to OGND.........................-0.3V to (OV
+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)
CC
CC
CC
CC
ESD on All Pins (Human Body Model)............................. 2000V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
= OV
= 1.8V, AGND = OGND = 0, f
= 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
CC
CC
SAMPLE
internal reference, digital output pins differential R = 100Ω 1ꢀ, C = 5pF, T = T
to T
, unless otherwise noted. ≥25°C guar-
L
L
A
MIN
MAX
anteed by production test, <25°C guaranteed by design and characterization. Typical values are at T = +25°C.)
A
PARAMETER
DC ACCURACY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
8
Bits
LSB
Integral Nonlinearity
INL
(Note 1)
-0.6
-0.9
-10
±0.2
±0.1
+0.6
+0.9
+10
Differential Nonlinearity
Transfer Curve Offset
Offset Temperature Drift
ANALOG INPUTS (INP, INN)
Full-Scale Input Voltage Range
DNL
No missing codes (Note 1)
(Note 1)
LSB
V
LSB
OS
20
µV/°C
V
(Note 1)
1100
1250
130
1375
mV
P-P
FS
Full-Scale Range Temperature
Drift
ppm/°C
1.38
0.18
Common-Mode Input Range
V
V
CM
Input Capacitance
C
3
pF
kΩ
IN
Differential Input Resistance
Full-Power Analog Bandwidth
REFERENCE (REFIO, REFADJ)
Reference Output Voltage
Reference Temperature Drift
R
3.00
1.18
4.4
600
6.5
IN
FPBW
Figure 8
MHz
V
1.24
90
1.30
V
REFIO
ppm/°C
AV
0.3
-
CC
REFADJ Input High Voltage
V
Used to disable the internal reference
V
REFADJ
SAMPLING CHARACTERISTICS
Maximum Sampling Rate
f
f
250
MHz
MHz
SAMPLE
Minimum Sampling Rate
20
SAMPLE
2
_______________________________________________________________________________________
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AV
= OV
= 1.8V, AGND = OGND = 0, f
= 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
CC
CC
SAMPLE
internal reference, digital output pins differential R = 100Ω 1ꢀ, C = 5pF, T = T
to T
, unless otherwise noted. ≥25°C guar-
L
L
A
MIN
MAX
anteed by production test, <25°C guaranteed by design and characterization. Typical values are at T = +25°C.)
A
PARAMETER
Clock Duty Cycle
SYMBOL
CONDITIONS
MIN
TYP
40 to 60
350
MAX
UNITS
ꢀ
Set by clock management circuit
Aperture Delay
t
ps
AD
Aperture Jitter
t
0.2
ps
RMS
AJ
CLOCK INPUTS (CLKP, CLKN)
Differential Clock Input Amplitude
(Note 2)
200
500
mV
P-P
Clock Input Common-Mode
Voltage Range
1.25
±0.25
V
Clock Differential Input
Resistance
11
±25ꢀ
R
C
kΩ
CLK
Clock Differential Input
Capacitance
5
pF
CLK
DYNAMIC CHARACTERISTICS (at -0.5dBFS)
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
= 10MHz, T ≥ +25°C
47.2
46.2
48.9
48.8
48.8
48.7
48.8
48.7
48.7
48.6
69
A
= 100MHz, T ≥ +25°C
A
Signal-to-Noise Ratio
SNR
SINAD
SFDR
dB
dB
= 180MHz
= 500MHz
= 10MHz, T ≥ +25°C
47.1
46.1
A
= 100MHz, T ≥ +25°C
A
Signal-to-Noise
and Distortion
= 180MHz
= 500MHz
= 10MHz, T ≥ +25°C
60
59
A
= 100MHz, T ≥ +25°C
68
Spurious-Free
Dynamic Range
A
dBc
dBc
= 180MHz
= 500MHz
= 10MHz
69.1
63.8
-74.6
-68.4
-69.1
-63.8
= 100MHz
= 180MHz
= 500MHz
Worst Harmonics
(HD2 or HD3)
f
f
= 99MHz at -7dBFS,
= 101MHz at -7dBFS
IN1
IMD
IMD
-70
-56
100
IN2
Two-Tone Intermodulation
Distortion
dBc
mV
f
f
= 498.5MHz at -7dBFS,
= 502.5MHz at -7dBFS
IN1
500
IN2
LVDS DIGITAL OUTPUTS (D0P/N–D7P/N, DCLKP/N)
Differential Output Voltage |V
|
250
400
OD
_______________________________________________________________________________________
3
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AV
= OV
= 1.8V, AGND = OGND = 0, f
= 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
CC
CC
SAMPLE
internal reference, digital output pins differential R = 100Ω 1ꢀ, C = 5pF, T = T
to T
, unless otherwise noted. ≥25°C guar-
L
L
A
MIN
MAX
anteed by production test, <25°C guaranteed by design and characterization. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
OV
CONDITIONS
MIN
TYP
MAX
UNITS
Output Offset Voltage
1.125
1.310
V
OS
LVCMOS DIGITAL INPUTS (CLKDIV, T/B)
0.2 x
Digital Input Voltage Low
Digital Input Voltage High
V
V
V
IL
AV
CC
0.8 x
V
IH
AV
CC
TIMING CHARACTERISTICS
CLK to Data Propagation Delay
CLK to DCLK Propagation Delay
t
Figure 4
Figure 4
1.5
ns
ns
PDL
t
2.85
CPDL
t
-
CPDL
Data Valid to DCLK Rising Edge
Figure 4 (Note 2)
20ꢀ to 80ꢀ, C = 5pF
0.92
1.35
1.86
ns
t
PDL
LVDS Output Rise-Time
LVDS Output Fall-Time
t
460
460
ps
ps
RISE
L
t
20ꢀ to 80ꢀ, C = 5pF
L
FALL
Clock
cycles
Output Data Pipeline Delay
t
8
LATENCY
POWER REQUIREMENTS
Analog Supply Voltage Range
Digital Supply Voltage Range
Analog Supply Current
AV
OV
1.70
1.70
1.80
1.80
220
45
1.90
1.90
290
75
V
V
CC
CC
I
f
f
f
= 100MHz
= 100MHz
= 100MHz
mA
AVCC
OVCC
IN
IN
IN
Digital Supply Current
I
mA
Analog Power Dissipation
P
477
1.6
657
mW
mV/V
ꢀFS/V
DISS
Offset
Gain
Power-Supply Rejection Ratio
(Note 3)
PSRR
1.9
Note 1: Static linearity and offset parameters are computed from a best-fit straight line through the code transition points. The full-
scale range is defined as 1023 x slope of the line.
Note 2: Parameter guaranteed by design and characterization; T = T
to T
.
MAX
A
MIN
Note 3: PSRR is measured with both analog and digital supplies connected to the same potential.
4
_______________________________________________________________________________________
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Typical Operating Characteristics
(AV
= OV
= 1.8V, AGND = OGND = 0, f
= 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test condi-
CC
CC
SAMPLE
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential R = 100Ω, T = +25°C.)
L
A
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
f
f
= 250.0057MHz
= 60.0294MHz
f
f
= 250.0057MHz
= 11.5054MHz
f = 250.0057MHz
SAMPLE
SAMPLE
IN
SAMPLE
IN
f
IN
= 183.5064MHz
A
IN
= -0.4885MHz
A
IN
= -0.4885MHz
A = -0.5245MHz
IN
SNR = 48.8dB
SFDR = 69.1dBc
HD2 = -77.2dBc
HD3 = -69.1dBc
SNR = 49dB
SNR = 48.9dB
SFDR = 71.1dBc
HD2 = -79.5dBc
HD3 = -71.9dBc
SFDR = 71.5dBc
HD2 = -79.2dBc
HD3 = -74.6dBc
HD2
HD3
HD3
40
HD3
HD2
HD2
0
20
40
60
80 100 120 140
0
20
40
60
80 100 120 140
0
20
60
80 100 120 140
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
SNR vs. ANALOG INPUT FREQUENCY
SFDR vs. ANALOG INPUT FREQUENCY
(f = 250.0057MHz, A = -0.5dBFS)
SAMPLE
(f
= 250.0057MHz, A = -0.5dBFS)
SAMPLE
IN
IN
0
50
80
74
68
62
56
50
f
f
A
= 250.0057MHz
= 500.516MHz
= -0.5235MHz
SAMLE
IN
IN
-10
-20
-30
-40
-50
-60
-70
-80
-90
FUNDAMENTAL
49
48
47
46
45
SNR = 48.8dB
SFDR = 63.8dBc
HD2 = -70.8dBc
HD3 = -63.8dBc
HD3
HD2
0
20
40
60
80 100 120 140
0
100
200
300
(MHz)
400
500
0
100
200 300
f (MHz)
IN
400
500
ANALOG INPUT FREQUENCY (MHz)
f
IN
HD2/HD3 vs. ANALOG INPUT FREQUENCY
SFDR vs. ANALOG INPUT AMPLITUDE
= 250.0057MHz, f = 60.0294MHz)
SAMPLE IN
(f
= 250.0057MHz, A = -0.5dBFS)
(f
(f
SAMPLE
IN
-50
50
45
40
35
30
25
20
75
70
65
60
55
50
45
40
35
30
HD3
-60
-70
-80
HD2
-90
-100
0
100
200
300
(MHz)
400
500
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
f
IN
ANALOG INPUT AMPLITUDE (dBFS)
ANALOG INPUT AMPLITUDE (dBFS)
_______________________________________________________________________________________
5
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Typical Operating Characteristics (continued)
(AV
= OV
= 1.8V, AGND = OGND = 0, f
= 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test condi-
CC
CC
SAMPLE
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential R = 100Ω, T = +25°C.)
L
A
SNR vs. f
(f = 60.0294MHz, A = -0.5dBFS)
HD2/HD3 vs. ANALOG INPUT AMPLITUDE
= 250.0057MHz, f = 60.0294MHz)
SFDR vs. f
SAMPLE
(f = 60.0294MHz, A = -0.5dBFS)
IN IN
SAMPLE
IN
(f
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
IN
SAMPLE
IN
49.0
48.5
48.0
47.5
47.0
46.5
90
80
70
60
50
40
HD3
HD2
20
60
100
f
140
180
220
260
-30
20
0
-25
-20
-15
-10
-5
0
20
60
100
f
140
180
220
260
(MHz)
ANALOG INPUT AMPLITUDE (dBFS)
(MHz)
SAMPLE
SAMPLE
HD2/HD3 vs. f
SAMPLE
TWO-TONE IMD PLOT (8192-POINT
DATA RECORD, COHERENT SAMPLING)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
(f = 60.03294MHz, A = -0.5dBFS)
IN
IN
0
0.5
0.4
-60
-68
f
f
f
= 250.0057MHz
= 99.0318MHz
SAMPLE
IN1
IN2
-10
= 101.046MHz
= A = -7dBFS
0.3
-20
-30
-40
-50
-60
-70
-80
-90
HD3
A
IN1
IN2
0.2
f
IMD = -70dBc
IN1
f
0.1
-76
IN2
0
HD2
2f
-
-84
-0.1
-0.2
-0.3
-0.4
-0.5
IN2
f
2f - f
IN1 IN2
IN1
-92
-100
0
20
40
60
80 100 120 140
60
100
140
180
220
260
0
32 64 96 128 160 192 224 256
DIGITAL OUTPUT CODE
f
(MHz)
ANALOG INPUT FREQUENCY (MHz)
SAMPLE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
SNR vs. TEMPERATURE (f = 65.0108MHz,
IN
GAIN BANDWIDTH PLOT
(f
= 250.0057MHz, A = -0.5dBFS)
f
= 249.856MHz, A = -0.5dBFS)
SAMPLE
IN
SAMPLE IN
2
0
50.0
49.5
49.0
48.5
48.0
47.5
47.0
46.5
46.0
0.5
0.4
0.3
-2
0.2
0.1
-4
0
-6
-0.1
-0.2
-0.3
-0.4
-0.5
-8
-10
-12
32 64 96 128 160 192 224 256
DIGITAL OUTPUT CODE
10
100
ANALOG INPUT FREQUENCY (MHz)
1000
-40
-15
10
35
60
85
°
TEMPERATURE ( C)
6
_______________________________________________________________________________________
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Typical Operating Characteristics (continued)
(AV
= OV
= 1.8V, AGND = OGND = 0, f
= 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test condi-
CC
CC
SAMPLE
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential R = 100Ω, T = +25°C.)
L
A
SINAD vs. TEMPERATURE (f = 65.0108MHz,
SFDR vs. TEMPERATURE (f = 65.0108MHz,
POWER DISSIPATION vs. f
SAMPLE
(f = 60.0294MHz, A = -0.5dBFS)
IN IN
IN
IN
f
= 249.856MHz, A = -0.5dBFS)
f
= 249.856MHz, A = -0.5dBFS)
SAMPLE
IN
SAMPLE
IN
50.0
49.5
49.0
48.5
48.0
47.5
47.0
46.5
46.0
75
70
65
60
55
50
490
480
470
460
450
440
430
420
410
400
-40
-15
10
35
60
85
-40
-15
10
35
60
85
20
60
100
f
140
180
220
260
°
°
TEMPERATURE ( C)
TEMPERATURE ( C)
(MHz)
SAMPLE
SNR vs. SUPPLY VOLTAGE
INTERNAL REFERENCE vs. SUPPLY VOLTAGE
(f = 250.0057MHz)
(f = 60.0294MHz, A = -0.5dBFS)
FS VOLTAGE vs. FS ADJUST RESISTOR
IN
IN
SAMPLE
50
49
48
47
46
45
44
43
1.2350
1.2340
1.2330
1.2320
1.2310
1.2300
1.34
1.32
1.30
1.28
1.26
1.24
1.22
1.20
1.18
1.16
MEASURED AT THE REFIO PIN
REFADJ = AV = OV
FIGURE 6
AV = OV
CC
CC
CC
CC
RESISTOR VALUE APPLIED
BETWEEN REFADJ AND AGND
RESISTOR VALUE APPLIED
BETWEEN REFADJ AND REFIO
1.5
1.6
1.7
1.8
1.9
2.0
2.1
1.5
1.6
1.7
1.8
1.9
2.0
2.1
0
100 200 300 400 500 600 700 800 900 1000
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FS ADJUST RESISTOR (Ω)
PROPAGATION DELAY TIMES
vs. TEMPERATURE
SINAD vs. CLOCK DUTY CYCLE (f = 1.8148MHz,
NOISE HISTOGRAM
(DC INPUT, 256k-POINT DATA RECORD)
IN
f
= 249.856MHz, A = -0.5dBFS)
SAMPLE
IN
6
50.0
49.5
49.0
48.5
48.0
47.5
47.0
46.5
46.0
2.0E+05
1.6E+05
1.2E+05
8.0E+04
4.0E+04
0.0E+00
f
= 250MHz
SAMPLE
5
4
3
2
1
0
131072
t
CPDL
t
PDL
0
0
-40
-15
10
35
60
85
10 20 30 40 50 60 70 80 90
CLOCK DUTY CYCLE (%)
126
127
DIGITAL OUTPUT NOISE
128
°
TEMPERATURE ( C)
_______________________________________________________________________________________
7
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Pin Description
PIN
NAME
AV
FUNCTION
1, 6, 11–14, 20,
25, 62, 63, 65
Analog Supply Voltage. Bypass each pin with a 0.1µF capacitor for best decoupling results.
CC
2, 5, 7, 10, 15, 16,
18, 19, 21, 24, 64,
66, 67, EP
AGND
REFIO
Analog Converter Ground. Connect the converter’s exposed paddle (EP) to AGND.
Reference Input/Output. With REFADJ pulled high through a 1kΩ resistor, this I/O port allows
an external reference source to be connected to the MAX1121. With REFADJ pulled low
through the same 1kΩ resistor, the internal 1.23V bandgap reference is active.
3
Reference-Adjust Input. REFADJ allows for full-scale range adjustments by placing a resistor
or trim potentiometer between REFADJ and AGND (decreases FS range) or REFADJ and
REFIO (increases FS range). If REFADJ is connected to AV
through a 1kΩ resistor, the
CC
4
REFADJ
internal reference can be overdriven with an external source connected to REFIO. If REFADJ
is connected to AGND through a 1kΩ resistor, the internal reference is used to determine the
full-scale range of the data converter.
8
9
INP
INN
Positive Analog Input Terminal
Negative Analog Input Terminal
Clock Divider Input. This LVCMOS-compatible input controls which speed the converter’s
digital outputs are updated. CLKDIV has an internal pulldown resistor.
CLKDIV = 0: ADC updates digital outputs at one-half the input clock rate.
CLKDIV = 1: ADC updates digital outputs at the input clock rate.
17
CLKDIV
CLKP
True Clock Input. This input requires an LVDS-compatible input level to maintain the
converter’s excellent performance.
22
23
Complementary Clock Input. This input requires an LVDS-compatible input level to maintain
the converter’s excellent performance.
CLKN
26, 45, 61
OGND
Digital Converter Ground. Ground connection for digital circuitry and output drivers.
Digital Supply Voltage. Bypass with a 0.1µF capacitor for best decoupling results.
No Connection. Do not connect to these pins.
Complementary Output Bit 0 (LSB)
27, 28, 41, 44, 60
OV
CC
29–36
37
N.C.
D0N
D0P
D1N
D1P
38
True Output Bit 0 (LSB)
39
Complementary Output Bit 1
40
True Output Bit 1
Complementary Clock Output. This output provides an LVDS-compatible output level and can
be used to synchronize external devices to the converter clock. There is a 2.1ns delay
between CLKN and DCLKN.
42
43
DCLKN
DCLKP
True Clock Output. This output provides an LVDS-compatible output level and can be used to
synchronize external devices to the converter clock. There is a 2.1ns delay between CLKP
and DCLKP.
46
47
48
49
D2N
D2P
D3N
D3P
Complementary Output Bit 2
True Output Bit 2
Complementary Output Bit 3
True Output Bit 3
8
_______________________________________________________________________________________
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Pin Description (continued)
PIN
50
51
52
53
54
55
56
57
NAME
D4N
D4P
D5N
D5P
D6N
D6P
D7N
D7P
FUNCTION
Complementary Output Bit 4
True Output Bit 4
Complementary Output Bit 5
True Output Bit 5
Complementary Output Bit 6
True Output Bit 6
Complementary Output Bit 7
True Output Bit 7
Complementary Output for Out-of-Range Control Bit. If an out-of-range condition is detected,
bit ORN flags this condition by transitioning low.
58
59
ORN
ORP
True Output for Out-of-Range Control Bit. If an out-of-range condition is detected, bit ORP
flags this condition by transitioning high.
Two’s Complement or Binary Output Format Selection. This LVCMOS-compatible input
controls the digital output format of the MAX1121. T/B has an internal pulldown resistor.
T/B = 0: Two’s complement output format
68
T/B
T/B = 1: Binary output format
CLKDIV
DCLKP
DCLKN
CLKP
CLKN
CLOCK-
DIVIDER
CONTROL
CLOCK
MANAGEMENT
INPUT
BUFFER
INP
INN
LVDS
DATA PORT
8-BIT PIPELINE
QUANTIZER CORE
T/H
D0P/N–D7P/N
8
2.2kΩ
2.2kΩ
ORP
ORN
REFERENCE
COMMON-MODE
BUFFER
MAX1121
REFIO
REFADJ
Figure 1. MAX1121 Block Diagram
_______________________________________________________________________________________
9
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
biased at a common-mode voltage of 1.4V and allow a
Detailed Description—
differential input voltage swing of 1.25V . Both inputs
P-P
Theory of Operation
are self-biased through 2.2kΩ resistors, resulting in a
typical differential input resistance of 4.4kΩ. It is recom-
mended to drive the analog inputs of the MAX1121 in
AC-coupled configuration to achieve best dynamic per-
formance. See the AC-Coupled Analog Inputs section for
a detailed discussion of this configuration.
The MAX1121 uses a fully differential, pipelined archi-
tecture that allows for high-speed conversion, opti-
mized accuracy and linearity, while minimizing power
consumption and die size.
Both positive (INP) and negative/complementary analog
input terminals (INN) are centered around a common-
mode voltage of 1.4V, and accept a differential analog
input voltage swing of ±0.3125V each, resulting in a typi-
On-Chip Reference Circuit
The MAX1121 features an internal 1.23V bandgap ref-
erence circuit (Figure 3), which, in combination with an
internal reference-scaling amplifier, determines the full-
scale range of the MAX1121. Bypass REFIO with a
0.1µF capacitor to AGND. To compensate for gain
errors or increase the ADC’s full-scale range, the volt-
age of this bandgap reference can be indirectly adjust-
ed by adding an external resistor (e.g., 100kΩ trim
potentiometer) between REFADJ and AGND or
REFADJ and REFIO. See the Applications Information
section for a detailed description of this process.
cal differential full-scale signal swing of 1.25V
.
P-P
INP and INN are buffered prior to entering each track-
and-hold (T/H) stage and are sampled when the differen-
tial sampling clock signal transitions high. A 2-bit ADC
following the first T/H stage then digitizes the signal, and
controls a 2-bit digital-to-analog converter (DAC).
Digitized and reference signals are then subtracted,
resulting in a fractional residue signal that is amplified
before it is passed on to the next stage through another
T/H amplifier. This process is repeated until the applied
input signal has successfully passed through all stages
of the 8-bit quantizer. Finally, the digital outputs of all
stages are combined and corrected for in the digital cor-
rection logic to generate the final output code. The result
is a 8-bit parallel digital output word in user-selectable
two’s complement or binary output formats with LVDS-
compatible output levels. See Figure 1 for a more
detailed view of the MAX1121 architecture.
Clock Inputs (CLKP, CLKN)
Designed for a differential LVDS clock input drive, it is
recommended to drive the clock inputs of the MAX1121
with an LVDS-compatible clock to achieve the best
dynamic performance. The clock signal source must be
a high-quality, low phase noise to avoid any degrada-
tion in the noise performance of the ADC. The clock
inputs (CLKP, CLKN) are internally biased to 1.2V,
accept a differential signal swing of 0.2V
to 1.0V
P-P
P-P
Analog Inputs (INP, INN)
INP and INN are the fully differential inputs of the
MAX1121. Differential inputs usually feature good rejec-
tion of even-order harmonics, which allows for enhanced
AC performance as the signals are progressing through
the analog stages. The MAX1121 analog inputs are self-
REFERENCE
ADC FULL-SCALE = REFT - REFB
SCALING
AMPLIFIER
REFT
REFB
G
REFERENCE
BUFFER
REFIO
AV
CC
0.1µF
1V
REFADJ
INP
INN
CONTROL LINE TO
DISABLE REFERENCE
BUFFER
2.2kΩ
2.2kΩ
1kΩ
TO COMMON-MODE INPUT
TO COMMON-MODE INPUT
AGND
AV
CC
AV / 2
CC
Figure 3. Simplified Reference Architecture
Figure 2. Simplified Analog Input Architecture
10 ______________________________________________________________________________________
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
INN
INP
CLKN
CLKP
t
t
CL
CH
t
AD
N
N + 1
N + 8
N + 9
t
CPDL
t
LATENCY
DCLKP
DCLKN
N - 8
N - 7
N
N + 1
t
- t
CPDL PDL
t
PDL
D0P/N–D7P/N
ORP/N
N - 8
N - 7
N - 1
N
N + 1
t
- t ~ 0.4 x t
with t = 1 / f
SAMPLE SAMPLE
CPDL PDL
SAMPLE
NOTE: THE ADC SAMPLES ON THE RISING EDGE OF CLKP. THE RISING EDGE OF DCLKP CAN BE USED TO EXTERNALLY LATCH THE OUTPUT DATA.
Figure 4. System and Output Timing Diagram
and are usually driven in AC-coupled configuration.
See the Differential, AC-Coupled Clock Input in the
Applications Information section for more circuit details
on how to drive CLKP and CLKN appropriately.
Although not recommended, the clock inputs also
accept a single-ended input signal.
OV
CC
The MAX1121 also features an internal clock manage-
ment circuit (duty-cycle equalizer) that ensures that the
clock signal applied to inputs CLKP and CLKN is
processed to provide a 50ꢀ duty cycle clock signal,
which desensitizes the performance of the converter to
variations in the duty cycle of the input clock source.
Note that the clock duty-cycle equalizer cannot be
turned off externally and requires a minimum clock fre-
quency of >20MHz to work appropriately and accord-
ing to data sheet specifications.
V
V
ON
OP
2.2kΩ
2.2kΩ
Clock Outputs (DCLKP, DCLKN)
The MAX1121 features a differential clock output, which
can be used to latch the digital output data with an
external latch or receiver. Additionally, the clock output
can be used to synchronize external devices (e.g.,
FPGAs) to the ADC. DCLKP and DCLKN are differential
outputs with LVDS-compatible voltage levels. There is a
2.1ns delay time between the rising (falling) edge of
CLKP (CLKN) and the rising edge of DCLKP (DCLKN).
See Figure 4 for timing details.
OGND
Figure 5. Simplified LVDS Output Architecture
______________________________________________________________________________________ 11
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Divide-by-2 Clock Control (CLKDIV)
The MAX1121 offers a clock control line (CLKDIV),
which supports the reduction of clock jitter in a system.
Connect CLKDIV to OGND to enable the ADC’s internal
divide-by-2 clock divider. Data is now updated at one-
half the ADC’s input clock rate. CLKDIV has an internal
pulldown resistor and can be left open for applications
that only operate with update rates one-half of the con-
1). The T/B control line is an LVCMOS-compatible input,
which allows the user to select the desired output for-
mat. Pulling T/B low outputs data in two’s complement
and pulling it high presents data in offset binary format
on the 10-bit parallel bus. T/B has an internal pulldown
resistor and may be left unconnected in applications
using only two’s complement output format. All LVDS
outputs provide a typical voltage swing of 0.4V around
a common-mode voltage of approximately 1.2V, and
must be terminated at the far end of each transmission
line pair (true and complementary) with 100Ω. The
LVDS outputs are powered from a separate power sup-
ply, which can be operated between 1.7V and 1.9V.
verter’s sampling rate. Connecting CLKDIV to OV
CC
allows data to be updated at the speed of the ADC input
clock.
System Timing Requirements
Figure 4 depicts the relationship between the clock
input and output, analog input, sampling event, and
data output. The MAX1121 samples on the rising
(falling) edge of CLKP (CLKN). Output data is valid on
the next rising (falling) edge of the DCLKP (DCLKN)
clock, but has an internal latency of nine clock cycles.
The MAX1121 offers an additional differential output
pair (ORP, ORN) to flag out-of-range conditions, where
out of range is above positive or below negative full
scale. An out-of-range condition is identified with ORP
(ORN) transitioning high (low).
Note: Although differential LVDS reduces single-ended
transients to the supply and ground planes, capacitive
loading on the digital outputs should still be kept as low
as possible. Using LVDS buffers on the digital outputs
of the ADC when driving off-board may improve overall
performance and reduce system timing constraints.
Digital Outputs (D0P/N–D7P/N, DCLKP/N,
ORP/N) and Control Input T/B
The digital outputs D0P/N–D7P/N, DCLKP/N, and ORP/N
are LVDS compatible, and data on D0P/N–D7P/N is pre-
sented in either binary or two’s complement format (Table
Table 1. MAX1121 Digital Output Coding
BINARY
DIGITAL OUTPUT CODE
(D7–D0)
TWO’S COMPLEMENT
DIGITAL OUTPUT CODE
(D7–D0)
INP ANALOG
VOLTAGE LEVEL
INN ANALOG
VOLTAGE LEVEL
OUT-OF-RANGE
ORP (ORN)
1111 1111
(exceeds positive full scale,
OR set)
0111 1111
(exceeds positive full scale,
OR set)
> V
+ 0.3125V
< V
- 0.3125V
CM
1 (0)
0 (1)
0 (1)
0 (1)
1 (0)
CM
1111 1111
(represents positive full
scale)
0111 1111
(represents positive full
scale)
V
+ 0.3125V
V
- 0.3125V
CM
CM
1000 0000 or
0111 1111
(represents midscale)
0000 0000 or
1111 1111
(represents midscale)
V
V
CM
CM
0000 0000
(represents negative full
scale)
1000 0000
(represents negative full
scale)
V
- 0.3125V
V
+ 0.3125V
CM
CM
0000 0000
1000 0000
(exceeds negative full scale, (exceeds negative full scale,
OR set) OR set)
< V
- 0.3125V
> V
+ 0.3125V
CM
CM
12 ______________________________________________________________________________________
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Applications Information
Full-Scale Range Adjustments Using the
ADC FULL-SCALE = REFT - REFB
Internal Bandgap Reference
REFERENCE-
SCALING
The MAX1121 supports a full-scale adjustment range of
10ꢀ (±5ꢀ). To decrease the full-scale range, an exter-
nal resistor value ranging from 13kΩ to 1MΩ may be
added between REFADJ and AGND. A similar
approach can be taken to increase the ADCs full-scale
range. Adding a variable resistor, potentiometer, or
predetermined resistor value between REFADJ and
REFIO increases the full-scale range of the data con-
verter. Figure 6 shows the two possible configurations
and their impact on the overall full-scale range adjust-
ment of the MAX1121. Do not use resistor values of less
than 13kΩ to avoid instability of the internal gain regula-
tion loop for the bandgap reference.
AMPLIFIER
REFT
REFB
G
REFERENCE
BUFFER
REFIO
0.1µF
1V
13kΩ
TO 1MΩ
REFADJ
CONTROL LINE TO
DISABLE REFERENCE
BUFFER
13kΩ
Differential, AC-Coupled, PECL-Compatible
Clock Input
TO 1MΩ
The preferred method of clocking the MAX1121 is differ-
entially with LVDS- or PECL-compatible input levels. To
accomplish this, a 50Ω reverse-terminated clock signal
source with low phase noise is AC-coupled into a fast dif-
ferential receiver such as the MC100LVEL16 (Figure 7).
The receiver produces the necessary PECL output levels
to drive the clock inputs of the data converter.
MAX1121
AV
CC
AV / 2
CC
Figure 6. Circuit Suggestions to Adjust the ADC’s Full-Scale
Range
V
CLK
0.1µF
8
0.1µF
SINGLE-ENDED
INPUT TERMINAL
7
6
0.1µF
50Ω
2
150Ω
MC100LVEL16
AV OV
CC CC
0.1µF
3
CLKN CLKP
INP
INN
150Ω
D0P/N–D7P/N
510Ω
510Ω
4
5
0.01µF
MAX1121
8
VGND
AGND
OGND
Figure 7. Differential, AC-Coupled, PECL-Compatible Clock Input Configuration
______________________________________________________________________________________ 13
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
AV
CC
OV
CC
SINGLE-ENDED
INPUT TERMINAL
0.1µF
15Ω
15Ω
ADT1–1WT
INP
INN
D0P/N–D7P/N
25Ω
25Ω
MAX1121
8
0.1µF
AGND
OGND
Figure 8. Transformer-Coupled Analog Input Configuration with Secondary-Side Termination
Differential, AC-Coupled Analog Input
An RF transformer provides an excellent solution to
convert a single-ended source signal to a fully differen-
AV
CC
OV
CC
SINGLE-ENDED
INPUT TERMINAL
tial signal, required by the MAX1121 for optimum
0.1µF
INP
dynamic performance. In general, the MAX1121 pro-
vides the best SFDR and THD with fully differential
input signals and it is not recommended to drive the
ADC inputs in single-ended configuration. In differential
input mode, even-order harmonics are usually lower
since INP and INN are balanced, and each of the ADC
inputs only requires half the signal swing compared to
a single-ended configuration.
D0P/N–D7P/N
50Ω
MAX1121
0.1µF
INN
8
25Ω
AGND
OGND
Figure 8 depicts a secondary-side termination of the 1:1
transformer into two separate 25Ω loads. Terminating
the transformer in this fashion reduces the potential
effects of transformer parasitics. The source impedance
combined with the shunt capacitance provided by a PC
board and the ADC’s parasitic capacitance reduce the
combined bandwidth to approximately 550MHz.
Figure 9. Single-Ended AC-Coupled Analog Input
Configuration
types can be combined and supplied from one source,
it is recommended to use separate sources to cut down
on performance degradation caused by digital switch-
ing currents, which can couple into the analog supply
Single-Ended, AC-Coupled Analog Input
Although not recommended, the MAX1121 can be
used in single-ended mode (Figure 9). Analog signals
can be AC-coupled to the positive input INP through a
0.1µF capacitor and terminated with a 50Ω resistor to
AGND. The negative input should be 25Ω reverse-ter-
minated and AC grounded with a 0.1µF capacitor.
network. Isolate analog and digital supplies (AV
and
CC
OV ) where they enter the PC board with separate
CC
networks of ferrite beads and capacitors to their corre-
sponding grounds (AGND, OGND).
To achieve optimum performance, provide each supply
with a separate network of a 47µF tantalum capacitor in
parallel with 10µF and 1µF ceramic capacitors.
Additionally, the ADC requires each supply pin to be
bypassed with separate 0.1µF ceramic capacitors
(Figure 10). Locate these capacitors directly at the ADC
supply pins or as close as possible to the MAX1121.
Choose surface-mount capacitors, which are preferably
located on the same side as the converter, to save
space and minimize the inductance.
Grounding, Bypassing, and Board
Layout Considerations
The MAX1121 requires board layout design techniques
suitable for high-speed data converters. This ADC pro-
vides separate analog and digital power supplies. The
analog and digital supply voltage pins accept input
voltage ranges of 1.7V to 1.9V. Although both supply
14 ______________________________________________________________________________________
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
BYPASSING—BOARD LEVEL
BYPASSING—ADC LEVEL
AV
CC
AV
OV
CC
CC
0.1µF
0.1µF
ANALOG POWER-
SUPPLY SOURCE
1µF
10µF
47µF
AGND
OGND
D0P/N–D7P/N
OV
CC
MAX1121
8
DIGITAL/OUTPUT-
DRIVER POWER-
SUPPLY SOURCE
1µF
10µF
47µF
AGND
OGND
NOTE: EACH POWER-SUPPLY PIN (ANALOG AND DIGITAL)
SHOULD BE DECOUPLED WITH AN INDIVIDUAL 0.1µF CAPACITOR CLOSE TO THE ADC.
Figure 10. Grounding, Bypassing, and Decoupling Recommendations for the MAX1121
Multilayer boards with separated ground and power
planes produce the highest level of signal integrity.
Consider the use of a split ground plane arranged to
match the physical location of analog and digital
ground on the ADC’s package. The two ground planes
should be joined at a single point so the noisy digital
ground currents do not interfere with the analog ground
plane. A major concern with this approach are the
dynamic currents that may need to travel long dis-
tances before they are recombined at a common
source ground, resulting in large and undesirable
ground loops. Ground loops can add to digital noise by
coupling back to the analog front end of the converter,
resulting in increased spur activity and a decreased
noise performance.
The MAX1121 is packaged in a 68-pin QFN-EP pack-
age (package code: G6800-4), providing greater
design flexibility, increased thermal efficiency, and opti-
mized AC performance of the ADC. The EP must be
soldered down to AGND.
In this package, the data converter die is attached to
an EP lead frame with the back of this frame exposed
at the package bottom surface, facing the PC board
side of the package. This allows a solid attachment of
the package to the PC board with standard infrared (IR)
flow soldering techniques.
Note that thermal efficiency is not the key factor, since
the MAX1121 features low-power operation. The
exposed pad is the key element to ensure a solid
ground connection between the DAC and the PC
board’s analog ground layer.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy, digital systems ground. To minimize the
effects of digital noise coupling, ground return vias can
be positioned throughout the layout to divert digital
switching currents away from the sensitive analog sec-
tions of the ADC. This does not require additional
ground splitting, but can be accomplished by placing
substantial ground connections between the analog
front end and the digital outputs.
Considerable care must be taken, when routing the
digital output traces for a high-speed, high-resolution
data converter. It is essential to keep trace lengths at a
minimum and place minimal capacitive loading (less
than 5pF) on any digital trace to prevent coupling to
sensitive analog sections of the ADC. It is recommend-
ed to run the LVDS output traces as differential lines
with 100Ω characteristic impedance from the ADC to
the LVDS load device.
______________________________________________________________________________________ 15
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Static Parameter Definitions
CLKP
Integral Nonlinearity (INL)
CLKN
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
ANALOG
INPUT
line can be either a best straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. However, the
t
AD
static linearity parameters for the MAX1121 are mea-
sured using the histogram method with an input fre-
quency of 10MHz.
t
AJ
SAMPLED
DATA (T/H)
Differential Nonlinearly (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function. The
MAX1121’s DNL specification is measured with the his-
togram method based on a 10MHz input tone.
HOLD
TRACK
TRACK
T/H
Figure 11. Aperture Jitter/Delay Specifications
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier fre-
quency (maximum signal component) to the RMS value
of the next-largest noise or harmonic distortion compo-
nent. SFDR is usually measured in dBc with respect to
the carrier frequency amplitude or in dBFS with respect
to the ADC’s full-scale range.
Dynamic Parameter Definitions
Aperture Jitter
Figure 11 depicts the aperture jitter (t ), which is the
AJ
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (t ) is the time defined between the
AD
Two-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) inter-
modulation products. The individual input tone levels
are at -7dB full scale.
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 11).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
Pin-Compatible Higher
Resolution Versions
RESOLUTION
(Bits)
SPEED GRADE
(Msps)
PART
SNR
= 6.02 x N + 1.76
dB dB
dB[max]
MAX1122
MAX1123
MAX1124
10
10
10
170
210
250
In reality, other noise sources such as thermal noise,
clock jitter, signal phase noise, and transfer function
nonlinearities are also contributing to the SNR calcula-
tion and should be considered when determining the
SNR in ADC.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to all spectral components excluding the fundamen-
tal and the DC offset. In case of the MAX1121, SINAD
is computed from a curve fit.
16 ______________________________________________________________________________________
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
1
21-0122
C
2
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
1
21-0122
C
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX1122
1.8V. 10-Bit. 170Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications
MAXIM
MAX1122BEGK+D
ADC, Proprietary Method, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, 10 X 10 MM, 0.90 MM HEIGHT, ROHS COMPLIANT, MO-220, QFN-68
MAXIM
MAX1122BEGK+TD
ADC, Proprietary Method, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, 10 X 10 MM, 0.90 MM HEIGHT, ROHS COMPLIANT, MO-220, QFN-68
MAXIM
MAX1122BEGK-D
ADC, Proprietary Method, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, 10 X 10 MM, 0.90 MM HEIGHT, MO-220, QFN-68
MAXIM
MAX1122BEGK-TD
ADC, Proprietary Method, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, 10 X 10 MM, 0.90 MM HEIGHT, MO-220, QFN-68
MAXIM
MAX1122EGK
ADC, Proprietary Method, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, 10 X 10 MM, 0.90 MM HEIGHT, MO-220, QFN-68
MAXIM
MAX1122EGK+TD
ADC, Proprietary Method, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, 10 X 10 MM, 0.90 MM HEIGHT, ROHS COMPLIANT, MO-220, QFN-68
MAXIM
MAX1122EGK-D
ADC, Proprietary Method, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, 10 X 10 MM, 0.90 MM HEIGHT, MO-220, QFN-68
MAXIM
MAX1122EGK-T
ADC, Proprietary Method, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, 10 X 10 MM, 0.90 MM HEIGHT, MO-220, QFN-68
MAXIM
MAX1122EGK-TD
ADC, Proprietary Method, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, 10 X 10 MM, 0.90 MM HEIGHT, MO-220, QFN-68
MAXIM
MAX1123
1.8V, 10-Bit, 210Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications
MAXIM
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