MAX1113CEE+T [MAXIM]
暂无描述;型号: | MAX1113CEE+T |
厂家: | MAXIM INTEGRATED PRODUCTS |
描述: | 暂无描述 转换器 模数转换器 光电二极管 |
文件: | 总20页 (文件大小:286K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
19-1231; Rev 1; 10/98
+5 V, Lo w -P o w e r, Mu lt i-Ch a n n e l,
S e ria l 8 -Bit ADCs
2/MAX13
Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
The MAX1112/MAX1113 are low-power, 8-bit, 8-chan-
nel analog-to-digital converters (ADCs) that feature an
internal track/hold, voltage reference, clock, and serial
interface. They operate from a single +4.5V to +5.5V
supply and consume only 135µA while sampling at
rates up to 50ksps. The MAX1112’s 8 analog inputs
and the MAX1113’s 4 analog inputs are software-con-
fig ura b le , a llowing unip ola r/b ip ola r a nd s ing le -
ended/differential operation.
♦ +4.5V to +5.5V Single Supply
♦ Low Power: 135µA at 50ksps
13µA at 1ksps
♦ 8-Channel Single-Ended or 4-Channel Differential
Inputs (MAX1112)
♦ 4-Channel Single-Ended or 2-Channel Differential
Inputs (MAX1113)
Successive-approximation conversions are performed
using either the internal clock or an external serial-inter-
face clock. The full-scale analog input range is deter-
mine d b y the 4.096V inte rna l re fe re nc e , or b y a n
♦ Internal Track/Hold; 50kHz Sampling Rate
♦ Internal 4.096V Reference
♦ SPI/QSPI/MICROWIRE-Compatible Serial Interface
♦ Software-Configurable Unipolar or Bipolar Inputs
externally applied reference ranging from 1V to V
.
DD
The 4-wire serial interface is compatible with the SPI™,
QSPI™, and MICROWIRE™ serial-interface standards.
A serial-strobe output provides the end-of-conversion
signal for interrupt-driven processors.
♦ Total Unadjusted Error: ±1LSB (max)
±0.3LSB (typ)
The MAX1112/MAX1113 ha ve a s oftwa re -p rog ra m-
mable, 2µA automatic power-down mode to minimize
power consumption. Using power-down, the supply
current is reduced to 13µA at 1ksps, and only 82µA at
10ksps. Power-down can also be controlled using the
SHDN input pin. Accessing the serial interface automat-
ically powers up the device.
Ord e rin g In fo rm a t io n
PART
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
20 Plastic DIP
20 SSOP
MAX1112CPP
MAX1112CAP
MAX1112C/D
Dice*
*Dice are specified at T = +25°C, DC parameters only.
A
The MAX1112 is available in 20-pin SSOP and DIP
packages. The MAX1113 is available in small 16-pin
QSOP and DIP packages.
Ordering Information continued at end of data sheet.
Fu n c t io n a l Dia g ra m
________________________Ap p lic a t io n s
Portable Data Logging
CS
SCLK
INPUT
SHIFT
REGISTER
INT
CLOCK
Hand-Held Measurement Devices
Medical Instruments
DIN
CONTROL
LOGIC
SHDN
System Diagnostics
CH0
CH1
CH2
OUTPUT
SHIFT
DOUT
Solar-Powered Remote Systems
REGISTER
SSTRB
ANALOG
INPUT
MUX
CH3
T/H
4–20mA-Powered Remote
Data-Acquisition Systems
CH4*
CH5*
CH6*
CH7*
CLOCK
IN
8-BIT
SAR ADC
OUT
REF
V
DD
COM
DGND
AGND
Pin Configurations appear at end of data sheet.
+4.096V
REFERENCE
REFOUT
MAX1112
MAX1113
REFIN
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
*MAX1112 ONLY
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
+5 V, Lo w -P o w e r, Mu lt i-Ch a n n e l,
S e ria l 8 -Bit ADCs
ABSOLUTE MAXIMUM RATINGS
V
to AGND..............................................................-0.3V to 6V
20 Plastic DIP (derate 11.11mW/°C above +70°C) ......889mW
20 SSOP (derate 8.00mW/°C above +70°C) ................640mW
20 CERDIP (derate 11.11mW/°C above +70°C) ..........889mW
Operating Temperature Ranges
DD
AGND to DGND.......................................................-0.3V to 0.3V
CH0–CH7, COM, REFIN,
REFOUT to AGND ...................................-0.3V to (V + 0.3V)
DD
Digital Inputs to DGND ...............................................-0.3V to 6V
MAX1112C_P/MAX1113C_E................................0°C to +70°C
MAX1112E_P/MAX1113E_E .............................-40°C to +85°C
MAX1112MJP/MAX1113MJE..........................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Digital Outputs to DGND............................-0.3V to (V + 0.3V)
DD
Continuous Power Dissipation (T = +70°C)
A
16 Plastic DIP (derate 10.53mW/°C above +70°C) ......842mW
16 QSOP (derate 8.30mW/°C above +70°C)................667mW
16 CERDIP (derate 10.00mW/°C above +70°C) ..........800mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +4.5V to +5.5V; unipolar input mode; COM = 0V; f
= 500kHz, external clock (50% duty cycle); 10 clocks/conversion
DD
SCLK
cycle (50ksps); 1µF capacitor at REFOUT; T = T
to T ; unless otherwise noted.)
MAX
A
MIN
2/MAX13
PARAMETER
DC ACCURACY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
8
Bits
LSB
Relative Accuracy (Note 1)
Differential Nonlinearity
Offset Error
INL
±0.1
±0.3
±0.5
±1
DNL
No missing codes over temperature
LSB
±1
LSB
Gain Error (Note 2)
Gain Temperature Coefficient
Total Unadjusted Error
Internal or external reference
External reference, 4.096V
MAX111_C/E
±1
LSB
±0.8
±0.3
ppm/°C
LSB
TUE
±1
Channel-to-Channel
Offset Matching
±0.1
LSB
DYNAMIC SPECIFICATIONS (10.034kHz sine-wave input, 4.096Vp-p, 50ksps, 500kHz external clock)
Signal-to-Noise
SINAD
49
dB
dB
and Distortion Ratio
Total Harmonic Distortion
THD
-70
(up to the 5th harmonic)
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
Small-Signal Bandwidth
SFDR
68
-75
1.5
800
dB
dB
V
= 4.096Vp-p, 25kHz (Note 3)
CH_
-3dB rolloff
MHz
kHz
Full-Power Bandwidth
2
_______________________________________________________________________________________
+5 V, Lo w -P o w e r, Mu lt i-Ch a n n e l,
S e ria l 8 -Bit ADCs
2/MAX13
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +4.5V to +5.5V; unipolar input mode; COM = 0V; f
= 500kHz, external clock (50% duty cycle); 10 clocks/conversion
SCLK
cycle (50ksps); 1µF capacitor at REFOUT; T = T
to T ; unless otherwise noted.)
MAX
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONVERSION RATE
Internal clock
25
55
Conversion Time (Note 4)
t
µs
CONV
External clock, 500kHz, 10 clocks/conversion
External clock, 2MHz
20
1
Track/Hold Acquisition Time
Aperture Delay
t
µs
ns
ACQ
10
Aperture Jitter
<50
400
ps
Internal Clock Frequency
kHz
kHz
MHz
(Note 5)
50
0
500
2
External Clock-Frequency Range
Used for data transfer only
ANALOG INPUT
Unipolar input, COM = 0V
V
REFIN
Input Voltage Range, Single-
Ended and Differential (Note 6)
V
COM ±
/ 2
Bipolar input, COM = V
/ 2
REFIN
V
REFIN
Multiplexer Leakage Current
Input Capacitance
On/off leakage current, V
= 0V or V
±0.01
18
±1
µA
pF
CH_
DD
INTERNAL REFERENCE
REFOUT Voltage
3.936
4.096
6
4.256
V
mA
REFOUT Short-Circuit Current
REFOUT Temperature Coefficient
Load Regulation (Note 7)
Capacitive Bypass at REFOUT
EXTERNAL REFERENCE AT REFIN
±50
4.5
ppm/°C
mV
0mA to 0.5mA output load
1
1
µF
V
DD
+
Input Voltage Range
V
50mV
Input Current
(Note 8)
1
20
µA
POWER REQUIREMENTS
Supply Voltage
V
DD
4.5
5.5
V
Operating mode
Reference disabled
Software
135
95
2
250
Full-scale input
= 10pF
C
LOAD
µA
Supply Current
I
DD
Power-down
3.2
10
±4
SHDN at DGND
Power-Supply Rejection
(Note 9)
V
= 4.5V to 5.5V; external reference,
DD
PSR
±0.4
mV
4.096V; full-scale input
_______________________________________________________________________________________
3
+5 V, Lo w -P o w e r, Mu lt i-Ch a n n e l,
S e ria l 8 -Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +4.5V to +5.5V; unipolar input mode; COM = 0V; f
= 500kHz, external clock (50% duty cycle); 10 clocks/conversion
SCLK
cycle (50ksps); 1µF capacitor at REFOUT; T = T
to T ; unless otherwise noted.)
MAX
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS: DIN, SCLK, CS
DIN, SCLK, CS Input High Voltage
DIN, SCLK, CS Input Low Voltage
DIN, SCLK, CS Input Hysteresis
DIN, SCLK, CS Input Leakage
DIN, SCLK, CS Input Capacitance
SHDN INPUT
V
3
V
V
IH
V
IL
0.8
V
HYST
0.2
V
I
IN
Digital inputs = 0V or V
±1
15
µA
pF
DD
C
(Note 5)
IN
V
V
- 0.4
V
V
SHDN Input High Voltage
SHDN Input Mid-Voltage
SH
DD
V
SM
1.1
V
DD
- 1.1
V
FLT
V
DD
/ 2
V
SHDN Voltage, Floating
SHDN = open
2/MAX13
V
SL
0.4
±4
V
SHDN Input Low Voltage
µA
SHDN Input Current
SHDN = 0V or V
DD
SHDN Maximum Allowed Leakage
for Mid-Input
±100
nA
V
SHDN = open
DIGITAL OUTPUTS: DOUT, SSTRB
I
= 5mA
0.4
0.8
SINK
Output Low Voltage
V
OL
I
= 16mA
SINK
Output High Voltage
V
OH
I
= 0.5mA
V - 0.5
DD
V
SOURCE
Three-State Leakage Current
Three-State Output Capacitance
I
±0.01
±10
15
µA
pF
CS = V
L
DD
C
CS = V (Note 5)
OUT
DD
4
_______________________________________________________________________________________
+5 V, Lo w -P o w e r, Mu lt i-Ch a n n e l,
S e ria l 8 -Bit ADCs
2/MAX13
TIMING CHARACTERISTICS (Figures 8 and 9)
(V = +4.5V to +5.5V, T = T
to T , unless otherwise noted.)
MAX
DD
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
1
TYP
MAX
UNITS
µs
Track/Hold Acquisition Time
DIN to SCLK Setup
t
ACQ
t
100
0
ns
DS
DIN to SCLK Hold
t
ns
DH
MAX111_C/E
MAX111_M
= 100pF
20
20
200
240
240
240
Figure 1,
= 100pF
SCLK Fall to Output Data Valid
t
ns
DO
C
LOAD
t
Figure 1, C
Figure 2, C
ns
ns
ns
ns
ns
ns
ns
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
DV
LOAD
LOAD
t
= 100pF
TR
t
100
0
CSS
CSH
t
t
200
200
CH
t
CL
t
C
= 100pF
LOAD
240
240
SSTRB
Figure 1, external clock mode only,
= 100pF
CS Fall to SSTRB Output Enable
(Note 5)
t
ns
ns
ns
SDV
C
LOAD
Figure 2, external clock mode only,
= 100pF
CS Rise to SSTRB Output
Disable (Note 5)
t
240
STR
C
LOAD
SSTRB Rise to SCLK Rise
(Note 5)
t
Figure 11, internal clock mode only
0
SCK
External reference
20
24
µs
Wakeup Time
t
WAKE
Internal reference (Note 10)
ms
Note 1: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
Note 2: = 4.096V, offset nulled.
V
REFIN
Note 3: On-channel grounded; sine wave applied to all off-channels.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5: Guaranteed by design. Not subject to production testing.
Note 6: Common-mode range for the analog inputs is from AGND to V
.
DD
Note 7: External load should not change during the conversion for specified accuracy.
Note 8: External reference at 4.096V, full-scale input, 500kHz external clock.
Note 9: Measured as | V (4.5V) - V (5.5V) |.
FS
FS
Note 10: 1µF at REFOUT; internal reference settling to 0.5LSB.
_______________________________________________________________________________________
5
+5 V, Lo w -P o w e r, Mu lt i-Ch a n n e l,
S e ria l 8 -Bit ADCs
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = +5.0V; f
= 500kHz; external clock (50% duty cycle); R = ∞; T = +25°C, unless otherwise noted.)
L
A
DD
SCLK
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
DIFFERENTIAL NONLINEARITY
vs. CODE
SUPPLY CURRENT vs. TEMPERATURE
180
10
8
0.3
0.2
0.1
0
OUTPUT CODE = FULL SCALE
SHDN = DGND
C
= 10pF
LOAD
160
140
120
100
V
= 5.5V
= 4.5V
DD
6
4
V
DD
-0.1
-0.2
-0.3
2
0
-60
-20
20
60
100
140
-60
-20
20
60
100
140
0
64
128
192
256
2/MAX13
TEMPERATURE (°C)
TEMPERATURE (°C)
DIGITAL CODE
INTEGRAL NONLINEARITY
vs. CODE
OFFSET ERROR vs. TEMPERATURE
FFT PLOT
0.6
0.5
0.4
0.3
0.2
0.1
0
0.20
0.15
0.10
0.05
0
20
0
f
= 10.034kHz, 4Vp-p
= 50ksps
CH_
f
SAMPLE
-20
-40
-60
-80
-100
-0.05
-0.10
-0.15
-0.20
100
-60
-20
20
60
140
0
64
128
192
256
0
5
10
15
20
25
TEMPERATURE (°C)
DIGITAL CODE
FREQUENCY (kHz)
6
_______________________________________________________________________________________
+5 V, Lo w -P o w e r, Mu lt i-Ch a n n e l,
S e ria l 8 -Bit ADCs
2/MAX13
P in De s c rip t io n
PIN
NAME
FUNCTION
MAX1112
MAX1113
1–4
5–8
1–4
—
CH0–CH3
CH4–CH7
Sampling Analog Inputs
Sampling Analog Inputs
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode.
Must be stable to ±0.5LSB.
9
5
6
7
COM
SHDN
REFIN
Three-Level Shutdown Input. Normally floats. Pulling SHDN low shuts the MAX1112/
MAX1113 down to 10µA (max) supply current; otherwise, the devices are fully opera-
tional. Pulling SHDN high shuts down the internal reference.
10
11
Reference Voltage Input for Analog-to-Digital Conversion. Connect to REFOUT to use
the internal reference.
12
13
14
8
9
REFOUT
AGND
Internal Reference Generator Output. Bypass with a 1µF capacitor to AGND.
Analog Ground
Digital Ground
10
DGND
Serial-Data Output. Data is clocked out on SCLK’s falling edge. High impedance when
CS is high.
15
11
12
DOUT
SSTRB
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1112/
MAX1113 begin the A/D conversion and goes high when the conversion is complete.
In external clock mode, SSTRB pulses high for two clock periods before the MSB is
shifted out. High impedance when CS is high (external clock mode only).
16
17
18
13
14
DIN
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is
high, DOUT is high impedance.
CS
Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode,
SCLK also sets the conversion speed (duty cycle must be 45% to 55%).
19
20
15
16
SCLK
V
DD
Positive Supply Voltage, +4.5V to +5.5V
+5V
+5V
3k
C
3k
C
DOUT
DOUT
DOUT
DOUT
3k
3k
C
LOAD
C
LOAD
LOAD
LOAD
DGND
DGND
b) High-Z to V and V to V
OL
DGND
DGND
a) High-Z to V and V to V
OH
OH
OL
OL
OH
a) V to High-Z
b) V to High-Z
OL
OH
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
_______________________________________________________________________________________
7
+5 V, Lo w -P o w e r, Mu lt i-Ch a n n e l,
S e ria l 8 -Bit ADCs
acquisition interval spans two SCLK cycles and ends
_______________De t a ile d De s c rip t io n
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
The MAX1112/MAX1113 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to an 8-bit digital output. A flexible seri-
al interface provides easy interface to microprocessors
(µPs). Figure 3 shows the Typical Operating Circuit.
on C
as a sample of the signal at IN+.
HOLD
The conversion interval begins with the input multiplex-
er switching C from the positive input (IN+) to the
HOLD
negative input (IN-). In single-ended mode, IN- is sim-
ply COM. This unbalances node ZERO at the input of
the comparator. The capacitive DAC adjusts during the
re ma ind e r of the c onve rs ion c yc le to re s tore nod e
ZERO to 0V within the limits of 8-bit resolution. This
action is equivalent to transferring a charge of 18pF x
P s e u d o -Diffe re n t ia l In p u t
The sampling architecture of the ADC’s analog com-
parator is illustrated in Figure 4, the equivalent input cir-
cuit. In single-ended mode, IN+ is internally switched to
the selected input channel, CH_, and IN- is switched to
COM. In differential mode, IN+ and IN- are selected
from the following p a irs : CH0/CH1, CH2/CH3,
CH4/CH5, a nd CH6/CH7. Config ure the MAX1112
channels with Table 1 and the MAX1113 channels with
Table 2.
(V
IN+
- V ) from C
to the binary-weighted capac-
IN-
HOLD
itive DAC, which in turn forms a digital representation of
the analog input signal.
Tra c k /Ho ld
The T/H enters its tracking mode on the falling clock
edge after the sixth bit of the 8-bit control byte has
been shifted in. It enters its hold mode on the falling
clock edge after the eighth bit of the control byte has
been shifted in. If the converter is set up for single-
ended inputs, IN- is connected to COM, and the con-
verter samples the “+” input; if it is set up for differential
inputs, IN- connects to the “-” input, and the difference
(IN+ - IN-) is sampled. At the end of the conversion, the
2/MAX13
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
b le within ± 0.5LSB (± 0.1LSB for b e s t re s ults ) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- (the selected
analog input) to AGND if necessary.
During the acquisition interval, the channel selected as
p os itive inp ut c onne c ts b a c k to IN+ , a nd C
charges to the input signal.
HOLD
the positive input (IN+) charges capacitor C
. The
HOLD
+5V
CAPACITIVE DAC
REFIN
V
DD
V
CH0
CH7
DD
0.1µF
1µF
COMPARATOR
ANALOG
INPUTS
INPUT
MUX
C
HOLD
AGND
DGND
COM
ZERO
–
+
CH0
CH1
18pF
CPU
CH2
6.5k
IN
MAX1112
MAX1113
R
CH3
C
SWITCH
HOLD
CH4*
CH5*
CH6*
CH7*
COM
TRACK
I/O
CS
REFOUT
REFIN
AT THE SAMPLING INSTANT,
SCLK
SCK (SK)
MOSI (SO)
MISO (SI)
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
DIN
T/H
SWITCH
1µF
DOUT
SSTRB
SHDN
V
SS
SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4*/CH5*, CH6*/CH7*.
*MAX1112 ONLY
Figure 3. Typical Operating Circuit
Figure 4. Equivalent Input Circuit
8
_______________________________________________________________________________________
+5 V, Lo w -P o w e r, Mu lt i-Ch a n n e l,
S e ria l 8 -Bit ADCs
2/MAX13
Table 1a. MAX1112 Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
+
–
–
–
–
–
–
–
–
+
+
+
+
+
+
+
Table 1b. MAX1112 Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+
–
+
–
+
–
+
–
–
–
+
–
+
–
+
+
Table 2a. MAX1113 Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
COM
0
1
0
1
0
0
1
1
X
X
X
X
+
–
–
–
–
+
+
+
Table 2b. MAX1113 Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
0
0
1
1
0
1
0
1
X
X
X
X
+
–
+
–
–
–
+
+
_______________________________________________________________________________________
9
+5 V, Lo w -P o w e r, Mu lt i-Ch a n n e l,
S e ria l 8 -Bit ADCs
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
age. However, for accurate conversions near full scale,
the inputs must not exceed V by more than 50mV or
DD
be lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over 2mA.
t
, is the minimum time needed for the signal to be
ACQ
acquired. It is calculated by:
The MAX1112/MAX1113 can be configured for differen-
tial or single-ended inputs with bits 2 and 3 of the con-
trol byte (Table 3). In single-ended mode, analog inputs
are internally referenced to COM with a full-scale input
t
= 6 x (R + R ) x 18pF
ACQ
S
IN
where R = 6.5kΩ, R = the source impedance of the
IN
S
input signal, and t
is never less than 1µs. Note that
ACQ
source impedances below 2.4kΩ do not significantly
range from COM to V
+ COM. For bipolar opera-
REFIN
affect the AC performance of the ADC.
tion, set COM to V
/ 2.
REFIN
In differential mode, choosing unipolar mode sets the
differential input range at 0V to V . In unipolar
mode, the output code is invalid (code zero) when a
negative differential input voltage is applied. Bipolar
In p u t Ba n d w id t h
The ADC’s input tracking circuitry has a 1.5MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
us ing und e rs a mp ling te c hniq ue s . To a void hig h-
frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
REFIN
mode sets the differential input range to ±V
/ 2.
REFIN
Note that in this mode, the common-mode input range
includes both supply rails. Refer to Table 4 for input
voltage ranges.
2/MAX13
Qu ic k Lo o k
To quickly evaluate the MAX1112/MAX1113’s analog
p e rforma nc e , us e the c irc uit of Fig ure 5. The
MAX1112/MAX1113 require a control byte to be written
to DIN before each conversion. Tying DIN to +5V feeds
An a lo g In p u t s
Internal protection diodes, which clamp the analog
input to V and AGND, allow the channel input pins to
swing from (AGND - 0.3V) to (V + 0.3V) without dam-
DD
DD
Table 3. Control-Byte Format
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
START
SEL2
SEL1
SEL0
UNI/BIP
SGL/DIF
PD1
PD0
BIT
NAME
DESCRIPTION
7 (MSB)
START
The first logic “1” bit after CS goes low defines the beginning of the control byte.
Select which of the input channels are to be used for the conversion (Tables 1 and 2).
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode (Table 4).
6
5
4
SEL2
SEL1
SEL0
3
UNI/BIP
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage differ-
ence between two channels is measured. See Tables 1 and 2.
2
SGL/DIF
1 = fully operational, 0 = power-down.
Selects fully operational or power-down mode.
1
PD1
PD0
1 = external clock mode, 0 = internal clock mode.
Selects external or internal clock mode.
0 (LSB)
10 ______________________________________________________________________________________
+5 V, Lo w -P o w e r, Mu lt i-Ch a n n e l,
S e ria l 8 -Bit ADCs
2/MAX13
Table 4. Full-Scale and Zero-Scale Voltages
UNIPOLAR MODE
Full Scale Zero Scale
+ COM COM
BIPOLAR MODE
Positive
Full Scale
Zero
Scale
Negative
Full Scale
+V
/ 2
-V
REFIN
/ 2
REFIN
V
REFIN
COM
+ COM
+ COM
in c ontrol b yte s of $FF (he x), whic h trig g e r s ing le -
ended, unipolar conversions on CH7 (MAX1112) or
CH3 (MAX1113) in external clock mode without power-
ing down between conversions. In external clock mode,
the SSTRB output pulses high for two clock periods
before the most significant bit (MSB) of the 8-bit con-
version result is shifted out of DOUT. Varying the ana-
log input alters the output code. A total of 10 clock
cycles is required per conversion. All transitions of the
SSTRB a nd DOUT outp uts oc c ur on SCLK’s fa lling
edge.
from DIN into the MAX1112/MAX1113’s internal shift reg-
ister. After CS falls, the first arriving logic “1” bit at DIN
defines the MSB of the control byte. Until this first start bit
arrives, any number of logic “0” bits can be clocked into
DIN with no effect. Table 3 shows the control-byte format.
The MAX1112/MAX1113 a re c omp a tib le with
MICROWIRE, SPI, and QSPI devices. For SPI, select the
correct clock polarity and sampling edge in the SPI con-
trol registers: set CPOL = 0 and CPHA = 0. MICROWIRE,
SPI, and QSPI all transmit a byte and receive a byte at the
same time. Using the Typical Operating Circuit (Figure 3),
the simplest software interface requires three 8-bit trans-
fers to perform a conversion (one 8-bit transfer to config-
ure the ADC, and two more 8-bit transfers to clock out the
Ho w t o S t a rt a Co n ve rs io n
A conversion is started by clocking a control byte into
DIN. With CS low, each rising edge on SCLK clocks a bit
V
DD
+5V
OSCILLOSCOPE
0.1µF
1µF
DGND
SCLK
AGND
MAX1112
MAX1113
CH7 (CH3)
SSTRB
DOUT*
0V TO
+4.096V
ANALOG
INPUT
CS
0.01µF
SCLK
500kHz
OSCILLATOR
CH3
CH4
COM
CH1
CH2
+5V
DIN
SSTRB
DOUT
REFOUT
REFIN
SHDN
N.C.
C1
1µF
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FF (HEX)
( ) ARE FOR THE MAX1113.
Figure 5. Quick-Look Circuit
______________________________________________________________________________________ 11
+5 V, Lo w -P o w e r, Mu lt i-Ch a n n e l,
S e ria l 8 -Bit ADCs
8-bit conversion result). Figure 6 shows the MAX1112/
MAX1113 common serial-interface connections.
I/O
SCK
CS
Simple Software Interface
SCLK
DOUT
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 50kHz to 500kHz.
MISO
+5V
MAX1112
MAX1113
1) Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.
SS
a) SPI
CS
SCK
CS
2) Use a general-purpose I/O line on the CPU to pull
CS low.
SCLK
DOUT
MISO
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
+5V
MAX1112
MAX1113
4) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB2.
SS
2/MAX13
5) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB3.
b) QSPI
I/O
SK
SI
CS
6) Pull CS high.
SCLK
DOUT
Figure 7 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion padded
with two leading zeros and six trailing zeros. The total
c onve rs ion time is a func tion of the s e ria l-c loc k
frequency and the amount of idle time between 8-bit
transfers. Make sure that the total conversion time does
not exceed 1ms, to avoid excessive T/H droop.
MAX1112
MAX1113
c) MICROWIRE
Figure 6. Common Serial-Interface Connections to the
MAX1112/MAX1113
CS
t
ACQ
1
4
8
12
16
20
24
SCLK
UNI/
BIP
SGL/
DIF
SEL2 SEL1 SEL0
PD1 PD0
DIN
START
SSTRB
RB2
B5
RB3
FILLED WITH ZEROS
RB1
DOUT
B7
B6
B4
B3
B2
B1
B0
ACQUISITION
CONVERSION
A/D STATE
IDLE
4µs
IDLE
(f
SCLK
= 500kHz)
Figure 7. Single-Conversion Timing, External Clock Mode, 24 Clocks
12 ______________________________________________________________________________________
+5 V, Lo w -P o w e r, Mu lt i-Ch a n n e l,
S e ria l 8 -Bit ADCs
2/MAX13
Digital Output
In unipolar input mode, the output is straight binary
(Figure 15). For bipolar inputs, the output is two’s-com-
plement (Figure 16). Data is clocked out at SCLK’s
falling edge in MSB-first format.
conversion steps. SSTRB pulses high for two clock
periods after the last bit of the control byte. Successive-
approximation bit decisions are made and appear at
DOUT on each of the next eight SCLK falling edges
(Figure 7). After the eight data bits are clocked out,
s ub s e q ue nt c loc k p uls e s c loc k out ze ros from the
DOUT pin.
Clo c k Mo d e s
The MAX1112/MAX1113 can use either an external ser-
ial clock or the internal clock to perform the successive-
approximation conversion. In both clock modes, the
external clock shifts data in and out of the devices. Bit
PD0 of the c ontrol b yte p rog ra ms the c loc k mod e .
Figures 8–11 show the timing characteristics common
to both modes.
SSTRB a nd DOUT g o into a hig h-imp e d a nc e s ta te
when CS goes high; after the next CS falling edge,
SSTRB outputs a logic low. Figure 9 shows the SSTRB
timing in external clock mode.
The conversion must complete in 1ms, or droop on the
sample-and-hold capacitors may degrade conversion
results. Use internal clock mode if the serial-clock fre-
quency is less than 50kHz, or if serial-clock interruptions
could cause the conversion interval to exceed 1ms.
External Clock
In external clock mode, the external clock not only
shifts data in and out, it also drives the analog-to-digital
CS
• • •
t
t
CH
t
CSH
CSS
t
CL
SCLK
• • •
t
DS
t
DH
DIN
• • •
t
DO
t
DV
t
DO
t
TR
DOUT
• • •
Figure 8. Detailed Serial-Interface Timing
CS
• • •
• • •
t
t
STR
SDV
• • •
• • •
SSTRB
t
SSTRB
t
SSTRB
SCLK
• • • •
• • • •
PD0 CLOCKED IN
Figure 9. External Clock Mode SSTRB Detailed Timing
______________________________________________________________________________________ 13
+5 V, Lo w -P o w e r, Mu lt i-Ch a n n e l,
S e ria l 8 -Bit ADCs
CS
1
4
8
15
2
3
5
6
7
9
10
11
12
16
17
18
SCLK
UNI/ SGL/
BIP DIF
SEL2 SEL1 SEL0
PD1 PD0
DIN
START
SSTRB
t
CONV
FILLED WITH
ZEROS
DOUT
B7
B6
B1
B0
CONVERSION
25µs TYP
A/D STATE
IDLE
IDLE
t
ACQ
4µs (f
= 500kHz)
SCLK
X
Figure 10. Internal Clock Mode Timing
CS
t
t
CONV
CSS
t
t
SCK
CSH
SSTRB
t
SSTRB
SCLK
PD0 CLOCK IN
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
Figure 11. Internal Clock Mode SSTRB Detailed Timing
Internal Clock
remaining bits in MSB-first format (Figure 10). CS does
not need to be held low once a conversion is started.
Pulling CS high prevents data from being clocked into
the MAX1112/MAX1113 and three-states DOUT, but it
does not adversely affect an internal clock-mode con-
version already in progress. When internal clock mode
is selected, SSTRB does not go into a high-impedance
state when CS goes high.
Internal clock mode frees the µP from the burden of
running the SAR conversion clock. This allows the con-
version results to be read back at the processor’s con-
venience, at any clock rate up to 2MHz. SSTRB goes
low at the start of the conversion and then goes high
when the conversion is complete. SSTRB is low for
25µs (typically), during which time SCLK should remain
low for best noise performance.
Figure 11 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX1112/MAX1113 at clock rates up to 2MHz, pro-
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the second falling clock edge produces the
MSB of the c onve rs ion a t DOUT, followe d b y the
vided that the minimum acquisition time, t
above 1µs.
, is kept
ACQ
14 ______________________________________________________________________________________
+5 V, Lo w -P o w e r, Mu lt i-Ch a n n e l,
S e ria l 8 -Bit ADCs
2/MAX13
CS
1
8
10
1
8
10
1
8
10 1
SCLK
DIN
S
CONTROL BYTE 2
S
CONTROL BYTE 3
S
CONTROL BYTE 0
S
CONTROL BYTE 1
B7
B7
B0
B7
B0
DOUT
SSTRB
CONVERSION RESULT 0
CONVERSION RESULT 1
CONVERSION RESULT 2
Figure 12a. Continuous Conversions, External Clock Mode, 10 Clocks/Conversion Timing
CS
SCLK
S
CONTROL BYTE 0
S
CONTROL BYTE 1
DIN
DOUT
B7
B7
B0
CONVERSION RESULT 0
CONVERSION RESULT 1
Figure 12b. Continuous Conversions, External Clock Mode, 16 Clocks/Conversion Timing
Da t a Fra m in g
The falling edge of CS does not start a conversion. The
first logic high clocked into DIN is interpreted as a start
bit and defines the first bit of the control byte. A conver-
sion starts on the falling edge of SCLK, after the eighth
bit of the control byte (the PD0 bit) is clocked into DIN.
The start bit is defined as:
If CS is toggled before the current conversion is com-
plete, then the next high bit clocked into DIN is recog-
nize d a s a s ta rt b it; the c urre nt c onve rs ion is
terminated, and a new one is started.
The fa s te s t the MAX1112/MAX1113 c a n run is 10
clocks per conversion. Figure 12a shows the serial-
interface timing necessary to perform a conversion
every 10 SCLK cycles in external clock mode.
The first high bit clocked into DIN with CS low any
time the converter is idle, e.g., after V is applied.
DD
Many microcontrollers require that conversions occur in
multiples of eight SCLK clocks; 16 clocks per conver-
sion is typically the fastest that a microcontroller can
drive the MAX1112/MAX1113. Figure 12b shows the
serial-interface timing necessary to perform a conver-
sion every 16 SCLK cycles in external clock mode.
OR
The first high bit clocked into DIN after the MSB of a
conversion in progress is clocked onto the DOUT
pin.
______________________________________________________________________________________ 15
+5 V, Lo w -P o w e r, Mu lt i-Ch a n n e l,
S e ria l 8 -Bit ADCs
Hard-Wired Power-Down
__________Ap p lic a t io n s In fo rm a t io n
Pulling SHDN low places the converters in hard-wired
power-down. Unlike software power-down, the conver-
sion is not completed; it stops coincidentally with SHDN
being brought low. SHDN also controls the state of the
internal reference (Table 5). Letting SHDN float enables
the internal 4.096V voltage reference. When returning to
P o w e r-On Re s e t
When power is first applied, and if SHDN is not pulled
low, inte rna l p owe r-on re s e t c irc uitry a c tiva te s the
MAX1112/MAX1113 in internal clock mode. SSTRB is
high on power-up and, if CS is low, the first logical 1 on
DIN is interpreted as a start bit. Until a conversion takes
place, DOUT shifts out zeros. No conversions should
be performed until the reference voltage has stabilized
(se e the Wa ke up Time spe c ific a tions in the Timing
Characteristics).
normal operation with SHDN floating, there is a t
RC
is
delay of approximately 1MΩ x C
, where C
LOAD
LOAD
the capacitive loading on the SHDN pin. Pulling SHDN
high disables the internal reference, which saves power
when using an external reference.
P o w e r-Do w n
When operating at speeds below the maximum sam-
pling rate, the MAX1112/MAX1113’s automatic power-
down mode can save considerable power by placing
the converters in a low-current shutdown state between
conversions. Figure 13 shows the average supply cur-
rent as a function of the sampling rate.
Ex t e rn a l Re fe re n c e
An external reference between 1V and V
should be
DD
connected directly at the REFIN terminal. The DC input
impedance at REFIN is extremely high, consisting of
leakage current only (typically 10nA). During a conver-
sion, the reference must be able to deliver up to 20µA
average load current and have an output impedance of
1kΩ or less at the conversion clock frequency. If the
reference has higher output impedance or is noisy,
bypass it close to the REFIN pin with a 0.1µF capacitor.
2/MAX13
Select power-down with PD1 of the DIN control byte
with SHDN high or floating (Table 3). Pull SHDN low at
any time to shut down the converters completely. SHDN
overrides PD1 of the control byte. Figures 14a and 14b
illustrate the various power-down sequences in both
external and internal clock modes.
If an external reference is used with the MAX1112/
MAX1113, tie SHDN to V to disable the internal refer-
ence and decrease power consumption.
DD
Software Power-Down
Software power-down is activated using bit PD1 of the
control byte. When software power-down is asserted, the
ADCs continue to operate in the last specified clock
mode until the conversion is complete. The ADCs then
power down into a low quiescent-current state. In internal
clock mode, the interface remains active, and conversion
re s ults ma y b e c loc ke d out a fte r the MAX1112/
MAX1113 have entered a software power-down.
1000
C
= 60pF
LOAD
CODE = 10101010
The first logical 1 on DIN is interpreted as a start bit,
which powers up the MAX1112/MAX1113. If the DIN byte
contains PD1 = 1, then the chip remains powered up. If
PD1 = 0, power-down resumes after one conversion.
100
C
= 30pF
LOAD
CODE = 11111111
C
= 30pF
LOAD
CODE = 10101010
V
= V
= 5V
DD REFIN
C
AT DOUT + SSTRB
Table 5. Hard-Wired Power-Down and
Internal Reference State
LOAD
10
0
10
20
30
40
50
SAMPLING RATE (ksps)
DEVICE
MODE
INTERNAL
REFERENCE
SHDN
STATE
1
Floating
0
Enabled
Enabled
Disabled
Enabled
Disabled
Figure 13. Average Supply Current vs. Sampling Rate
Power-Down
16 ______________________________________________________________________________________
+5 V, Lo w -P o w e r, Mu lt i-Ch a n n e l,
S e ria l 8 -Bit ADCs
2/MAX13
CLOCK
MODE
INTERNAL
EXTERNAL
EXTERNAL
SHDN
SETS POWER-
DOWN MODE
SETS EXTERNAL
CLOCK MODE
SETS EXTERNAL
CLOCK MODE
S X X X X X 1 1
S X X X X X 0 1
S X X X X X 1 1
DIN
DOUT
MODE
DATA VALID
POWERED UP
DATA VALID
DATA
INVALID
POWERED
UP
POWER-
DOWN
POWER-
DOWN
POWERED UP
Figure 14a. Power-Down Modes, External Clock Timing Diagram
INTERNAL CLOCK MODE
S X X X X X 0 0
SETS POWER-DOWN MODE
SETS INTERNAL
CLOCK MODE
S X X X X X 1 0
S
DIN
DATA VALID
DATA VALID
DOUT
SSTRB
CONVERSION
CONVERSION
POWER-DOWN
POWERED UP
MODE
POWERED
UP
Figure 14b. Power-Down Modes, Internal Clock Timing Diagram
In t e rn a l Re fe re n c e
To use the MAX1112/MAX1113 with the internal refer-
ence, connect REFIN to REFOUT. The full-scale range
of the MAX1112/MAX1113 with the internal reference is
typically 4.096V with unipolar inputs, and ±2.048V with
b ip ola r inp uts . The inte rna l re fe re nc e s hould b e
bypassed to AGND with a 1µF capacitor placed as
close to the REFIN pin as possible.
Tra n s fe r Fu n c t io n
Table 4 shows the full-scale voltage ranges for unipolar
and bipolar modes. Figure 15 depicts the nominal,
unipolar I/O transfer function, and Figure 16 shows the
bipolar I/O transfer function when using a 4.096V refer-
ence. Code transitions occur at integer LSB values.
Outp ut c od ing is b ina ry, with 1LSB = 16mV
(4.096V/256) for unipolar operation and 1LSB = 16mV
[(4.096V/2 - -4.096V/2)/256] for bipolar operation.
______________________________________________________________________________________ 17
+5 V, Lo w -P o w e r, Mu lt i-Ch a n n e l,
S e ria l 8 -Bit ADCs
OUTPUT CODE
FULL-SCALE
SUPPLIES
TRANSITION
11111111
11111110
+5V
GND
11111101
FS = V
+ COM
REFIN
R* = 10Ω
V
REFIN
1LSB =
256
00000011
00000010
V
DD
AGND
DGND
+5V DGND
00000001
00000000
DIGITAL
CIRCUITRY
MAX1112
MAX1113
2/MAX13
0
1
2
3
FS
FS - 1LSB
(COM)
INPUT VOLTAGE (LSB)
* OPTIONAL
Figure 15. Unipolar Transfer Function
Figure 17. Power-Supply Grounding Connections
La yo u t , Gro u n d in g , a n d Byp a s s in g
For best performance, use printed circuit boards. Wire-
wra p b oa rd s a re not re c omme nd e d . Boa rd la yout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
OUTPUT CODE
V
REFIN
+FS =
+ COM
2
01111111
01111110
V
REFIN
COM =
-FS =
2
-V
REFIN
2
+ COM
00000010
00000001
00000000
Figure 17 shows the recommended system ground
connections. A single-point analog ground (star ground
point) should be established at AGND, separate from
the logic ground. Connect all other analog grounds and
DGND to the s ta r g round . No othe r d ig ita l s ys te m
g round s hould b e c onne c te d to this g round . The
ground return to the power supply for the star ground
should be low impedance and as short as possible for
noise-free operation.
V
REFIN
256
1LSB =
11111111
11111110
11111101
10000001
10000000
High-frequency noise in the V
power supply may
DD
affect the comparator in the ADC. Bypass the supply to
the star ground with 0.1µF and 1µF capacitors close to
COM
INPUT VOLTAGE (LSB)
-FS
1
2
the V
p in of the MAX1112/MAX1113. Minimize
DD
+FS - LSB
capacitor lead lengths for best supply-noise rejection. If
the +5V power supply is very noisy, a 10Ω resistor can
be connected to form a lowpass filter.
Figure 16. Bipolar Transfer Function
18 ______________________________________________________________________________________
+5 V, Lo w -P o w e r, Mu lt i-Ch a n n e l,
S e ria l 8 -Bit ADCs
2/MAX13
P in Co n fig u ra t io n s
TOP VIEW
CH0
CH1
CH2
CH3
V
1
2
20 DD
CH0
CH1
1
2
3
4
5
6
7
8
V
SCLK
CS
16
15
14
19
18
17
16
15
14
13
12
11
DD
SCLK
CS
3
CH2
DIN
4
MAX1112
CH3
MAX1113
CH4
CH5
CH6
CH7
13 DIN
SSTRB
DOUT
DGND
AGND
REFOUT
REFIN
5
COM
12 SSTRB
11 DOUT
6
SHDN
REFIN
REFOUT
7
10
9
DGND
AGND
8
COM
9
SHDN
10
DIP/QSOP
DIP/SSOP
Ord e rin g In fo rm a t io n (c o n t in u e d )
___________________Ch ip In fo rm a t io n
PART
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
0°C to +70°C
PIN-PACKAGE
20 Plastic DIP
20 SSOP
TRANSISTOR COUNT: 1996
MAX1112EPP
MAX1112EAP
MAX1112MJP
MAX1113CPE
MAX1113CEE
MAX1113EPE
MAX1113EEE
MAX1113MJE
SUBSTRATE CONNECTED TO DGND
20 CERDIP**
16 Plastic DIP
16 QSOP
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
16 Plastic DIP
16 QSOP
16 CERDIP**
**Contact factory for availability.
______________________________________________________________________________________ 19
+5 V, Lo w -P o w e r, Mu lt i-Ch a n n e l,
S e ria l 8 -Bit ADCs
________________________________________________________P a c k a g e In fo rm a t io n
2/MAX13
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