MAX1113EEE+ [MAXIM]
ADC, Successive Approximation, 8-Bit, 1 Func, 4 Channel, Serial Access, CMOS, PDSO16, ROHS COMPLIANT, QSOP-16;
| 型号： | MAX1113EEE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Successive Approximation, 8-Bit, 1 Func, 4 Channel, Serial Access, CMOS, PDSO16, ROHS COMPLIANT, QSOP-16 光电二极管 转换器 |
| 文件： | 总20页 (文件大小：378K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1231; Rev 2; 4/11
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
General Description
____________________________Features
The MAX1112/MAX1113 low-power, 8-bit, 8-channel
analog-to-digital converters (ADCs) feature an internal
track/hold, voltage reference, clock, and serial inter-
face. They operate from a single 4.5V to 5.5V supply
and consume only 135µA while sampling at rates up to
50ksps. The MAX1112’s 8 analog inputs and the
MAX1113’s 4 analog inputs are software-configurable,
allowing unipolar/bipolar and single-ended/differential
operation.
♦ 4.5V to 5.5V Single Supply
♦ Low Power: 135µA at 50ksps
13µA at 1ksps
♦ 8-Channel Single-Ended or 4-Channel Differential
Inputs (MAX1112)
♦ 4-Channel Single-Ended or 2-Channel Differential
Inputs (MAX1113)
Successive-approximation conversions are performed
using either the internal clock or an external serial-inter-
face clock. The full-scale analog input range is deter-
mined by the 4.096V internal reference, or by an
♦ Internal Track/Hold; 50kHz Sampling Rate
♦ Internal 4.096V Reference
♦ SPI/QSPI/MICROWIRE-Compatible Serial Interface
♦ Software-Configurable Unipolar or Bipolar Inputs
externally applied reference ranging from 1V to V
.
DD
The 4-wire serial interface is compatible with the SPI™,
QSPI™, and MICROWIRE™ serial-interface standards.
A serial-strobe output provides the end-of-conversion
signal for interrupt-driven processors.
♦ Total Unadjusted Error: 1 LSB (max)
0.3 LSB (typ)
The MAX1112/MAX1113 have a software-program-
mable, 2µA automatic power-down mode to minimize
power consumption. Using power-down, the supply
current is reduced to 13µA at 1ksps, and only 82µA at
10ksps. Power-down can also be controlled using the
SHDN input pin. Accessing the serial interface automat-
ically powers up the device.
Ordering Information continued at end of data sheet.
Functional Diagram
CS
SCLK
The MAX1112 is available in a 20-pin SSOP package.
The MAX1113 is available in a small 16-pin QSOP
package.
INPUT
INT
SHIFT
REGISTER
DIN
CLOCK
CONTROL
LOGIC
SHDN
________________________Applications
Portable Data Logging
CH0
CH1
CH2
OUTPUT
SHIFT
REGISTER
DOUT
SSTRB
ANALOG
INPUT
MUX
Hand-Held Measurement Devices
Medical Instruments
CH3
T/H
CH4*
CH5*
CH6*
CH7*
CLOCK
IN
8-BIT
SAR ADC
OUT
System Diagnostics
REF
V
DD
COM
Solar-Powered Remote Systems
DGND
AGND
+4.096V
REFERENCE
REFOUT
MAX1112
MAX1113
4mA to 20mA-Powered Remote
Data-Acquisition Systems
REFIN
*MAX1112 ONLY
Pin Configurations appear at end of data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
DD
V
to AGND............................................................-0.3V to +6V
Operating Temperature Ranges
AGND to DGND.....................................................-0.3V to +0.3V
CH0–CH7, COM, REFIN,
MAX1112CAP/MAX1113CEE...............................0°C to +70°C
MAX1112EAP/MAX1113EEE ............................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
REFOUT to AGND ...................................-0.3V to (V
+ 0.3V)
DD
Digital Inputs to DGND.............................................-0.3V to +6V
Digital Outputs to DGND............................-0.3V to (V + 0.3V)
DD
Continuous Power Dissipation (T = +70°C)
A
QSOP (derate 8.30mW/°C above +70°C).....................667mW
SSOP (derate 8.00mW/°C above +70°C) .....................640mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 4.5V to 5.5V; unipolar input mode; V
= 0V; f
= 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle
SCLK
DD
COM
(50ksps); 1µF capacitor at REFOUT; T = T
to T ; unless otherwise noted.)
A
MIN
MAX
PARAMETER
DC ACCURACY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
8
Bits
LSB
Relative Accuracy (Note 1)
Differential Nonlinearity
Offset Error
INL
0.1
0.3
0.5
1
DNL
No missing codes over temperature
LSB
1
LSB
Gain Error (Note 2)
Gain Temperature Coefficient
Total Unadjusted Error
Internal or external reference
External reference, 4.096V
1
LSB
0.8
0.3
ppm/°C
LSB
TUE
1
Channel-to-Channel
Offset Matching
0.1
LSB
DYNAMIC SPECIFICATIONS (10.034kHz sine-wave input, 4.096V , 50ksps, 500kHz external clock)
P-P
Signal-to-Noise
SINAD
49
dB
dB
and Distortion Ratio
Total Harmonic Distortion
THD
-70
(Up to the 5th Harmonic)
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
Small-Signal Bandwidth
SFDR
68
-75
1.5
800
dB
dB
V
= 4.096V , 25kHz (Note 3)
P-P
CH_
-3dB rolloff
MHz
kHz
Full-Power Bandwidth
2
_______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
= 4.5V to 5.5V; unipolar input mode; V
= 0V; f
= 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle
DD
COM
SCLK
(50ksps); 1µF capacitor at REFOUT; T = T
to T ; unless otherwise noted.)
A
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONVERSION RATE
Internal clock
25
55
Conversion Time (Note 4)
t
µs
CONV
External clock, 500kHz, 10 clocks/conversion
External clock, 2MHz
20
1
Track/Hold Acquisition Time
Aperture Delay
t
µs
ns
ACQ
10
Aperture Jitter
< 50
400
ps
Internal Clock Frequency
kHz
kHz
MHz
(Note 5)
50
0
500
2
External Clock-Frequency Range
Used for data transfer only
ANALOG INPUT
Unipolar input, V
= 0V
V
REFIN
COM
Input Voltage Range, Single-
Ended and Differential (Note 6)
V
COM
Bipolar input, V
= V
/2
COM
REFIN
V
/2
REFIN
Multiplexer Leakage Current
Input Capacitance
On/off leakage current, V
= 0V or V
0.01
18
1
µA
pF
CH_
DD
INTERNAL REFERENCE
REFOUT Voltage
3.936
4.096
6
4.256
V
mA
REFOUT Short-Circuit Current
REFOUT Temperature Coefficient
Load Regulation (Note 7)
Capacitive Bypass at REFOUT
EXTERNAL REFERENCE AT REFIN
50
ppm/°C
mV
0 to 0.5mA output load
4.5
1
1
µF
V
+
DD
50
Input Voltage Range
V
Input Current
(Note 8)
1
20
µA
POWER REQUIREMENTS
Supply Voltage
V
DD
4.5
5.5
V
Operating mode
Reference disabled
Software
135
95
2
250
Full-scale input
= 10pF
C
LOAD
µA
Supply Current
I
DD
Power-down
3.2
10
4
SHDN at DGND
Power-Supply Rejection
(Note 9)
V
DD
= 4.5V to 5.5V; external reference,
PSR
0.4
mV
4.096V; full-scale input
_______________________________________________________________________________________
3
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
= 4.5V to 5.5V; unipolar input mode; V
= 0V; f
= 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle
DD
COM
SCLK
(50ksps); 1µF capacitor at REFOUT; T = T
to T ; unless otherwise noted.)
A
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (DIN, SCLK, CS)
DIN, SCLK, CS Input High Voltage
DIN, SCLK, CS Input Low Voltage
DIN, SCLK, CS Input Hysteresis
DIN, SCLK, CS Input Leakage
DIN, SCLK, CS Input Capacitance
SHDN INPUT
V
3
V
V
IH
V
0.8
IL
V
0.2
V
HYST
I
IN
Digital inputs = 0V or V
(Note 5)
1
µA
pF
DD
C
15
IN
V
V
- 0.4
V
V
SHDN Input High Voltage
SH
DD
V
SM
1.1
V
DD
- 1.1
SHDN Input Mid-Voltage
V
V
= open
V /2
DD
V
SHDN Voltage, High Impedance
SHDN Input Low Voltage
FLT
SHDN
V
0.4
4
V
SL
µA
SHDN Input Current
SHDN = 0V or V
SHDN = open
DD
SHDN Maximum Allowed Leakage
for Mid-Input
100
nA
V
DIGITAL OUTPUTS (DOUT, SSTRB)
I
I
I
= 5mA
0.4
0.8
SINK
Output Low Voltage
V
OL
= 16mA
SINK
Output High Voltage
V
= 0.5mA
V - 0.5
DD
V
OH
SOURCE
Three-State Leakage Current
Three-State Output Capacitance
I
0.01
10
15
µA
pF
CS = V
CS = V
L
DD
DD
C
(Note 5)
OUT
4
_______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
TIMING CHARACTERISTICS (Figures 8 and 9)
(V
DD
= 4.5V to 5.5V, T = T
A
to T
, unless otherwise noted.)
MAX
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
1
TYP
MAX
UNITS
µs
Track/Hold Acquisition Time
DIN to SCLK Setup
t
ACQ
t
100
0
ns
DS
DH
DO
DIN to SCLK Hold
t
ns
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
t
Figure 1, C
Figure 1, C
Figure 2, C
= 100pF
= 100pF
= 100pF
20
200
240
240
ns
LOAD
LOAD
LOAD
t
ns
DV
t
TR
ns
t
100
0
ns
CSS
CSH
t
ns
t
200
200
ns
CH
t
CL
ns
t
C
LOAD
= 100pF
240
240
ns
SSTRB
Figure 1, external clock mode only,
= 100pF
CS Fall to SSTRB Output Enable
t
ns
ns
ns
SDV
C
LOAD
(Note 5)
Figure 2, external clock mode only,
= 100pF
CS Rise to SSTRB Output
Disable (Note 5)
t
240
STR
C
LOAD
SSTRB Rise to SCLK Rise
(Note 5)
t
Figure 11, internal clock mode only
0
SCK
External reference
20
24
µs
Wakeup Time
t
WAKE
Internal reference (Note 10)
ms
Note 1: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
Note 2: = 4.096V, offset nulled.
V
REFIN
Note 3: On-channel grounded; sine wave applied to all off-channels.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5: Guaranteed by design. Not subject to production testing.
Note 6: Common-mode range for the analog inputs is from AGND to V
.
DD
Note 7: External load should not change during the conversion for specified accuracy.
Note 8: External reference at 4.096V, full-scale input, 500kHz external clock.
Note 9: Measured as | V (4.5V) - V (5.5V) |.
FS
FS
Note 10: 1µF at REFOUT; internal reference settling to 0.5 LSB.
_______________________________________________________________________________________
5
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
__________________________________________Typical Operating Characteristics
(V
= 5.0V; f
= 500kHz; external clock (50% duty cycle); R = ∞; T = +25°C, unless otherwise noted.)
SCLK L
A
DD
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
DIFFERENTIAL NONLINEARITY
vs. CODE
SUPPLY CURRENT vs. TEMPERATURE
180
10
8
0.3
0.2
0.1
0
OUTPUT CODE = FULL SCALE
SHDN = DGND
C
= 10pF
LOAD
160
140
120
100
V
= 5.5V
= 4.5V
DD
6
4
V
DD
-0.1
-0.2
-0.3
2
0
-60
-20
20
60
100
140
-60
-20
20
60
100
140
0
64
128
192
256
TEMPERATURE (°C)
TEMPERATURE (°C)
DIGITAL CODE
INTEGRAL NONLINEARITY
vs. CODE
OFFSET ERROR vs. TEMPERATURE
FFT PLOT
0.6
0.5
0.4
0.3
0.2
0.1
0
0.20
0.15
0.10
0.05
0
20
0
f
f
= 10.034kHz, 4V
= 50ksps
CH_
SAMPLE
P-P
-20
-40
-60
-80
-100
-0.05
-0.10
-0.15
-0.20
100
-60
-20
20
60
140
0
64
128
192
256
0
5
10
15
20
25
TEMPERATURE (°C)
DIGITAL CODE
FREQUENCY (kHz)
6
_______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
Pin Description
PIN
NAME
FUNCTION
MAX1112
MAX1113
1–4
5–8
1–4
—
CH0–CH3
CH4–CH7
Sampling Analog Inputs
Sampling Analog Inputs
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode.
Must be stable to 0.5 LSB.
9
5
6
7
COM
SHDN
REFIN
Three-Level Shutdown Input. Normally high impedance. Pulling SHDN low shuts the
MAX1112/MAX1113 down to 10µA (max) supply current; otherwise, the devices are
fully operational. Pulling SHDN high shuts down the internal reference.
10
11
Reference Voltage Input for Analog-to-Digital Conversion. Connect to REFOUT to use
the internal reference.
12
13
14
8
9
REFOUT
AGND
Internal Reference Generator Output. Bypass with a 1µF capacitor to AGND.
Analog Ground
Digital Ground
10
DGND
Serial-Data Output. Data is clocked out on SCLK’s falling edge. High impedance when
CS is high.
15
11
12
DOUT
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1112/
MAX1113 begin the A/D conversion and goes high when the conversion is complete.
In external clock mode, SSTRB pulses high for two clock periods before the MSB is
shifted out. High impedance when CS is high (external clock mode only).
16
SSTRB
17
18
13
14
DIN
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is
high, DOUT is high impedance.
CS
Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode,
SCLK also sets the conversion speed (duty cycle must be 45% to 55%).
19
20
15
16
SCLK
Positive Supply Voltage, 4.5V to 5.5V. Bypass to AGND with 0.1µF and 1µF capacitor
V
DD
as close as possible to the device. Place the 0.1µF capacitor closer to V
.
P-P
+5V
+5V
3kΩ
3kΩ
DOUT
DOUT
DOUT
DOUT
3kΩ
3kΩ
C
C
LOAD
C
LOAD
C
LOAD
LOAD
DGND
DGND
b) High-Z to V and V to V
OL
DGND
DGND
a) High-Z to V and V to V
OH
OH
OL
OL
OH
a) V to High-Z
b) V to High-Z
OL
OH
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
_______________________________________________________________________________________
7
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
acquisition interval spans two SCLK cycles and ends
_______________Detailed Description
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
The MAX1112/MAX1113 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to an 8-bit digital output. A flexible seri-
al interface provides easy interface to microprocessors
(µPs). Figure 3 shows the Typical Operating Circuit.
on C
as a sample of the signal at IN+.
HOLD
The conversion interval begins with the input multiplex-
er switching C from the positive input (IN+) to the
HOLD
negative input (IN-). In single-ended mode, IN- is sim-
ply COM. This unbalances node ZERO at the input of
the comparator. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 8-bit resolution. This
action is equivalent to transferring a charge of 18pF x
Pseudo-Differential Input
The sampling architecture of the ADC’s analog com-
parator is illustrated in Figure 4, the equivalent input cir-
cuit. In single-ended mode, IN+ is internally switched to
the selected input channel, CH_, and IN- is switched to
COM. In differential mode, IN+ and IN- are selected
from the following pairs: CH0/CH1, CH2/CH3,
CH4/CH5, and CH6/CH7. Configure the MAX1112
channels with Table 1 and the MAX1113 channels with
Table 2.
(V
- V ) from C
to the binary-weighted capac-
IN+
IN-
HOLD
itive DAC, which in turn forms a digital representation of
the analog input signal.
Track/Hold
The T/H enters its tracking mode on the falling clock
edge after the sixth bit of the 8-bit control byte has
been shifted in. It enters its hold mode on the falling
clock edge after the eighth bit of the control byte has
been shifted in. If the converter is set up for single-
ended inputs, IN- is connected to COM, and the con-
verter samples the “+” input; if it is set up for differential
inputs, IN- connects to the “-” input, and the difference
(IN+ - IN-) is sampled. At the end of the conversion, the
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within 0.5 LSB ( 0.1 LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- (the selected
analog input) to AGND if necessary.
During the acquisition interval, the channel selected as
positive input connects back to IN+, and C
charges to the input signal.
HOLD
the positive input (IN+) charges capacitor C
. The
HOLD
+5V
CAPACITIVE DAC
REFIN
V
DD
V
CH0
CH7
DD
0.1μF
1μF
COMPARATOR
ANALOG
INPUTS
INPUT
MUX
C
HOLD
AGND
DGND
COM
ZERO
–
+
CH0
CH1
18pF
CPU
CH2
6.5kΩ
R
MAX1112
MAX1113
IN
CH3
C
SWITCH
HOLD
CH4*
CH5*
CH6*
CH7*
COM
TRACK
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
CS
AT THE SAMPLING INSTANT,
REFOUT
REFIN
SCLK
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
T/H
SWITCH
DIN
1μF
DOUT
SSTRB
SHDN
V
SS
SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4*/CH5*, CH6*/CH7*.
*MAX1112 ONLY
Figure 3. Typical Operating Circuit
Figure 4. Equivalent Input Circuit
8
_______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
Table 1a. MAX1112 Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
+
–
–
–
–
–
–
–
–
+
+
+
+
+
+
+
Table 1b. MAX1112 Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+
–
+
–
+
–
+
–
–
–
+
–
+
–
+
+
Table 2a. MAX1113 Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
COM
0
1
0
1
0
0
1
1
X
X
X
X
+
–
–
–
–
+
+
+
Table 2b. MAX1113 Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
0
0
1
1
0
1
0
1
X
X
X
X
+
–
+
–
–
–
+
+
_______________________________________________________________________________________
9
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
age. However, for accurate conversions near full scale,
the inputs must not exceed V by more than 50mV or
DD
be lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over 2mA.
t
, is the minimum time needed for the signal to be
ACQ
acquired. It is calculated by:
The MAX1112/MAX1113 can be configured for differen-
tial or single-ended inputs with bits 2 and 3 of the con-
trol byte (Table 3). In single-ended mode, analog inputs
are internally referenced to COM with a full-scale input
t
= 6 x (R + R ) x 18pF
ACQ
S
IN
where R = 6.5kΩ, R = the source impedance of the
IN
S
input signal, and t
is never less than 1µs. Note that
ACQ
source impedances below 2.4kΩ do not significantly
range from COM to V
+ COM. For bipolar opera-
REFIN
affect the AC performance of the ADC.
tion, set COM to V
/2.
REFIN
In differential mode, choosing unipolar mode sets the
differential input range at 0V to V . In unipolar
Input Bandwidth
The ADC’s input tracking circuitry has a 1.5MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-
frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
REFIN
mode, the output code is invalid (code zero) when a
negative differential input voltage is applied. Bipolar
mode sets the differential input range to
V
/2.
REFIN
Note that in this mode, the common-mode input range
includes both supply rails. See Table 4 for input voltage
ranges.
Quick Look
To quickly evaluate the MAX1112/MAX1113’s analog
performance, use the circuit of Figure 5. The
MAX1112/MAX1113 require a control byte to be written
to DIN before each conversion. Tying DIN to +5V feeds
Analog Inputs
Internal protection diodes, which clamp the analog
input to V
and AGND, allow the channel input pins to
DD
swing from (AGND - 0.3V) to (V
+ 0.3V) without dam-
DD
Table 3. Control-Byte Format
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
START
SEL2
SEL1
SEL0
UNI/BIP
SGL/DIF
PD1
PD0
BIT
NAME
DESCRIPTION
7 (MSB)
START
The first logic “1” bit after CS goes low defines the beginning of the control byte.
Select which of the input channels are to be used for the conversion (Tables 1 and 2).
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode (Table 4).
6
5
4
SEL2
SEL1
SEL0
3
UNI/BIP
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage differ-
ence between two channels is measured (Tables 1 and 2).
2
SGL/DIF
1 = fully operational, 0 = power-down.
Selects fully operational or power-down mode.
1
PD1
PD0
1 = external clock mode, 0 = internal clock mode.
Selects external or internal clock mode.
0 (LSB)
10 ______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
Table 4. Full-Scale and Zero-Scale Voltages
UNIPOLAR MODE
Full Scale Zero Scale
+ COM COM
BIPOLAR MODE
Positive
Full Scale
Zero
Scale
Negative
Full Scale
+V /2
REFIN
-V
REFIN
/2
V
REFIN
COM
+ COM
+ COM
in control bytes of $FF (hex), which trigger single-
ended, unipolar conversions on CH7 (MAX1112) or
CH3 (MAX1113) in external clock mode without power-
ing down between conversions. In external clock mode,
the SSTRB output pulses high for two clock periods
before the most significant bit (MSB) of the 8-bit con-
version result is shifted out of DOUT. Varying the ana-
log input alters the output code. A total of 10 clock
cycles is required per conversion. All transitions of the
SSTRB and DOUT outputs occur on SCLK’s falling
edge.
from DIN into the MAX1112/MAX1113’s internal shift reg-
ister. After CS falls, the first arriving logic “1” bit at DIN
defines the MSB of the control byte. Until this first start bit
arrives, any number of logic “0” bits can be clocked into
DIN with no effect. Table 3 shows the control-byte format.
The MAX1112/MAX1113 are compatible with
MICROWIRE, SPI, and QSPI devices. For SPI, select the
correct clock polarity and sampling edge in the SPI con-
trol registers: set CPOL = 0 and CPHA = 0. MICROWIRE,
SPI, and QSPI all transmit a byte and receive a byte at the
same time. Using the Typical Operating Circuit (Figure 3),
the simplest software interface requires three 8-bit trans-
fers to perform a conversion (one 8-bit transfer to config-
ure the ADC, and two more 8-bit transfers to clock out the
How to Start a Conversion
A conversion is started by clocking a control byte into
DIN. With CS low, each rising edge on SCLK clocks a bit
V
DD
+5V
OSCILLOSCOPE
0.1µF
1µF
DGND
SCLK
AGND
MAX1112
MAX1113
CH7 (CH3)
SSTRB
DOUT*
0V TO
+4.096V
ANALOG
INPUT
CS
0.01µF
SCLK
500kHz
OSCILLATOR
CH3
CH4
COM
CH1
CH2
+5V
DIN
SSTRB
DOUT
REFOUT
REFIN
SHDN
N.C.
C1
1µF
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FF (HEX)
( ) ARE FOR THE MAX1113.
Figure 5. Quick-Look Circuit
______________________________________________________________________________________ 11
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
8-bit conversion result). Figure 6 shows the MAX1112/
MAX1113 common serial-interface connections.
I/O
SCK
CS
Simple Software Interface
SCLK
DOUT
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 50kHz to 500kHz.
MISO
+5V
MAX1112
MAX1113
1) Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.
SS
a) SPI
CS
SCK
CS
2) Use a general-purpose I/O line on the CPU to pull
CS low.
SCLK
DOUT
MISO
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
+5V
MAX1112
MAX1113
4) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB2.
SS
5) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB3.
b) QSPI
I/O
SK
SI
CS
6) Pull CS high.
SCLK
DOUT
Figure 7 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion padded
with two leading zeros and six trailing zeros. The total
conversion time is a function of the serial-clock
frequency and the amount of idle time between 8-bit
transfers. Make sure that the total conversion time does
not exceed 1ms, to avoid excessive T/H droop.
MAX1112
MAX1113
c) MICROWIRE
Figure 6. Common Serial-Interface Connections to the
MAX1112/MAX1113
CS
t
ACQ
1
4
8
12
16
20
24
SCLK
UNI/
BIP
SGL/
DIF
SEL2 SEL1 SEL0
PD1 PD0
DIN
START
SSTRB
RB2
B5
RB3
FILLED WITH ZEROS
RB1
DOUT
B7
B6
B4
B3
B2
B1
B0
ACQUISITION
CONVERSION
A/D STATE
IDLE
4μs
IDLE
(f
= 500kHz)
SCLK
Figure 7. Single-Conversion Timing, External Clock Mode, 24 Clocks
12 ______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
Digital Output
In unipolar input mode, the output is straight binary
(Figure 15). For bipolar inputs, the output is two’s-com-
plement (Figure 16). Data is clocked out at SCLK’s
falling edge in MSB-first format.
conversion steps. SSTRB pulses high for two clock
periods after the last bit of the control byte. Successive-
approximation bit decisions are made and appear at
DOUT on each of the next eight SCLK falling edges
(Figure 7). After the eight data bits are clocked out,
subsequent clock pulses clock out zeros from the
DOUT pin.
Clock Modes
The MAX1112/MAX1113 can use either an external ser-
ial clock or the internal clock to perform the successive-
approximation conversion. In both clock modes, the
external clock shifts data in and out of the devices. Bit
PD0 of the control byte programs the clock mode.
Figures 8–11 show the timing characteristics common
to both modes.
SSTRB and DOUT go into a high-impedance state
when CS goes high; after the next CS falling edge,
SSTRB outputs a logic low. Figure 9 shows the SSTRB
timing in external clock mode.
The conversion must complete in 1ms, or droop on the
sample-and-hold capacitors can degrade conversion
results. Use internal clock mode if the serial-clock fre-
quency is less than 50kHz, or if serial-clock interruptions
could cause the conversion interval to exceed 1ms.
External Clock
In external clock mode, the external clock not only
shifts data in and out, it also drives the analog-to-digital
CS
• • •
• • •
t
t
t
CSH
CSS
CH
t
CL
SCLK
t
DS
t
DH
DIN
• • •
• • •
t
t
DV
t
t
TR
DO
DO
DOUT
Figure 8. Detailed Serial-Interface Timing
CS
• • •
• • •
t
t
STR
SDV
• • •
• • •
SSTRB
t
SSTRB
t
SSTRB
SCLK
• • • •
• • • •
PD0 CLOCKED IN
Figure 9. External Clock Mode SSTRB Detailed Timing
______________________________________________________________________________________ 13
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
CS
1
4
8
15
2
3
5
6
7
9
10
11
12
16
17
18
SCLK
UNI/ SGL/
SEL2 SEL1 SEL0
PD1 PD0
BIP
DIF
DIN
START
SSTRB
t
CONV
FILLED WITH
ZEROS
DOUT
B7
B6
B1
B0
CONVERSION
25µs TYP
A/D STATE
IDLE
IDLE
t
ACQ
4µs (f
= 500kHz)
SCLK
Figure 10. Internal Clock Mode Timing
CS
t
t
CONV
CSS
t
t
SCK
CSH
SSTRB
t
SSTRB
SCLK
PD0 CLOCK IN
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
Figure 11. Internal Clock Mode SSTRB Detailed Timing
Internal Clock
remaining bits in MSB-first format (Figure 10). CS does
not need to be held low once a conversion is started.
Pulling CS high prevents data from being clocked into
the MAX1112/MAX1113 and three-states DOUT, but it
does not adversely affect an internal clock-mode con-
version already in progress. When internal clock mode
is selected, SSTRB does not go into a high-impedance
state when CS goes high.
Internal clock mode frees the µP from the burden of
running the SAR conversion clock. This allows the con-
version results to be read back at the processor’s con-
venience, at any clock rate up to 2MHz. SSTRB goes
low at the start of the conversion and then goes high
when the conversion is complete. SSTRB is low for
25µs (typ), during which time SCLK should remain low
for best noise performance.
Figure 11 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX1112/MAX1113 at clock rates up to 2MHz, pro-
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the second falling clock edge produces the
MSB of the conversion at DOUT, followed by the
vided that the minimum acquisition time, t , is kept
ACQ
above 1µs.
14 ______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
CS
1
8
10
1
8
10
1
8
10 1
SCLK
DIN
S
CONTROL BYTE 2
S
CONTROL BYTE 3
S
CONTROL BYTE 0
S
CONTROL BYTE 1
B7
B7
B0
B7
B0
DOUT
SSTRB
CONVERSION RESULT 0
CONVERSION RESULT 1
CONVERSION RESULT 2
Figure 12a. Continuous Conversions, External Clock Mode, 10 Clocks/Conversion Timing
CS
SCLK
S
CONTROL BYTE 0
S
CONTROL BYTE 1
DIN
DOUT
B7
B7
B0
CONVERSION RESULT 0
CONVERSION RESULT 1
Figure 12b. Continuous Conversions, External Clock Mode, 16 Clocks/Conversion Timing
Data Framing
The falling edge of CS does not start a conversion. The
first logic high clocked into DIN is interpreted as a start
bit and defines the first bit of the control byte. A conver-
sion starts on the falling edge of SCLK, after the eighth
bit of the control byte (the PD0 bit) is clocked into DIN.
The start bit is defined as:
If CS is toggled before the current conversion is com-
plete, then the next high bit clocked into DIN is recog-
nized as a start bit; the current conversion is
terminated, and a new one is started.
The fastest the MAX1112/MAX1113 can run is 10
clocks per conversion. Figure 12a shows the serial-
interface timing necessary to perform a conversion
every 10 SCLK cycles in external clock mode.
The first high bit clocked into DIN with CS low any
time the converter is idle, e.g., after V
is applied.
DD
Many microcontrollers require that conversions occur in
multiples of eight SCLK clocks; 16 clocks per conver-
sion is typically the fastest that a microcontroller can
drive the MAX1112/MAX1113. Figure 12b shows the
serial-interface timing necessary to perform a conver-
sion every 16 SCLK cycles in external clock mode.
OR
The first high bit clocked into DIN after the MSB of a
conversion in progress is clocked onto the DOUT
pin.
______________________________________________________________________________________ 15
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
Hard-Wired Power-Down
__________Applications Information
Pulling SHDN low places the converters in hard-wired
power-down. Unlike software power-down, the conversion
is not completed; it stops coincidentally with SHDN being
brought low. SHDN also controls the state of the internal
reference (Table 5). Letting SHDN high impedance
enables the internal 4.096V voltage reference. When
returning to normal operation with SHDN high impedance,
Power-On Reset
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1112/MAX1113 in internal clock mode. SSTRB is
high on power-up and, if CS is low, the first logical 1 on
DIN is interpreted as a start bit. Until a conversion takes
place, DOUT shifts out zeros. No conversions should
be performed until the reference voltage has stabilized
(see the Wakeup Time specifications in the Timing
Characteristics).
there is a t
delay of approximately 1MΩ x C
,
LOAD
RC
where C
is the capacitive loading on the SHDN pin.
LOAD
Pulling SHDN high disables the internal reference, which
saves power when using an external reference.
Power-Down
When operating at speeds below the maximum sam-
pling rate, the MAX1112/MAX1113’s automatic power-
down mode can save considerable power by placing
the converters in a low-current shutdown state between
conversions. Figure 13 shows the average supply cur-
rent as a function of the sampling rate.
External Reference
An external reference between 1V and V
should be
DD
connected directly at the REFIN terminal. The DC input
impedance at REFIN is extremely high, consisting of
leakage current only (typically 10nA). During a conver-
sion, the reference must be able to deliver up to 20µA
average load current and have an output impedance of
1kΩ or less at the conversion clock frequency. If the
reference has higher output impedance or is noisy,
bypass it close to the REFIN pin with a 0.1µF capacitor.
Select power-down with PD1 of the DIN control byte
with SHDN high or high impedance (Table 3). Pull
SHDN low at any time to shut down the converters com-
pletely. SHDN overrides PD1 of the control byte.
Figures 14a and 14b illustrate the various power-down
sequences in both external and internal clock modes.
If an external reference is used with the MAX1112/
MAX1113, connect SHDN to V
to disable the internal
DD
reference and decrease power consumption.
Software Power-Down
Software power-down is activated using bit PD1 of the
control byte. When software power-down is asserted, the
ADCs continue to operate in the last specified clock
mode until the conversion is complete. The ADCs then
power down into a low quiescent-current state. In internal
clock mode, the interface remains active, and conversion
results can be clocked out after the MAX1112/
MAX1113 have entered a software power-down.
1000
C
= 60pF
LOAD
CODE = 10101010
The first logical 1 on DIN is interpreted as a start bit,
which powers up the MAX1112/MAX1113. If the DIN byte
contains PD1 = 1, then the chip remains powered up. If
PD1 = 0, power-down resumes after one conversion.
100
C
= 30pF
LOAD
CODE = 11111111
C
= 30pF
LOAD
CODE = 10101010
V
C
= V
= 5V
REFIN
DD
Table 5. Hard-Wired Power-Down and
Internal Reference State
AT DOUT + SSTRB
LOAD
10
0
10
20
30
40
50
SAMPLING RATE (ksps)
DEVICE
MODE
INTERNAL
REFERENCE
SHDN
STATE
1
Enabled
Enabled
Disabled
Enabled
Disabled
High Impedance
0
Figure 13. Average Supply Current vs. Sampling Rate
Power-Down
16 ______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
CLOCK
MODE
INTERNAL
EXTERNAL
EXTERNAL
SHDN
SETS POWER-
DOWN MODE
SETS EXTERNAL
CLOCK MODE
SETS EXTERNAL
CLOCK MODE
S
X
X X X X 1
1
S X
X
X X X 0
1
S
X X X X X 1
1
DIN
DOUT
MODE
DATA VALID
DATA VALID
DATA
INVALID
POWERED
UP
POWER-
DOWN
POWER-
DOWN
POWERED UP
POWERED UP
Figure 14a. Power-Down Modes, External Clock Timing Diagram
INTERNAL CLOCK MODE
SETS POWER-DOWN MODE
SETS INTERNAL
CLOCK MODE
S
X
X X X X 1
0
S X
X
X X X 0
0
S
DIN
DATA VALID
DATA VALID
DOUT
SSTRB
CONVERSION
CONVERSION
POWER-DOWN
POWERED UP
MODE
POWERED
UP
Figure 14b. Power-Down Modes, Internal Clock Timing Diagram
Internal Reference
To use the MAX1112/MAX1113 with the internal refer-
ence, connect REFIN to REFOUT. The full-scale range
of the MAX1112/MAX1113 with the internal reference is
typically 4.096V with unipolar inputs, and 2.048V with
bipolar inputs. The internal reference should be
bypassed to AGND with a 1µF capacitor placed as
close to the REFIN pin as possible.
Transfer Function
Table 4 shows the full-scale voltage ranges for unipolar
and bipolar modes. Figure 15 depicts the nominal,
unipolar I/O transfer function, and Figure 16 shows the
bipolar I/O transfer function when using a 4.096V refer-
ence. Code transitions occur at integer LSB values.
Output coding is binary, with 1 LSB = 16mV
(4.096V/256) for unipolar operation and 1 LSB = 16mV
[(4.096V/2 - -4.096V/2)/256] for bipolar operation.
______________________________________________________________________________________ 17
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
OUTPUT CODE
FULL-SCALE
SUPPLIES
TRANSITION
11111111
11111110
+5V
GND
11111101
FS = V
+ COM
REFIN
V
R* = 10Ω
REFIN
256
1 LSB =
00000011
00000010
V
AGND
DGND
+5V
DGND
DD
00000001
00000000
DIGITAL
CIRCUITRY
MAX1112
MAX1113
0
1
2
3
FS
(COM)
INPUT VOLTAGE (LSB)
FS - 1 LSB
*OPTIONAL
Figure 15. Unipolar Transfer Function
Figure 17. Power-Supply Grounding Connections
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Wire-
wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
OUTPUT CODE
V
REFIN
2
+FS =
+ COM
01111111
01111110
V
REFIN
COM =
2
-V
REFIN
2
-FS =
+ COM
Figure 17 shows the recommended system ground
connections. A single-point analog ground (star ground
point) should be established at AGND, separate from
the logic ground. Connect all other analog grounds and
DGND to the star ground. No other digital system
ground should be connected to this ground. The
ground return to the power supply for the star ground
should be low impedance and as short as possible for
noise-free operation.
00000010
00000001
00000000
V
REFIN
1 LSB =
256
11111111
11111110
11111101
10000001
10000000
High-frequency noise in the V
power supply can
DD
affect the comparator in the ADC. Bypass the supply to
the star ground with 0.1µF and 1µF capacitors close to
COM
INPUT VOLTAGE (LSB)
-FS
the V
pin of the MAX1112/MAX1113. Minimize
DD
1
+FS - LSB
capacitor lead lengths for best supply-noise rejection. If
the 5V power supply is very noisy, a 10Ω resistor can
be connected to form a lowpass filter.
2
Figure 16. Bipolar Transfer Function
18 ______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
Pin Configurations
TOP VIEW
CH0
CH1
CH2
CH3
V
1
2
DD
20
19
18
17
16
15
14
13
12
11
CH0
CH1
1
2
3
4
5
6
7
8
V
SCLK
CS
16
15
14
DD
SCLK
CS
3
CH2
DIN
4
MAX1112
CH3
MAX1113
CH4
CH5
CH6
CH7
13 DIN
SSTRB
DOUT
DGND
AGND
REFOUT
REFIN
5
COM
12 SSTRB
11 DOUT
6
SHDN
REFIN
REFOUT
7
10
9
DGND
AGND
8
COM
9
SHDN
10
QSOP
SSOP
Ordering Information
___________________Chip Information
PROCESS:CMOS
PART
TEMP RANGE
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
20 SSOP
Dice*
SUBSTRATE CONNECTED TO DGND
MAX1112CAP+
MAX1112C/D
MAX1112EAP+
MAX1113CEE+
MAX1113EEE+
-40°C to +85°C
0°C to +70°C
40°C to +85°C
20 SSOP
16 QSOP
16 QSOP
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*Dice are specified at T = +25°C, DC parameters only.
A
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
20 SSOP
16 QSOP
A20+1
E16+1
21-0056
21-0055
90-0094
90-0167
______________________________________________________________________________________ 19
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
6/97
Initial release
—
Updated General Description, Features, Ordering Information, Absolute
Maximum Ratings, Electrical Characteristics, Timing Characteristics, Pin
Description, Tables 3 and 4, 5, Power-Down, Software Power-Down, Hard-
Wired Power-Down, External Reference and Layout, Grounding, and
Bypassing, and Chip Information sections.
1-8, 10, 11, 13, 14,
16, 18, 19
2
4/11
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, inc.
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