MAX11101EWC [MAXIM]
14-Bit, +5V, 200ksps ADC with 10μA Shutdown; 14位， + 5V ， 200ksps的ADC，具有10μA停机
| 型号： | MAX11101EWC |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 14-Bit, +5V, 200ksps ADC with 10μA Shutdown |
| 文件： | 总19页 (文件大小：2827K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-6047; Rev 1; 1/12
General Description
Features
The MAX11101 low-power, 14-bit analog-to-digital con-
verter (ADC) features a successive approximation ADC,
automatic power-down, fast 1.1Fs wake-up, and a high-
speed SPI/QSPI™/MICROWIRE®-compatible interface.
The MAX11101 operates with a single +5V analog supply
and features a separate digital supply, allowing direct
interfacing with 2.7V to 5.25V digital logic.
S 14-Bit Resolution, 1 LSB DNL
S +5V Single-Supply Operation
S Adjustable Logic Level (2.7V to 5.25V)
S Input Voltage Range: 0 to V
REF
S Internal Track-and-Hold, 4MHz Input Bandwidth
S SPI/QSPI/MICROWIRE-Compatible Serial Interface
S Small 10-Pin µMAX and WLP Packages
At the maximum sampling rate of 200ksps, the MAX11101
typically consumes 2.45mA. Power consumption is typi-
cally 12.25mW (V
= V
= 5V) at a 200ksps
AVDD
DVDD
S Low Power
(max) sampling rate. AutoShutdown™ reduces supply
current to 140FA at 10ksps and to less than 10FA at
reduced sampling rates.
2.45mA at 200ksps
140µA at 10ksps
0.1µA in Power-Down Mode
Excellent dynamic performance and low power, com-
bined with ease of use and small package size (10-pin
M
FMAX and 12-bump WLP), make the MAX11101 ideal
for battery-powered and data-acquisition applications
or for other circuits with demanding power consumption
and space requirements.
Functional Diagram
Applications
DVDD
AVDD
Motor Control
Industrial Process Control
Industrial I/O Modules
REF
AIN
OUTPUT
BUFFER
14-BIT SAR
ADC
TRACK-AND-
HOLD
DOUT
Data-Acquisition Systems
Thermocouple Measurements
Accelerometer Measurements
Portable- and Battery-Powered Equipment
AGND
SCLK
CONTROL
CS
MAX11101
Ordering Information appears at end of data sheet.
DGND
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National Semiconductor Corp.
AutoShutdown is a trademark and µMAX is a registered trademark of Maxim Integrated Products, Inc.
For related parts and recommended products to use with this part, refer to: www.maxim-ic.com/MAX11101.related
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For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .......................................................-0.3V to +6V
DVDD to DGND.......................................................-0.3V to +6V
DGND to AGND ...................................................-0.3V to +0.3V
Continuous Power Dissipation (T = +70NC)
A
FMAX (derate 5.6mW/NC above +70NC) .....................444mW
WLP (derate 16.1mW/NC above +70NC)......1300mW (Note 1)
Operating Temperature Range.......................... -40NC to +85NC
Maximum Junction Temperature.....................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (FMAX only; soldering, 10s).............+300NC
Soldering Temperature (reflow) ......................................+260NC
AIN, REF to AGND ............................... -0.3V to (V
+ 0.3V)
AVDD
SCLK, CS to DGND.................................................-0.3V to +6V
DOUT to DGND.................................... -0.3V to (V + 0.3V)
DVDD
Maximum Current Into Any Pin ....................................... Q50mA
Note 1: All WLP devices are 100% production tested at T = +25NC. Specifications over temperature limits are guaranteed by
A
design and characterization..
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= V
= 4.75V to 5.25V, f
= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), V
= 4.096V, T = T
to
AVDD
DVDD
SCLK
REF
A
MIN
T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 2)
Resolution
14
-1
-1
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
Transition Noise
Offset Error
INL
(Note 3)
+1
+1
DNL
No missing codes over temperature
RMS noise
0.5
Q0.32
0.2
LSB
RMS
1
mV
%FSR
Gain Error (Note 4)
Offset Drift
Q0.002
0.4
0.01
ppm/°C
ppm/°C
Gain Drift (Note 4)
0.2
DYNAMIC SPECIFICATIONS (1kHz sine wave, 4.096V ) (Note 2)
P-P
Signal-to-Noise Plus Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
Full-Power Bandwidth
Full-Linear Bandwidth
CONVERSION RATE
Conversion Time
SINAD
SNR
81
82
84
84
-99
101
4
dB
dB
THD
-86
dB
SFDR
87
dB
-3dB point
MHz
kHz
SINAD > 81dB
20
t
(Note 5)
5
240
4.8
Fs
MHz
ns
CONV
Serial Clock Frequency
Aperture Delay
f
0.1
SCLK
15
Aperture Jitter
< 50
ps
Sample Rate
f
f
/24
SCLK
200
ksps
Fs
S
Track/Hold Acquisition Time
t
1.1
ACQ
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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= 4.75V to 5.25V, f
= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), V
= 4.096V, T = T
to
AVDD
DVDD
SCLK
REF
A
MIN
T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT (AIN)
Input Range
V
0
V
V
AIN
REF
1
Input Leakage Current
EXTERNAL REFERENCE
Input Voltage Range
SCLK idle
0.01
FA
V
3.8
V
AVDD
150
V
REF
V
V
= 4.096V, f
= 4.8MHz
60
REF
SCLK
Input Current
I
= 4.096V, SCLK idle
0.01
0.01
10
FA
REF
REF
CS = DVDD, SCLK idle
DIGITAL INPUTS (SCLK, CS)
0.7 x
Input High Voltage
V
V
= 2.7V to 5.25V
= 2.7V to 5.25V
V
V
IH
DVDD
V
DVDD
0.3 x
Input Low Voltage
V
V
V
IL
DVDD
V
DVDD
Input Leakage Current
Input Hysteresis
I
= 0 to V
Q0.1
0.2
15
Q1
FA
V
IN
IN
DVDD
V
HYST
Input Capacitance
C
pF
IN
DIGITAL OUTPUT (DOUT)
V
DVDD
Output High Voltage
Output Low Voltage
V
I
I
= 0.5mA, V
= 2.7V to 5.25V
DVDD
V
V
OH
SOURCE
- 0.25
V
= 2mA, V
SINK
= 2.7V to 5.25V
0.4
OL
DVDD
Three-State Output Leakage
Current
I
CS = DVDD
CS = DVDD
Q0.1
Q10
FA
pF
L
Three-State Output Capacitance
POWER SUPPLIES
Analog Supply
C
15
OUT
V
V
4.75
2.7
5.25
5.25
2.5
V
V
AVDD
DVDD
AVDD
Digital Supply
Analog Supply Current
I
CS = DGND, 200ksps
CS = DGND,
DOUT = all zeros, 200ksps
1.85
0.6
mA
Digital Supply Current
I
1.0
10
mA
FA
dB
DVDD
I
+
AVDD
Shutdown Supply Current
Power-Supply Rejection Ratio
CS = DVDD, SCLK = idle
0.1
68
I
DVDD
V
= V
= 4.75V to 5.25V, full-
AVDD
DVDD
PSRR
scale input (Note 6)
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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
TIMING CHARACTERISTICS
(V
= V
= 4.75V to 5.25V, f
= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), V
= 4.096V, T = T
to
AVDD
DVDD
SCLK
REF
A
MIN
T
, unless otherwise noted. Typical values are at T = +25°C.) (See Figure 1, Figure 2, Figure 3, and Figure 6.)
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Fs
Acquisition Time
t
1.1
ACQ
SCLK to DOUT Valid
t
C
C
C
= 50pF
= 50pF
= 50pF
50
80
80
ns
DO
DOUT
DOUT
DOUT
t
ns
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Pulse Width
DV
t
ns
TR
t
50
ns
CSW
t
100
ns
CS Fall to SCLK Rise Setup
CS Rise to SCLK Rise Hold
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Period
CSS
t
0
ns
CSH
t
65
65
ns
CH
t
ns
CL
t
208
ns
CP
TIMING CHARACTERISTICS
(V
= 4.75V to 5.25V, V
= 2.7V to 5.25V, f
= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), V = +4.096V,
REF
AVDD
DVDD
SCLK
T
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (See Figure 1, Figure 2, Figure 3, and Figure 6.)
A
MIN
MAX A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Fs
Acquisition Time
t
1.1
ACQ
SCLK to DOUT Valid
t
C
C
C
= 50pF
= 50pF
= 50pF
100
100
80
ns
DO
DOUT
DOUT
DOUT
t
ns
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Pulse Width
DV
t
ns
TR
CSW
t
50
ns
t
100
ns
CS Fall to SCLK Rise Setup
CS Rise to SCLK Rise Hold
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Period
CSS
t
0
ns
CSH
t
t
65
65
ns
CH
t
ns
CL
208
ns
CP
Note 2: V
= V
= +5V.
AVDD
DVDD
Note 3: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 4: Offset and reference errors nulled.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Defined as the change in positive full scale caused by a Q5% variation in the nominal supply voltage.
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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Typical Operating Characteristics
(V
= V
= 5V, f
= 4.8MHz, C
= 50pF, V
= +4.096V, T = +25°C, unless otherwise noted.)
AVDD
DVDD
SCLK
LOAD
REF A
INTEGRAL NONLINEARITY (INL)
vs. CODE
DIFFERENTIAL NONLINEARITY (DNL)
vs. CODE
INL AND DNL
vs. ANALOG SUPPLY VOLTAGE
0.5
0.4
0.5
0.4
0.5
0.3
MAX INL
0.3
0.3
0.2
0.2
0.1
0.1
0.1
0
0
MAX DNL
MIN DNL
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-1.5
-0.1
-0.3
-0.5
MIN INL
0
4096
8192
12288
16384
0
4096
8192
12288
16384
4.75
4.85
4.95
5.05
(V)
5.15
5.25
2048
6144
10240
14336
2048
6144
10240
14336
V
AVDD
OUTPUT CODE (DECIMAL)
OUTPUT CODE (DECIMAL)
MAX11101 FFT
SINAD VS. FREQUENCY
INL AND DNL vs. TEMPERATURE
100
0.5
0.3
0
-20
-40
-60
-80
90
80
MAX INL
70
60
0.1
50
40
MAX DNL
MIN DNL
-0.1
-0.3
-0.5
30
20
-100
-120
-140
MIN INL
f
= 200kHz
10
0
SAMPLE
-40
-15
10
35
60
85
0
10 20 30 40 50 60 70 80 90 100
FREQUENCY (kHz)
0.1
1
10
100
TEMPERATURE (°C)
FREQUENCY (kHz)
SFDR VS. FREQUENCY
THD VS. FREQUENCY
110
100
90
0
-10
-20
f
= 200kHz
SAMPLE
80
70
60
50
40
30
20
10
0
-30
-40
-50
-60
-70
-80
-90
-100
-110
f
= 200kHz
SAMPLE
0.1
1
10
100
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Typical Operating Characteristics (continued)
(V
= V
= 5V, f
= 4.8MHz, C
= 50pF, V = +4.096V, T = +25°C, unless otherwise noted.)
REF A
AVDD
DVDD
SCLK
LOAD
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SAMPLE RATE
10.0000
1.90
1.0000
0.1000
0.0100
0.0010
0.0001
1.88
1.86
1.84
1.82
1.80
I
AVDD
I
DVDD
1
10
100
1000
4.75
4.75
4.75
4.85
4.95
5.05
(V)
5.15
5.25
5.25
5.25
SAMPLE RATE (ksps)
V
AVDD
SHUTDOWN SUPPLY CURRENT
VS. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
20
18
16
14
12
10
8
2.5
2.0
1.5
1.0
0.5
0
I
AVDD
6
4
I
2
DVDD
0
-40
-15
10
35
60
85
4.85
4.95
5.05
5.15
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT
VS. TEMPERATURE
OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
450
400
350
300
250
200
150
100
50
500
300
V
= V
= +5V
AVDD
DVDD
100
-100
-300
-500
0
4.85
4.95
5.05
(V)
5.15
-40
-15
10
35
60
85
V
AVDD
TEMPERATURE (°C)
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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Typical Operating Characteristics (continued)
(V
= V
= 5V, f
= 4.8MHz, C
= 50pF, V = +4.096V, T = +25°C, unless otherwise noted.)
REF A
AVDD
DVDD
SCLK
LOAD
GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
0.010
OFFSET ERROR vs. TEMPERATURE
500
300
100
0.006
0.002
-100
-300
-500
-0.002
-0.006
-0.010
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
(V)
5.15
5.25
TEMPERATURE (°C)
V
AVDD
SIGNAL-TO-NOISE RATIO (SNR) AND
SIGNAL-TO-NOISE AND DISTORTION
RATIO (SINAD) vs. TEMPERATURE
GAIN ERROR vs. TEMPERATURE
0.010
0.006
85.5
85.3
85.1
84.9
84.7
84.5
f
= 1kHz
IN
SNR
0.002
-0.002
-0.006
-0.010
SINAD
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Pin Configurations
TOP VIEW
(BUMP SIDE DOWN)
MAX11101
1
2
3
4
TOP VIEW
+
REF
AVDD
REF
AGND
SCLK
+
DOUT
DGND
DVDD
AGND
AIN
1
10 SCLK
A
B
C
2
3
4
5
9
8
7
6
CS
AGND
AIN
DGND
DVDD
CS
MAX11101
AGND
AVDD
REF
AGND
DOUT
µMAX
WLP
Pin Description
PIN
NAME
FUNCTION
WLP
A1, B2
A2
µMAX
External Reference Voltage Input. Sets the analog voltage range. Bypass to AGND with a 4.7FF
capacitor.
6
7
REF
AVDD
AGND
Analog +5V Supply Voltage. Bypass to AGND with a 0.1FF capacitor.
A3, B1,
C2
4, 8
Analog Ground
Serial Clock Input. SCLK drives the conversion process and clocks out data at data rates up to
4.8MHz.
A4
B3
10
2
SCLK
DGND
Digital Ground
Active Low Chip Select Input. Forcing CS high places the MAX11101 in shutdown with a typical
current of 0.1FA. A high-to-low transition on CS activates normal operating mode and initiates a
conversion.
B4
9
CS
C1
C3
5
3
AIN
Analog Input
DVDD
Digital Supply Voltage. Bypass to DGND with a 0.1FF capacitor.
Serial Data Output. Data changes state on SCLK’s falling edge. DOUT is high impedance when
CS is high.
C4
1
DOUT
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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Detailed Description
V
DD
The MAX11101 includes an input track-and-hold (T/H)
and successive-approximation register (SAR) circuitry to
convert an analog input signal to a digital 14-bit output.
Figure 4 shows the MAX11101 in its simplest configura-
tion. The serial interface requires only three digital lines
(SCLK, CS, and DOUT) and provides an easy interface
to microprocessors (FPs).
1mA
DOUT
1mA
DOUT
C
LOAD
= 50pF
C
= 50pF
LOAD
DGND
a) V TO V
DGND
b) HIGH-Z TO V AND V TO V
OL
The MAX11101 has two power modes: normal and shut-
down. Driving CS high places the MAX11101 in shut-
down, reducing the supply current to 0.1FA (typ), while
pulling CS low places the MAX11101 in normal operating
mode. Falling edges on CS initiate conversions that are
driven by SCLK. The conversion result is available at
DOUT in unipolar serial format. The serial data stream
consists of eight zeros followed by the data bits (MSB
first). Figure 3 shows the interface-timing diagram.
OL
OH
OL
OH
Figure 1. Load Circuits for DOUT Enable Time and SCLK to
DOUT Delay Time
V
DD
1mA
Analog Input
Figure 5 illustrates the input sampling architecture of the
ADC. The voltage applied at REF sets the full-scale input
voltage.
DOUT
1mA
DOUT
C
LOAD
= 50pF
C
LOAD
= 50pF
DGND
a) V TO HIGH-Z
DGND
Track-and-Hold (T/H)
In track mode, the analog signal is acquired on the inter-
nal hold capacitor. In hold mode, the T/H switches open
and the capacitive DAC samples the analog input.
b) V TO HIGH-Z
OH
OL
Figure 2. Load Circuits for DOUT Disable Time
CS
t
CSW
t
t
CH
CL
t
t
CSS
CSH
SCLK
t
CP
t
DO
t
TR
t
DV
DOUT
Figure 3. Detailed Serial Interface Timing
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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
where R
impedance, and t
impedance less than 1kIdoes not significantly affect the
= 800I, R = the input signal’s source
S
IN
is never less than 1.1Fs. A source
ACQ
AIN
REF
CS
SCLK
DOUT
CS
AIN
SCLK
DOUT
ADC’s performance.
V
REF
4.7µF
To improve the input signal bandwidth under AC condi-
tions, drive AIN with a wideband buffer (> 4MHz) that
can drive the ADC’s input capacitance and settle quickly.
MAX11101
AVDD
+5V
+5V
0.1µF
DVDD
AGND
DGND
Input Bandwidth
The ADC’s input tracking circuitry has a 4MHz small-
signal bandwidth, so it is possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by using
undersampling techniques. To avoid aliasing of unwant-
ed high-frequency signals into the frequency band of
interest, use anti-alias filtering.
0.1µF
GND
Figure 4. Typical Operating Circuit
REF
Analog Input Protection
TRACK
CAPACITIVE DAC
AIN
Internal protection diodes, which clamp the analog input to
ZERO
AVDD and/or AGND, allow the input to swing from V
-
AGND
C
SWITCH
3pF
C
DAC
32pF
HOLD
0.3V to V
+ 0.3V, without damaging the device.
AVDD
R
IN
800Ω
GND
If the analog input exceeds 300mV beyond the supplies,
limit the input current to 10mA.
TRACK
HOLD
Digital Interface
AUTOZERO
RAIL
Initialization After Power-Up
and Starting a Conversion
Figure 5. Equivalent Input Circuit
The digital interface consists of two inputs, SCLK and
CS, and one output, DOUT. A logic-high on CS places
the MAX11101 in shutdown (autoshutdown) and places
DOUT in a high-impedance state. A logic-low on CS
places the MAX11101 in the fully powered mode.
During the acquisition, the analog input (AIN) charges
capacitor CDAC. The acquisition interval ends on the
falling edge of the sixth clock cycle (Figure 6). At this
instant, the T/H switches open. The retained charge on
CDAC represents a sample of the input.
To start a conversion, pull CS low. A falling edge on CS
initiates an acquisition. SCLK drives the A/D conversion
and shifts out the conversion results (MSB first) at DOUT.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to zero within the limits of
14-bit resolution. At the end of the conversion, force CS
high and then low to reset the input side of the CDAC
switches back to AIN, and charge CDAC to the input
signal again.
Timing and Control
Conversion-start and data-read operations are con-
trolled by the CS and SCLK digital inputs (Figure 6
and Figure 7). Ensure that the duty cycle on SCLK is
between 40% and 60% at 4.8MHz (the maximum clock
frequency). For lower clock frequencies, ensure that
the minimum high and low times are at least 65ns.
Conversions with SCLK rates less than 100kHz may
result in reduced accuracy due to leakage.
The time required for the T/H to acquire an input signal is
a function of how quickly its input capacitance is charged.
If the input signal’s source impedance is high, the acqui-
sition time lengthens and more time must be allowed
between conversions. The acquisition time (t ) is the
ACQ
Note: Coupling between SCLK and the analog inputs
(AIN and REF) may result in an offset. Variations in
frequency, duty cycle, or other aspects of the clock
signal’s shape result in changing offset.
maximum time the device takes to acquire the signal. Use
the following formula to calculate acquisition time:
t
= 11(R + R ) x 35pF
S IN
ACQ
���������������������������������������������������������������� Maxim Integrated Products 10
MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
CS
24
1
4
6
8
12
16
20
SCLK
DOUT
t
t
CL
CSS
t
CSH
t
CH
D10 D9 D8
D7 D6 D5 D4
D3 D2 D1
D0
S1 S0
D13 D12 D11
t
t
DO
t
ACQ
DN
t
TR
Figure 6. External Timing Diagram
COMPLETE CONVERSION SEQUENCE
CS
DOUT
CONVERSION 0
POWERED UP
CONVERSION 1
POWERED UP
POWERED DOWN
Figure 7. Shutdown Sequence
A CS falling edge initiates an acquisition sequence. The
analog input is stored in the capacitive DAC, DOUT
changes from high impedance to logic-low, and the ADC
begins to convert after the sixth clock cycle. SCLK drives
the conversion process and shifts out the conversion
result on DOUT.
out, and prior to the rising edge of CS, produce trail-
ing zeros at DOUT and have no effect on the converter
operation.
Force CS high after reading the conversion’s LSB to
reset the internal registers and place the MAX11101 in
shutdown. For maximum throughput, force CS low again
to initiate the next conversion immediately after the speci-
SCLK begins shifting out the data (MSB first) after the fall-
ing edge of the 8th SCLK pulse. Twenty-four falling clock
edges are needed to shift out the eight leading zeros, 14
data bits, and 2 sub-bits (S1 and S0). Extra clock pulses
occurring after the conversion result has been clocked
fied minimum time (t ).
CSW
Note: Forcing CS high in the middle of a conversion
immediately aborts the conversion and places the
MAX11101 in shutdown.
���������������������������������������������������������������� Maxim Integrated Products 11
MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Output Coding and Transfer Function
The data output from the MAX11101 is binary and Figure 8
depicts the nominal transfer function. Code transitions
occur halfway between successive-integer LSB values
Input Buffer
Most applications require an input buffer amplifier to
achieve 14-bit accuracy. If the input signal is multi-
plexed, switch the input channel immediately after acqui-
sition, rather than near the end of or after a conversion
(Figure 9). This allows the maximum time for the input
buffer amplifier to respond to a large step change in the
input signal. The input amplifier must have a slew rate of
at least 2V/Fs to complete the required output voltage
change before the beginning of the acquisition time.
(V
REF
= 4.096V and 1 LSB = 250FV or 4.096V/16384).
Applications Information
External Reference
The MAX11101 requires an external reference with a volt-
age range between 3.8V and AVDD. Connect the exter-
nal reference directly to REF. Bypass REF to AGND with
a 4.7FF capacitor. When not using a low-ESR bypass
capacitor, use a 0.1FF ceramic capacitor in parallel with
the 4.7FF capacitor. Noise on the reference degrades
conversion accuracy.
At the beginning of the acquisition, the internal sampling
capacitor array connects to AIN (the amplifier output),
causing some output disturbance. Ensure that the sampled
voltage has settled before the end of the acquisition time.
Digital Noise
Digital noise can couple to AIN and REF. The conversion
clock (SCLK) and other digital signals active during input
acquisition contribute noise to the conversion result. Noise
signals synchronous with the sampling interval result in
an effective input offset. Asynchronous signals produce
random noise on the input, whose high-frequency compo-
nents may be aliased into the frequency band of interest.
Minimize noise by presenting a low impedance (at the
frequencies contained in the noise signal) at the inputs.
This requires bypassing AIN to AGND, or buffering the
input with an amplifier that has a small-signal bandwidth
of several MHz, or preferably both. AIN has about 4MHz
of bandwidth.
The input impedance at REF is 40I for DC currents.
During a conversion, the external reference at REF must
deliver 100FA of DC load current and have an output
impedance of 10I or less.
For optimal performance, buffer the reference through
an op amp and bypass the REF input. Consider the
MAX11101’s equivalent input noise (80FV
choosing a reference.
) when
RMS
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
Distortion
Avoid degrading dynamic performance by choosing an
amplifier with distortion much less than the MAX11101’s
total harmonic distortion (THD = -99dB at 1kHz) at
frequencies of interest. If the chosen amplifier has
insufficient common-mode rejection, which results in
degraded THD performance, use the inverting configu-
ration (positive input grounded) to eliminate errors from
this source. Low temperature-coefficient, gain-setting
resistors reduce linearity errors caused by resistance
changes due to self-heating. To reduce linearity errors
due to finite amplifier gain, use amplifier circuits with suf-
ficient loop gain at the frequencies of interest.
11 . . . 110
11 . . . 101
FS = V
REF
V
REF
1LSB =
16384
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
0
1
2
3
FS
DC Accuracy
To improve DC accuracy, choose a buffer with an offset
much less than the MAX11101’s offset (1mV (max) for
+5V supply), or whose offset can be trimmed while main-
taining stability over the required temperature range.
FS - 3/2 LSB
INPUT VOLTAGE (LSB)
Figure 8. Unipolar Transfer Function, Full Scale (FS) = V
Zero Scale (ZS) = GND
,
REF
���������������������������������������������������������������� Maxim Integrated Products 12
MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
A0
A1
IN1
IN2
4-TO-1
MUX
MAX11101
IN3
IN4
AIN
CS
OUT
CLK
CS
ACQUISITION
CONVERSION
A0
A1
CHANGE MUX INPUT HERE
Figure 9. Change Multiplexer Input Near Beginning of Conversion to Allow Time for Slewing and Settling
Observe the SCLK to DOUT valid timing characteris-
tic. Clock data into the FP on SCLK’s rising edge.
Serial Interfaces
The MAX11101’s interface is fully compatible with SPI,
QSPI, and MICROWIRE standard serial interfaces.
3) Pull CS high at or after the 24th falling clock edge. If
CS remains low, trailing zeros are clocked out after
the 2 sub-bits, S1 and S0.
If a serial interface is available, establish the CPU’s
serial interface as master, so that the CPU generates the
serial clock for the MAX11101. Select a clock frequency
between 100kHz and 4.8MHz:
4) With CS high, wait at least 50ns (t ) before starting a
CSW
new conversion by pulling CS low. A conversion can be
aborted by pulling CS high before the conversion ends.
Wait at least 50ns before starting a new conversion.
1) Use a general-purpose I/O line on the CPU to pull CS
low.
Data can be output in three 8-bit sequences or continu-
ously. The bytes contain the results of the conversion pad-
ded with eight leading zeros before the MSB. If the serial
clock has not been idled after the sub-bits (S1 and S0) and
CS has been kept low, DOUT sends trailing zeros.
2) Activate SCLK for a minimum of 24 clock cycles. The
serial data stream of eight leading zeros followed by
the MSB of the conversion result begins at the fall-
ing edge of CS. DOUT transitions on SCLK’s falling
edge and the output is available in MSB-first format.
���������������������������������������������������������������� Maxim Integrated Products 13
MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
SPI and MICROWIRE Interfaces
When using the SPI (Figure 10a) or MICROWIRE (Figure 10b)
I/O
SCK
CS
interfaces, set CPOL = 0 and CPHA = 0. Conversion
begins with a falling edge on CS (Figure 10c). Three con-
secutive 8-bit readings are necessary to obtain the entire
14-bit result from the ADC. DOUT data transitions on
the serial clock’s falling edge. The first 8-bit data stream
contains all leading zeros. The second 8-bit data stream
contains the MSB through D6. The third 8-bit data stream
contains D5 through D0 followed by S1 and S0.
SCLK
DOUT
MISO
V
DD
SPI
MAX11101
SS
Figure 10a. SPI Connections
I/O
SK
CS
SCLK
DOUT
SI
MICROWIRE
MAX11101
Figure 10b. MICROWIRE Connections
1ST BYTE READ
4
2ND BYTE READ
1
6
8
12
16
SCLK
CS
0
0
0
0
0
0
0
0
D13
D12
D11
D10
D9
D8
D7
D6
D5
DOUT*
MSB
*WHEN CS IS HIGH, DOUT = HIGH-Z
3RD BYTE READ
20
24
HIGH-Z
D5
D4
D3
D2
D1
D0
S1
S0
LSB
Figure 10c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA =0)
���������������������������������������������������������������� Maxim Integrated Products 14
MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
CS
SCK
CS
SCLK
DOUT
MISO
V
DD
QSPI
MAX11101
SS
Figure 11a. QSPI Connections
24
1
4
6
8
12
16
20
SCLK
CS
END OF
ACQUISITION
HIGH-Z
D10 D9 D8
D7 D6 D5 D4
D3 D2 D1
D0
S1 S0
D13 D12 D11
MSB
DOUT*
LSB
*WHEN CS IS HIGH, DOUT = HIGH-Z
Figure 11b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
PIC16 with SSP Module and PIC17 Interface
The MAX11101 is compatible with a PIC16/PIC17 micro-
controller (FC) using the synchronous serial-port (SSP)
module.
V
V
DD
DD
SCLK
DOUT
CS
SCK
SDI
I/O
To establish SPI communication, connect the controller
as shown in Figure 12a. Configure the PIC16/PIC17 as
system master, by initializing its synchronous serial-port
control register (SSPCON) and synchronous serial-port
status register (SSPSTAT) to the bit patterns shown in
Table 1 and Table 2.
PIC16/17
MAX11101
GND
In SPI mode, the PIC16/PIC17 FC allows 8 bits of data
to be synchronously transmitted and received simulta-
neously. Three consecutive 8-bit readings (Figure 12b)
are necessary to obtain the entire 14-bit result from the
ADC. DOUT data transitions on the serial clock’s falling
edge and is clocked into the FC on SCLK’s rising edge.
The first 8-bit data stream contains all zeros. The second
8-bit data stream contains the MSB through D6. The third
8-bit data stream contains bits D5 through D0 followed
by S1 and S0.
Figure 12a. SPI Interface Connection for a PIC16/PIC17
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0 and
CPHA = 0, the MAX11101 supports a maximum f
of 4.8MHz. Figure 11a shows the MAX11101 connected
to a QSPI master and Figure 11b shows the associated
interface timing.
SCLK
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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
1ST BYTE READ
2ND BYTE READ
12
16
SCLK
CS
0
0
0
0
0
0
0
0
D5
D13
D12
D11
D10
D9
D8
D7
D6
DOUT*
MSB
*WHEN CS IS HIGH, DOUT = HIGH-Z
3RD BYTE READ
20
24
HIGH-Z
D5
D4
D3
D2
D1
D0
S1
S0
LSB
Figure 12b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 =0001)
Table 1. Detailed SSPCON Register Contents
MAX11101
SETTINGS
CONTROL BIT
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL
SSPOV
BIT 7
BIT 6
X
X
Write Collision Detection Bit
Receive Overflow Detect Bit
Synchronous Serial-Port Enable Bit:
SSPEN
BIT 5
1
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins.
CKP
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
1
Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
SSPM3
SSPM2
SSPM1
SSPM0
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and selects f
= f
/16
CLK
OSC
Table 2. Detailed SSPSTAT Register Contents
MAX11101
SETTINGS
CONTROL BIT
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPSTAT)
SMP
CKE
D/A
P
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
1
X
X
X
X
X
X
SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time.
SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock.
Data Address Bit
STOP Bit
S
START Bit
R/W
UA
BF
Read/Write Bit Information
Update Address
Buffer Full Status Bit
���������������������������������������������������������������� Maxim Integrated Products 16
MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Effective Number of Bits
Effective number of bits (ENOB) indicate the global
Definitions
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC error consists of quantiza-
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
tion noise only. With an input range equal to the full-scale
on an actual transfer function from a straight line. This
range of the ADC, calculate the effective number of bits
straight line can be either a best-fit straight line fit or a line
drawn between the end points of the transfer function,
as follows:
once offset and gain errors have been nullified. The static
linearity parameters for the MAX11101 are measured
using the endpoint method.
ENOB = (SINAD – 1.76)/6.02
Figure 13 shows the effective number of bits as a function
of the MAX11101’s input frequency.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A DNL
error specification of 1 LSB guarantees no missing codes
and a monotonic transfer function.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
2
2
2
2
V
+ V + V + V
3 4 5
2
Aperture Definitions
THD = 20 ×log
V1
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between samples. Aperture delay (t ) is the
AD
time between the falling edge of the sampling clock and
the instant when the actual sample is taken.
where V is the fundamental amplitude and V through
V are the 2nd- through 5th-order harmonics.
5
1
2
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quantiza-
tion error (residual error). The ideal, theoretical minimum
analog-to-digital noise is caused by quantization noise
error only and results directly from the ADCs resolution
(N bits):
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest fre-
quency component.
14
12
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantiza-
tion noise: thermal noise, reference noise, clock jitter, etc.
SNR is computed by taking the ratio of the RMS signal to
the RMS noise, which includes all spectral components
minus the fundamental, the first five harmonics, and the
DC offset.
10
8
6
4
2
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals.
f
= 200kHz
1
SAMPLE
0
0.1
10
100
INPUT FREQUENCY (kHz)
Signal
RMS
SINAD(dB) = 20 ×log
Figure 13. Effective Number of Bits vs. Input Frequency
Noise + Distortion
(
)
RMS
���������������������������������������������������������������� Maxim Integrated Products 17
MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Supplies, Layout, Grounding and Bypassing
Use PCBs with separate analog and digital ground
planes. Do not use wire-wrap boards. Connect the two
ground planes together at the MAX11101. Isolate the
digital supply from the analog with a low-value resistor
(10I) or ferrite bead when the analog and digital sup-
plies come from the same source (Figure 14).
Ordering Information
PART
TEMP RANGE
-40NC to +85NC
-40NC to +85NC
PIN-PACKAGE
10 FMAX
MAX11101EUB+
MAX11101EWC+
12 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
Constraints on sequencing the power supplies and
inputs are as follows:
Chip Information
U Apply AGND before DGND.
PROCESS: BiCMOS
UApply AIN and REF after AVDD and AGND are present.
U DVDD is independent of the supply sequencing.
Package Information
Ensure that digital return currents do not pass through
the analog ground and that return-current paths are
low impedance. A 5mA current flowing through a PCB
ground trace impedance of only 0.05I creates an error
voltage of about 250FV, 1 LSB error with a 4V full-scale
system.
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
The board layout should ensure that digital and analog
signal lines are kept separate. Do not run analog and dig-
ital (especially the SCLK and DOUT) lines parallel to one
another. If one must cross another, do so at right angles.
10 FMAX
U10+2
21-0061
90-0330
Refer to
Application
Note 1891
12 WLP
W121A2+1
21-0009
The ADCs high-speed comparator is sensitive to high-
frequency noise on the AVDD power supply. Bypass an
excessively noisy supply to the analog ground plane with
a 0.1FF capacitor in parallel with a 1FF to 10FF low-ESR
capacitor. Keep capacitor leads short for best supply-
noise rejection.
AIN
REF
CS
SCLK
DOUT
CS
AIN
SCLK
DOUT
V
REF
4.7µF
MAX11101
AVDD
+5V
10Ω
0.1µF
DVDD
AGND
DGND
0.1µF
GND
Figure 14. Powering AVDD and DVDD from a Single Supply
���������������������������������������������������������������� Maxim Integrated Products 18
MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1
9/11
Initial release
Revised the Absolute Maximum Ratings and Electrical Characteristics.
—
1/12
2–4
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
19
©
2012 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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