MAX11102AUB/V+T [MAXIM]
ADC, Successive Approximation, 12-Bit, 1 Func, 2 Channel, Serial Access, CMOS, PDSO10, 3 X 5 MM, ROHS COMPLIAT, UMAX-10;
| 型号： | MAX11102AUB/V+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Successive Approximation, 12-Bit, 1 Func, 2 Channel, Serial Access, CMOS, PDSO10, 3 X 5 MM, ROHS COMPLIAT, UMAX-10 |
| 文件： | 总30页 (文件大小：2106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5245; Rev 5; 8/11
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
General Description
Features
S 2Msps/3Msps Conversion Rate, No Pipeline Delay
S 12-/10-/8-Bit Resolution
The MAX11102/MAX11103/MAX11105/MAX11106/
MAX11110/MAX11111/MAX11115/MAX11116/
MAX11117 are 12-/10-/8-bit, compact, high-speed, low-
power, successive approximation analog-to-digital con-
verters (ADCs). These high-performance ADCs include a
high-dynamic range sample-and-hold and a high-speed
serial interface. These ADCs accept a full-scale input
from 0V to the power supply or to the reference voltage.
S 1-/2-Channel, Single-Ended Analog Inputs
S Low-Noise 73dB SNR
S Variable I/O: 1.5V to 3.6V (Dual-Channel Only)
Allows the Serial Interface to Connect Directly
to 1.5V, 1.8V, 2.5V, or 3V Digital Systems
The MAX11102/MAX11103/MAX11106/MAX11111 fea-
ture dual, single-ended analog inputs connected to the
ADC core using a 2:1 MUX. The devices also include a
separate supply input for data interface and a dedicated
input for reference voltage. In contrast, the single-chan-
nel devices generate the reference voltage internally
from the power supply.
S 2.2V to 3.6V Supply Voltage
S Low Power
3.7mW at 2Msps
5.2mW at 3Msps
Very Low Power Consumption at 2.5µA/ksps
S External Reference Input (Dual-Channel Devices Only)
S 1.3µA Power-Down Current
These ADCs operate from a 2.2V to 3.6V supply and
consume only 5.2mW at 3Msps and 3.7mW at 2Msps.
The devices include full power-down mode and fast
wake-up for optimal power management and a high-
speed 3-wire serial interface. The 3-wire serial interface
directly connects to SPIK, QSPIK, and MICROWIREK
devices without external logic.
S SPI-/QSPI-/MICROWIRE-Compatible Serial
Interface
S 10-Pin, 3mm x 3mm TDFN Package
S 10-Pin, 3mm x 5mm µMAX Package
S 6-Pin, 2.8mm x 2.9mm SOT23 Package
S Wide -40NC to +125NC Operation
Excellent dynamic performance, low voltage, low power,
ease of use, and small package size make these con-
verters ideal for portable battery-powered data-acquisi-
tion applications, and for other applications that demand
low-power consumption and minimal space.
Applications
Data Acquisition
Portable Data Logging
These ADCs are available in a 10-pin TDFN package,
Medical Instrumentation
®
10-pin FMAX package, and a 6-pin SOT23 package.
Battery-Operated Systems
Communication Systems
Automotive Systems
These devices operate over the -40NC to +125NC tem-
perature range.
Ordering Information
PART
PIN-PACKAGE
10 FMAX-EP*
10 TDFN-EP*
10 FMAX-EP*
BITS
12
SPEED (Msps)
NO. OF CHANNELS
TOP MARK
+AABH
+AWI
MAX11102AUB+
MAX11102ATB+
MAX11103AUB+
2
2
3
2
2
2
12
12
+AAAV
Ordering Information continued at end of data sheet.
Note: All devices are specified over the -40°C to +125°C operating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
V
to GND............................................................-0.3V to +4V
10-Pin TDFN (derate 24.4mW/NC above +70NC).......1951mW
10-Pin FMAX (derate 8.8mW/NC above +70NC)........707.3mW
Operating Temperature Range....................... .-40NC to +125NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
DD
REF, OVDD, AIN1, AIN2, AIN to GND ........-0.3V to the lower of
(V + 0.3V) and +4V
DD
CS, SCLK, CHSEL, DOUT TO GND............-0.3V to the lower of
(V + 0.3V) and +4V
OVDD
AGND to GND......................................................-0.3V to +0.3V
Input/Output Current (all pins) ...........................................50mA
Continuous Power Dissipation (T = +70NC)
A
6-Pin SOT23 (derate 8.7mW/NC above +70NC)...........696mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS (MAX11102/MAX11103)
(V
DD
= 2.2V to 3.6V, V
= V , V
= V . MAX11102: f
= 32MHz, 50% duty cycle, 2Msps. MAX11103: f
= 48MHz,
SCLK
REF
DD OVDD
DD
SCLK
50% duty cycle, 3Msps. C
= 10pF, T = -40NC to +125NC, unless otherwise noted. Typical values are at T = +25NC.)
DOUT
A
A
PARAMETER
DC ACCURACY
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
12
Bits
LSB
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
DNL
OE
Q1
Q1
Q3
Q3
No missing codes
Excluding offset and reference errors
Q0.3
Q1
Gain Error
GE
Total Unadjusted Error
TUE
Q1.5
Channel-to-Channel Offset
Matching
Q0.4
LSB
LSB
Channel-to-Channel Gain
Matching
Q0.05
DYNAMIC PERFORMANCE (MAX11103: f
= 1MHz, MAX11102: f = 0.5MHz)
AIN_
AIN_
MAX11103
70
70
72
72.5
72
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
SINAD
dB
dB
dB
dB
dB
MAX11102
MAX11103
70.5
70.5
SNR
THD
SFDR
IMD
MAX11102
73
MAX11103
-85
-85
85
-75
-76
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
MAX11102
MAX11103
76
77
MAX11102
85
MAX11103: f = 1.0003MHz, f = 0.99955MHz
MAX11102: f = 500.15kHz, f = 499.56kHz
1
2
-84
1
2
Full-Power Bandwidth
Full-Linear Bandwidth
Small-Signal Bandwidth
Crosstalk
-3dB point
SINAD > 68dB
40
2.5
45
MHz
MHz
MHz
dB
-90
2
______________________________________________________________________________________
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11102/MAX11103) (continued)
(V
DD
= 2.2V to 3.6V, V
= V , V
= V . MAX11102: f
= 32MHz, 50% duty cycle, 2Msps. MAX11103: f
= 48MHz,
SCLK
REF
DD OVDD
DD
SCLK
50% duty cycle, 3Msps. C
= 10pF, T = -40NC to +125NC, unless otherwise noted. Typical values are at T = +25NC.)
DOUT
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONVERSION RATE
MAX11103
MAX11102
MAX11103
MAX11102
0.03
0.02
260
391
52
3
2
Throughput
Msps
ns
Conversion Time
Acquisition Time
Aperture Delay
Aperture Jitter
t
ns
ns
ps
ACQ
4
From CS falling edge
15
MAX11103
MAX11102
0.48
0.32
48
32
Serial-Clock Frequency
f
MHz
CLK
ANALOG INPUT (AIN1, AIN2)
Input Voltage Range
V
AIN_
0
V
V
REF
Input Leakage Current
I
0.002
20
Q1
FA
ILA
Track
Hold
Input Capacitance
C
AIN_
pF
V
4
EXTERNAL REFERENCE INPUT (REF)
V
+
DD
0.05
Reference Input-Voltage Range
V
1
REF
ILR
Reference Input Leakage
Current
I
Conversion stopped
0.005
5
Q1
FA
Reference Input Capacitance
C
pF
REF
DIGITAL INPUTS (SCLK, CS, CHSEL)
0.75 x
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Hysteresis
V
V
V
V
IH
V
OVDD
0.25 x
V
IL
V
OVDD
0.15 x
V
HYST
V
OVDD
0.001
2
Digital Input Leakage Current
Digital Input Capacitance
DIGITAL OUTPUT (DOUT)
I
Inputs at GND or V
Q1
FA
IL
DD
C
pF
IN
0.85 x
Output High Voltage
Output Low Voltage
V
I
I
= 200FA
SOURCE
V
V
OH
V
OVDD
0.15 x
V
= 200FA
SINK
OL
OL
V
OVDD
High-Impedance Leakage
Current
I
Q1.0
FA
pF
High-Impedance Output
Capacitance
C
OUT
4
_______________________________________________________________________________________
3
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11102/MAX11103) (continued)
(V
DD
= 2.2V to 3.6V, V
= V , V
= V . MAX11102: f
= 32MHz, 50% duty cycle, 2Msps. MAX11103: f
= 48MHz,
SCLK
REF
DD OVDD
DD
SCLK
50% duty cycle, 3Msps. C
= 10pF, T = -40NC to +125NC, unless otherwise noted. Typical values are at T = +25NC.)
DOUT
A
A
PARAMETER
POWER SUPPLY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Positive Supply Voltage
V
2.2
1.5
3.6
V
V
DD
Digital I/O Supply Voltage
V
V
DD
OVDD
MAX11103, V
MAX11102, V
MAX11103, V
MAX11102, V
MAX11103
= V
= V
= V
= V
3.3
2.6
AIN_
AIN_
AIN_
AIN_
GND
GND
GND
GND
I
VDD
Positive Supply Current
(Full-Power Mode)
mA
mA
0.33
0.22
I
OVDD
1.98
1.48
1.3
Positive Supply Current (Full-
Power Mode), No Clock
I
VDD
MAX11102
Power-Down Current
Line Rejection
I
Leakage only
10
FA
PD
V
DD
= +2.2V to +3.6V, V
= 2.2V
0.7
LSB/V
REF
TIMING CHARACTERISTICS (Note 1)
Quiet Time
t
(Note 2)
(Note 2)
(Note 2)
4
10
5
ns
ns
ns
Q
t
CS Pulse Width
1
2
t
CS Fall to SCLK Setup
CS Falling Until DOUT High-
Impedance Disabled
t
t
(Note 2)
1
ns
ns
3
4
Figure 2, V
Figure 2, V
= 2.2V - 3.6V
= 1.5V - 2.2V
15
16.5
60
Data Access Time After SCLK
Falling Edge
OVDD
OVDD
SCLK Pulse Width Low
SCLK Pulse Width High
t
t
Percentage of clock period (Note 2)
Percentage of clock period (Note 2)
40
40
%
%
5
6
60
Data Hold Time From SCLK
Falling Edge
SCLK Falling Until DOUT High-
Impedance
t
t
Figure 3
5
ns
7
8
Figure 4 (Note 2)
2.5
14
1
ns
Power-Up Time
Conversion cycle (Note 2)
Cycle
ELECTRICAL CHARACTERISTICS (MAX11105)
(V
DD
= 2.2V to 3.6V, f
= 32MHz, 50% duty cycle, 2Msps, C
= 10pF, T = -40NC to +125NC, unless otherwise noted. Typical
DOUT A
SCLK
values are at T = +25NC.)
A
PARAMETER
DC ACCURACY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
12
Bits
LSB
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
Q1
Q1
Q3
Q3
DNL
OE
No missing codes
Excluding offset and reference errors
Q0.3
Q1
Gain Error
GE
Total Unadjusted Error
DYNAMIC PERFORMANCE
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
TUE
Q1.5
SINAD
SNR
f
f
= 500kHz
= 500kHz
70
72.5
73
dB
dB
AIN
70.5
AIN
4
______________________________________________________________________________________
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11105) (continued)
(V
DD
= 2.2V to 3.6V, f
= 32MHz, 50% duty cycle, 2Msps, C
= 10pF, T = -40NC to +125NC, unless otherwise noted. Typical
DOUT A
SCLK
values are at T = +25NC.)
A
PARAMETER
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
Full-Linear Bandwidth
Small-Signal Bandwidth
CONVERSION RATE
Throughput
SYMBOL
CONDITIONS
MIN
TYP
-85
85
MAX
UNITS
dB
THD
SFDR
IMD
f
f
= 500kHz
= 500kHz
-76
AIN
AIN
77
dB
f = 500.15 kHz, f = 499.56 kHz
-84
40
dB
1
2
-3dB point
SINAD > 68dB
MHz
MHz
MHz
2.5
45
0.02
391
52
2
Msps
ns
Conversion Time
Acquisition Time
t
ns
ACQ
Aperture Delay
4
ns
From CS falling edge
Aperture Jitter
15
ps
Serial Clock Frequency
ANALOG INPUT
f
0.32
0
32
MHz
CLK
Input Voltage Range
Input Leakage Current
V
V
DD
V
AIN
I
0.002
20
Q1
FA
ILA
Track
Hold
Input Capacitance
C
pF
AIN
4
DIGITAL INPUTS (SCLK, CS, CHSEL)
0.75 x
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Hysteresis
V
V
V
V
IH
V
VDD
0.25 x
V
IL
V
VDD
0.15 x
V
HYST
V
VDD
Digital Input Leakage Current
Digital Input Capacitance
DIGITAL OUTPUT (DOUT)
I
Inputs at GND or V
0.001
2
Q1
FA
IL
DD
C
pF
IN
0.85 x
Output High Voltage
Output Low Voltage
V
I
I
= 200FA
SOURCE
V
V
OH
V
VDD
0.15 x
V
= 200FA
SINK
OL
OL
V
VDD
High-Impedance Leakage
Current
I
Q1.0
FA
pF
High-Impedance Output
Capacitance
C
OUT
4
POWER SUPPLY
Positive Supply Voltage
V
2.2
3.6
2.6
V
DD
Positive Supply Current
(Full-Power Mode)
I
V
= V
mA
VDD
AIN
GND
_______________________________________________________________________________________
5
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11105) (continued)
(V
DD
= 2.2V to 3.6V, f
= 32MHz, 50% duty cycle, 2Msps, C
= 10pF, T = -40NC to +125NC, unless otherwise noted. Typical
DOUT A
SCLK
values are at T = +25NC.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Positive Supply Current (Full-
Power Mode), No Clock
I
1.48
mA
VDD
Power-Down Current
Line Rejection
I
Leakage only
= +2.2V to +3.6V
1.3
0.7
10
FA
PD
V
LSB/V
DD
TIMING CHARACTERISTICS (Note 1)
Quiet Time
t
(Note 2)
(Note 2)
(Note 2)
4
10
5
ns
ns
ns
Q
t
CS Pulse Width
1
2
t
CS Fall to SCLK Setup
CS Falling Until DOUT High-
Impedance Disabled
t
(Note 2)
1
ns
ns
3
4
Data Access Time After SCLK
Falling Edge
t
Figure 2, V
= +2.2V to +3.6V
15
DD
SCLK Pulse Width Low
SCLK Pulse Width High
t
t
Percentage of clock period (Note 2)
Percentage of clock period (Note 2)
40
40
60
60
%
%
5
6
Data Hold Time From SCLK
Falling Edge
t
Figure 3
5
ns
7
8
SCLK Falling Until DOUT High-
Impedance
t
Figure 4 (Note 2)
2.5
14
1
ns
Power-Up Time
Conversion cycle (Note 2)
Cycle
ELECTRICAL CHARACTERISTICS (MAX11106)
(V
DD
= 2.2V to 3.6V, V
= V , V
= V , f
= 48MHz, 50% duty cycle, 3Msps; C
= 10pF, T = -40NC to +125NC,
A
REF
DD OVDD
DD SCLK
DOUT
MIN
10
unless otherwise noted. Typical values are at T = +25NC.)
A
PARAMETER
DC ACCURACY
SYMBOL
CONDITIONS
TYP
MAX
UNITS
Resolution
Bits
LSB
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
DNL
OE
Q0.4
Q0.4
Q1
No missing codes
Excluding offset and reference errors
Q0.5
0
Gain Error
GE
Q1
Total Unadjusted Error
TUE
Q0.5
Channel-to-Channel Offset
Matching
Q0.05
LSB
LSB
Channel-to-Channel Gain
Matching
Q0.05
DYNAMIC PERFORMANCE
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
SINAD
SNR
f
f
f
f
= 1MHz
= 1MHz
= 1MHz
= 1MHz
61
61
61.8
61.8
-83
dB
dB
dB
dB
AIN_
AIN_
AIN_
AIN_
Total Harmonic Distortion
Spurious-Free Dynamic Range
THD
-74
SFDR
75
6
______________________________________________________________________________________
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11106) (continued)
(V
DD
= 2.2V to 3.6V, V
= V , V
= V , f
= 48MHz, 50% duty cycle, 3Msps; C
= 10pF, T = -40NC to +125NC,
DOUT A
REF
DD OVDD
DD SCLK
unless otherwise noted. Typical values are at T = +25NC.)
A
PARAMETER
Intermodulation Distortion
Full-Power Bandwidth
Full-Linear Bandwidth
Small-Signal Bandwidth
Crosstalk
SYMBOL
CONDITIONS
MIN
TYP
-82
40
MAX
UNITS
dB
IMD
f = 1.0003MHz, f = 0.99955MHz
1
2
-3dB point
SINAD > 60dB
MHz
MHz
MHz
dB
2.5
45
-90
CONVERSION RATE
Throughput
0.03
260
52
3
Msps
ns
Conversion Time
Acquisition Time
t
ns
ACQ
Aperture Delay
4
ns
From CS falling edge
Aperture Jitter
15
ps
Serial-Clock Frequency
ANALOG INPUT (AIN1, AIN2)
Input Voltage Range
Input Leakage Current
f
0.48
0
48
MHz
CLK
V
V
V
AIN_
REF
I
0.002
20
Q1
FA
ILA
Track
Hold
Input Capacitance
C
pF
V
AIN-_
4
EXTERNAL REFERENCE INPUT (REF)
V
+
DD
0.05
Reference Input-Voltage Range
V
1
REF
ILR
Reference Input Leakage
Current
I
Conversion stopped
0.005
5
Q1
FA
Reference Input Capacitance
C
pF
REF
DIGITAL INPUTS (SCLK, CS, CHSEL)
0.75 x
Digital Input-High Voltage
Digital Input-Low Voltage
Digital Input Hysteresis
V
V
V
V
IH
V
OVDD
0.25 x
V
IL
V
OVDD
0.15 x
V
HYST
V
OVDD
0.001
2
Digital Input Leakage Current
Digital Input Capacitance
DIGITAL OUTPUT (DOUT)
I
IL
Inputs at GND or V
Q1
FA
DD
C
pF
IN
0.85 x
Output-High Voltage
Output-Low Voltage
V
I
I
= 200µA
SOURCE
V
V
OH
V
OVDD
0.15 x
V
= 200µA
SINK
OL
V
OVDD
High-Impedance Leakage
Current
I
Q1.0
FA
pF
OL
High-Impedance Output
Capacitance
C
OUT
4
_______________________________________________________________________________________
7
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11106) (continued)
(V
DD
= 2.2V to 3.6V, V
= V , V
= V , f
= 48MHz, 50% duty cycle, 3Msps; C
= 10pF, T = -40NC to +125NC,
DOUT A
REF
DD OVDD
DD SCLK
unless otherwise noted. Typical values are at T = +25NC.)
A
PARAMETER
POWER SUPPLY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Positive Supply Voltage
Digital I/O Supply Voltage
V
2.2
1.5
3.6
V
V
DD
V
V
DD
OVDD
I
V
V
= V
GND
3.3
Positive Supply Current (Full-
Power Mode)
VDD
AIN_
mA
mA
I
= V
0.33
OVDD
AIN_
GND
Positive Supply Current (Full-
Power Mode), No Clock
I
1.98
VDD
Power-Down Current
Line Rejection
I
Leakage only
= +2.2V to +3.6V, V
1.3
10
FA
PD
V
= 2.2V
REF
0.17
LSB/V
DD
TIMING CHARACTERISTICS (Note 1)
Quiet Time
t
(Note 2)
(Note 2)
(Note 2)
4
10
5
ns
ns
ns
Q
t
CS Pulse Width
1
2
t
CS Fall to SCLK Setup
CS Falling Until DOUT High-
Impedance Disabled
t
t
(Note 2)
1
ns
ns
3
4
V
V
= 2.2V - 3.6V
= 1.5V - 2.2V
15
16.5
60
Data Access Time After SCLK
Falling Edge (Figure 2)
OVDD
OVDD
SCLK Pulse Width Low
SCLK Pulse Width High
t
t
Percentage of clock period (Note 2)
Percentage of clock period (Note 2)
40
40
%
%
5
6
60
Data Hold Time From SCLK
Falling Edge
t
t
Figure 3
5
ns
7
8
SCLK Falling Until DOUT High-
Impedance
Figure 4 (Note 2)
2.5
14
1
ns
Power-Up Time
Conversion cycle (Note 2)
Cycle
ELECTRICAL CHARACTERISTICS (MAX11110/MAX11117)
(V
DD
= 2.2V to 3.6V. MAX11110: f
= 32MHz, 50% duty cycle, 2Msps. MAX11117: f
= 48MHz, 50% duty cycle, 3Msps.
SCLK
SCLK
C
DOUT
= 10pF, T = -40NC to +125NC, unless otherwise noted. Typical values are at T = +25NC.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
10
Bits
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
INL
Q1
Q1
DNL
No missing codes
MAX11117
MAX11110
Q0.5
Q0.3
Q1.65
Q1.2
Offset Error
OE
LSB
Excluding offset and reference errors,
MAX11117
Q0.7
Q1.4
Q1
Gain Error
GE
LSB
LSB
Excluding offset and reference errors,
MAX11110
Q0.15
Q1
Total Unadjusted Error
TUE
8
______________________________________________________________________________________
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11110/MAX11117) (continued)
(V
DD
= 2.2V to 3.6V. MAX11110: f
= 32MHz, 50% duty cycle, 2Msps. MAX11117: f
= 48MHz, 50% duty cycle, 3Msps.
SCLK
SCLK
C
DOUT
= 10pF, T = -40NC to +125NC, unless otherwise noted. Typical values are at T = +25NC.)
A
A
PARAMETER
SYMBOL
CONDITIONS
= 1MHz, MAX11110: f = 0.5MHz)
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE (MAX11117: f
AIN
AIN
MAX11117
MAX11110
MAX11117
MAX11110
MAX11117
MAX11110
MAX11117
MAX11110
59
60.5
59
61.5
61.5
61.5
61.5
-85
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
SINAD
dB
dB
dB
dB
dB
SNR
THD
SFDR
IMD
60.5
-74
-73
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
-85
75
75
MAXX11117: f = 1.0003MHz, f = 0.99955MHz
MAX11110: f = 500.15kHz, f = 499.56kHz
1
2
-82
1
2
Full-Power Bandwidth
Full-Linear Bandwidth
Small-Signal Bandwidth
CONVERSION RATE
-3dB point
40
2.5
45
MHz
MHz
MHz
SINAD > 60dB
MAX11117
MAX11110
MAX11117
MAX11110
0.03
0.02
260
391
52
3
2
Throughput
Msps
ns
Conversion Time
Acquisition Time
Aperture Delay
Aperture Jitter
t
ns
ns
ps
ACQ
4
From CS falling edge
15
MAX11117
MAX11110
0.48
0.32
48
32
Serial Clock Frequency
f
MHz
CLK
ANALOG INPUT (AIN)
Input Voltage Range
Input Leakage Current
V
0
V
V
AIN
DD
I
0.002
20
Q1
FA
ILA
Track
Hold
Input Capacitance
C
pF
AIN
4
DIGITAL INPUTS (SCLK, CS, CHSEL)
0.75 x
Digital Input-High Voltage
Digital Input-Low Voltage
Digital Input Hysteresis
V
V
V
V
IH
V
DD
0.25 x
V
IL
V
DD
0.15 x
V
HYST
V
DD
Digital Input Leakage Current
Digital Input Capacitance
I
Inputs at GND or V
0.001
2
Q1
FA
IL
DD
C
pF
IN
_______________________________________________________________________________________
9
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11110/MAX11117) (continued)
(V
DD
= 2.2V to 3.6V. MAX11110: f
= 32MHz, 50% duty cycle, 2Msps. MAX11117: f
= 48MHz, 50% duty cycle, 3Msps.
SCLK
SCLK
C
DOUT
= 10pF, T = -40NC to +125NC, unless otherwise noted. Typical values are at T = +25NC.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUT (DOUT)
0.85 x
Output-High Voltage
V
I
= 200µA
SOURCE
V
V
OH
V
DD
0.15 x
Output-Low Voltage
V
I = 200µA
SINK
OL
OL
V
DD
High-Impedance Leakage
Current
I
Q1.0
FA
pF
High-Impedance Output
Capacitance
C
OUT
4
POWER SUPPLY
Positive Supply Voltage
V
2.2
3.6
3.55
2.6
V
DD
MAX11117, V
MAX11110, V
MAX11117
= V
= V
Positive Supply Current
(Full-Power Mode)
AIN
GND
I
mA
VDD
AIN
GND
1.98
1.48
1.3
Positive Supply Current
(Full-Power Mode), No Clock
I
mA
VDD
MAX11110
Power-Down Current
Line Rejection
I
Leakage only
10
FA
PD
V
DD
= +2.2V to +3.6V
0.17
LSB/V
TIMING CHARACTERISTICS (Note 1)
Quiet Time
t
(Note 2)
(Note 2)
(Note 2)
4
10
5
ns
ns
ns
Q
t
CS Pulse Width
1
2
t
CS Fall to SCLK Setup
CS Falling Until DOUT High-
Impedance Disabled
t
t
(Note 2)
1
ns
ns
3
4
Data Access Time After SCLK
Falling Edge
Figure 2, V
= +2.2V to +3.6V
15
DD
SCLK Pulse Width Low
SCLK Pulse Width High
t
t
Percentage of clock period (Note 2)
Percentage of clock period (Note 2)
40
40
60
60
%
%
5
6
Data Hold Time From SCLK
Falling Edge
t
t
Figure 3
5
ns
7
8
SCLK Falling Until DOUT High-
Impedance
Figure 4 (Note 2)
2.5
14
1
ns
Power-Up Time
Conversion cycle (Note 2)
Cycle
10 _____________________________________________________________________________________
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11111)
(V
DD
= 2.2V to 3.6V, V
= V , V
= V , f
= 48MHz, 50% duty cycle, 3Msps, C
= 10pF, T = -40NC to +125NC,
A
REF
DD OVDD
DD SCLK
DOUT
MIN
8
unless otherwise noted. Typical values are at T = +25NC.)
A
PARAMETER
DC ACCURACY
SYMBOL
CONDITIONS
TYP
MAX
UNITS
Resolution
Bits
LSB
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
DNL
OE
Q0.15
Q0.15
Q0.7
No missing codes
Excluding offset and reference errors
0.45
0
Gain Error
GE
Q0.2
Total Unadjusted Error
TUE
0.5
Channel-to-Channel Offset
Matching
0.01
0.01
LSB
LSB
Channel-to-Channel Gain
Matching
DYNAMIC PERFORMANCE
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
Full-Linear Bandwidth
Small-Signal Bandwidth
Crosstalk
SINAD
SNR
f
f
f
f
= 1MHz
= 1MHz
= 1MHz
= 1MHz
49
49
49.8
49.8
-75
67
dB
dB
AIN_
AIN_
AIN_
AIN_
THD
-67
dB
SFDR
IMD
63
dB
f = 1.0003MHz, f = 0.99955MHz
-65
40
dB
1
2
-3dB point
SINAD > 49dB
MHz
MHz
MHz
dB
2.5
45
-90
CONVERSION RATE
Throughput
0.03
260
52
3
Msps
ns
Conversion Time
Acquisition Time
t
ns
ACQ
Aperture Delay
4
ns
From CS falling edge
Aperture Jitter
15
ps
Serial-Clock Frequency
ANALOG INPUT (AIN1, AIN2)
Input Voltage Range
Input Leakage Current
f
0.48
0
48
MHz
CLK
V
V
REF
V
AIN_
I
0.002
20
Q1
FA
ILA
Track
Hold
Input Capacitance
C
pF
V
AIN_
4
EXTERNAL REFERENCE INPUT (REF)
V
+
DD
0.05
Reference Input Voltage Range
V
I
1
REF
Reference Input Leakage Current
Reference Input Capacitance
Conversion stopped
0.005
5
Q1
FA
ILR
C
pF
REF
______________________________________________________________________________________ 11
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11111) (continued)
(V
DD
= 2.2V to 3.6V, V
= V , V
= V , f
= 48MHz, 50% duty cycle, 3Msps, C
= 10pF, T = -40NC to +125NC,
DOUT A
REF
DD OVDD
DD SCLK
unless otherwise noted. Typical values are at T = +25NC.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
0.75 x
TYP
MAX
UNITS
DIGITAL INPUTS (SCLK, CS)
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Hysteresis
V
IH
V
V
V
V
OVDD
0.25 x
V
IL
V
OVDD
0.15 x
V
HYST
V
OVDD
0.001
Digital Input Leakage Current
Digital Input Capacitance
DIGITAL OUTPUT (DOUT)
I
Inputs at GND or V
Q1
FA
IL
DD
C
IN
2
pF
0.85 x
Output High Voltage
Output Low Voltage
V
I
I
= 200µA (Note 2)
SOURCE
V
V
OH
V
OVDD
0.15 x
V
= 200µA (Note 2)
SINK
OL
V
OVDD
High-Impedance Leakage
Current
High-Impedance Output
Capacitance
I
Q1.0
FA
pF
OL
C
OUT
4
POWER SUPPLY
Positive Supply Voltage
Digital I/O Supply Voltage
V
2.2
1.5
3.6
V
V
DD
V
V
DD
OVDD
I
V
V
= V
GND
3.3
Positive Supply Current
(Full-Power Mode)
VDD
AIN_
mA
mA
I
= V
0.33
OVDD
AIN_
GND
Positive Supply Current
(Full-Power Mode), No Clock
I
1.98
VDD
Power-Down Current
Line Rejection
I
Leakage only
= +2.2V to +3.6V, V
1.3
10
FA
PD
V
= 2.2V
REF
0.17
LSB/V
DD
TIMING CHARACTERISTICS (Note 1)
Quiet Time
t
(Note 2)
(Note 2)
(Note 2)
4
10
5
ns
ns
ns
Q
t
CS Pulse Width
1
2
t
CS Fall to SCLK Setup
CS Falling Until DOUT High-
Impedance Disabled
t
(Note 2)
1
ns
ns
3
4
V
V
= 2.2V - 3.6V
= 1.5V - 2.2V
15
16.5
60
Data Access Time After SCLK
Falling Edge (Figure 2)
OVDD
t
OVDD
SCLK Pulse Width Low
SCLK Pulse Width High
t
t
Percentage of clock period (Note 2)
Percentage of clock period (Note 2)
40
40
%
%
5
60
6
Data Hold Time From SCLK
Falling Edge
SCLK Falling Until DOUT High-
Impedance
t
Figure 3
5
ns
7
8
t
Figure 4 (Note 2)
2.5
14
1
ns
Power-Up Time
Conversion cycle (Note 2)
Cycle
12 _____________________________________________________________________________________
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11115/MAX11116)
(V
DD
= 2.2V to 3.6V. MAX11115: f
= 32MHz, 50% duty cycle, 2Msps. MAX11116: f
= 48MHz, 50% duty cycle, 3Msps.
SCLK
SCLK
C
DOUT
= 10pF, T = -40NC to +125NC, unless otherwise noted. Typical values are at T = +25NC.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
8
Bits
LSB
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
DNL
OE
Q0.25
Q0.25
Q0.75
Q0.5
No missing codes
Excluding offset and reference errors
Q0.45
Q0.04
Q0.75
Gain Error
GE
Total Unadjusted Error
TUE
DYNAMIC PERFORMANCE (MAX11116: f
= 1MHz MAX11115: f = 500kHz)
AIN
AIN
MAX11116
49
49
49
49
49.5
49.5
49.5
49.5
-70
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
SINAD
dB
dB
dB
dB
dB
MAX11115
MAX11116
SNR
THD
SFDR
IMD
MAX11115
MAX11116
-66
-67
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
MAX11115
-75
MAX11116
63
63
66
MAX11115
66
MAX11116: f = 1.0003MHz, f = 0.99955MHz
MAX11115: f = 500.15kHz, f = 499.56kHz
1
2
-65
1
2
Full-Power Bandwidth
Full-Linear Bandwidth
Small-Signal Bandwidth
CONVERSION RATE
-3dB point
40
2.5
45
MHz
MHz
MHz
SINAD > 49dB
MAX11116
MAX11115
MAX11116
MAX11115
0.03
0.02
260
391
52
3
2
Throughput
Msps
ns
Conversion Time
Acquisition Time
Aperture Delay
Aperture Jitter
t
ns
ns
ps
ACQ
4
From CS falling edge
15
MAX11116
MAX11115
0.48
0.32
48
32
Serial-Clock Frequency
f
MHz
CLK
ANALOG INPUT (AIN)
Input Voltage Range
Input Leakage Current
V
0
V
V
AIN
DD
I
0.002
20
Q1
FA
ILA
Track
Hold
Input Capacitance
C
pF
V
AIN
4
DIGITAL INPUTS (SCLK, CS)
0.75 x
DD
Digital Input High Voltage
V
IH
V
______________________________________________________________________________________ 13
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11115/MAX11116) (continued)
(V
DD
= 2.2V to 3.6V. MAX11115: f
= 32MHz, 50% duty cycle, 2Msps. MAX11116: f
= 48MHz, 50% duty cycle, 3Msps.
SCLK
SCLK
C
DOUT
= 10pF, T = -40NC to +125NC, unless otherwise noted. Typical values are at T = +25NC.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.25 x
Digital Input Low Voltage
Digital Input Hysteresis
V
V
IL
V
DD
0.15
V
V
HYST
V
DD
Digital Input Leakage Current
Digital Input Capacitance
DIGITAL OUTPUT (DOUT)
I
Inputs at GND or V
0.001
2
Q1
FA
IL
DD
C
pF
IN
0.85 x
Output High Voltage
Output Low Voltage
V
I
= 200µA
SOURCE
V
V
OH
V
DD
0.15 x
V
I = 200µA
SINK
OL
OL
V
DD
High-Impedance Leakage
Current
I
Q1.0
FA
pF
High-Impedance Output
Capacitance
C
OUT
4
POWER SUPPLY
Positive Supply Voltage
V
2.2
3.6
3.55
2.6
V
DD
MAX11116, V
MAX11115, V
MAX11116
= V
Positive Supply Current (Full-
Power Mode)
AIN
GND
I
mA
VDD
= V
AIN
GND
1.98
1.48
1.3
Positive Supply Current (Full-
Power Mode), No Clock
I
mA
VDD
MAX11115
Power-Down Current
Line Rejection
I
Leakage only
10
FA
PD
V
DD
= +2.2V to +3.6V
0.17
LSB/V
TIMING CHARACTERISTICS (Note 1)
Quiet Time
t
(Note 2)
(Note 2)
(Note 2)
4
10
5
ns
ns
ns
Q
t
CS Pulse Width
1
2
t
CS Fall to SCLK Setup
CS Falling Until DOUT High-
Impedance Disabled
t
t
(Note 2)
1
ns
ns
3
4
Data Access Time After SCLK
Falling Edge
Figure 2, V
= +2.2V to +3.6V
15
DD
SCLK Pulse Width Low
SCLK Pulse Width High
t
t
Percentage of clock period (Note 2)
Percentage of clock period (Note 2)
40
40
60
60
%
%
5
6
Data Hold Time From SCLK
Falling Edge
t
t
Figure 3
5
ns
7
8
SCLK Falling Until DOUT High-
Impedance
Figure 4 (Note 2)
2.5
14
1
ns
Power-Up Time
Conversion cycle (Note 2)
Cycle
Note 1: All timing specifications given are with a 10pF capacitor.
Note 2: Guaranteed by design in characterization; not production tested.
14 _____________________________________________________________________________________
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
SAMPLE
SAMPLE
t
1
t
6
t
5
CS
t
2
SCLK
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
HIGH
IMPEDANCE
HIGH
IMPEDANCE
DOUT
(MSB)
t
3
t
t
t
t
4
7
8 QUIET
t
t
ACQ
CONVERT
1/f
SAMPLE
Figure 1. Interface Signals for Maximum Throughput, 12-Bit Devices
t
7
t
4
SCLK
DOUT
SCLK
DOUT
V
V
IH
IL
V
IH
OLD DATA
NEW DATA
OLD DATA
NEW DATA
V
IL
Figure 3. Hold Time After SCLK Falling Edge
Figure 2. Setup Time After SCLK Falling Edge
t
8
SCLK
HIGH IMPEDANCE
DOUT
Figure 4. SCLK Falling Edge DOUT Three-State
______________________________________________________________________________________ 15
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
µMAX Typical Operating Characteristics
(MAX11103AUB+, T = +25°C, unless otherwise noted.)
A
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
OFFSET ERROR vs. TEMPERATURE
1.0
0.5
0
1.0
0.5
0
3
2
f
S
= 3.0Msps
f
S
= 3.0Msps
1
0
-1
-2
-3
-0.5
-1.0
-0.5
-1.0
0
1000
2000
3000
4000
0
1000
2000
3000
4000
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (˚C)
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
GAIN ERROR vs. TEMPERATURE
HISTOGRAM FOR 30,000 CONVERSIONS
3
2
35,000
30,000
25,000
20,000
15,000
10,000
5000
1
0
-1
-2
-3
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (˚C)
2046
2047
2048
2049
2050
DIGITAL CODE OUTPUT
SNR AND SINAD
vs. ANALOG INPUT FREQUENCY
THD vs. ANALOG INPUT FREQUENCY
75
74
73
72
71
70
-60
-70
f
S
= 3Msps
f = 3Msps
S
SNR
-80
-90
SINAD
-100
-110
-120
0
300
600
f
900
(kHz)
1200
1500
0
300
600
f
900
(kHz)
1200
1500
IN
IN
16 _____________________________________________________________________________________
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
µMAX Typical Operating Characteristics (continued)
(MAX11103AUB+, T = +25°C, unless otherwise noted.)
A
SFDR vs. ANALOG INPUT FREQUENCY
THD vs. INPUT RESISTANCE
130
120
110
100
90
-70
-75
f
f
= 3.0Msps
S
f
S
= 3Msps
= 1.0183MHz
IN
-80
-85
-90
80
-95
70
-100
0
300
600
900
(kHz)
1200
1500
0
20
40
60
80
100
f
IN
R (I)
IN
REFERENCE CURRENT
vs. SAMPLING RATE
1MHz SINE-WAVE INPUT
(16,834-POINT FFT PLOT)
200
150
100
50
0
-20
f
f
= 3.0Msps
= 1.0183MHz
S
IN
-40
-60
A
= -91.2dB
HD3
250
-80
A
= -110.3dB
HD2
-100
-120
0
0
500 1000 1500 2000 2500 3000
(ksps)
0
500
750
1000
1250
1500
f
FREQUENCY (kHz)
S
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
SNR vs. REFERENCE VOLTAGE
73.5
73.0
72.5
72.0
71.5
71.0
3.5
3.2
2.9
2.6
2.3
2.0
f
= 3Msps
= 1.0183MHz
S
f
IN
V
= 3.6V
DD
V
V
= 3.0V
DD
DD
= 2.2V
5
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
(V)
-40 -25 -10
20 35 50 65 80 95 110 125
V
REF
TEMPERATURE (˚C)
______________________________________________________________________________________ 17
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
SOT Typical Operating Characteristics
(MAX11105AUB+, T = +25°C, unless otherwise noted.)
A
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
1.0
1.0
0.5
0
f
= 2.0Msps
f
= 2.0Msps
S
S
0.5
0
-0.5
-1.0
-0.5
-1.0
0
1000
2000
3000
4000
0
1000
2000
3000
4000
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
OFFSET ERROR vs. TEMPERATURE
GAIN ERROR vs. TEMPERATURE
3
2
2
1
1
0
0
-1
-2
-3
-4
-1
-2
-3
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (˚C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (˚C)
SNR AND SINAD
vs. ANALOG INPUT FREQUENCY
HISTOGRAM FOR 30,000 CONVERSIONS
73.5
73.0
72.5
72.0
71.5
35,000
30,000
25,000
20,000
15,000
10,000
5000
f
S
= 2.0Msps
SNR
SINAD
0
0
200
400
f
600
(kHz)
800
1000
2046
2047
2048
2049
2050
DIGITAL CODE OUTPUT
IN
18 _____________________________________________________________________________________
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
SOT Typical Operating Characteristics (continued)
(MAX11105AUB+, T = +25°C, unless otherwise noted.)
A
THD vs. ANALOG INPUT FREQUENCY
SFDR vs. ANALOG INPUT FREQUENCY
-80
110
105
100
95
f
S
= 2.0Msps
f = 2.0Msps
S
-85
-90
-95
-100
-105
-110
90
85
80
0
200
400
600
(kHz)
800
1000
0
200
400 600
f (kHz)
IN
800
1000
f
IN
500kHz SINE-WAVE INPUT
(16,834-POINT FFT PLOT)
THD vs. INPUT RESISTANCE
0
-20
-75
-80
f
f
= 2.0Msps
= 500.122kHz
f
f
= 2.0Msps
= 500.122kHz
S
S
IN
IN
-40
-85
-60
A
HD3
= -96.5dB
A
HD2
= -92.0dB
-90
-80
-95
-100
-120
-100
0
250
500
FREQUENCY (kHz)
750
1000
0
20
40
60
80
100
R
(I)
IN
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
SNR vs. REFERENCE VOLTAGE (V
)
DD
75
74
73
72
71
2.6
2.4
2.2
2.0
1.8
1.6
f
f
= 2.0Msps
S
V
V
= 3.6V
DD
= 500.122kHz
IN
= 3.0V
DD
V
= 2.2V
DD
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
(V)
-40 -25 -10
5
20 35 50 65 80 95 110 125
V
DD
TEMPERATURE (˚C)
______________________________________________________________________________________ 19
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Pin Configurations
TOP VIEW
TOP VIEW
TOP VIEW
+
V
1
2
3
6
5
4
CS
DD
+
+
AIN1
1
2
3
4
5
10
9
SCLK
DOUT
OVDD
CHSEL
CS
AIN1
AIN2
AGND
REF
1
10 SCLK
MAX11105
MAX11110
MAX11115
MAX11116
MAX11117
AIN2
AGND
REF
GND
AIN
DOUT
SCLK
2
3
4
5
9
8
7
6
DOUT
OVDD
CHSEL
CS
MAX11102
MAX11103
8
MAX11102
MAX11103
MAX11106
MAX11111
7
V
DD
6
EP*
SOT23
µMAX
EP*
V
DD
TDFN
*CONNECT EXPOSED PAD TO GROUND PLANE. DEVICES DO NOT OPERATE WHEN EP IS NOT CONNECTED TO GROUND!
Pin Description
PIN
NAME
AIN1
FUNCTION
TDFN
µMAX
SOT23
Analog Input Channel 1. Single-ended analog input with respect to AGND with range
of 0V to V
1
1
—
.
REF
Analog Input Channel 2. Single-ended analog input with respect to AGND with range
of 0V to V
2
2
—
3
AIN2
REF.
Analog Input Channel. Single-ended analog input with respect to GND with range of
0V to V
—
—
AIN
DD.
—
3
—
3
2
GND
Ground. Connect GND to the GND ground plane.
—
AGND Analog Ground. Connect AGND directly the GND ground plane.
External Reference Input. REF defines the signal range of the input signal AIN1/AIN2:
4
5
4
5
—
1
REF
0V to V
capacitor.
. The range of V
is 1V to V
Bypass REF to AGND with 10FF || 0.1FF
REF
REF
DD.
Positive Supply Voltage. Bypass V
range is 2.2V to 3.6V. For the SOT23 package, V
with a 10FF || 0.1FF capacitor to GND. V
DD
DD
V
also defines the signal range of
DD
DD
the input signal AIN: 0V to V
.
DD
Active-Low Chip-Select Input. The falling edge of CS samples the analog input signal,
starts a conversion, and frames the serial data transfer.
6
7
6
7
6
—
—
5
CS
Channel Select. Set CHSEL high to select AIN2 for conversion. Set CHSEL low to
select AIN1 for conversion.
CHSEL
OVDD
DOUT
SCLK
GND
Digital Interface Supply for SCLK, CS, DOUT, and CHSEL. The OVDD range is 1.5V
8
8
to V . Bypass OVDD with a 10FF || 0.1FF capacitor to GND.
DD
Three-State Serial Data Output. ADC conversion results are clocked out on the falling
edge of SCLK, MSB first. See Figure 1.
9
9
Serial Clock Input. SCLK drives the conversion process. DOUT is updated on the fall-
ing edge of SCLK. See Figures 2 and 3.
10
—
10
—
4
Exposed Pad (TDFN and FMAX only). Connect EP directly to a solid ground plane.
Devices do not operate unless EP is connected to ground!
EP
20 _____________________________________________________________________________________
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Functional Diagrams
V
OVDD
V
DD
DD
MAX11105/MAX11110/
MAX11115/MAX11116/
MAX11117
CS
CS
MAX11102/MAX11103/
MAX11106/MAX11111
CONTROL
LOGIC
CONTROL
LOGIC
SCLK
SCLK
DOUT
OUTPUT
BUFFER
DOUT
OUTPUT
BUFFER
SAR
SAR
CHSEL
AIN
AIN1
AIN2
CDAC
= V
MUX
CDAC
V
REF
REF
DD
AGND
GND (EP)
GND
Typical Operating Circuit
V
DD
OVDD
V
OVDD
+3V
AIN1
AIN2
MAX11102
MAX11103
MAX11106
MAX11111
SCLK
DOUT
SCK
CPU
ANALOG
INPUTS
MISO
SS
AGND
REF
CS
+2.5V
CHSEL
GND (EP)
V
DD
SCLK
DOUT
SCK
+3V
MAX11105
MAX11110
MAX11115
MAX11116
MAX11117
MISO
SS
CPU
GND
AIN
CS
ANALOG
INPUT
______________________________________________________________________________________ 21
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
These ADCs include a power-down feature allowing
Detailed Description
minimized power consumption at 2.5FA/ksps for lower
throughput rates. The wake-up and power-down feature
is controlled by using the SPI interface as described in
the Operating Modes section.
The MAX11102/MAX11103/MAX11105/MAX11106/MAX11110/
MAX11111/MAX11115/MAX11116/MAX11117 are fast,
12-/10-/8-bit, low-power, single-supply ADCs. The
devices operate from a 2.2V to 3.6V supply and con-
Serial Interface
The devices feature a 3-wire serial interface that directly
connects to SPI, QSPI, and MICROWIRE devices without
external logic. Figures 1 and 5 show the interface sig-
nals for a single conversion frame to achieve maximum
throughput.
sume only 8.3mW (V
= 3V)/5.2mW (V
= 2.2V) at
= 2.2V) at
DD
DD
3Msps and 6.2mW (V
DD
= 3V)/3.7mW (V
DD
2Msps. The 3Msps devices are capable of sampling
at full rate when driven by a 48MHz clock and the
2Msps devices can sample at full rate when driven by
a 32MHz clock. The dual-channel devices provide a
separate digital supply input (OVDD) to power the digi-
tal interface enabling communication with 1.5V, 1.8V,
2.5V, or 3V digital systems.
The falling edge of CS defines the sampling instant.
Once CS transitions low, the external clock signal
(SCLK) controls the conversion.
The conversion result appears at DOUT, MSB first, with a
leading zero followed by the 12-bit, 10-bit, or 8-bit result.
A 12-bit result is followed by two trailing zeros, a 10-bit
result is followed by four trailing zeros, and an 8-bit result
is followed by six trailing zeros. See Figures 1 and 5.
The SAR core successively extracts binary-weighted bits
in every clock cycle. The MSB appears on the data bus
during the 2nd clock cycle with a delay outlined in the
timing specifications. All extracted data bits appear suc-
cessively on the data bus with the LSB appearing during
the 13th/11th/9th clock cycle for 12-/10-/8-bit operation.
The serial data stream of conversion bits is preceded by
a leading “zero” and succeeded by trailing “zeros.” The
data output (DOUT) goes into high-impedance state dur-
ing the 16th clock cycle.
The dual-channel devices feature a dedicated refer-
ence input (REF). The input signal range for AIN1/AIN2
is defined as 0V to V
with respect to AGND. The
REF
single-channel devices use V
as the reference. The
DD
input signal range of AIN is defined as 0V to V
respect to GND.
with
DD
SAMPLE
SAMPLE
CS
SCLK
DOUT
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
HIGH
IMPEDANCE
HIGH
IMPEDANCE
SAMPLE
SAMPLE
CS
SCLK
DOUT
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
HIGH
IMPEDANCE
HIGH
IMPEDANCE
Figure 5. 10-/8-Bit Timing Diagrams
22 _____________________________________________________________________________________
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
To sustain the maximum sample rate, all devices have to
The source impedance of the external driving stage in
conjunction with the sampling switch resistance affects
the settling performance. The THD vs. Input Resistance
graph in the Typical Operating Characteristics shows
THD sensitivity as a function of the signal source imped-
ance. Keep the source impedance at a minimum for
high-dynamic performance applications. Use a high-
performance op amp such as the MAX4430 to drive the
analog input, thereby decoupling the signal source and
the ADC.
be resampled immediately after the 16th clock cycle. For
lower sample rates, the CS falling edge can be delayed
leaving DOUT in a high-impedance condition. Pull CS
high after the 10th SCLK falling edge (see the Operating
Modes section).
Analog Input
The devices produce a digital output that corresponds to
the analog input voltage within the specified operating
range of 0 to V
for the dual-channel devices and 0 to
REF
While the ADC is in conversion mode, the sampling
V
DD
for the single-channel devices.
switch is open presenting a pin capacitance, C (C
P
P
Figure 6 shows an equivalent circuit for the analog input
AIN (for single-channel devices) and AIN1/AIN2 (for
dual-channel devices). Internal protection diodes D1/D2
confine the analog input voltage within the power rails
= 5pF), to the driving stage. See the Applications
Information section for information on choosing an
appropriate buffer for the ADC.
(V , GND). The analog input voltage can swing from
ADC Transfer Function
The output format is straight binary. The code transi-
tions midway between successive integer LSB values
DD
GND - 0.3V to V
+ 0.3V without damaging the device.
DD
The electric load presented to the external stage driv-
ing the analog input varies depending on which mode
the ADC is in: track mode vs. conversion mode. In track
such as 0.5 LSB, 1.5 LSB, etc. The LSB size for single-
n
channel devices is V /2 and for dual-channel devices
DD
n
is V
/2 , where n is the resolution. The ideal transfer
REF
mode, the internal sampling capacitor C (16pF) has to
S
characteristic is shown in Figure 10.
be charged through the resistor R (R = 50I) to the input
voltage. For faithful sampling of the input, the capacitor
Operating Modes
voltage on C has to settle to the required accuracy dur-
S
The ICs offer two modes of operation: normal mode and
power-down mode. The logic state of the CS signal
during a conversion activates these modes. The power-
down mode can be used to optimize power dissipation
with respect to sample rate.
ing the track time.
SWITCH CLOSED IN TRACK MODE
SWITCH OPEN IN CONVERSION MODE
V
DD
Normal Mode
In normal mode, the devices are powered up at all times,
thereby achieving their maximum throughput rates.
Figure 7 shows the timing diagram of these devices in
normal mode. The falling edge of CS samples the analog
input signal, starts a conversion, and frames the serial
data transfer.
D1
D2
C
S
R
AIN1/AIN2
AIN
C
P
Figure 6. Analog Input Circuit
KEEP CS LOW UNTIL AFTER THE 10TH SCLK FALLING EDGE
PULL CS HIGH AFTER THE 10TH SCLK FALLING EDGE
CS
SCLK
DOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VALID DATA
HIGH
HIGH
IMPEDANCE
IMPEDANCE
Figure 7. Normal Mode
______________________________________________________________________________________ 23
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
PULL CS HIGH AFTER THE 2ND AND BEFORE THE 10TH SCLK FALLING EDGE
CS
SCLK
DOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
HIGH
IMPEDANCE
INVALID
DATA
INVALID DATA OR HIGH IMPEDANCE
HIGH IMPEDANCE
Figure 8. Entering Power-Down Mode
CS
SCLK
DOUT
HIGH
IMPEDANCE
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
N
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
INVALID DATA (DUMMY CONVERSION)
VALID DATA
HIGH
IMPEDANCE
HIGH
IMPEDANCE
Figure 9. Exiting Power-Down Mode
edge terminates the conversion, DOUT goes into high-
impedance mode, and the device enters power-down
mode. See Figure 8.
OUTPUT CODE
FS - 1.5 x LSB
111...111
111...110
111...101
Power-Down Mode
In power-down mode, all bias circuitry is shut down
drawing typically only 1.3FA of leakage current. To save
power, put the device in power-down mode between
conversions. Using the power-down mode between
conversions is ideal for saving power when sampling the
analog input infrequently.
Entering Power-Down Mode
To enter power-down mode, drive CS high between the
2nd and 10th falling edges of SCLK (see Figure 8). By
pulling CS high, the current conversion terminates and
DOUT enters high impedance.
000...010
000...001
000...000
ANALOG
INPUT (LSB)
n
n
n
0
1
2
3
2 -2 2 -1 2
Exiting Power-Down Mode
To exit power-down mode, implement one dummy con-
version by driving CS low for at least 10 clock cycles
(see Figure 9). The data on DOUT is invalid during this
dummy conversion. The first conversion following the
dummy cycle contains a valid conversion result.
FULL SCALE (FS):
AIN1/AIN2 = REF (TDFN, µMax)
AIN = V (SOT)
DD
n = RESOLUTION
Figure 10. ADC Transfer Function
The power-up time equals the duration of the dummy
cycle, and is dependent on the clock frequency. The
power-up time for 3Msps operation (48MHz SCLK) is
333ns. The power-up time for 2Msps operation (32MHz
SCLK) is 500ns.
To remain in normal mode, keep CS low until the falling
edge of the 10th SCLK cycle. Pulling CS high after the
10th SCLK falling edge keeps the part in normal mode.
However, pulling CS high before the 10th SCLK falling
24 _____________________________________________________________________________________
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
The user can also power down the ADC between con-
versions by using the power-down mode. Figure 12
shows for the 3Msps device that as the sample rate is
reduced, the device remains in the power-down state
Supply Current vs. Sampling Rate
For applications requiring lower throughput rates, the
user can reduce the clock frequency (f ) to lower the
SCLK
sample rate. Figure 11 shows the typical supply current
(I ) as a function of sample rate (f for the 3Msps
longer and the average supply current (I ) drops
VDD
VDD
S)
accordingly. Figure 14 pertains to the 2Msps devices.
devices. The part operates in normal mode and is never
powered down. Figure 13 pertains to the 2Msps devices.
5
4
V
= 3V
V
= 3V
DD
DD
f
= VARIABLE
f
= VARIABLE
SCLK
SCLK
4
3
2
1
0
16 CYCLES/CONVERSION
16 CYCLES/CONVERSION
3
2
1
0
0
500 1000 1500 2000 2500 3000
0
500
1000
1500
2000
f
S
(ksps)
f
S
(ksps)
Figure 11. Supply Current vs. Sample Rate (Normal Operating
Mode, 3Msps Devices)
Figure 13. Supply Current vs. Sample Rate (Normal Operating
Mode, 2Msps Devices)
3.0
2.0
V
= 3V
DD
V
= 3V
= 32MHz
DD
f
= 48MHz
SCLK
f
SCLK
2.5
2.0
1.5
1.0
0.5
0
1.5
1.0
0.5
0
0
200
400
600
(ksps)
800
1000
0
100
200 300
f (ksps)
S
400
500
f
S
Figure 12. Supply Current vs. Sample Rate (Device Powered
Down Between Conversions, 3Msps Devices)
Figure 14. Supply Current vs. Sample Rate (Device Powered
Down Between Conversions, 2Msps Devices)
______________________________________________________________________________________ 25
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Dual-Channel Operation
Applications Information
The MAX11102/MAX11103/MAX11106/MAX11111 fea-
Layout, Grounding, and Bypassing
For best performance, use PCBs with a solid ground
plane. Ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another or digital
ture dual-input channels. These devices use a channel-
select (CHSEL) input to select between analog input AIN1
(CHSEL = 0) or AIN2 (CHSEL = 1). As shown in Figure
15, the CHSEL signal is required to change between the
2nd and 12th clock cycle within a regular conversion to
guarantee proper switching between channels.
lines underneath the ADC package. Noise in the V
DD
power supply, OVDD, and REF affects the ADC’s perfor-
mance. Bypass the V , OVDD, and REF to ground with
0.1FF and 10FF bypass capacitors. Minimize capacitor
lead and trace lengths for best supply-noise rejection.
DD
14-Cycle Conversion Mode
The ICs can operate with 14 cycles per conversion.
Figure 16 shows the corresponding timing diagram.
Observe that DOUT does not go into high-impedance
Choosing an Input Amplifier
It is important to match the settling time of the input
amplifier to the acquisition time of the ADC. The conver-
sion results are accurate when the ADC samples the
input signal for an interval longer than the input signal’s
worst-case settling time. By definition, settling time is
the interval between the application of an input voltage
step and the point at which the output signal reaches
mode. Also, observe that t
needs to be sufficiently
ACQ
long to guarantee proper settling of the analog input
voltage. See the Electrical Characteristics table for t
ACQ
requirements and the Analog Input section for a descrip-
tion of the analog inputs.
CS
SCLK
CHSEL
DOUT
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
DATA CHANNEL AIN2
DATA CHANNEL AIN1
Figure 15. Channel Select Timing Diagram
SAMPLE
SAMPLE
CS
SCLK
DOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
(MSB)
t
ACQ
1/f
SAMPLE
t
CONVERT
Figure 16. 14-Clock Cycle Operation
26 _____________________________________________________________________________________
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
and stays within a given error band centered on the
Choosing a Reference
For devices using an external reference, the choice of
the reference determines the output accuracy of the
ADC. An ideal voltage reference provides a perfect initial
accuracy and maintains the reference voltage indepen-
dent of changes in load current, temperature, and time.
Considerations in selecting a reference include initial
voltage accuracy, temperature drift, current source,
sink capability, quiescent current, and noise. Figure 17
shows a typical application circuit using the MAX6126
to provide the reference voltage. The MAX6033 and
MAX6043 are also excellent choices.
resulting steady-state amplifier output level. The ADC
input sampling capacitor charges during the sampling
cycle, referred to as the acquisition period. During this
acquisition period, the settling time is affected by the
input resistance and the input sampling capacitance.
This error can be estimated by looking at the settling of
an RC time constant using the input capacitance and
the source impedance over the acquisition time period.
Figure 17 shows a typical application circuit. The
MAX4430, offering a settling time of 37ns at 16 bits, is
an excellent choice for this application. See the THD
vs. Input Resistance graph in the Typical Operating
Characteristics.
+5V
0.1µF
10µF
3V
V
OVDD
100pF COG
V
DD
OVDD
500I
10µF
0.1µF
SCK
10µF
0.1µF
AGND
AIN1
500I
5
AIN1
3
10I
1
MAX11102
MAX11103
MAX11106
MAX11111
MAX4430
470pF
COG CAPACITOR
-5V
SCLK
DOUT
CS
V
4
DC
2
AIN2
REF
MISO
SS
470pF
COG CAPACITOR
CPU
+5V
0.1µF
10µF
CHSEL
10µF
+5V
EP
0.1µF
10µF
7
8
2
1
OUTF
OUTS
IN
100pF COG
0.1µF
1µF
500I
0.1µF
MAX6126
4
3
GNDS
NR
500I
5
AIN2
3
4
0.1µF
10I
GND
1
MAX4430
-5V
V
DC
2
0.1µF
10µF
Figure 17. Typical Application Circuit
______________________________________________________________________________________ 27
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Signal-to-Noise Ratio and Distortion
(SINAD)
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. For
these devices, the straight line is a line drawn between
the end points of the transfer function after offset and
gain errors are nulled.
SINAD is a dynamic figure of merit that indicates the
converter’s noise and distortion performance. SINAD
is computed by taking the ratio of the RMS signal to
the RMS noise plus distortion. RMS noise plus distor-
tion includes all spectral components to the Nyquist
frequency excluding the fundamental and the DC offset:
.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A DNL
error specification of 1 LSB or less guarantees no mis-
sing codes and a monotonic transfer function.
SIGNAL
RMS
SINAD(dB) = 20 × log
NOISE + DISTORTION
(
)
RMS
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
Offset Error
The deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, that is, AGND + 0.5 LSB.
Gain Error
The deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal after adjusting for the offset
2
2
2
2
5
V
+ V + V + V
3 4
2
THD = 20 × log
V
1
error, that is, V
- 1.5 LSB.
REF
Aperture Jitter
where V is the fundamental amplitude and V –V are
the amplitudes of the 2nd- through 5th-order harmonics.
1
2
5
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples.
Spurious-Free Dynamic Range (SFDR)
SFDR is a dynamic figure of merit that indicates the low-
est usable input signal amplitude. SFDR is the ratio of
the RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest spuri-
ous component, excluding DC offset. SFDR is specified
in decibels with respect to the carrier (dBc).
Aperture Delay
Aperture delay (t ) is the time between the falling edge
AD
of sampling clock and the instant when an actual sample
is taken.
Signal-to-Noise Ratio (SNR)
SNR is a dynamic figure of merit that indicates the con-
verter’s noise performance. For a waveform perfectly
reconstructed from digital samples, the theoretical maxi-
mum SNR is the ratio of the full-scale analog input (RMS
value) to the RMS quantization error (residual error).
The ideal, theoretical minimum analog-to-digital noise
is caused by quantization error only and results directly
from the ADC’s resolution (N bits):
Full-Power Bandwidth
Full-power bandwidth is the frequency at which the input
signal amplitude attenuates by 3dB for a full-scale input.
Full-Linear Bandwidth
Full-linear bandwidth is the frequency at which the
signal-to-noise ratio and distortion (SINAD) is equal to a
specified value.
SNR (dB) (MAX) = (6.02 x N + 1.76) (dB)
Intermodulation Distortion
Any device with nonlinearities creates distortion prod-
ucts when two sine waves at two different frequencies
In reality, there are other noise sources such as thermal
noise, reference noise, and clock jitter that also degrade
SNR. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spectral
components to the Nyquist frequency excluding the
fundamental, the first five harmonics, and the DC offset.
(f and f ) are applied into the device. Intermodulation
1
2
distortion (IMD) is the total power of the IM2 to IM5 inter-
modulation products to the Nyquist frequency relative to
the total input power of the two input tones, f and f . The
1
2
.
individual input tone levels are at -6dBFS
28 _____________________________________________________________________________________
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Ordering Information (continued)
PART
PIN-PACKAGE
10 TDFN-EP*
6 SOT23
BITS
12
12
10
10
8
SPEED (Msps)
NO. OF CHANNELS
TOP MARK
+AWV
MAX11103ATB+
MAX11105AUT+
MAX11106ATB+
MAX11110AUT+
MAX11111ATB+
MAX11115AUT+
MAX11116AUT+
MAX11117AUT+
3
2
3
2
3
2
3
3
2
1
2
1
2
1
1
1
+ACON
+AWJ
10 TDFN-EP*
6 SOT23
+ACOD
+AWL
10 TDFN-EP*
6 SOT23
8
+ACOP
+ACOX
+ACOY
6 SOT23
8
6 SOT23
10
Note: All devices are specified over the -40°C to +125°C operating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Chip Information
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PROCESS: CMOS
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
10 TDFN-EP
10 µMAX-EP
6 SOT23
T1033+2
U10E+3
U6+1
21-0137
21-0109
21-0058
90-0061
90-0148
90-0175
______________________________________________________________________________________ 29
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
4/10
7/10
9/10
Initial release of the MAX11102/MAX11103/MAX11105/MAX11110/MAX11115
/MAX11116/MAX11117
0
1
2
—
1–30
29
Initial release of the MAX11106/MAX11111.
Corrected the package code of the µMAX package in the Package Information
section.
Changed the typical power consumption to 2.2V in the General Description,
Features, and Detailed Description sections.
3
4
5
10/10
2/11
8/11
1, 22
4, 5, 8, 9, 10,
12, 13, 14, 27
Update style, change voltage in Figure 17.
1, 4, 6, 8, 10,
12, 14, 29
Updated the Ordering Information and Electrical Characteristics sections.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
30
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
©
相关型号：
©2020 ICPDF网 联系我们和版权申明