MAX11060GUU+T [MAXIM]
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| 型号： | MAX11060GUU+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
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19-5741ꢀ Rev 1ꢀ 4/11
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
4K/MAX160
General Description
Features
o Four Fully Differential Simultaneously Sampled
The MAX11040K/MAX11060 are 24-/16-bit, 4-channel,
simultaneous-sampling, sigma-delta analog-to-digital
converters (ADCs). The devices allow simultaneous
sampling of as many as 32 channels using a built-in
cascade feature to synchronize as many as eight
devices. The serial interface of the devices allows read-
ing data from all the cascaded devices using a single
command. Four modulators simultaneously convert
each fully differential analog input with a programmable
data output rate ranging from 0.25ksps to 64ksps. The
devices achieve 106dB SNR at 16ksps and 117dB SNR
at 1ksps (MAX11040K). The devices operate from a
single +3V supply. The differential analog input range is
2.2V when using the internal referenceꢀ an eꢁternal
reference is optional. Each input is overvoltage protect-
ed up to 6V without damage. The devices use an
internal crystal oscillator or an eꢁternal source for clock.
Channels
o Cascadable for Up to 32 Channels of
Simultaneous Sampling
o 106dB (MAX11040K) SNR at 16ksps
o 117dB (MAX11040K) SNR at 1ksps
o 0.25% Error Over a 1000:1 Dynamic Range,
Processed Over 16.7ms (MAX11040K)
o
o
2.2ꢀ FullꢁScale ꢂnput Range
6ꢀ Overvoltage Protected ꢂnputs
o ꢂnternal Crystal Oscillator
o 2.5ꢀ, 50ppm/°C ꢂnternal Reference or External
Reference
o Programmable Output Data Rate
0.25ksps to 64ksps Range
0.065% Resolution
o Programmable Sampling Phase
0 to 333µs Delay in 1.33µs Steps
The devices are compatible with SPI™, QSPI™,
MICROWIRE™, and DSP-compatible 4-wire serial inter-
faces. An on-board interface logic allows one serial inter-
face (with a single chip select) to control up to eight
cascaded devices or 32 simultaneous sampling analog
input channels.
o SPꢂꢁ/QSPꢂꢁ/MꢂCROWꢂREꢁ/DSPꢁCompatible 4ꢁWire
Serial ꢂnterface
o Cascadable ꢂnterface Allows Control of Up to
Eight Devices with a Single CS Signal
o 3.0ꢀ to 3.6ꢀ Analog Supply ꢀoltage
The devices are ideally suited for power-management
systems. Each channel includes an adjustable sam-
pling phase enabling internal compensation for phase
shift due to eꢁternal dividers, transformers, or filters at
the inputs. The output data rate is adjustable with a
0.065% resolution (at 16ksps or below) to track the
varying frequency of a periodic input. A SYNC input
allows periodic alignment of the conversion timing of
multiple devices with a remote timing source.
o 2.7ꢀ to ꢀ
Digital Supply ꢀoltage
AꢀDD
o 38ꢁPin TSSOP Package
Functional Diagram
OVRFLW FAULT
The devices are available in a 38-pin TSSOP package speci-
fied over the -40°C to +105°C industrial temperature range.
AIN0+
AIN0-
SYNC
24-/16-BIT
ADC
DIGITAL
FILTER
Applications
Power-Protection Relay Equipment
Multiphase Power Systems
DRDYIN
REF0
AIN1+
AIN1-
DRDYOUT
24-/16-BIT
ADC
DIGITAL
FILTER
REGISTERS AND
DIGITAL
CONTROL
CASCIN
SERIAL
INTERFACE
CASCOUT
REF1
AIN2+
24-/16-BIT
ADC
DIGITAL
FILTER
Industrial Data-Acquisition Systems
Medical Instrumentation
CS
AIN2-
SCLK
REF2
AIN3+
DIN
24-/16-BIT
ADC
DIGITAL
FILTER
AIN3-
REF3
DOUT
Ordering Information
PART
MAX11040KGUU+ -40°C to +105°C
MAX11060GUU+ -40°C to +105°C
TEMP RANGE
PꢂNꢁPACKAGE
38 TSSOP
MAX11040K
MAX11060
2.5V
REFERENCE
CRYSTAL
OSCILLATOR
REFIO
38 TSSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
AGND
XIN
XOUT
CLKOUT
DGND
MICROWIRE is a trademark of National Semiconductor Corp.
SPI/QSPI are trademarks of Motorola, Inc.
________________________________________________________________ Maxim ꢂntegrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1ꢁ888ꢁ629ꢁ4642,
or visit Maxim’s website at www.maximꢁic.com.
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
ABSOLUTE MAXꢂMUM RATꢂNGS
AVDD to AGND ........................................................-0.3V to +4V
AIN_ _ to AGND (V
< 3V or V
< 2.7V or
AVDD
DVDD
DVDD to DGND......................................-0.3V to (V
AGND to DGND.....................................................-0.3V to +0.3V
+ 0.3V)
FAULTDIS = 1 or SHDN = 1 or
f < 20MHz)........................................-3.5V to +3.5V
XIN CLOCK
AVDD
DIN, SCLK, CS, XIN, SYNC, DRDYIN,
CASCIN to DGND..............................-0.3V to (V
DOUT, DRDYOUT, CASCOUT, CLKOUT,
REFIO, REF_ to AGND............................-0.3V to (V
Maꢁimum Current into Any Pin............................................50mA
+ 0.3V)
AVDD
+ 0.3V)
DVDD
Continuous Power Dissipation (T = +70°C)
A
XOUT to DGND..................................-0.3V to (V
FAULT, OVRFLW to DGND ...................................-0.3V to +4.0V
AIN_+ to AIN_- ......................................................-6.0V to +6.0V
+ 0.3V)
TSSOP (derated 13.7mW/°C above +70°C) ..............1096mW
Operating Temperature Range .........................-40°C to +105°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
DVDD
AIN_ _ to AGND (V
≥ 3V, V
≥ 2.7V, FAULTDIS = 0,
AVDD
DVDD
SHDN = 0, f
≥ 20MHz)....................-6.0V to +6.0V
XIN CLOCK
Stresses beyond those listed under “Absolute Maꢁimum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Eꢁposure to
absolute maꢁimum rating conditions for eꢁtended periods may affect device reliability.
ELECTRꢂCAL CHARACTERꢂSTꢂCS
(V
= +3.0V to +3.6V, V
= +2.7V to V
, f
= 24.576MHz, f
= 16ksps, V
= +2.5V (eꢁternal), C
=
AV
DD
DV
DD
AV
DD XIN CLOCK
OUT
REFIO
REFIO
C
REF0
= C
= C
= C
= 1μF to AGND, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
MAX A
REF1
REF2
REF3
A
MIN
PARAMETER
SYMBOL
CONDꢂTꢂONS
MꢂN
TYP
MAX
UNꢂTS
DC ACCURACY (Note 2)
MAX11040K
MAX11060
24
16
Resolution
Bits
4K/MAX160
24-bit no missing code (MAX11040K)ꢀ
16-bit no missing code (MAX11060)
Differential Nonlinearity
DNL
INL
0.1
LSB
T = +25°C and +105°C (MAX11040K)
A
0.001
0.004
0.006
Integral Nonlinearity (Note 3)
%FS
T
A
= -40°C (MAX11040K)
MAX11060
0.001
Offset Error
-1
-1
+1
+1
mV
%FS
Gain Error
(Note 4)
(Note 5)
(Note 5)
Offset-Error Drift
Gain-Error Drift
0.5
1
ppm/°C
ppm/°C
% FS
Change in Gain Error vs. f
f
= 0.25ksps to 64ksps
< 0.025
0.03
OUT
OUT
Channel-to-Channel Gain Matching
DYNAMꢂC SPECꢂFꢂCATꢂONS (62.5Hz sineꢁwave input, 2.17ꢀ
% FS
)
PꢁP
(Note 6) (MAX11040K)
(Note 6) (MAX11060)
103
106
Signal-to-Noise Ratio
SNR
dB
dB
94.5
T = +25°C and +105°C (MAX11040K)
A
-94
-90
Total Harmonic Distortion
THD
T = -40°C (MAX11040K)
A
MAX11060
T = +25°C and +105°C (MAX11040K)
-106
98
93
89
A
Signal-to-Noise Plus Distortion
SINAD
SFDR
T
A
= -40°C (MAX11040K)
dB
MAX11060
T = +25°C and +105°C (MAX11040K)
94
94
89
100
A
Spurious-Free Dynamic Range
Relative Accuracy (Note 7)
dB
%
T
A
= -40°C (MAX11040K)
MAX11060
100
0.1%FS input (MAX11040K)
6.0%FS input (MAX11040K)
0.25
0.005
2
_______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
4K/MAX160
ELECTRꢂCAL CHARACTERꢂSTꢂCS (continued)
(V
= +3.0V to +3.6V, V
= +2.7V to V
, f
= 24.576MHz, f
= 16ksps, V
= +2.5V (eꢁternal), C
=
AV
DD
DV
DD
AV
DD XIN CLOCK
OUT
REFIO
REFIO
C
REF0
= C
= C
= C
= 1μF to AGND, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
MAX A
REF1
REF2
REF3
A
MIN
PARAMETER
SYMBOL
CONDꢂTꢂONS
MꢂN
TYP
3.4
MAX
UNꢂTS
kHz
Bandwidth
Latency
-3dB
(Note 8)
405
μs
Passband Flatness
From DC to 1.4kHz
FS vs. 0.1% FS
< 0.1
< 0.01
0.0001
0.001
-130
dB
Amplitude-Dependent Phase Error
Channel-to-Channel Phase Matching
Phase-Error Drift
0.12
Degrees
Degrees
Degrees
dB
Channel-to-Channel Isolation
Common-Mode Rejection
CMRR
109
dB
ANALOG ꢂNPUTS (AꢂN_+, AꢂN_ꢁ)
Differential FS Input Range
Single-Ended Positive Input Range
Single-Ended Negative Input Range
Positive Fault Threshold
V
V
- V
AIN_-
-2.2
-2.2
+2.2
+2.2
+2.2
2.65
-2.25
V
V
IN
AIN_+
V
Referenced to AGND
Referenced to AGND
AIN_+
V
-2.2
V
AIN_-
V
V
V
or V
or V
(Note 9)
(Note 9)
2.25
-2.65
V
PFT
AIN_+
AIN_+
AIN_-
AIN_-
Negative Fault Threshold
V
V
NFT
Fault Pin Response Time
2.5
130
μs
V
V
V
≤ V ≤ V
IN PFT
NFT
Input Impedance
Z
kΩ
IN
< V
or V > V
PFT
> 0.5
0.01
3.072
4.0
IN
NFT
IN
DC Leakage Current
I
+ = V
-
1
μA
Msps
pF
IN
AIN_
AIN_
Input Sampling Rate
f
f = f
S
/8
S
XINCLOCK
Input Sampling Capacitance
ꢂNTERNAL REFERENCE
REFIO Output Voltage
REFIO Output Resistance
REFIO Temp Drift
V
T
A
= T
MAX
2.4
2.5
1
2.6
V
REF
kΩ
50
ppm/°C
ppm/
1000hr
REFIO Long-Term Stability
200
REFIO Output Noise
3
μV
RMS
REFIO Power-Supply Rejection
EXTERNAL REFERENCE
REFIO Input Voltage
PSRR
75
dB
V
2.3
2.7
V
REF
REFIO Sink Current
200
200
10
μA
μA
pF
REFIO Source Current
REFIO Input Capacitance
CRYSTAL OSCꢂLLATOR (XꢂN, XOUT)
Tested Resonant Frequency
Maꢁimum Crystal ESR
(Note 10)
24.576
30
MHz
Ω
Oscillator Startup Time
Oscillator Stability
< 2
10
ms
V
= 3.3V, eꢁcluding crystal
ppm/°C
pF
DVDD
Maꢁimum Oscillator Load
10
_______________________________________________________________________________________
3
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
ELECTRꢂCAL CHARACTERꢂSTꢂCS (continued)
(V
= +3.0V to +3.6V, V
= +2.7V to V
, f
= 24.576MHz, f
= 16ksps, V
= +2.5V (eꢁternal), C
=
AV
DD
DV
DD
AV
DD XIN CLOCK
OUT
REFIO
REFIO
C
REF0
= C
= C
= C
= 1μF to AGND, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
MAX A
REF1
REF2
REF3
A
MIN
PARAMETER
SYMBOL
CONDꢂTꢂONS
MꢂN
TYP
MAX
UNꢂTS
DꢂGꢂTAL ꢂNPUTS (SCLK, CS, DꢂN, SYNC, CASCꢂN, DRDYIN, XꢂN)
0.3 ꢁ
Input Low Voltage
Input High Voltage
V
V
V
IL
V
DVDD
0.7 ꢁ
V
IH
V
DVDD
Input Hysteresis
V
V
= 3.0V
DVDD
100
0.01
15
mV
μA
pF
HYS
Input Leakage Current
Input Capacitance
I
1
L
C
IN
CMOS DꢂGꢂTAL OUTPUTS (DOUT, CASCOUT, DRDYOUT, CLKOUT)
0.15 ꢁ
Output Low Voltage
Output High Voltage
V
I
= 5mA
SINK
V
V
OL
V
DVDD
0.85 ꢁ
V
I
I = 1mA
SOURCE
OH
V
DVDD
Three-State Leakage Current
Three-State Capacitance
1
μA
pF
LT
4K/MAX160
C
15
30
OUT
OPENꢁDRAꢂN DꢂGꢂTAL OUTPUTS (OVRFLW, FAULT)
0.15 ꢁ
Output Low Voltage
Output High Voltage
V
I
= 5mA
V
OL
SINK
V
DVDD
0.85 ꢁ
V
Internal pullup only
V
OH
V
DVDD
Internal Pullup Resistance
POWER REQUꢂREMENTS
Analog Supply Voltage
Digital Supply Voltage
kΩ
AV
DV
3.0
2.7
3.6
V
DD
V
V
DD
AVDD
35
Normal operation
25
0.1
11
mA
μA
mA
μA
dB
dB
Analog Supply Current (Note 11)
Digital Supply Current (Note 11)
I
AVDD
Shutdown and f
= 0Hz
= 0Hz
5
XINCLOCK
Normal operation
Shutdown and f
15
I
DVDD
0.3
70
XINCLOCK
AC Positive-Supply Rejection
DC Positive-Supply Rejection
ESD PROTECTꢂON
All Pins
V
V
= 3.3V + 100mV
at 1kHz
P-P
AVDD
AVDD
= V
= 3.0V to 3.6V
75
DVDD
ESD
Human Body Model
2.5
kV
TꢂMꢂNG CHARACTERꢂSTꢂCS (Figures 7–10)
SCLK Clock Period
t
50
20
10
0
ns
ns
ns
ns
ns
SCP
SCLK Pulse Width (High and Low)
DIN or CS to SCLK Fall Setup
SCLK Fall to DIN Hold
t
PW
t
SU
HD
t
SCLK Rise to CS Rise
t
0
CSH1
4
_______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
4K/MAX160
ELECTRꢂCAL CHARACTERꢂSTꢂCS (continued)
(V
= +3.0V to +3.6V, V
= +2.7V to V
, f
= 24.576MHz, f
= 16ksps, V
= +2.5V (eꢁternal), C
=
AV
DD
DV
DD
AV
DD XIN CLOCK
OUT
REFIO
REFIO
C
REF0
= C
= C
= C
= 1μF to AGND, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
MAX A
REF1
REF2
REF3
A
MIN
PARAMETER
SYMBOL
CONDꢂTꢂONS
MꢂN
TYP
10
MAX
UNꢂTS
C
= 30pF
= 100pF
= 30pF
= 30pF
1.5
16
LOAD
LOAD
LOAD
LOAD
SCLK Rise to DOUT Valid
t
ns
DOT
C
C
C
< 16
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Pulse Width
t
0.3
0.7
16
20
16
ns
ns
ns
ns
ns
DOE
DOD
CSW
t
t
CASCIN-to-SCLK Rise Setup
SCLK Rise to CASCOUT Valid
t
16
SC
t
C
= 100pF
20
COT
LOAD
XIN
SYNC Pulse Width
t
2
Clock
Cycles
SYN
XIN Clock Pulse Width
DRDYIN to DRDYOUT
XIN Clock to DRDYOUT Delay
XIN Clock Period
t
16
ns
ns
ns
ns
ns
ns
ns
ms
XPW
t
C
= 30pF
20
40
DRDY
LOAD
t
DRDYIN = DGND
XDRDY
t
t
40
16
5
XP
SS
HS
XIN Clock to SYNC Setup
SYNC to XIN Clock Hold
XIN-to-CLKOUT Delay
Power-On Reset Delay
(Note 12)
(Note 12)
t
t
40
XCD
(Note 13)
< 1
Note 1: Devices are production tested at +105°C. Specifications to -40°C are guaranteed by design.
Note 2: Tested at V = V = +3.0V.
AV
DD
DV
DD
Note 3: Integral nonlinearity is the deviation of the analog value at any code from its ideal value after the offset and gain errors are
removed.
Note 4: Offset nulled.
Note 5: Offset and gain drift defined as change in offset and gain error vs. full scale.
Note 6: Noise measured with AIN_+ = AIN_- = AGND.
Note 7: Relative accuracy is defined as the difference between the actual RMS amplitude and the ideal RMS amplitude of a 62.5Hz
sine wave, measured over one cycle at a 16ksps data rate, eꢁpressed as a fraction of the ideal RMS amplitude. The rela-
tive accuracy specification refers to the maꢁimum error eꢁpected over 1 million measurements. Calculated from SNR. Not
production tested.
Note 8: Latency is a function of the sampling rate and XIN clock.
Note 9: Voltage levels below the positive fault threshold and above the negative fault threshold, relative to AGND on each individ-
ual AIN_+ and AIN_- input, do not trigger the analog input protection circuitry.
Note 10: Test performed using RXD MP35.
Note 11: All digital inputs at DGND or DVDD.
Note 12: SYNC is captured by the subsequent XIN clock if this specification is violated.
Note 13: Delay from DVDD eꢁceeds 2.0V until digital interface is operational.
_______________________________________________________________________________________
5
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Typical Operating Characteristics (MAX11040K)
(V
= V
= 3.3V, f
= 24.576MHz, f
= 16ksps, V
= 2.5V (eꢁternal), C
= C
= C
= C
=
REF2
AV
DD
DV
DD
XIN CLOCK
OUT
REFIO
REFIO
REF0
REF1
C
REF3
= 1μF, T = +25°C, unless otherwise noted.)
A
HISTOGRAM OF RMS AMPLITUDE
AT 0.1% FS
MAXIMUM EXPECTED ERROR OF CALCULATED
INL vs. DIFFERENTIAL INPUT VOLTAGE
RMS AMPLITUDE vs. INPUT AMPLITUDE
0.005
0.004
0.003
0.002
0.001
0
1
500
1 MILLION 62.5Hz CYCLES
450
400
350
300
250
200
150
100
50
0.1
0.01
-0.001
-0.002
-0.003
-0.004
-0.005
0.001
0
-2.5
-1.5
-0.5
0.5
1.5
2.5
0.01
0.1
1
10
100
DIFFERENTIAL INPUT VOLTAGE (V)
INPUT AMPLITUDE (% FS)
RMS AMPLITUDE (% FS)
SIGNAL-TO-NOISE RATIO
vs. OUTPUT DATA RATE
FFT vs. FREQUENCY AT FULL SCALE
FFT vs. FREQUENCY AT 0.1% FULL SCALE
4K/MAX160
0
-20
-40
-60
130
120
110
100
90
60Hz SINE-WAVE INPUT
60Hz SINE-WAVE INPUT
-40
-80
-60
-100
-120
-140
-160
-180
-80
-100
-120
-140
80
0
1000 2000 3000 4000 5000 6000 7000 8000
FREQUENCY (Hz)
0
1000 2000 3000 4000 5000 6000 7000 8000
FREQUENCY (Hz)
0.1
1
10
100
OUTPUT DATA RATE (ksps)
RMS AMPLITUDE GAIN ERROR
vs. OUTPUT DATA RATE
RMS AMPLITUDE
vs. SOURCE RESISTANCE
RMS AMPLITUDE
vs. INPUT FREQUENCY
0.05
0.04
0.03
0.02
0.01
0
1
0
0.1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-0.1
-0.2
-0.3
-0.4
-0.5
-0.01
-0.02
-0.03
-0.04
-0.05
100
1000
10,000
100,000
10
100
1000
10,000
100,000
10
100
1000
10,000
OUTPUT DATA RATE (Hz)
SOURCE RESISTANCE (Ω)
INPUT FREQUENCY (Hz)
6
_______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
4K/MAX160
Typical Operating Characteristics (MAX11040K continued)
(V
= V
= 3.3V, f
= 24.576MHz, f
= 16ksps, V
= 2.5V (eꢁternal), C
= C
= C
= C
=
REF2
AV
DD
DV
DD
XIN CLOCK
OUT
REFIO
REFIO
REF0
REF1
C
REF3
= 1μF, T = +25°C, unless otherwise noted.)
A
TOTAL HARMONIC DISTORTION
vs. INPUT FREQUENCY
0.10
OFFSET ERROR vs. SUPPLY VOLTAGE
OFFSET ERROR vs. TEMPERATURE
-80
-90
0.10
0.08
0.06
0.04
0.02
0
AVDD = DVDD
AVDD = DVDD
0.08
0.06
0.04
0.02
0
-100
-110
-120
-130
-0.02
-0.04
-0.06
-0.08
-0.10
-0.02
-0.04
-0.06
-0.08
-0.10
3.0
3.1
3.2
3.3
3.4
3.5
3.6
0
500
1000
1500
2000
-40
-11
18
47
76
105
SUPPLY VOLTAGE (V)
INPUT FREQUENCY (Hz)
TEMPERATURE (°C)
GAIN ERROR
vs. TEMPERATURE
GAIN ERROR vs. SUPPLY VOLTAGE
GAIN ERROR DRIFT
1.0
0.8
0
-0.02
-0.04
-0.06
-0.08
-0.10
1.0
0.8
AVDD = DVDD
V
= V
DVDD
= 3.3V
AVDD
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
3.0
3.1
3.2
3.3
3.4
3.5
3.6
0
100 200 300 400 500 600 700 800 900 1000
TIME (hr)
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Typical Operating Characteristics (MAX11040K continued)
(V
= V
= 3.3V, f
= 24.576MHz, f
= 16ksps, V
= 2.5V (eꢁternal), C
= C
= C
= C
=
REF2
AV
DD
DV
DD
XIN CLOCK
OUT
REFIO
REFIO
REF0
REF1
C
REF3
= 1μF, T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
30
25
20
15
10
5
30
500
400
300
200
100
0
V
AVDD
= V
= 3.3V
AVDD = DVDD
DVDD
AVDD = DVDD
25
20
I
AVDD
I
AVDD
15
10
5
I
DVDD
I
DVDD
I
DVDD
I
AVDD
0
0
3.0
3.1
3.2
3.3
3.4
3.5
3.6
-40
-11
18
47
76
105
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
4K/MAX160
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
CRYSTAL OSCILLATOR STARTUP TIME
MAX11040K/11060 toc20
1000
V
= V
DVDD
= 3.6V
AVDD
800
600
400
200
0
CLKOUT
500mV/div
I
AVDD
I
DVDD
-40
-11
18
47
76
105
40μs/div
TEMPERATURE (°C)
8
_______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
4K/MAX160
Pin Configuration
TOP VIEW
+
AIN0-
AIN0+
REF0
1
2
3
4
5
6
7
8
9
38 AIN2-
37 AIN2+
36 REF2
AGND
AIN1-
AIN1+
REF1
35 AGND
34 AIN3-
33 AIN3+
32 REF3
MAX11040K
MAX11060
AGND
REFIO
31 AGND
30 AVDD
29 AGND
28 DGND
27 DVDD
26 XIN
AGND 10
DGND 11
DVDD 12
CASCIN 13
CASCOUT 14
CS 15
25 XOUT
24 SYNC
23 DRDYIN
22 DRDYOUT
21 CLKOUT
20 OVRFLW
SCLK 16
DIN 17
DOUT 18
FAULT 19
TSSOP
Pin Description
PꢂN
1
NAME
AIN0-
AIN0+
REF0
FUNCTꢂON
Negative Analog Input Channel 0
Positive Analog Input Channel 0
2
3
ADC0 Buffered Reference Voltage. Bypass REF0 with a 1μF capacitor to AGND.
4, 8, 10,
29, 31, 35
AGND
Analog Ground
5
6
7
AIN1-
AIN1+
REF1
Negative Analog Input Channel 1
Positive Analog Input Channel 1
ADC1 Buffered Reference Voltage. Bypass REF1 with a 1μF capacitor to AGND.
Reference Voltage Output/Input. Reference voltage for analog-to-digital conversion. In internal reference
mode, the reference buffer provides a +2.5V nominal output. In eꢁternal reference mode, overdrive REFIO
with an eꢁternal reference between 2.3V to 2.7V. Bypass REFIO with a 1μF capacitor to AGND.
9
REFIO
_______________________________________________________________________________________
9
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Pin Description (continued)
PꢂN
NAME
FUNCTꢂON
11, 28
DGND
Digital Ground
Positive Digital Supply Voltage. Bypass each DVDD to DGND with a 1μF capacitor in parallel with a
0.01μF capacitor as close as possible to the device.
12, 27
DVDD
Cascade Input. A logic-low on CASCIN while CS is a logic-low during the last cycle of a byte signals the
device to perform the requested data transfer during subsequent bytes using DIN and DOUT. Once the
13
CASCIN requested transfer is completed, the part three-states DOUT and ignores DIN until a new command is
issued. CASCIN is clocked in at the rising edge of SCLK. Connect CASCIN to DGND when not daisy
chaining multiple devices. See the Multiple Device Connection section for connection recommendations.
Cascade Output. CASCOUT is driven low during the last cycle of the last byte of a data transfer to signal
the neꢁt device in the daisy-chain to begin transferring data on the neꢁt byte. CASCOUT changes after
the rising edge of SCLK. Leave CASCOUT unconnected when not daisy chaining multiple devices. See
the Multiple Device Connection section.
14
15
CASCOUT
Active-Low Chip-Select Input. A falling edge on CS while CASCIN is a logic-low enables DIN and DOUT
for data transfer. A logic-high on CS prevents data from being clocked in on DIN and places DOUT in a
CS
high-impedance state.
Serial-Clock Input. Clocks in data at DIN on the falling edge of SCLK and clocks out data at DOUT on the
rising edge of SCLK. SCLK must idle high (CPOL = 1).
16
17
SCLK
DIN
4K/MAX160
Serial Data Input. Data at DIN is clocked in on the falling edge of SCLK.
Serial Data Output. The drive for DOUT is enabled by a falling edge on CS while CASCIN is low or by a
falling edge on CASCIN while CS is low. DOUT is disabled/three-stated when CS is high or after the
appropriate number of data bytes have been transferred in response to the requested command. Data is
clocked out at DOUT on the rising edge of SCLK.
18
19
20
21
DOUT
FAULT
Active-Low Overvoltage Fault Indicator Output. FAULT goes low when any analog input goes outside the fault
threshold range (between V
and V
). The FAULT output is open drain with a 30kΩ internal pullup
PFT
NFT
resistor, allowing wire-NOR functionality. See the Analog Input Overvoltage and Fault Protection section.
Active-Low Channel Data Overflow Output. OVRFLW goes low when a conversion result goes outside the
voltage range bounded by the positive and negative full scale on one or more of the analog input
channels or when FAULT goes low. The OVRFLW output is open drain with a 30kΩ internal pullup resistor,
allowing wire-NOR functionality. See the Analog Input Overvoltage and Fault Protection section.
OVRFLW
CLKOUT
Buffered Clock Output. When the XTALEN bit in the configuration register is 1 and a crystal is installed
between XIN and XOUT, CLKOUT provides a buffered version of the internal oscillator’s clock. Setting the
XTALEN bit to 0 places CLKOUT in a high-impedance state.
10 ______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
4K/MAX160
Pin Description (continued)
PꢂN
NAME
FUNCTꢂON
Active-Low Data Ready Output. When DRDYIN = 0, DRDYOUT outputs a logic-low to indicate the
DRDYOUT availability of a new conversion result. DRDYOUT transitions high at the neꢁt CS falling edge or when
DRDYIN = 1. See the Multiple Device Connection section.
22
Active-Low Data Ready Input. A logic-high at DRDYIN causes DRDYOUT to output a logic-high. When
DRDYIN = 0, DRDYOUT outputs a logic-low when a new conversion result is available. See the Multiple
Device Connection section. Connect DRDYIN to DGND when not daisy chaining multiple devices.
23
24
25
DRDYIN
SYNC
Sampling Synchronization Input. The falling edge of SYNC aligns sampling and output data so that
multiple devices sample simultaneously. Synchronize multiple devices running from independent crystals
by connecting DRDYOUT of the last device in the chain to the SYNC inputs of all devices in the chain.
Connect SYNC to DGND for single device operation. See the Multiple Device Connection section.
Crystal Oscillator Output. Connect a 24.576MHz eꢁternal crystal or resonator between XIN and XOUT
when using the internal oscillator. Leave XOUT unconnected when driving with an eꢁternal frequency. See
the Crystal Oscillator section.
XOUT
Crystal Oscillator/Clock Input. Connect a 24.576MHz eꢁternal crystal or resonator between XIN and XOUT
when using the internal oscillator or drive XIN with an eꢁternal clock and leave XOUT unconnected. See
the Crystal Oscillator section.
26
30
XIN
Positive Analog Supply Voltage. Bypass to AGND with a 1μF capacitor in parallel with a 0.01μF capacitor
as close as possible to the device.
AVDD
32
33
34
36
37
38
REF3
AIN3+
AIN3-
REF2
ADC3 Buffered Reference Voltage. Bypass with a 1μF capacitor to AGND.
Positive Analog Input Channel 3
Negative Analog Input Channel 3
ADC2 Buffered Reference Voltage. Bypass with a 1μF capacitor to AGND.
Positive Analog Input Channel 2
AIN2+
AIN2-
Negative Analog Input Channel 2
______________________________________________________________________________________ 11
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
the effective sample rate of the ADC, is software pro-
grammable.
Typical Operating Circuit
The devices operate from a single 3.0V to 3.6V analog
3.3V
3.3V
1µF
1µF
supply and a 2.7V to V
digital supply. The 4-wire
AVDD
serial interface is SPI/QSPI/MICROWIRE and DSP com-
patible.
0.01µF
0.01µF
ADC Modulator
Each channel of the devices performs analog-to-
digital conversion on its input using a dedicated
switched-capacitor sigma-delta modulator. The modula-
tor converts the input signal into low-resolution digital data
for which the average value represents the digitized sig-
nal information at 3.072Msps for a 24.576MHz XIN clock.
This data stream is then presented to the digital filter for
processing to remove the high-frequency noise that cre-
ates a high-resolution 24-/16-bit output data stream.
20pF
24.576MHz
20pF
AVDD
DVDD
XIN
AIN0+
AIN0-
AIN0+
AIN0-
REF0
XOUT
1µF
CLKOUT
CASCOUT
CASCIN
MAX11040K
MAX11060
AIN1+
AIN1-
AIN1+
AIN1-
REF1
1µF
The input sampling network of the analog input consists
OVRFLW
FAULT
of a pair of 4pF capacitors (C
), the bottom
SAMPLE
AIN2+
AIN2-
AIN2+
AIN2-
REF2
plates of which are connected to AIN_+ and AIN_- dur-
ing the track phase and then shorted together during
the hold phase (see Figure 1). The internal switches
have a total series resistance of 400Ω. Given a
24.576MHz XIN clock, the switching frequency is
3.072MHz. The sampling phase lasts for 120ns.
1µF
CS
SCLK
4K/MAX160
AIN3+
AIN3-
AIN3+
AIN3-
REF3
DIN
MICROCONTROLLER
OR DSP
DOUT
1µF
SYNC
DRDYOUT
REFIO
DRDYIN
DGND
1µF
AGND
MAX11040K
MAX11060
TRACK
AIN_+
AIN_-
C
SAMPLE+
Detailed Description
HOLD
TO ADC
C
SAMPLE-
The MAX11040K/MAX11060 are 24-/16-bit, simultane-
ous-sampling, 4-channel, sigma-delta ADCs including
support for synchronized sampling and daisy chaining
of the serial interface across multiple (up to eight)
devices. The serial interface of the set of synchronized
devices behaves as one device. Each channel includes
a differential analog input, a sigma-delta modulator, a
digital decimation filter, an independent programmable
sampling delay, and a buffered reference signal from
the internal or an eꢁternal reference. The device con-
tains an internal crystal oscillator. The output data rate,
TRACK
R
R
ON
ON
AVDD/2
Figure 1. Simplified Track/Hold Stage
12 ______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
4K/MAX160
Since the transfer function of a digital filter is repeatable
and predictable, it is possible to correct for frequency-
dependent attenuation in downstream software. See
the Compensating for the Rolloff of the Digital Filter in a
Typical FFT Analysis section. The transfer function is
defined by the following equation:
Digital Filter
The devices contain an on-chip digital lowpass filter
that processes the data stream from each modulator
and generates the high-resolution output data. The low-
pass filter frequency response is determined by the
programmable output data rate. At the nominal 16ksps
output data rate, the -3dB bandwidth of the filter is
3.4kHz. The passband flatness is better than 0.1dB
from 0 to 1.74kHz. The notches are located at 5.75kHz
and 7.195kHz. These frequencies scale linearly with the
output data rate. See Figure 2 and Table 1 for the fre-
quency response at different data rates.
3
⎛
⎜
⎜
⎜
⎜
⎞
⎟
⎟
⎟
⎟
⎛
⎞
f
AIN
f
× sin π ×
SAMPLE
⎜
⎟
f
⎝
⎛
⎠
SAMPLE
Gain(f ) =
AIN
⎞
f
AIN
XINCLOCK
f
× sin π ×
XINCLOCK
⎜
⎟
⎜
⎝
⎟
⎠
f
⎝
⎠
×
FIR_Gain(f
(
)
)
AIN
1
0
where:
Gain is the filter gain.
f
f
is the analog input frequency.
-1
-2
-3
-4
-5
-6
AIN
is the programmed output data rate, nominally
SAMPLE
16kHz.
f
is the clock frequency at XIN, nominally
XINCLOCK
24.576MHz.
FIR_Gain (f ) is the normalized gain of the FIR filter
AIN
with the following filter coefficients, as a function of the
analog input frequency f
applied at the output data rate:
. These coefficients are
AIN
0
0.04 0.08 0.12 0.16 0.20 0.24 0.28
/f
f
AIN SAMPLE
+ 0.022
- 0.074
- 0.036
+ 0.312
+ 0.552
+ 0.312
- 0.036
- 0.074
+ 0.022
Figure 2. Digital Filter Response
Table 1. Bandwidth vs. Output Data Rate
OUTPUT DATA ꢁ3dB BANDWꢂDTH ꢁ0.1dB BANDWꢂDTH
RATE (ksps)
(kHz)
(kHz)
0.5
1
0.11
0.21
0.42
0.85
1.69
2.11
2.54
3.38
6.78
13.5
0.05
0.11
0.22
0.43
0.87
1.09
1.31
1.74
3.48
6.96
2
4
8
10
12
16
32
64
______________________________________________________________________________________ 13
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Modulator Clock
The modulator clock is created by dividing the frequen-
cy at the XIN input by a factor of 8. The XIN input is dri-
ven either directly by an eꢁternal clock or by the
on-chip crystal oscillator.
Analog Input Overvoltage
and Fault Protection
The full-scale differential input range of the devices is
0.88V
. The converter accurately represents any
REF
input for which the positive and negative analog inputs
are separated by a magnitude of less than 0.88V
.
REF
Crystal Oscillator
The on-chip oscillator requires an eꢁternal crystal (or
resonator) with a 24.576MHz operating frequency con-
nected between XIN and XOUT, as shown in Figure 3.
As in any crystal-based oscillator circuit, the oscillator
The device includes special circuitry that protects it
against voltages on the analog inputs up to +6V.
Setting FAULTDIS = 1 disables the protection circuitry.
There are two mechanisms of overvoltage detection
and protection: full-scale overflow and overvoltage
fault. Full-scale overflow occurs if the magnitude of the
applied input voltage on any one or more channels is
frequency is sensitive to the capacitive load (C ). C is
L
L
the capacitance that the crystal needs from the oscilla-
tor circuit and not the capacitance of the crystal. The
input capacitance across XIN and XOUT is 1.5pF.
greater than 0.88V
. In this case, the digital output is
REF
clipped to positive or negative full scale and the OVRFLW
flag goes low. Overvoltage fault occurs if the magni-
tude of an applied input voltage on any one or more
channels goes outside the fault-detection thresholds.
The reaction to an overvoltage fault is dependent on
whether the fault-protection circuitry is enabled. If
enabled, the input-protection circuits engage and the
FAULT flag goes low. A full-scale overflow or an over-
voltage fault condition on any one channel does not
affect the output data for the other channels.
Choose a crystal with a 24.576MHz oscillation frequen-
cy and an ESR less than 30Ω, such as the MP35 from
RXD Technologies. See Figure 3 for the block diagram
of the crystal oscillator. Set XTALEN = 1 in the configu-
ration register to enable the crystal oscillator. The
CLKOUT output provides a buffered version of the
clock that is capable of driving eight devices, allowing
synchronized operation from a single crystal. See the
Multiple Device Synchronization section in the
Applications Information section.
4K/MAX160
The input protection circuits allow up to 6V relative to
AGND on each input, and up to 6V differentially
between AIN+ and AIN-, without damaging the devices
only if the following conditions are satisfied: power is
applied, the devices are not in shutdown mode, a clock
frequency of at least 20MHz is available at XIN, and
FAULTDIS = 0. The analog inputs allow up to 3.5V rel-
ative to AGND when either devices are placed in shut-
down mode, the clock stops, or FAULTDIS = 1.
External Clock
To use an eꢁternal clock, set XTALEN = 0 in the
Configuration register and connect an eꢁternal clock
source (20MHz–25MHz) to XIN. CLKOUT becomes
high impedance.
During an overvoltage fault condition, the impedance
between AIN_+ and AIN_- reduces to as low as 0.5kΩ.
MAX11040K
MAX11060
The output structure and cascading features of FAULT
and OVRFLW are discussed in the Multiple Device
Digital Interface section.
20pF
XIN
24.576MHz
OSCILLATOR
Analog ꢂnput Overflow
Detection and Recovery (OVRFLW)
24.576MHz
The OVRFLW flag is set based on the ADC conversion
result. When the applied voltage on one or more analog
inputs goes outside the positive or negative full scale
XOUT
20pF
( 0.88V
), OVRFLW asserts after a delay defined by
REF
the latency of the converter, coincident with the DRDYOUT
of the full-scale clamped conversion result (see Figure
4). The specifics of the latency are discussed earlier in
the data sheet in the Latency section.
Figure 3. Crystal Oscillator Input
14 ______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
4K/MAX160
When the analog input voltage changes between the
the latency of the converter, the ADC conversion result
prematurely jumps to the full-scale value when a fault is
detected (see Detection Discontinuity in Figure 4).
During a fault condition and the subsequent fault-
recovery time, the ADC conversion result remains at full
scale. This creates a discontinuity in the digital conver-
sion result only if the fault recovery time is greater than
the latency plus the time that the input changes
between the fault threshold and the ADC full scale (see
Recovery Discontinuity in Figure 4). Neither of these
steps occur if the fault-protection circuitry is disabled
(FAULTDIS = 1), or if the input is slow relative to the
above descriptions (see Figure 5).
ADC full scale and the fault threshold faster than the
latency of the converter, OVRFLW goes low with the
FAULT output. OVRFLW remains invalid until a valid
clock frequency is available at XIN.
OvervoltageꢁFault Detection and Recovery (FAULT)
With overvoltage-fault protection enabled (FAULTDIS =
0), FAULT immediately transitions from a high to low
when any of the analog inputs go outside the voltage
range bounded by the fault-detection thresholds V
PFT
and V
.
NFT
Once the analog inputs return back within the fault
thresholds, the FAULT interrupt output goes high after a
delay called the fault-recovery time. The fault-recovery
time is:
For data rates faster than 32ksps (FSAMPC = 111), the
converter output may contain invalid data for up to
188μs after FAULT returns high. To prevent this behav-
ior, disable the overvoltage-fault protection by setting
the FAULTDIS bit in the configuration register to 1 when
using FSAMPC = 111, and limit the analog input swing
to 3.5V.
20 ꢁ t
< fault-recovery time < 25 ꢁ t
DOUT
DOUT
where t
XINCLOCK
is the data output period determined by
DOUT
f
and the selected output data rate.
In the event the analog input voltage changes between
the ADC full scale and the fault threshold faster than
FAULT-DETECTION
THRESHOLD
(V OR |V |)
PFT
NFT
|AIN+ - AIN-|
DETECTION
DISCONTINUITY
RECOVERY
DISCONTINUITY
FULL SCALE
(|0.88V |)
REF
LATENCY
RECOVERY TIME
DIGITAL OUTPUT
DATA AT DOUT
LATENCY
LATENCY
LATENCY
FAULT
OVRFLW
Figure 4. High-Frequency Analog Input Overvoltage Detection and Recovery
______________________________________________________________________________________ 15
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
FAULT-DETECTION
THRESHOLD
(V OR |V |)
PFT
NFT
|AIN+ - AIN-|
LATENCY
LATENCY
FULL SCALE
(|0.88V |)
REF
RECOVERY TIME
LATENCY
DIGITAL OUTPUT
DATA AT DOUT
LATENCY
FAULT
OVRFLW
4K/MAX160
Figure 5. Low-Frequency Analog Input Overvoltage Detection and Recovery
Reference
The devices operate with either a +2.5V internal
REF0
bandgap reference or an eꢁternal reference source
between +2.3V and +2.7V applied at REFIO. Bypass
REFIO and each REF_ to AGND with a 1μF capacitor.
The reference voltage sets the positive and negative
full-scale voltage according to the following formula:
REF1
REF2
REF3
FS = 0.88 V
REFIO
The reference voltage at REFIO (eꢁternal or internal) is
individually buffered to generate the reference voltages
at REF0 to REF3 (see Figure 6.) These independent
buffers minimize the potential for crosstalk between
each of the internal ADCs.
+2.5V
REFERENCE
REFIO
Serial Interface
The devices’ interface is fully compatible with SPI/DSP
standard serial interfaces (compatible with SPI modes
CPOL = 1, CPHA = 0). The serial interface provides
access to four on-chip registers: Sampling Instant
Control register (32 bits), Data Rate Control register (16
bits), Configuration register (8 bits), and Data register
(96 bits). All serial-interface commands begin with a
command byte, which addresses a specific register,
followed by data bytes with a data length that depends
on the specific register addressed and the number of
Figure 6. REFIO Input
devices cascaded (see Figures 7, 8, and the Registers
section).
The serial interface consists of eight signals: CS,
SCLK, DIN, DOUT, CASCIN, CASCOUT, DRDYIN,
and DRDYOUT. CASCIN, CASCOUT, DRDYIN, and
DRDYOUT are used for daisy chaining multiple devices
together. See the Multiple Device Connection section
for details on how to connect CASCIN, CASCOUT,
16 ______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
4K/MAX160
DRDYIN, and DRDYOUT. For single-device applications,
ferred MSB first. Drive CS high to disable the interface
connect CASCIN and DRDYIN to DGND and drive CS
low to transfer data in and out of the devices. With
DRDYIN low, a falling edge at the data-ready signal out-
put (DRDYOUT) indicates that new conversion results
are available for reading in the 96-bit data register. A
falling edge on SCLK clocks in data at DIN. Data at
DOUT changes on the rising edge of SCLK and is valid
on the falling edge of SCLK. DIN and DOUT are trans-
and place DOUT in a high-impedance state.
An interface operation with the devices takes effect on
the last rising edge of SCLK. If CS goes high before the
complete transfer, the write is ignored. Every data
transfer is initiated by the command byte. The com-
mand byte consists of an R/W bit and 7 address bits
(see Table 2.) Figures 7 and 8 show the timing for read
and write operations, respectively.
t
CSW
t
SU
t
SCP
t
PW
CS
t
PW
t
DCD
SCLK
t
SU
t
CSH1
DIN
R/W A6 A5 A4 A3 A2 A1 A0
t
t
DOT
HD
COMMAND ADDRESS
HIGH-Z
HIGH-Z
DOUT
B7 B6 B5 B4 B3 B2 B1 B0
t
DOE
DATA LENGTH (NUMBER OF BYTES) DEPENDS
ON THE REGISTER BEING READ (SEE TABLE 2)
DRDYIN
t
DRDY
DATA READY
DRDYOUT
Figure 7. General Read-Operation Timing Diagram
t
CSW
t
SU
CS
t
CSH1
DIN
R/W A6 A5 A4 A3 A2 A1 A0
B7 B6 B5 B4 B3 B2 B1 B0
t
HD
SCLK
t
SU
t
t
PW
SCP
t
PW
DATA LENGTH (NUMBER OF BYTES) DEPENDS ON
THE REGISTER BEING WRITTEN (SEE TABLE 2)
HIGH-Z
HIGH-Z
DOUT
Figure 8. General Write-Operation Timing Diagram
______________________________________________________________________________________ 17
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Registers
The devices include four registers accessible by 7
command bytes. The command bytes provide read
and write access to the Data Rate Control register, the
Sampling Instant Control register, and the Configuration
register, and read access to the Data register. See
Table 2. Figure 9 shows the CASCIN and CASOUT
timing diagram. Figure 10 is the XIN clock, CLKOUT,
SYNC, and DRDYOUT timing diagram.
SCLK
t
COT
CASCOUT
(DEVICE n)
CASCIN
(DEVICE n+1)
Table 2. Command Bytes
t
SC
ADDRESS
[A6:A0]
DATA
LENGTH*
R/W
FUNCTꢂON
Write Sampling Instant
Control Register
0
1
0
1
0
1000000
1000000
1010000
1010000
1100000
32 ꢁ n** bits
32 ꢁ n bits
16 bits
Figure 9. CASCIN and CASCOUT Timing Diagram
Read Sampling Instant
Control Register
Write Data-Rate Control
Register
t
t
XP
XPW
XIN CLOCK
4K/MAX160
Read Data-Rate Control
Register
16 bits
t
XCD
Write Configuration
Register
8 ꢁ n bits
8 ꢁ n bits
CLKOUT
t
HS
Read Configuration
Register
1
1
1100000
1110000
t
SS
SYNC
96 ꢁ n bits Read Data Register
t
XDRDY
t
SYN
*All data lengths are proportional to the number of cascaded
devices eꢁcept for reads and writes to the Data Rate Control
register. When accessing the Data Rate Control register, the
data length is fiꢁed at 16 bits. These 16 bits are automatically
written to all cascaded devices.
DRDYOUT
**n is the total number of cascaded devices.
Figure 10. XIN Clock, CLKOUT, SYNC, and DRDYOUT Timing
Diagram
18 ______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
4K/MAX160
Sampling ꢂnstant Control Register
By default, the devices sample all 4 input channels
simultaneously. To delay the sampling instant on one or
more channels, program the appropriate byte in the
Sampling Instant Control register. The delay of the
actual sampling instant of each individual channel from
the default sampling instant (PHI_[7:0] = 0ꢁ00) is
adjustable between 32 to 819,121 XIN clock cycles,
which is 1.3μs to 333μs with f
at 24.576MHz
XINCLOCK
(see Table 3.)
Configuration Register
The Configuration register contains 5 bits that control the
functionality of the devices. The default state is 0ꢁ00.
The data length of the Configuration register is 8 bits
per cascaded device (see Table 4).
Table 3. Sampling ꢂnstant Control Register
BꢂT
NAME
DESCRꢂPTꢂON
Channel 0 sample instant adjust. PHI0 delays sampling instant on channel 0 by 32 XIN clock cycles per
LSB, up to 8192 cycles total (1.3μs resolutionꢀ 333μs range at XIN of 24.576MHz).
[31:24]
PHI0[7:0]
Channel 1 sample instant adjust. PHI1 delays sampling instant on channel 1 by 32 XIN clock cycles per
LSB, up to 8192 cycles total (1.3μs resolutionꢀ 333μs range at XIN of 24.576MHz).
[23:16]
[15:8]
[7:0]
PHI1[7:0]
PHI2[7:0]
PHI3[7:0]
Channel 2 sample instant adjust. PHI2 delays sampling instant on channel 2 by 32 XIN clock cycles per
LSB, up to 8192 cycles total (1.3μs resolutionꢀ 333μs range at XIN of 24.576MHz).
Channel 3 sample instant adjust. PHI3 delays sampling instant on channel 3 by 32 XIN clock cycles per
LSB, up to 8192 cycles total (1.3μs resolutionꢀ 333μs range at XIN of 24.576MHz).
Table 4. Configuration Register
BꢂT
NAME
DESCRꢂPTꢂON
Shutdown bit. Set SHDN high to place the device in shutdown mode. In shutdown mode, the internal
oscillator, fault circuitry, and internal bandgap reference are turned off. Set SHDN low for normal operation.
7
SHDN
Reset bit. Set RST high to reset all registers to the default states eꢁcept for the RST bit, and realign
sampling clocks and output data.
6
5
RST
Enable 24-bit resolution bit for the MAX11040K. Set EN24BIT high to enable the 24-bit data output. Set
EN24BIT low to enable 19-bit data output with device address and channel address tags. Tables 5 and 6
specify the Data register for both states of this bit. Set to 0 for MAX11060.
EN24BIT
Internal oscillator enable bit. When using the on-chip crystal oscillator as the clock source, set XTALEN high
to enable the crystal oscillator and provide a buffered version of the crystal clock at the CLKOUT output.
When using an eꢁternal clock source, set XTALEN low to disable the internal crystal oscillator and three-
state the CLKOUT output. Connect the eꢁternal clock source to the XIN input.
4
3
XTALEN
Overvoltage fault-protection disable bit. Set FAULTDIS high to disable the overvoltage fault-protection
circuits. For FAULTDIS = 0, the absolute maꢁimum input range is 6V. Analog inputs beyond the fault-
detection threshold range trip the fault-protection circuits. The output remains clipped for a fault-recovery
time (typically < 1.57ms) after the inputs return within the fault-detection threshold range. For FAULTDIS =
1, the absolute maꢁimum input range is only 3.5V, but there is no fault-recovery delay. See the
Overvoltage Fault Detection and Recovery (FAULT) section.
FAULTDIS
PDBUF
PDBUF = 1 disables the internal reference buffer. Use this mode when an eꢁternal reference is usedꢀ
otherwise, PDBUF should be set to 0 to enable the internal reference buffer.
2
[1:0]
Reserved Must set to 0.
______________________________________________________________________________________ 19
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Data Register
The Data register contains the results of the ADC con-
version. The result is reported in two’s complement for-
mat. The register contains one or two pieces of
information, depending on the state of EN24BIT in the
Configuration register. When EN24BIT is set to zero, the
Data register contains the ADC data truncated to 19
bits, followed by the device and channel addresses
(see Table 5). When EN24BIT is set to one, the data
contained in the Data register represents the 24-bit
conversion (see Table 6). The data length of the Data
register is 96 bits for each cascaded device. Figure 11
shows the sequence of the conversion result output of
all channels for two cascaded devices. Table 7 is the
data register for the MAX11060.
If the results are not read back prior to completion of
the neꢁt conversion, the data is overwritten.
Table 5. Data Register (EN24BꢂT = 0) (MAX11040K)
BꢂT
NAME
DESCRꢂPTꢂON
[95:77]
[76:74]
[73:72]
[71:53]
[52:50]
[49:48]
[47:29]
[28:26]
[25:24]
[23:5]
CH0DATA[18:0] Channel 0 19-bit conversion result (two’s complement)
IC[2:0]
00
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 0 address tag = 00
CH1DATA[18:0] Channel 1 19-bit conversion result (two’s complement)
IC[2:0]
01
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 1 address tag = 01
CH2DATA[18:0] Channel 2 19-bit conversion result (two’s complement)
4K/MAX160
IC[2:0]
10
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 2 address tag = 10
CH3DATA[18:0] Channel 3 19-bit conversion result (two’s complement)
[4:2]
IC[2:0]
11
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 3 address tag = 11
[1:0]
Table 6. Data Register (EN24BꢂT = 1) (MAX11040K)
BꢂT
NAME
DESCRꢂPTꢂON
[95:72]
[71:48]
[47:24]
[23:0]
CH0DATA[23:0] Channel 0 24-bit conversion result (two’s complement)
CH1DATA[23:0] Channel 1 24-bit conversion result (two’s complement)
CH2DATA[23:0] Channel 2 24-bit conversion result (two’s complement)
CH3DATA[23:0] Channel 3 24-bit conversion result (two’s complement)
Table 7. Data Register (MAX11060)
BꢂT
NAME
CH0DATA[15:0]
000
DESCRꢂPTꢂON
Channel 0 16-bit conversion result (two’s complement)
—
[95:80]
[79:77]
[76:74]
[73:72]
[71:56]
[55:53]
[52:50]
[49:48]
[47:32]
IC[2:0]
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 0 address tag = 00
00
CH1DATA[15:0]
000
Channel 1 16-bit conversion result (two’s complement)
—
IC[2:0]
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 1 address tag = 01
01
CH2DATA[15:0]
Channel 2 16-bit conversion result (two’s complement)
20 ______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
4K/MAX160
Table 7. Data Register (MAX11060) (continued)
BꢂT
[31:29]
[28:26]
[25:24]
[23:8]
[7:5]
NAME
DESCRꢂPTꢂON
000
—
IC[2:0]
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 2 address tag = 10
10
CH3DATA[15:0]
000
Channel 3 16-bit conversion result (two’s complement)
—
[4:2]
IC[2:0]
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 3 address tag = 11
[1:0]
11
CS
DIN
SCLK
DOUT
24 CYCLES
24 CYCLES
24 CYCLES
24 CYCLES
24 CYCLES
24 CYCLES
24 CYCLES
24 CYCLES
CHANNEL 0
DEVICE 0
CHANNEL 1
DEVICE 0
CHANNEL 2
DEVICE 0
CHANNEL 3
DEVICE 0
CHANNEL 0
DEVICE 1
CHANNEL 1
DEVICE 1
CHANNEL 2
DEVICE 1
CHANNEL 3
DEVICE 1
CASCOUT0
(CASCIN0 = 0)
DEVICE 1 TAKES OVER SPI BUS
CASCOUT1
DRDYOUT0
(DRDYIN0 = 0)
DEVICE 0 DATA READY
DRDYOUT1
DEVICE 0 AND DEVICE 1 DATA READY
Figure 11. 192-Bit Data Read Operation Diagram for Two Cascaded Devices
Data Rate Control Register
The Data Rate Control register controls the output data
period, which corresponds to the output data rate of
the ADC. The data period is controlled by both a
coarse (FSAMPC[2:0]) and a fine (FSAMPF[10:0])
adjustment (see Table 8).
Divider = Coarse Cycle Factor ꢁ 384 + Fine Cycle
Factor ꢁ FSAMPF[10:0]
Note: Fractional results for the divider are rounded
down to the nearest integer. Coarse cycle factor and
fine cycle factor come from Table 8. The effect of
FSAMPF[10:0] in the formula has limitations as noted in
the table.
The final data rate is derived by dividing the XIN clock
frequency by a divider value. The divider value is a
function of FSAMPC[2:0] and FSAMPF[10:0]:
Eꢁamples of output data rate vs. FSAMPC[2:0] and
FSAMPF[10:0] are shown in Table 9. Table 10 shows
typical device performance for various data rate settings.
Data Rate = f /Divider
XINCLOCK
______________________________________________________________________________________ 21
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
The data length of the Data-Rate Control register is 16
bits total for writes and reads (see Table 2). Changes to
the Data-Rate Control register take effect after 16 con-
version periods (Figure 12), i.e., the ADC continues to
operate at the old data rate for another 16 periods. Also,
the last sample at the old data rate (sample 16 in Figure
12) may contain some noise component and should be
discarded. Changes in data rate should be limited to
5% for correct operation. The data rate register should
not be updated more than once every 32 data rate peri-
ods.
is available for reading (DRDYOUT goes low). The laten-
cy of the converter is specified by the following equation:
Latency = (6 ꢁ t ) + (PHI ꢁ 1.3μs) + 30μs
DOUT
where t
is the data output period (inverse of the
DOUT
programmed sample rate) determined by XINCLOCK
and the selected output data rate, and PHI is the pro-
grammed sampling instant delay for the channel in ques-
tion (0 ≤ PHI ≤ 255). The latency is approꢁimately 405μs
at 16ksps.
Because the two filters operate at different output data
rates, a skew builds up between them over the 16 sam-
ples that both are in operation. For eꢁample, at 30ksps,
the minimum data rate step size is 0.125%ꢀ so over 16
samples, the difference becomes 2%. This causes the
period from sample 16 to sample 17 to be different by
this amount.
Note: Write to the data rate register in the time window of
10ns after the rising edge of DRDYOUT and 100ns
before the falling edge of DRDYOUT.
The digital filter determines the latency. Latency is
defined as the time between the effective point in time
that a sample is taken and when the resulting digital data
4K/MAX160
16
1
2
17
15
DRDYOUT
CS
DATA AT THE OLD
DATA RATE
DATA AT THE NEW
DATA RATE
CHANGE DATA RATE
DATA READ
Figure 12. Timing Diagram for a Data-Rate Change
22 ______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
4K/MAX160
Table 8. DataꢁRate Control Register
BꢂTS
NAME
FSAMPC[2:0]
Reserved
DESCRꢂPTꢂON
Output data rate coarse adjust bits. FSAMPC[2:0] sets the coarse cycle factor.
Coarse Cycle
Factor
Sample Rate in ksps
FSAMPC
(f
= 24.576MHz)
XIN CLOCK
000
001
010
011
100
101
110
111
4
128
64
32
16
8
16
0.5
1
[15:13]
[12:11]
2
4
8
2
32
64
1
Set to 0.
Output data rate fine adjusts bits. FSAMPF[10:0] increases the output data period by a number of
XIN clock cycles. This number is the value of the register times the fine cycle factor. Values of
FSAMPF greater than 1535 have no additional effect.
FSAMPC
000
XIN Fine Cycle Factor
1 cycle
001
32 cycles
16 cycles
8 cycles
[10:0]
FSAMPF[10:0]
010
011
100
4 cycles
101
2 cycles
110
1 cycle
111
1 cycle
Table 9. Examples of Output Data Rate as a Function of FSAMPC[2:0] and FSAMPF[10:0]
FSAMPF OUTPUT DATA PERꢂOD
RESOLUTꢂON
(24.576MHz CLOCK CYCLES)
OUTPUT DATA
RATE (sps)
OUTPUT DATA PERꢂOD
(24.576MHz CLOCK CYCLES)
FSAMPC[2:0] FSAMPF[10:0]
11ꢁꢁꢁꢁꢁꢁꢁꢁꢁ
250.1
250.1
98272
98272
49184
49152
49136
49136
24592
24576
24568
24568
12296
12288
10111111111
001
32
16
8
00000000001
499.7
00000000000
11ꢁꢁꢁꢁꢁꢁꢁꢁꢁ
500.0
500.2
10111111111
010
500.2
00000000001
999.3
00000000000
11ꢁꢁꢁꢁꢁꢁꢁꢁꢁ
1000.0
1000.3
1000.3
1998.7
2000.0
10111111111
011
00000000001
00000000000
______________________________________________________________________________________ 23
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Table 9. Examples of Output Data Rate as a Function of FSAMPC[2:0] and
FSAMPF[10:0] (continued)
FSAMPF OUTPUT DATA PERꢂOD
RESOLUTꢂON
(24.576MHz CLOCK CYCLES)
OUTPUT DATA
RATE (sps)
OUTPUT DATA PERꢂOD
(24.576MHz CLOCK CYCLES)
FSAMPC[2:0] FSAMPF[10:0]
11ꢁꢁꢁꢁꢁꢁꢁꢁꢁ
2000.7
2000.7
3997.4
4000.0
4001.3
4001.3
7994.8
8000.0
8002.6
8002.6
15990
16000
16010
16010
31958
32000
32042
32042
63834
64000
12284
12284
6148
6144
6142
6142
3074
3072
3071
3071
1537
1536
1535
1535
769
10111111111
100
4
2
1
1
1
00000000001
00000000000
11ꢁꢁꢁꢁꢁꢁꢁꢁꢁ
10111111111
101
00000000001
00000000000
11ꢁꢁꢁꢁꢁꢁꢁꢁꢁ
10111111111
000
00000000001
00000000000
11ꢁꢁꢁꢁꢁꢁꢁꢁꢁ
4K/MAX160
1011111111ꢁ
110
0000000001ꢁ
0000000000ꢁ
11ꢁꢁꢁꢁꢁꢁꢁꢁꢁ
768
767
101111111ꢁꢁ
111
767
000000001ꢁꢁ
385
000000000ꢁꢁ
384
Table 10. Typical Performance vs. Output Data Rate
RELATꢂꢀE
SNR OF 24ꢁBꢂT ACCURACY OF
RELATꢂꢀE
ACCURACY OF
SꢂNGLE CYCLE
AT 60Hz (%)
OUTPUT
ꢁ3dB
ꢁ0.1dB
FAULT
RECOꢀERY
TꢂME (µs)
LATENCY
(µs)
DATA RATE BANDWꢂDTH BANDWꢂDTH
DATA (dB)
256 DATA
POꢂNTS (%)
(ksps)
(kHz)
(kHz)
0.5
1
0.11
0.21
0.42
0.85
1.69
2.11
2.54
3.38
6.78
13.5
0.05
0.11
0.22
0.43
0.87
1.09
1.31
1.74
3.48
6.96
12030
6030
3030
1530
780
16375
8375
4375
2375
1375
1175
1042
875
117
115
113
111
108
107
106
105
97
0.04
0.05
0.06
0.08
0.11
0.13
0.14
0.16
0.40
2.51
0.23
0.20
0.17
0.16
0.16
0.16
0.16
0.16
0.28
1.26
2
4
8
10
12
16
32
64
630
530
405
218
625
124
500
81
24 ______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
4K/MAX160
n, which is driven by the CASCOUT of device n-1,
allows device n to take over the SPI bus until all eꢁpect-
ed data is written or readꢀ at this point, device n pulls its
CASCOUT output low. Similarly, CASCOUT of device n
drives CASCIN of device n+1. Figures 12 and 14 show
read operations, including CASCIN and CASCOUT tim-
ings, for two cascaded devices and eight cascaded
devices, respectively. The operation described above
applies to all register operations eꢁcept for writes to the
Data-Rate Control register. A fiꢁed 16-bit word is written
to the Data-Rate Control registers of all devices in the
chain, independent of the number of cascaded devices
(see Figure 15). Reading from the Data-Rate Control
register returns 16 bits per cascaded device.
Multiple Device Connection
Daisy chain up to eight devices for applications that
require up to 32 simultaneously sampled inputs over a
single SPI-/DSP-compatible serial interface with a single
chip-select signal, and single interface commands that
apply to all devices in the chain. The eight devices effec-
tively operate as one device.
There are two aspects to cascading multiple devices:
the digital interface and the mechanism for keeping
multiple devices sampling simultaneously.
There are many configurations for connecting multiple
devicesꢀ one is described in the neꢁt section, others
are described in the Synchronizing Multiple Devices
section within the Applications Information section.
Connecting the open-drain OVRFLW output of all
devices together creates one signal that summarizes
the overflow information of all devices. This is also true
of the FAULT output. Connecting together these out-
puts from multiple devices has the effect of a “wire
NOR.” Any device that has an active condition on these
outputs is allowed to pull the line low.
Multiple Device Digital ꢂnterface
Figure 13 shows the most common way to daisy chain
the digital interface of multiple devices.
SPI bus arbitration is performed using CASCIN and
CASCOUT. A falling edge at the CASCIN input of device
SYNC
CS
SYNC
CS
SYNC
CS
SCLK
DIN
SCLK
DIN
SCLK
DIN
MAX11040K
MAX11060
MAX11040K
MAX11060
MAX11040K
MAX11060
CASCIN
DRDYIN
CASCOUT
CASCIN
DRDYIN
CASCOUT
CASCIN
DRDYIN
DRDYOUT
DSP OR
MICROCONTROLLER
DEVICE 0
DEVICE n
DEVICE n+1
FAULT
OVRFLW
FAULT
OVRFLW
DOUT
FAULT
OVRFLW
DOUT
DOUT
XIN
XOUT CLKOUT
XIN
XIN
CASCADE UP TO 8 DEVICES
Figure 13. Daisy Chaining Multiple Devices
______________________________________________________________________________________ 25
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
There are two ways to use a single line to indicate that
all devices have their data ready, depending on
whether they are clocked synchronously. If all devices
have the same XIN clock and have been synchronized
using SYNC or reset commands, the DRDYOUT of any
device in the chain is used to represent all of them.
Alternatively, if the devices use a different XIN clock,
connect DRDYIN of device 0 to ground, and connect
DRDYIN of device n to the DRDYOUT of device n-1 for
all devices. DRDYOUT does not go low until DRDIN is
low and the conversion of the device is complete. In this
configuration, DRDYOUT of the last device goes low only
when all devices in the chain have their data ready.
t
CSW
CS
DIN
SCLK
DOUT
4K/MAX160
DEVICE 0
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
DEVICE 5
DEVICE 6
DEVICE 7
CASCOUT0
(CASCIN0 = 0)
CASCOUT1
CASCOUT2
CASCOUT3
CASCOUT4
CASCOUT5
CASCOUT6
CASCOUT7
Figure 14. Configuration Register Read Operation Timing Diagram for Eight Cascaded Devices
26 ______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
4K/MAX160
CS
DIN
B15 B14 B13
X
X
B10 B9 B8
B7 B6 B5 B4 B3 B2 B1 B0
SCLK
HIGH-Z
HIGH-Z
DOUT
CASCOUT0
(CASCIN0 = 0)
CASCOUT1
CASCOUT2
CASCOUT3
CASCOUT4
CASCOUT5
CASCOUT6
CASCOUT7
X = RESERVED
Figure 15. Data Rate Controller Register Write Operation Timing Diagram for Eight Cascaded Devices
______________________________________________________________________________________ 27
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
SYNC for Simultaneous
Sampling with Multiple Devices
OUT with a period t . The effect of a SYNC falling edge
S
as shown in Figure 16 is described in sequence below:
The SYNC input permits multiple devices to sample
simultaneously. The mismatch between the power-up
reset of multiple devices causes the devices to begin
conversion at different times. After a falling edge on the
SYNC input, the device completes the current conver-
sion and then synchronizes subsequent conversions
(see Figure 16).
1) A SYNC falling edge is issued two XIN clock cycles
after the DRDYOUT event 2.
2) The converter remembers the two XIN clock cycles,
and completes the current sample, issuing DRDYOUT
event 3 a period of t after DRDYOUT event 2.
S
3) Then, the converter pauses for the remembered time
period, two XIN clock cycles for this eꢁample.
Upon a SYNC falling edge, the devices measure the time
between the SYNC falling edge to the preceding DRDY-
OUT falling edge, wait until the neꢁt DRDYOUT falling
edge, then pause the ADC for the measured amount of
time. Figure 16 shows an eꢁample where the converter
is regularly sampling the input and producing a DRDY-
4) Correspondingly, DRDYOUT event 4 is issued two
XIN cycles later than it would have without the
SYNC falling edge.
5) The process continues as normal with DRDYOUT
event 5 appearing t after DRDYOUT event 4.
S
NOTE: THE LATENCY IS NOT TO SCALE.
4K/MAX160
t
S
1
DELAY 2
CYCLES
t
S
t
S
2
t
S
3
AIN_
4
t
S
5
6
S
t
S
t
t
S
S
t
t
S
XIN
DRDYOUT
1
2
3
4
5
SYNC
MEASURE
PAUSE
Figure 16. Effect of a SYNC Falling Edge
28 ______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
4K/MAX160
Referring back to the analog input, since the entire sam-
pling section of the converter also paused for two clock
cycles, the sampling point for sample 5 is also paused
by two clock cycles, possibly creating a small distur-
bance at the SYNC falling edge. This disturbance is fil-
tered with the digital filter, which makes it less distinct.
OUTPUT CODE
FS = +0.88 x V
ZS = 0
REFIO
FULL-SCALE
TRANSITION
011...111
If the SYNC falling edge occurred during the same XIN
clock period as the DRDYOUT signal, the disturbance
does not affect the periodic timing since the SYNC
falling edge would demand a pause of zero XIN clock
cycles. Hence, connecting the DRDYOUT of one con-
verter to the SYNC inputs of many converters, as illus-
trated in Figure 13, aligns the sampling of the
converters on the first SYNC falling edge, but does not
disturb a regular sampling process for future samples.
011..110
-FS = -0.88 x V
REFIO
2(0.88 x V
)
REFIO
1 LSB =
000...011
000...010
000...001
000...000
111...111
N*
2
*N = 19 FOR 19-BIT TRANSFER
FUNCTION,
N = 24 FOR 24-BIT TRANSFER
FUNCTION
N = 16 FOR MAX11060
111...110
See the Multiple Device Synchronization section for dif-
ferent ways to use the SYNC input.
100...001
100...000
Transfer Function
Figures 17 shows the bipolar I/O transfer function.
Code transitions occur halfway between successive-
integer LSB values. Output coding is binary, with 1 LSB
-FS
0
FS
FS - 3/2 LSB
DIFFERENTIAL INPUT VOLTAGE (LSB)
= (0.88 ꢁ V
) ꢁ 2/524,288 in 19-bit mode, (0.88 ꢁ
REFIO
V ) ꢁ 2/16,777,216 in 24-bit mode, and (0.88 ꢁ
REFIO
V ) ꢁ 2/65536 for the MAX11060.
REFIO
Figure 17. ADC Transfer Function
Power-On Reset
The serial interface, logic, digital filter, and modulator
circuits reset to zero at power-up. The power-on reset
circuit releases this reset no more than 1ms after
V
DV
rises above 2V.
DD
______________________________________________________________________________________ 29
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
between the clock sources by resynchronizing after
Applications Information
Multiple Device Synchronization
each conversion when DRDYOUT transitions low. In
this configuration, the maꢁimum correction caused by a
SYNC edge is one XIN clock cycle.
Synchronizing Multiple Devices
Using a Shared XꢂN Clock Source
The resulting sampling rate is determined by the sampling
frequency of the device with the slowest clock source,
plus the delay through the DRDYIN to DRDYOUT chain
between this slowest device and the end of the chain.
To synchronize multiple devices sharing a single XIN
clock source, transition the SYNC input that is shared
by all devices high to low. When an eꢁternal sync
source is not available, connect DRDYOUT of one
device to the SYNC input of all devices in the chain.
The devices ignore any SYNC transitions applied dur-
ing the power-on reset.
Synchronizing Multiple Devices
to an ꢂndependent Clock Source
To periodically synchronize multiple devices to an inde-
pendent timing source, connect the timing source to
the SYNC inputs of the devices. If minimal jitter is
important in the application, program the devices to a
frequency slightly slower than the eꢁternal frequency,
such that SYNC falling edges only occur a short time
after the DRDYOUT signals.
Synchronizing Multiple Devices
Using ꢂndependent XꢂN Clock Sources
If it is undesirable to connect the XIN clock sources
together, due to EMI or other reasonsꢀ use DRDYIN,
DRDYOUT, and SYNC to align the conversion timing as
shown in Figure 18. This minimizes the effects of drift
4K/MAX160
SYNC
CS
SYNC
CS
SYNC
CS
SCLK
DIN
SCLK
DIN
SCLK
DIN
MAX11040K
MAX11060
MAX11040K
MAX11060
MAX11040K
MAX11060
CASCIN
DRDYIN
CASCOUT
DRDYOUT
CASCIN
DRDYIN
CASCOUT
DRDYOUT
CASCIN
DRDYIN
DRDYOUT
DSP OR
MICROCONTROLLER
DEVICE 0
DEVICE n
DEVICE n+1
FAULT
OVRFLW
FAULT
OVRFLW
DOUT
FAULT
OVRFLW
DOUT
DOUT
XIN
XOUT CLKOUT
XIN
XOUT
XIN
XOUT
CASCADE UP TO 8 DEVICES
Figure 18. One Crystal per Device and All SYNC Inputs Driven by DRDYOUT of the Last Device in the Chain
30 ______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
4K/MAX160
Eꢁample:
Assume f
Signal Distortion at SYNC Falling Edges
Each SYNC falling edge causes a disruption in the digi-
tal filter timing proportional to the delay from the previ-
ous falling edge of DRDYOUT to the falling edge of
SYNC. Any analysis of the output data that assumes a
uniform sampling period sees an error proportional to
that delay, with a maꢁimum value determined by the
maꢁimum derivative of the analog input. Figure 19
shows the effect of this discontinuity at output sample 5.
= 60Hz, f = 16ksps, and eight total
AIN_
S
devices in the chain.
Device 1 has the longest t
therefore the worst-case SYNC error.
delay,
DRDYOUT_TO_SYNC
If device 1 has the fastest XIN clock in the chain, and
device 2 has the slowest XIN clock in the chain, and
they differ by 0.1%, device 1 completes its conversion
as much as 0.1% earlier than device 2. Hence, the
delay of device 2 is:
Assuming a 60Hz 2.2V sine wave, the maꢁimum pos-
sible error on any given sample caused by a SYNC
falling edge is:
0.1% ꢁ (1/16kHz ) = 62.5ns
The signal then propagates down the chain at a time
delay of nominally 20ns for each device.
V
= 2.2V ꢁ 2π ꢁ 60Hz ꢁ t
ERROR_MAX
DRDYOUT_TO_SYNC
DRDYOUT_TO_SYNC
= 0.83μV/ns ꢁ t
The total delay back to the SYNC falling edge after
The delay from DRDYOUT to SYNC is quantized to
within one cycle of the 24.576MHz clock. SYNC pulses
that are asynchronous to DRDYOUT may cause large
errors. To eliminate this error, use a single clock source
for all devices and avoid disrupting the output data tim-
ing with SYNC pulses while making high-precision
measurements. Alternately, minimize the delay from
DRDYOUT to SYNC to minimize the error.
going through siꢁ additional delays is:
t
= 62.5ns + 6 ꢁ 20ns = 182.5ns
DELAY
Maꢁimum % Error = 2π ꢁ f ꢁ t
IN
DRDYOUT_TO_SYNC ꢁ
= 2 ꢁ π ꢁ 60Hz ꢁ 182.5ns ꢁ 100% = 0.007%
100%
The above error is relative to the signal level, not to the
full scale of the data converter.
NOTE: THE LATENCY IS NOT TO SCALE.
t
S
t
S
1
t
S
2
t
S
3
t
DRYOUT_TO_SYNC
5
AIN_
4
t
S
6
t
t
t
S
S
S
t
S
DRDYOUT
SYNC
1
2
3
4
PAUSE FOR
DRYOUT_TO_SYNC
MEASURE
t
t
DRYOUT_TO_SYNC
1
2
RECONSTRUCTED
DIGITAL OUTPUT
3
4
DISCONTINUITY DUE TO SYNC EVENT
5
6
Figure 19. Eꢁample of Discontinuity in Reconstructed Digital Output Due to SYNC Falling Edge with a Large DRDYOUT-to-SYNC Delay
______________________________________________________________________________________ 31
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Source Impedance and
Input Sampling Network
Analog Filtering
The analog filtering requirements in front of the devices
are considerably reduced compared to a conventional
converter with no on-chip filtering. The internal digital
filter has significant rejection of signals higher than the
Nyquist frequency of the output data rate that would
alias back into the sampled signal.
The source impedance that drives the analog inputs
affects the sampling period.
Lowꢁꢂmpedance Sources
Minimize the source impedance to ensure the input
capacitor fully charges during the sampling phase.
The required source resistance is defined by the
equation below:
The internal digital filter does not provide rejection
close to the harmonics of the 3.072MHz modulator fre-
quency. For eꢁample, assuming an output data rate of
16ksps if the XIN clock is set to 24.576MHz, then the
band between 3.0686MHz and 3.0750MHz is not
eꢁplicitly filtered. Since this unfiltered band is very
small compared to its actual frequency, very little
broadband noise enters through this mechanism. If
focused narrowband noise in this band is present, a
simple analog filter can create significant attenuation at
this frequency because the ratio of passband-to-stop-
band frequency is large.
t
SAMP
R
<
−R
INT
SOURCE_MAX
1
Error
⎛
⎝
⎞
K ꢁ C
ꢁ In
⎜
⎟
⎠
SAMP
120ns
=
− 2600Ω
1
Error
⎛
⎝
⎞
1.5 ꢁ 4pF ꢁ In
⎜
⎟
⎠
where K = 1.5 and R
= 2600Ω.
INT
In addition, because the device’s common-mode rejec-
tion eꢁtends out to several 100kHz, the common-mode
noise susceptibility in this frequency range is substan-
tially reduced.
For eꢁample, the required source resistance to achieve
0.1% accuracy is:
120ns
4K/MAX160
R
<
− 2600Ω
SOURCE_MAX
1
⎛
⎝
⎞
1.5 ꢁ 4pF ꢁ ln
⎜
⎟
⎠
Providing additional filtering in some applications
ensures that differential noise signals outside the fre-
quency band of interest do not saturate the analog
modulator.
0.1%
120ns
1.5 ꢁ 4pF ꢁ ln 1000
=
=
− 2600Ω
(
)
The modulator saturates if the input voltage eꢁceeds its
full scale ( 2.2V). The digital filter does not prevent a
large signal in the filter stopband from saturating the
modulator. If signals outside the band of interest cause
violation of this full scale while accurate conversion of
passband signals is desired, then additional analog fil-
tering is required to prevent saturation.
120ns
1.5 ꢁ 4pF ꢁ 6.91− 2600Ω = 294Ω
Highꢁꢂmpedance Sources
If the source impedance is greater than
R
, as defined in the Low-Impedance
SOURCE_MAX
Sources section, place a 0.1μF bypass capacitor
between AIN_+ and AIN_- to provide transient charge.
The average switched-capacitor load with a proper
bypass capacitor and XIN clock frequency =
24.576MHz is equivalent to a 130kΩ resistor connect-
ed between AIN_+ and AIN_-. This resistance is inde-
pendent of the value of the 0.1μF bypass capacitor. If
another XIN clock frequency is chosen, this resistance
is directly proportional to the XIN clock period.
Compensating for the Rolloff of
the Digital Filter in Typical FFT Analysis
To calculate FIR_GAIN(f
):
AIN_
1) Decide the number of evenly spaced frequencies
between DC and the Nyquist frequency of the output
data rate at which correction factors are desired,
which is usually the same as the FFT result.
2) Create an array with a length that is 2ꢁ the number of
the desired frequencies. (Again, the result is likely to
correlate with the time domain array that is loaded
into an FFT algorithm.)
Although the addition of a bypass capacitor helps charge
the devices’ 0 input capacitor, some gain error due to
resistive drop across the source resistance still remains.
Calculate this gain error using the following equation:
3) Fill this array with the filter coefficients provided in
the Digital Filter section. Fill the rest of the array with
zeros.
R
R
SOURCE
+ 130kΩ
SOURCE
SOURCE
ΔGain =
=
R
+ R
R
SOURCE
LOAD
4) Take an FFT of this array. The result represents the
response of the devices’ built-in FIR filter.
32 ______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
4K/MAX160
To compensate the result of an FFT for the devices’ out-
put data:
Lay out the traces in perpendicular directions when a
digital line and an analog line cross each other.
1) Calculate the inverse (1/ꢁ) of the equation provided
in the Digital Filter section for each frequency in the
FFT.
Bypass AVDD to the analog ground plane with a 0.1μF
capacitor in parallel with a 1μF to 10μF low-ESR capac-
itor. Keep capacitor leads short for best supply-noise
rejection. Bypass REF+ and REF- with a 0.1μF capaci-
tor to GND. Place all bypass capacitors as close as
possible to the device for optimum decoupling.
2) Multiply the FFT of the devices’ output data by the
result of the above step.
Power Supplies
AVDD and DVDD provide power to the devices. The
AVDD powers up the analog section, while the DVDD
powers up the digital section. The power supply for
AVDD and DVDD ranges from +3.0V to +3.6V and 2.7V
Crystal Layout
Follow these basic layout guidelines when placing a
crystal on a PCB with the devices to avoid coupled
noise:
to V
, respectively. Bypass AVDD to AGND with a
1) Place the crystal as close as possible to XIN and
XOUT. Keeping the trace lengths between the crys-
tal and inputs as short as possible reduces the
probability of noise coupling by reducing the length
of the “antennae.” Keep the XIN and XOUT lines
close to each other to minimize the loop area of the
clock lines. Keeping the trace lengths short also
decreases the amount of stray capacitance.
AVDD
1μF electrolytic capacitor in parallel with a 0.1μF ceramic
capacitor and bypass DVDD to DGND with a 1μF elec-
trolytic capacitor in parallel with a 0.1μF ceramic capaci-
tor. For improved performance, place the bypass
capacitors as close as possible to the device.
Layout, Grounding, and Bypassing
The best layout and grounding design always comes
from a thorough analysis of the complete system. This
includes the signal source’s dependence and sensitivi-
ty on ground currents, and knowledge of the various
currents that could travel through the various potential
grounding paths.
2) Keep the crystal solder pads and trace width to XIN
and XOUT as small as possible. The larger these
bond pads and traces are, the more likely it is that
noise will couple from adjacent signals.
3) Place a guard ring (connect to ground) around the
crystal to isolate the crystal from noise coupled from
adjacent signals.
Use PCBs with separate analog and digital ground
planes. Connect the two ground planes together only at
the devices’ GND input. Isolate the digital supply from
the analog with a low-value resistor (10Ω) or ferrite
bead when the analog and digital supplies come from
the same source.
4) Ensure that no signals on other PCB layers run
directly below the crystal or below the traces to XIN
and XOUT. The more the crystal is isolated from
other signals on the board, the less likely for noise to
couple into the crystal.
Ensure that digital return currents do not pass through
the analog ground and that return-current paths are low
impedance. A 5mA current flowing through a PCB
ground trace impedance of only 0.05Ω creates an error
voltage of approꢁimately 250μV.
5) Place a local ground plane on the PCB layer imme-
diately below the crystal guard ring. This helps to
isolate the crystal from noise coupling from signals
on other PCB layers.
Note: Keep the ground plane in the vicinity of the
crystal only and not on the entire board.
Ensure that digital and analog signal lines are kept sepa-
rate. Do not run digital (especially the SCLK and DOUT)
lines parallel to any analog lines or under the devices.
______________________________________________________________________________________ 33
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Package Information
Chip Information
For the latest package outline information and land patterns, go
to www.maximꢁic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffiꢁ character, but the drawing per-
tains to the package regardless of RoHS status.
PROCESS: BiCMOS
LAND
PATTERN NO.
PACKAGE
TYPE
PACKAGE
CODE
OUTLꢂNE
NO.
90ꢁ0140
38 TSSOP
U38+3
21ꢁ0081
4K/MAX160
34 ______________________________________________________________________________________
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
4K/MAX160
Revision History
REꢀꢂSꢂON REꢀꢂSꢂON
PAGES
CHANGED
DESCRꢂPTꢂON
NUMBER
DATE
0
1
2/11
4/11
Initial release of the MAX11040K
Initial release of the MAX11060
—
1
Maꢁim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maꢁim product. No circuit patent licenses are
implied. Maꢁim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 35
© 2011 Maꢁim Integrated Products
Maꢁim is a registered trademark of Maꢁim Integrated Products, Inc.
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