MAX1107 [MAXIM]
Single-Supply, Low-Power, Serial 8-Bit ADCs; 单电源，低功耗，串行8位ADC
| 型号： | MAX1107 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Single-Supply, Low-Power, Serial 8-Bit ADCs |
| 文件： | 总16页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1432; Rev 0; 3/99
S in g le -S u p p ly, Lo w -P o w e r,
S e ria l 8 -Bit ADCs
6/MAX107
Ge n e ra l De s c rip t io n
Fe a t u re s
The MAX1106/MAX1107 low-power, 8-bit, single-channel,
analog-to-digital converters (ADCs) feature an internal
track/hold (T/H), voltage reference, clock, and serial inter-
face. The MAX1106 is specified from +2.7V to +3.6V and
consumes only 96µA. The MAX1107 is specified from
+4.5V to +5.5V and consumes only 107µA. The analog
inputs are pin-configurable, allowing unipolar and single-
ended or differential operation.
♦ Single Supply: +2.7V to +3.6V (MAX1106)
+4.5V to +5.5V (MAX1107)
♦ Low Power: 96µA at +3V and 25ksps
0.5µA in Power-Down Mode
♦ Pin-Programmable Configuration
♦ 0 to V
Input Voltage Range
DD
The full-scale analog input range is determined by the
internal reference of +2.048V (MAX1106) or +4.096V
(MAX1107), or by an externally applied reference rang-
♦ Internal Track/Hold
♦ Internal Reference: +2.048V (MAX1106)
+4.096V (MAX1107)
ing from 1V to V . The MAX1106/MAX1107 also feature
DD
a pin-selectable power-down mode that reduces power
consumption to 0.5µA when the device is not in use. The
3-wire serial interface directly connects to SPI™, QSPI™,
a nd MICROWIRE™ d e vic e s without e xte rna l log ic .
Conversions up to 25ksps are performed using the inter-
nal clock.
♦ 1V to V
Reference Input Range
DD
♦ SPI/QSPI/MICROWIRE-Compatible Serial Interface
♦ Small 10-Pin µMAX Package
Ord e rin g In fo rm a t io n
The MAX1106/MAX1107 are available in a 10-pin µMAX
p a c ka g e with a footp rint tha t is jus t 20% of a n
8-pin plastic DIP.
PART
TEMP. RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
10 µMAX
MAX1106CUB
MAX1106EUB
MAX1107CUB
MAX1107EUB
10 µMAX
Ap p lic a t io n s
Portable Data Logging
10 µMAX
10 µMAX
Hand-Held Measurement Devices
Medical Instruments
System Diagnostics
Fu n c t io n a l Dia g ra m
Solar-Powered Remote Systems
4–20mA-Powered Remote Systems
Receive-Signal-Strength Indicators
V
DD
CONVST
SCLK
OUTPUT
SHIFT
REGISTER
P in Co n fig u ra t io n
DOUT
SHDN
MAX1106
MAX1107
TOP VIEW
INTERNAL
OSCILLATOR
V
1
2
3
4
5
10 SCLK
DD
CONTROL
LOGIC
IN+
IN-
9
8
7
6
DOUT
MAX1106
MAX1107
SAR
IN+
T/H
ANALOG
SHDN
CONVST
REFIN
INPUT
MUX
GND
IN-
CHARGE
REDISTRIBUTION
DAC
REFOUT
REFOUT
INTERNAL
REFERENCE
µMAX
REFIN
GND
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
S in g le -S u p p ly, Lo w -P o w e r,
S e ria l 8 -Bit ADCs
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND..............................................................-0.3V to +6V
Operating Temperature Ranges
IN+, IN-, REFIN, REFOUT,
DOUT to GND..........................................-0.3V to (V + 0.3V)
SHDN, SCLK, CONVST to GND...............................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
MAX110_CUB ......................................................0°C to +70°C
MAX110_EUB ...................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
DD
A
10-pin µMAX (derate 5.6mW/°C above +70°C) ............444mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX1106
(V = +2.7V to +3.6V; IN- to GND; f
= 2MHz; 25ksps conversion rate; 1µF capacitor at REFOUT; external +2.048V reference at
DD
SCLK
REFIN; T = T
to T
; unless otherwise noted. Typical values are at T = +25°C.)
A
MIN
MAX
A
PARAMETER
DC ACCURACY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
6/MAX107
Resolution
8
Bits
LSB
LSB
LSB
V
= 2.7V to 3.6V
±0.15
±0.2
±0.5
DD
Relative Accuracy (Note 1)
Differential Nonlinearity
Offset Error
INL
V
DD
= 5.5V (Note 2)
DNL
No missing codes over temperature
±1
±1
V
DD
= 2.7V to 3.6V
= 5.5V (Note 2)
±0.2
±0.5
V
DD
Gain Error (Note 3)
±1
±1
LSB
Gain Temperature Coefficient
±0.8
±0.5
ppm/°C
T
= +25°C
A
Total Unadjusted Error
TUE
LSB
T
A
= T to T
MIN MAX
DYNAMIC PERFORMANCE (10kHz sine-wave input, 2.048Vp-p, 25ksps conversion rate)
Signal-to-Noise Plus Distortion
SINAD
49
dB
dB
Total Harmonic Distortion
(up to the 5th harmonic)
THD
-70
Spurious-Free Dynamic Range
Small-Signal Bandwidth
Full-Power Bandwidth
SFDR
68
1.5
0.8
dB
BW
-3dB rolloff
MHz
MHz
-3dB
ANALOG INPUTS
Input Voltage Range (Note 4)
V
IN_
V
IN+
to V
0
V
REFIN
V
IN-
On/off-leakage current,
or V = 0 or V
Input Leakage Current
Input Capacitance
±0.01
18
±1
µA
pF
V
IN+
IN-
DD
C
IN
2
_______________________________________________________________________________________
S in g le -S u p p ly, Lo w -P o w e r,
S e ria l 8 -Bit ADCs
6/MAX107
ELECTRICAL CHARACTERISTICS—MAX1106 (continued)
(V = +2.7V to +3.6V; IN- to GND; f
= 2MHz; 25ksps conversion rate; 1µF capacitor at REFOUT; external +2.048V reference at
DD
SCLK
REFIN; T = T
to T
; unless otherwise noted. Typical values are at T = +25°C.)
A
MIN
MAX
A
PARAMETER
TRACK/HOLD
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Conversion Time
t
Figure 7
35
µs
µs
CONV
Track/Hold Acquisition Time
Aperture Delay
t
1
ACQ
10
ns
Aperture Jitter
<50
400
ps
Internal Clock Frequency
External Clock Frequency Range
INTERNAL REFERENCE
Output Voltage
kHz
MHz
For data transfer only
2
V
1.968
2.048
150
±50
4
2.128
V
µA
REFOUT
REF Short-Circuit Current
REF Tempco
I
(Note 5)
REFSC
ppm/°C
mV
Load Regulation
0 to 0.5mA (Note 6)
Capacitive Bypass at REFOUT
EXTERNAL REFERENCE
Input Voltage Range
Input Current
1
µF
V
REFIN
1.0
V
DD
+ 0.05
20
V
+2.048V at REFIN, full scale
1
µA
POWER REQUIREMENTS
Supply Voltage
V
DD
2.7
3
5.5
V
V
DD
= 3.6V, C = 10pF
96
250
L
Supply Current (Notes 2, 7)
I
µA
mV
DD
V
= 5.5V, C = 10pF
115
DD
L
Power down, V = 3.6V
0.5
2.5
±4
DD
Power-Supply Rejection (Note 8)
PSR
Full-scale input, V = 2.7V to 3.6V
±0.4
DD
DIGITAL INPUTS (SHDN, SCLK, and CONVST)
V
≤ 3.6V
2
3
V
DD
Threshold Voltage High
V
IH
V
DD
> 3.6V
Threshold Voltage Low
Input Hysteresis
V
0.8
V
V
IL
V
HYST
0.2
15
Input Current High
Input Current Low
Input Capacitance
I
IH
±1
±1
µA
µA
pF
I
IL
C
IN
_______________________________________________________________________________________
3
S in g le -S u p p ly, Lo w -P o w e r,
S e ria l 8 -Bit ADCs
ELECTRICAL CHARACTERISTICS—MAX1106 (continued)
(V = +2.7V to +3.6V; IN- to GND; f
= 2MHz; 25ksps conversion rate; 1µF capacitor at REFOUT; external +2.048V reference at
DD
SCLK
REFIN; T = T
to T
; unless otherwise noted. Typical values are at T = +25°C.)
A
MIN
MAX
A
PARAMETER
DIGITAL OUTPUT (DOUT)
Output High Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
OH
I
= 0.5mA
V - 0.5
DD
V
SOURCE
I
= 5mA
0.4
V
SINK
Output Low Voltage
V
OL
I
= 16mA
0.8
±0.01
15
SINK
Three-State Leakage Current
I
L
Figure 6, DOUT High-Z
Figure 6, DOUT High-Z
±10
µA
pF
Three-State Output Capacitance
C
OUT
TIMING CHARACTERISTICS (Figures 6 and 7)
Acquisition Time
t
1
µs
µs
ACQ
CONVST Pulse Width High
t
t
1
CSPW
CONVST Fall to Output Data
Valid
35
µs
CONV
6/MAX107
CONVST Rise to Output Enable
SCLK Fall to Output Data Valid
SCLK Pulse Width High
t
Figure 1, C
Figure 1, C
= 100pF
= 100pF
240
200
ns
ns
ns
ns
ns
ns
ns
µs
ms
DV
LOAD
LOAD
t
20
DO
t
200
200
CH
SCLK Pulse Width Low
t
CL
SCLK Low to Output Disable
SCLK Low to CONVST Rise
SHDN Fall to Output Disable
t
Figure 2, C
Figure 2, C
= 100pF
= 100pF
240
240
TR
LOAD
LOAD
t
100
SCC
t
SHDN
External reference
20
12
Wake-Up Time
t
WAKE
Internal reference (Note 9)
4
_______________________________________________________________________________________
S in g le -S u p p ly, Lo w -P o w e r,
S e ria l 8 -Bit ADCs
6/MAX107
ELECTRICAL CHARACTERISTICS—MAX1107
(V = +4.5V to +5.5V; IN- = GND; f
= 2MHz; 25ksps conversion rate; 1µF capacitor at REFOUT; external +4.096V reference at
DD
SCLK
REFIN; T = T
to T
; unless otherwise noted. Typical values are at T = +25°C.)
A
MIN
MAX
A
PARAMETER
DC ACCURACY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
8
Bits
LSB
Relative Accuracy (Note 1)
Differential Nonlinearity
Offset Error
INL
±0.15
±0.2
±0.8
±0.5
±0.5
±1
DNL
No missing codes over temperature
LSB
±1
LSB
Gain Error (Note 3)
Gain Temperature Coefficient
±1
LSB
ppm/°C
T
A
= +25°C
±1
Total Unadjusted Error
TUE
LSB
T
A
= T to T
MIN MAX
DYNAMIC PERFORMANCE (10kHz sine-wave input, 4.096Vp-p, 25ksps conversion rate)
Signal-to-Noise Plus Distortion
SINAD
49
dB
dB
Total Harmonic Distortion
(up to the 5th harmonic)
THD
-70
Spurious-Free Dynamic Range
Small-Signal Bandwidth
Full-Power Bandwidth
SFDR
68
1.5
0.8
dB
BW
-3dB rolloff
MHz
MHz
-3dB
ANALOG INPUTS
Input Voltage Range (Note 4)
V
V
to V
0
1
V
V
IN_
IN+
IN-
REFIN
On/off-leakage current,
or V = 0 or V
Input Leakage Current
±0.01
18
±1
µA
pF
V
IN+
IN-
DD
Input Capacitance
C
IN
TRACK/HOLD
Conversion Time
t
Figure 7
35
µs
µs
CONV
Track/Hold Acquisition Time
Aperture Delay
t
ACQ
10
ns
Aperture Jitter
<50
400
ps
Internal Clock Frequency
External Clock Frequency Range
INTERNAL REFERENCE
Output Voltage
kHz
MHz
For data transfer only
2
V
3.936
4.096
5
4.256
V
mA
REFOUT
REF Short-Circuit Current
REF Tempco
I
REFSC
±50
4
ppm/°C
mV
Load Regulation
0 to 0.5mA (Note 6)
Capacitive Bypass at REFOUT
1
µF
_______________________________________________________________________________________
5
S in g le -S u p p ly, Lo w -P o w e r,
S e ria l 8 -Bit ADCs
ELECTRICAL CHARACTERISTICS—MAX1107 (continued)
(V = +4.5V to +5.5V; IN- = GND; f
= 2MHz; 25ksps conversion rate; 1µF capacitor at REFOUT; external +4.096V reference at
DD
SCLK
REFIN; T = T
to T
; unless otherwise noted. Typical values are at T = +25°C.)
A
MIN
MAX
A
PARAMETER
EXTERNAL REFERENCE
Input Voltage Range
Input Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
REFIN
1.0
V
+ 0.05
20
V
DD
4.096V at REFIN, full scale
1
µA
POWER REQUIREMENTS
Supply Voltage
V
4.5
5
5.5
250
2.5
±4
V
DD
V
= 5.5V, C = 10pF,
L
DD
115
0.5
full-scale input
Supply Current (Notes 2, 7)
I
DD
µA
Power down, V = 4.5V to 5.5V
DD
External reference = 4.096V,
full-scale input, V = 4.5V to 5.5V
Power-Supply Rejection (Note 8)
PSR
±0.4
mV
DD
DIGITAL INPUTS (SHDN, SCLK, and CONVST)
6/MAX107
Threshold Voltage High
Threshold Voltage Low
Input Hysteresis
V
3
V
V
IH
V
IL
0.8
V
HYST
0.2
15
V
Input Current High
I
IH
±1
±1
µA
µA
pF
Input Current Low
I
IL
Input Capacitance
C
IN
DIGITAL OUTPUT (DOUT)
Output High Voltage
V
I
= 0.5mA
V - 0.5
DD
V
V
OH
SOURCE
I
= 5mA
0.4
SINK
Output Low Voltage
V
OL
I
= 16mA
0.8
±0.01
15
SINK
Three-State Leakage Current
I
Figure 6, DOUT High-Z
Figure 6, DOUT High-Z
±10
µA
pF
L
Three-State Output Capacitance
C
OUT
TIMING CHARACTERISTICS (Figures 6 and 7)
Acquisition Time
t
1
µs
µs
ACQ
CONVST Pulse Width High
t
t
1
CSPW
CONVST Fall to Output Data
Valid
35
µs
CONV
CONVST Rise to Output Enable
SCLK Fall to Output Data Valid
SCLK Pulse Width High
t
Figure 1, C
Figure 1, C
= 100pF
= 100pF
240
200
ns
ns
ns
DV
LOAD
LOAD
t
20
DO
t
200
CH
6
_______________________________________________________________________________________
S in g le -S u p p ly, Lo w -P o w e r,
S e ria l 8 -Bit ADCs
6/MAX107
ELECTRICAL CHARACTERISTICS—MAX1107 (continued)
(V = +4.5V to +5.5V; IN- = GND; f
= 2MHz; 25ksps conversion rate; 1µF capacitor at REFOUT; external +4.096V reference at
DD
SCLK
REFIN; T = T
to T
; unless otherwise noted. Typical values are at T = +25°C.)
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
240
UNITS
ns
SCLK Pulse Width Low
t
200
CL
SCLK Low to Output Disable
SCLK Low to CONVST Rise
SHDN Fall to Output Disable
t
TR
Figure 2, C
Figure 2, C
= 100pF
= 100pF
ns
LOAD
LOAD
t
100
ns
SCC
t
240
ns
µs
SHDN
External reference
20
12
Wake-Up Time
t
WAKE
Internal reference (Note 9)
ms
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 2: See Typical Operating Characteristics.
Note 3:
V
= +2.048V (MAX1106), V
= +4.096V (MAX1107), offset nulled.
REFOUT
REFOUT
Note 4: Common-mode range (IN+, IN-) GND to V
.
DD
Note 5: REFOUT supplies typically 2.5mA under normal operating conditions.
Note 6: External load should not change during the conversion for specified accuracy.
Note 7: Power consumption with CMOS levels.
Note 8: Measured as
V
FS
(2.7V) - V (3.6V) for MAX1106, and measured as
V (4.5V) - V (5.5V) for MAX1107.
FS FS
FS
Note 9: 1µF at REFOUT, internal reference settling to 0.5LSB.
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
= +5.0V (MAX1107); f = 2MHz; 25ksps conversion rate; external reference; 1µF at REFOUT;
SCLK
(V
DD
= +3.0V (MAX1106), V
DD
T
A
= +25°C; unless otherwise noted.)
SHUTDOWN SUPPLY CURRENT
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
vs. SUPPLY VOLTAGE
0.50
0.45
200
200
175
150
125
100
75
DOUT = 10101010
= 10pF
INTERNAL REFERENCE
MAX1106 (V = 2.7V TO 5.5V)
DD
C
LOAD
MAX1107 (V = 4.5V TO 5.5V)
DD
175
150
125
100
75
INTERNAL REFERENCE
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
C
LOAD
= 10pF
DOUT = 10101010
MAX1107, V = 5.0V
DD
C
= 47pF
LOAD
MAX1106, V = 3.0V
DD
DOUT = 10101010
C
LOAD
= 10pF
DOUT = 11111111
50
50
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40 -20
0
20
40
60
80 100
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
S in g le -S u p p ly, Lo w -P o w e r,
S e ria l 8 -Bit ADCs
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V
DD
= +3.0V (MAX1106), V
= +5.0V (MAX1107); f
= 2MHz; 25ksps conversion rate; external reference; 1µF at REFOUT;
DD
SCLK
T
A
= +25°C; unless otherwise noted.)
OFFSET ERROR vs. TEMPERATURE
OFFSET ERROR vs. REFERENCE VOLTAGE
OFFSET ERROR vs. SUPPLY VOLTAGE
0.5
0.5
0.4
0.20
0.4
0.3
0.15
0.10
0.05
0
0.3
0.2
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
-0.05
-0.10
-0.15
-0.20
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40 -20
0
20
40
60
80 100
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
REFERENCE VOLTAGE (V)
6/MAX107
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
GAIN ERROR vs. SUPPLY VOLTAGE
GAIN ERROR vs. TEMPERATURE
GAIN ERROR vs. REFERENCE VOLTAGE
0.5
0.4
1.0
0.8
1.0
0.8
0.6
0.4
0.2
0
0.3
0.2
0.6
0.4
0.1
0.2
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40 -20
0
20
40
60
80 100
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
REFERENCE VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
DIFFERENTIAL NONLINEARITY
vs. SUPPLY VOLTAGE
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
0
50
100
150
200
250
300
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
DIGITAL CODE
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
8
_______________________________________________________________________________________
S in g le -S u p p ly, Lo w -P o w e r,
S e ria l 8 -Bit ADCs
6/MAX107
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V
DD
= +3.0V (MAX1106), V
= +5.0V (MAX1107); f
= 2MHz; 25ksps conversion rate; external reference; 1µF at REFOUT;
DD
SCLK
T
A
= +25°C; unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
FFT PLOT
CONVERSION TIME vs. SUPPLY VOLTAGE
0.5
20
0
21.5
21.0
20.5
20.0
19.5
19.0
18.5
f
= 10.34kHz, 2Vp-p
IN+
0.4
0.3
0.2
0.1
0
f
= 25088Hz
SAMPLE
-20
-40
-60
-80
-100
-0.1
-0.2
-0.3
-0.4
-0.5
0
50
100
150
200
250
300
0
2
4
6
8
10
12
14
0
1
2
3
4
5
6
DIGITAL CODE
FREQUENCY (kHz)
SUPPLY VOLTAGE (V)
NORMALIZED REFERENCE VOLTAGE
vs. TEMPERATURE
CONVERSION TIME vs. TEMPERATURE
25
24
23
22
21
20
19
18
17
16
15
1.0010
1.0005
1.0000
0.9995
0.9990
V
DD
= 3V
V
DD
= 5V
0.9985
0.9980
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
P in De s c rip t io n
PIN
1
NAME
FUNCTION
V
DD
Positive Supply Voltage
Positive Analog Input. Sampled. Input range from GND to V
2
IN+
IN-
.
DD
3
Negative Analog Input. Input range from GND to V
.
DD
4
GND
Ground.
5
REFOUT
Internal Reference Output. Bypass with 1µF to ground. 2.048V for MAX1106, 4.096V for MAX1107.
Reference Voltage Input. Reference voltage for analog-to-digital conversion. Connect REFOUT to REFIN
6
REFIN
for internal reference. Input range from 1V to V
.
DD
Conversion Start Input. Toggle CONVST high for 1µs minimum and then low to start internal conversion.
Data is not clocked out unless CONVST is low.
7
8
CONVST
SHDN
Active-Low Shutdown. Connect to V for normal operation.
DD
Serial Data Output. Data is clocked out on the falling edge of SCLK. DOUT is high impedance in shutdown
or after all data is clocked out.
9
DOUT
SCLK
10
Serial Clock Input. Clocks data out of serial interface.
_______________________________________________________________________________________
9
S in g le -S u p p ly, Lo w -P o w e r,
S e ria l 8 -Bit ADCs
V
DD
VDD
3k
C
3k
DOUT
DOUT
DOUT
DOUT
3k
3k
C
LOAD
C
LOAD
C
LOAD
LOAD
GND
GND
GND
GND
b) High-Z to V and V to V
OL
a) V to V
OL
OH
OL
OH
a) V to High-Z
b) V to High-Z
OL
OH
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
_______________De t a ile d De s c rip t io n
V
DD
The MAX1106/MAX1107 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to an 8-bit digital output. A simple ser-
ial interface provides easy interface to microprocessors
(µPs). No external hold capacitors are required. All of
the MAX1106/MAX1107 operating modes are pin con-
figurable: internal or external reference, single-ended
or pseudo-differential unipolar conversion, and power
down. Figure 3 shows the typical operating circuit.
V
V
IN+
DD
DD
6/MAX107
0.1µF
1µF
ANALOG
INPUTS
MAX1106
MAX1107
GND
IN-
CPU
ON
OFF
SHDN
I/O
CONVST
SCLK
REFOUT
REFIN
SCK (SK)
1µF
An a lo g In p u t s
DOUT
MISO (SI)
Track/Hold
The inp ut a rc hite c ture of the ADCs is illus tra te d in
Figure 4’s equivalent-input circuit of and is composed
of the T/H, the input multiplexer, the input comparator,
the switched capacitor DAC, and the auto-zero rail.
GND
Figure 3. Typical Operating Circuit
The device is in acquisition mode most of the time.
During the acquisition interval, the positive input (IN+)
is tracked and is connected to the holding capacitor
GND
CAPACITIVE DAC
REFIN
(C
). The acquisition interval ends with the falling
HOLD
edge of CONVST. At this point the T/H switch opens
and C is connected to the negative input (IN-),
HOLD
retaining charge on C
IN+. Onc e c onve rs ion is c omp le te the T/H re turns
immediately to its tracking mode.
as a sample of the signal at
HOLD
IN+
IN-
C
HOLD
COMPARATOR
18pF
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
R
6.5k
IN
HOLD
TRACK
t
, is the minimum time needed for the signal to be
ACQ
acquired. It is calculated by:
AUTOZERO
RAIL
t
= 6(R + R )18pF
ACQ
S
IN
Figure 4. Equivalent Input Circuit
10 ______________________________________________________________________________________
S in g le -S u p p ly, Lo w -P o w e r,
S e ria l 8 -Bit ADCs
6/MAX107
where R = 6.5kΩ, R = the source impedance of the
from (GND - 0.3V) to (V
+ 0.3V) without damage.
IN
S
DD
input signal, and t
must never be less than 1µs.
However, for accurate conversions, the inputs must not
ACQ
This is easily achieved by respecting the minimum
CONVST high interval required and the time required to
clock the data out.
exceed (V + 50mV) or be less than (GND - 50mV).
DD
The MAX1106/MAX1107 input range is from GND to
V
DD
. The output code is invalid (code zero) when a
negative input voltage (or a negative differential input
voltage) is applied. The reference input-voltage range
Pseudo-Differential Input
The MAX1106/MAX1107 input configuration is pseudo-
differential to the extent that only the signal at the sam-
p le d inp ut (IN+) is s tore d in the hold ing c a p a c itor
at REFIN is from 1V to (V + 50mV).
DD
Input Bandwidth
(C
). IN- mus t re ma in s ta b le within ± 0.5LSB
HOLD
The ADC’s input tracking circuitry has a 1.5MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
(±0.1LSB for best results) in relation to GND during a
conversion.
If a varying signal is applied at the IN- input, its ampli-
tude and frequency need to be limited. The following
equations determine the relationship between the maxi-
mum signal amplitude and its frequency to maintain
±0.5LSB accuracy:
S e ria l In t e rfa c e
The MAX1106/MAX1107 have a 3-wire serial interface.
The CONVST and SCLK inputs are used to control the
d e vic e , while the thre e -s ta te DOUT p in is us e d to
access the result of conversion.
Assuming a sinusoidal signal at the IN- input,
υIN-
=
V
sin(2πft)
(
)
IN-
under the maximum voltage variation is determined by
The serial interface provides easy connection to micro-
controllers with SPI, QSPI, and MICROWIRE serial inter-
faces at clock rates up to 2MHz. For SPI and QSPI, set
CPOL = CPHA = 0 in the SPI control registers of the
microcontroller. Figure 5 shows the MAX1106/MAX1107
common serial-interface connections.
∆υ
V
REFIN
1 LSB
IN-
max
= 2πf V
≤
=
IN-
(
)
8
∆t
t
CONV
2 t
CONV
a 60Hz signal at IN- with an amplitude of 1.2V will
generate ±0.5LSB of error. This is with a 35µs conver-
sion time (maximum t
) and a reference voltage of
CONV
Digital Inputs and Outputs
The log ic le ve ls of the MAX1106/MAX1107 d ig ita l
inputs are set to accept voltage levels from both 3V
and 5V systems regardless of the supply voltages.
4.096V. When a DC reference voltage is used at IN-,
connect a 0.1µF capacitor from IN_ to GND to minimize
noise at the input.
The common-mode input range of IN+ and IN- is GND
A conversion is started by toggling CONVST. CONVST
idles low and needs to be set high for at least 1µs to
perform the autozero adjustment. CONVST must remain
low during conversion and until the result of conversion
has been clocked out.
to +V . Full-scale is achieved when (V - V ) =
DD
IN-
IN+
V
. V
must be higher than V
.
REFIN IN+
IN-
Conversion Process
The comparator negative input is connected to the auto-
zero rail. Since the device requires only a single supply,
the ZERO node at the input of the comparator equals
After CONVST is set low, allow 35µs for the conversion
to be completed. While the internal conversion is in
progress DOUT is low. Conversion is controlled by an
internal 400kHz oscillator. The MSB is present at the
DOUT pin immediately after conversion is completed.
The conversion result is clocked out at the DOUT pin
a nd is c od e d in s tra ig ht b ina ry (Fig ure 9). Da ta is
clocked out at SCLK’s falling edge in MSB-first format
at rates up to 2MHz. Once all data bits are clocked out,
DOUT goes high impedance at the falling edge of the
eighth SCLK pulse.
V /2. The capacitive DAC restores node ZERO to have
DD
0V difference at the comparator inputs within the limits
of 8-bit resolution. This action is equivalent to transfer-
ring a charge of 18pF(V
- V ) from C
to the
HOLD
IN+
IN-
binary-weighted capacitive DAC which, in turn, forms a
digital representation of the analog-input signal.
Input Voltage Range
Internal protection diodes that clamp the analog input to
V
DD
and GND allow the input pins (IN+ and IN-) to swing
______________________________________________________________________________________ 11
S in g le -S u p p ly, Lo w -P o w e r,
S e ria l 8 -Bit ADCs
Starting SCLK before conversion is complete corrupts
the conversion in progress, and the data clocked out at
DOUT does not represent the input signal. Bringing
CONVST high at anytime during a conversion or while
the data is clocked out will result in an incorrect conver-
sion. A new conversion can be restarted only if all eight
data bits of conversion have been clocked out. Toggle
CONVST after all data is clocked out to restart a new
conversion.
I/O
SCK
CONVST
SCLK
MISO
DOUT
+3V
MAX1106
MAX1107
SS
SHDN is used to place the MAX1106/MAX1107 in low-
power mode (see Power-Down section). In this mode
DOUT is hig h imp e d a nc e a nd a ny c onve rs ion in
progress is stopped immediately. If a conversion is
stopped by SHDN going low, the device must be reset
by waiting 35µs and clearing the output register with
eight SCLKs before the next conversion.
a) SPI
CS
SCK
CONVST
SCLK
DOUT
MISO
+3V
Ho w t o P e rfo rm a Co n ve rs io n
The MAX1106/MAX1107 converts an input signal using
the internal clock. This frees the µP from the burden of
running the SAR conversion clock, and allows the con-
version results to be read back at the µP’s convenience
at any clock rate up to 2MHz.
MAX1106
MAX1107
6/MAX107
SS
b) QSPI
CONVST
I/O
SK
SI
SCLK
DOUT
Figures 6 and 7 show the serial interface timing charac-
teristics. CONVST idles low. Toggle CONVST high for at
least 1µs to perform the autozero adjustment. After
CONVST g oe s low, c onve rs ion s ta rts imme d ia te ly.
Allow 35µs for the internal conversion to complete and
issue the MSB of the conversion at DOUT. CONVST
needs to be held low once a conversion is started,
while SCLK should remain low during conversion for
best noise performance. An internal register stores data
when the conversion is in progress. SCLK clocks the
MAX1106
MAX1107
c) MICROWIRE
Figure 5. Common Serial-Interface Connections
t
CSPW
1µs
(MIN)
CONVST
SCLK
100µs (MAX)
1
8
MSB
D7
LSB
HIGH-Z
HIGH-Z
D6
D5
D4
D3
D2
D1
D0
DOUT
ACQ
ACQUISITION
CONVERSION
= 35µs (MAX)
A/D STATE
t
CONV
Figure 6. Conversion Timing Diagram
12 ______________________________________________________________________________________
S in g le -S u p p ly, Lo w -P o w e r,
S e ria l 8 -Bit ADCs
6/MAX107
t
CSPW
CONVST
SCLK
t
SCC
t
CH
t
CL
#8
#1
t
CONV
t
DV
t
TR
t
DV
t
DO
DOUT
Figure 7. Detailed Serial Interface Timing
data out of this register at any time after the conversion
is complete. After the eighth data-bit has clocked out,
DOUT goes high impedance and remains so with addi-
tional SCLKs.
Normally leave CONVST low until a new conversion
needs to be started. CONVST should be high for a
maximum of 100µs to maintain the 8-bit accuracy of the
Autozero Circuit.
CONVST
5V/div
SCLK
5V/div
The acquisition time, t
, starts immediately after the
ACQ
end of conversion and a new conversion can be started
immediately after all data has been clocked out by tog-
gling CONVST high. Figure 8 shows a timing diagram
for a conversion at the data rate of 40ksps. Typically
20µs are necessary for the conversion to complete, 4µs
for reading the eight bits of data with a serial clock of
2MHz, and 1µs to complete the zero rail adjustment
and acquisition. The conversion time is guaranteed to
be less than 35µs, therefore the data rate should be
limited to 25ksps unless the conversion time for the
specific condition is known. Conversion time can be
determined by measuring the time between CONVST
falling edge and DOUT rising edge with a full-scale
input voltage.
t
CONV
DOUT
5V/div
5µs/div
Figure 8. 40ksps Timing Diagram
CONVST low will not start a conversion. No conversions
should be performed until the reference voltage (inter-
nal or external) has stabilized.
S h u t d o w n Op e ra t io n
Pulling SHDN low places the converter in low-current
power-down mode. In this state the converter draws
typically 0.5µA. In shutdown the analog biasing circuit
and the internal bandgap reference are powered down,
and DOUT goes high impedance.
__________Ap p lic a t io n s In fo rm a t io n
P o w e r-On Re s e t
When power is first applied with SHDN high or connect-
ed to V , the MAX1106/MAX1107 is in track mode.
DD
Conversion can be started by toggling CONVST high to
low as soon as the reference is settled when using the
internal reference, or after 20µs when an external refer-
ence is used. Powering up the MAX1106/MAX1107 with
The conversion stops coincidentally with SHDN going
low. If shutdown occurs during a conversion, power up,
wait 35µs, and clock SCLK eight times.
______________________________________________________________________________________ 13
S in g le -S u p p ly, Lo w -P o w e r,
S e ria l 8 -Bit ADCs
When operating at speeds below the maximum sam-
pling rate, the MAX1106/MAX1107’s power-down mode
can save considerable power by placing the converter
in a low-current shutdown state between conversions.
Pull SHDN low after the conversion byte has been read
to shut down the device completely.
OUTPUT CODE
11111111
FULL-SCALE
TRANSITION
11111110
11111101
CONVST should remain low most of the time and tog-
gled high for 1µs (100µs max) for the autozero adjust-
ment. An external reference is recommended for best
a c c ura c y whe n us ing the s hutd own fe a ture . This
requires only 20µs for the internal biasing circuit to sta-
bilize before starting a new conversion. Alternatively,
the internal reference can be used, but additional time
is re q uire d for the re fe re nc e to s ta b ilize (whe n
byp a sse d by a 1µF c a p a c itor; a t da ta ra te s a b ove
1ksps, the reference stabilizes within 1LSB in 200µs). If
the re fe re nc e is c omp le te ly d is c ha rg e d it re q uire s
12ms to settle. No conversions should be performed
until the reference voltage has stabilized.
FS = V
1LSB = V
+ V
REFIN IN-
REFIN
256
00000011
00000010
00000001
00000000
0
1
2
3
FS
FS - 1LSB
(IN-)
INPUT VOLTAGE (LSB)
6/MAX107
Figure 9. Input/Output Transfer Function
In t e rn a l o r Ex t e rn a l Vo lt a g e Re fe re n c e
An external reference between 1V and V should be
DD
Tra n s fe r Fu n c t io n
Fig ure 9 d e pic ts the input/output tra nsfe r func tion.
Code transitions occur at integer LSB values. Output
coding is binary; with a 2.048V reference 1LSB = 8mV
connected directly at the REFIN pin. To use the internal
re fe re nc e , c onne c t REFOUT d ire c tly to REFIN a nd
bypass REFOUT with a 1µF capacitor. The DC input
impedance at REFIN is extremely high, consisting of
leakage current only (typically 10nA). During a conver-
sion, the reference must be able to deliver up to 20µA
average load current and have an output impedance of
1kΩ or less at the conversion clock frequency. If the
reference has higher output impedance or is noisy,
bypass it close to the REFIN pin with a 0.1µF capacitor.
The internal reference is active as long as SHDN is high
and powers down when SHDN is low.
(V
REFIN
/ 256). For single-ended operation connect IN-
to GND. Full-scale is achieved at V
= V
- 1LSB.
IN+
REFIN
For pseudo-differential operation the V voltage range
IN-
is from GND to V , where full-scale is achieved at
DD
V
IN+
= V
+ V - 1LSB. V
should not be higher
REFIN
IN-
IN+
than V
+ 50mV. Negative input voltages are invalid
DD
and give a zero output code. Voltages greater than full-
scale give an all ones output code.
14 ______________________________________________________________________________________
S in g le -S u p p ly, Lo w -P o w e r,
S e ria l 8 -Bit ADCs
6/MAX107
La yo u t , Gro u n d in g , a n d Byp a s s in g
For best performance, use printed circuit boards. Wire-
wra p b oa rd s a re not re c omme nd e d . Boa rd la yout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another or run
digital lines underneath the ADC package.
SYSTEM POWER SUPPLIES
GND
+3V/+5V
Figure 10 shows the recommended system-ground
connections. A single-point analog ground (star-ground
p oint) s hould b e e s ta b lis he d a t the A/D g round .
Connect all analog grounds to the star ground. No digi-
tal-system ground should be connected to this point.
The ground return to the power supply for the star
ground should be low impedance and as short as pos-
sible for noise-free operation.
1µF
10Ω
0.1µF
GND
IN-
V
DGND
V
DD
DD
High-frequency noise in the V
affect the comparator in the ADC. Bypass the supply to
the star ground with 0.1µF and 1µF capacitors close to
power supply may
DD
DIGITAL
CIRCUITRY
MAX1106
MAX1107
the V
p in of the MAX1106/MAX1107. Minimize
DD
capacitor lead lengths for best supply-noise rejection. If
the power supply is very noisy, a 10Ω resistor can be
connected to form a lowpass filter.
Figure 10. Power-Supply Connections
Ch ip In fo rm a t io n
TRANSISTOR COUNT: 2373
______________________________________________________________________________________ 15
S in g le -S u p p ly, Lo w -P o w e r,
S e ria l 8 -Bit ADCs
P a c k a g e In fo rm a t io n
6/MAX107
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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